Light emitting element, display device including the same, and method of manufacturing the same

Abstract

A light emitting element, a display device including the light emitting element, and a method for manufacturing the light emitting element are provided. The light emitting element includes: a first semiconductor layer; a light emitting layer on the first semiconductor layer; a second semiconductor layer on the light emitting layer; a second electrode on the second semiconductor layer; and a first electrode disposed on the first semiconductor layer and spaced apart from the light emitting layer and the second semiconductor layer, in which the first semiconductor layer includes one or more concave patterns between the first electrode and the second electrode.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0163243, filed with the Korean Intellectual Property Office on November 22, 2023, the disclosure of which is incorporated herein by reference. Technical field

[0003] This specification relates to a light - emitting element and a display device including the light - emitting element, and more particularly to a light - emitting diode (LED) and a display device using the LED. Background art

[0004] As display devices for monitors of computers, televisions, cellular phones, etc., there are organic light - emitting display (OLED) devices as self - emitting devices, liquid - crystal display (LCD) devices that require a separate light source, etc.

[0005] The application range of display devices has diversified to personal digital assistants and monitors of computers and televisions, and display devices with a large display area and reduced volume and weight are being studied.

[0006] In addition, recently, display devices including light - emitting diodes (LEDs) have received attention as next - generation display devices. Since LEDs are formed of inorganic materials rather than organic materials, they have excellent reliability, so that their lifespan is longer than that of liquid - crystal display devices or organic light - emitting display devices. In addition, LEDs have a fast light - emitting speed, excellent light - emitting efficiency, and strong impact resistance, so that they have excellent stability and can display images with high brightness. Summary of the invention

[0007] An object to be achieved by this specification is to provide a light - emitting element having improved light extraction efficiency and a display device including the light - emitting element.

[0008] Another object to be achieved by this specification is to provide a light - emitting element that reduces the brightness deviation depending on the viewing angle and a display device including the light - emitting element.

[0009] The objects of the present disclosure are not limited to the above - mentioned objects, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

[0010] According to one aspect of the present disclosure, a light-emitting element is provided. The light-emitting element includes: a first semiconductor layer; a light-emitting layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the light-emitting layer; a second electrode disposed on the second semiconductor layer; and a first electrode disposed on the first semiconductor layer and spaced apart from the light-emitting layer and the second semiconductor layer, wherein the first semiconductor layer includes one or more concave patterns between the first electrode and the second electrode.

[0011] According to one aspect of the present disclosure, a display device is provided. The display device includes: a substrate including a plurality of sub-pixels; a plurality of light-emitting elements disposed in the plurality of sub-pixels on the substrate; a plurality of transistors disposed on the substrate; and a connection electrode configured to connect the plurality of transistors and the plurality of light-emitting elements, wherein each of the plurality of light-emitting elements includes at least one concave pattern disposed on a side surface of the plurality of light-emitting elements, and wherein the connection electrode is disposed to overlap a part of the concave pattern.

[0012] According to one aspect of the present disclosure, a method of manufacturing a light-emitting element is provided. The method includes: disposing a first semiconductor layer, a light-emitting layer, a second semiconductor layer, and a second electrode on a wafer; performing mesa etching on partial regions of the light-emitting layer and the second semiconductor layer to form mesa regions; forming a first cover layer covering the mesa regions; etching the first semiconductor layer in regions not covered by the first cover layer to form concave patterns; forming a second cover layer; etching the first semiconductor layer in regions covered by the second cover layer and removing the second cover layer to form a first electrode on the first semiconductor layer; forming a third cover layer that only covers the concave patterns, lower regions of the concave patterns, and the first electrode; forming a packaging layer on the third cover layer; and removing the third cover layer.

[0013] Other details of the exemplary embodiments are included in the detailed description and the drawings.

[0014] According to the present specification, a light extraction pattern is disposed on a side surface of the light-emitting element so that the light-emitting element can be stably bonded to a panel.

[0015] According to the present specification, an electrode is disposed in the concave pattern so that the light-emitting element can be easily connected to a panel.

[0016] According to the present specification, the appearance of stains caused by a change in viewing angle can be minimized.

[0017] The effects according to the present disclosure are not limited to those exemplified above, and more different effects are included in the present specification. Description of the Drawings

[0018] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 is a schematic cross-sectional view of a light-emitting element according to an embodiment of the present specification;

[0020] Figures 2A to 2G is a process diagram for explaining a method of manufacturing a light-emitting element according to an embodiment of the present specification;

[0021] Figures 3A to 3D is a cross-sectional view of a light-emitting element according to a comparative embodiment and an exemplary embodiment of the present specification;

[0022] Figures 4A to 4D is for explaining Figures 3A to 3D the effects of the light-emitting element in;

[0023] Figure 5 is a schematic cross-sectional view of a light-emitting element according to another embodiment of the present specification;

[0024] Figure 6 is a schematic configuration diagram of a display device according to an embodiment of the present specification;

[0025] Figure 7 is a cross-sectional view of a pixel region of a display device according to an embodiment of the present specification;

[0026] Figure 8A and Figure 8B are cross-sectional views for explaining a method of manufacturing a display device according to an embodiment of the present specification;

[0027] Figure 9 is a cross-sectional view of a pixel region of a display device according to another embodiment of the present specification; and

[0028] Figures 10A to 10F is a process diagram for explaining a method of manufacturing a display device according to another embodiment of the present specification. Detailed Embodiments

[0029] Advantages and characteristics of the present disclosure and methods for achieving these advantages and characteristics will be clear from the following exemplary embodiments described in detail in conjunction with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only as examples so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0030] The shapes, sizes, ratios, angles, numbers, etc. shown in the drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, like reference numerals generally denote like elements. In addition, in the following description of the present disclosure, detailed descriptions of known related arts may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "comprising", "having", and "consisting of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". Any reference to the singular may include the plural unless otherwise expressly stated.

[0031] Even if not explicitly stated, components are construed to include a normal error range.

[0032] When terms such as "on", "above", "below", and "next to" are used to describe the positional relationship between two parts, unless these terms are used together with the terms "immediately" or "directly", one or more parts may be located between these two parts.

[0033] When an element or layer is disposed "on" another element or layer, the other layer or the other element may be directly disposed on the other element or directly disposed therebetween.

[0034] Although terms such as "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below may be the second component in the technical concept of the present disclosure.

[0035] Throughout the specification, like reference numerals generally denote like elements.

[0036] For convenience of description, the dimensions and thicknesses of each component shown in the drawings are shown, and the present disclosure is not limited to the dimensions and thicknesses of the components shown.

[0037] The features of the various embodiments of the present disclosure may be partially or completely adhered to or combined with each other and may be interlocked and operated in technically different ways, and the embodiments may be executed independently of each other or in association with each other.

[0038] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the drawings.

[0039] Figure 1 is a schematic cross-sectional view of a light-emitting element according to an embodiment of the present specification.

[0040] Refer to Figure 1, the light-emitting element ED1 includes a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and a packaging layer 126.

[0041] The light-emitting element ED1 can have various structures, such as a lateral structure, a vertical structure, and a flip-chip structure. The lateral light-emitting element includes a first electrode and a second electrode horizontally disposed at two opposite sides of the light-emitting layer. The vertical light-emitting element includes a first electrode and a second electrode disposed at the upper side and the lower side of the light-emitting layer. The flip-chip light-emitting element is substantially the same as the lateral light-emitting element in structure. The lateral light-emitting element has a first electrode and a second electrode horizontally disposed at the upper side of the light-emitting layer, while the flip-chip light-emitting element has a first electrode and a second electrode horizontally disposed at the lower side of the light-emitting layer. Hereinafter, the description will be made on the assumption that the light-emitting element ED1 has a lateral structure. However, the type of the light-emitting element ED1 is not limited thereto.

[0042] The first semiconductor layer 121 is disposed at the lowermost side of the light-emitting element ED1. The first semiconductor layer 121 can be a layer formed by doping n-type and p-type impurities in a specific material. For example, the first semiconductor layer 121 can be a layer formed by doping n-type and p-type impurities in a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). In this case, the p-type impurity can be magnesium (Mg), zinc (Zn), beryllium (Be), etc. The n-type impurity can be silicon (Si), germanium (Ge), tin (Sn), etc. However, the present disclosure is not limited thereto. In this specification, the first semiconductor layer 121 is defined as an n-type semiconductor layer, that is, a layer doped with n-type impurities. However, the present disclosure is not limited thereto.

[0043] The first semiconductor layer 121 includes a first portion 121-1, a second portion 121-2, and a third portion 121-3.

[0044] The first portion 121-1 is the portion disposed at the lowermost side of the first semiconductor layer 121.

[0045] The second portion 121-2 is disposed on the first portion 121-1. The second portion 121-2 is a concave pattern CP.

[0046] The concave pattern CP is a portion formed to be recessed along the direction toward the center of the first semiconductor layer 121. Therefore, the minimum width of the second portion 121-2 provided with the concave pattern CP can be smaller than the width of the top surface of the first portion 121-1 and the width of the bottom surface of the third portion 121-3. In addition, the minimum width of the second portion 121-2 can be smaller than the width of the bottom surface of the first portion 121-1 and the width of the top surface of the third portion 121-3.

[0047] The concave pattern CP can be set to surround the lateral portion of the second part 121-2. At the same time, Figure 1 It is shown that the concave pattern CP has a circular shape. However, the present disclosure is not limited thereto. The concave pattern CP can be formed to define an inclined surface. In this case, the concave pattern CP can be formed along the crystal direction of the first semiconductor layer 121. For example, when the angle of the crystal surface of the material constituting the first semiconductor layer 121 is 73°, the concave pattern CP can have an inclination angle of 73°. However, the present disclosure is not limited thereto. At the same time, Figure 1 In the cross-sectional view, one concave pattern CP is shown provided on the second part 121-2. However, the number of the concave patterns CP is not limited thereto, and a plurality of concave patterns CP can be provided.

[0048] A third part 121-3 is provided on the second part 121-2. The width of the bottom surface of the third part 121-3 connected to the second part 121-2 can be greater than the width of the top surface of the second part 121-2. Thus, the first semiconductor layer 121 can be provided in an undercut shape. However, the present disclosure is not limited thereto. Additionally, the width of the third part 121-3 can increase in the downward direction. However, the present disclosure is not limited thereto.

[0049] A light-emitting layer 122 and a second semiconductor layer 123 are provided on the first semiconductor layer 121.

[0050] The width of the light-emitting layer 122 and the width of the second semiconductor layer 123 can be smaller than the width of the top surface of the first semiconductor layer 121 provided on the concave pattern CP. For example, the entire light-emitting layer 122 and the entire second semiconductor layer 123 can overlap with the top surface of the first semiconductor layer 121, and the entire second semiconductor layer 123 can overlap with the top surface of the light-emitting layer 122.

[0051] At the same time, the minimum width of the second part 121-2 on which the concave pattern CP is provided can be smaller than the width of the light-emitting layer 122 and the width of the second semiconductor layer 123. However, the present disclosure is not limited thereto.

[0052] The light-emitting layer 122 can emit light by receiving holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123. The light-emitting layer 122 can be configured as a single layer or a multi-quantum well (MQW) structure. For example, the light-emitting layer 122 can be made of indium gallium nitride (InGaN), gallium nitride (GaN), etc. However, the present disclosure is not limited thereto.

[0053] A second semiconductor layer 123 is provided on the light-emitting layer 122. The second semiconductor layer 123 may be a layer formed by doping an n-type and a p-type impurity in a specific material. For example, the second semiconductor layer 123 may be a layer formed by doping an n-type and a p-type impurity in a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). In addition, the p-type impurity may be magnesium (Mg), zinc (Zn), beryllium (Be), etc. The n-type impurity may be silicon (Si), germanium (Ge), tin (Sn), etc. However, the present disclosure is not limited thereto. In the present specification, the second semiconductor layer 123 is defined as a p-type semiconductor layer, that is, a layer doped with a p-type impurity. However, the present disclosure is not limited thereto.

[0054] A first electrode 124 is provided on the first semiconductor layer 121. The first semiconductor layer 121 may be a semiconductor layer doped with an n-type impurity, and the first electrode 124 may be a cathode. The first electrode 124 may be provided on one of the side surface and the top surface of the first semiconductor layer 121 that is exposed from the light-emitting layer 122 and the second semiconductor layer 123. For example, the first electrode 124 may be provided on the top surface of the first portion 121-1 that is exposed through the second portion 121-2. The first electrode 124 may be provided on the top surface of the first portion 121-1 that extends from the concave pattern CP, and the top surface of the first portion 121-1 may be flat. In this case, the first electrode 124 may extend from the top surface of the first portion 121-1 and cover the side surface of the first portion 121-1. However, the present disclosure is not limited thereto.

[0055] Meanwhile, at least a part of the first electrode 124 may be provided on the first portion 121-1 that is provided outside the light-emitting layer 122, the second semiconductor layer 123, and the second electrode 125. For example, at least a part of the top surface of the first portion 121-1 that is exposed through the second portion 121-2 may be provided outside the light-emitting layer 122, the second semiconductor layer 123, and the second electrode 125. In this case, the first electrode 124 may be provided on the first portion 121-1 that is provided outside the light-emitting layer 122, the second semiconductor layer 123, and the second electrode 125.

[0056] For example, as Figure 1 shown, a part of the first electrode 124 may be provided outside the two opposite ends E of the third portion 121-3. Therefore, in the case where the light-emitting layer 122, the second semiconductor layer 123, and the second electrode 125 are provided inside the two opposite ends E of the third portion 121-3, the first electrode 124 may be provided outside the light-emitting layer 122, the second semiconductor layer 123, and the second electrode 125. Meanwhile, Figure 1It is shown that the first electrode 124 is only disposed outside the two opposite ends E of the third portion 121-3. However, the present disclosure is not limited thereto. A part of the first electrode 124 may be disposed inside the two opposite ends E of the third portion 121-3. Therefore, a part of the first electrode 124 may be disposed to overlap the light-emitting layer 122, the second semiconductor layer 123, and the second electrode 125. However, the present disclosure is not limited thereto.

[0057] The first electrode 124 may be made of a conductive material, such as a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof. However, the present disclosure is not limited thereto.

[0058] A second electrode 125 is disposed on the second semiconductor layer 123. The second electrode 125 may be disposed on the top surface of the second semiconductor layer 123. In this case, the second semiconductor layer 123 may be a semiconductor layer doped with p-type impurities, and the second electrode 125 may be an anode. The second electrode 125 may be made of a conductive material, such as a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof. However, the present disclosure is not limited thereto.

[0059] An encapsulation layer 126 is disposed on the second semiconductor layer 123. The encapsulation layer 126 may protect the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123. The encapsulation layer may surround at least a part of the first semiconductor layer 121, at least a part of the light-emitting layer 122, at least a part of the second semiconductor layer 123, and at least a part of the second electrode 125. For example, the encapsulation layer 126 may be disposed only in the region disposed above the concave pattern CP. Therefore, the encapsulation layer 126 may be disposed to surround a partial region of the first semiconductor layer 121 disposed on the concave pattern CP, and surround the light-emitting layer 122 and the second semiconductor layer 123. The encapsulation layer 126 may not be adjacent to the first electrode 124 and the partial region of the first semiconductor layer 121 disposed below the concave pattern CP. In addition, the second electrode 125 may be exposed from the encapsulation layer 126 to connect the light-emitting element ED1 to the display panel.

[0060] Meanwhile, the light-emitting element ED1 may include light-emitting elements configured to emit light beams of different colors. For example, the light-emitting element ED1 may include a red light-emitting element, a blue light-emitting element, and a green light-emitting element.

[0061] The red light-emitting element, the green light-emitting element, and the blue light-emitting element may commonly include a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and a packaging layer 126, but have concave patterns CP different in shape and number.

[0062] The spectrum emitted from the light-emitting element ED1 can be adjusted according to the area, angle, and size of the concave pattern CP. Accordingly, the shape and number of the concave pattern CP can be adjusted according to the wavelength of the light emitted from the light-emitting element ED1 so that the light-emitting element ED1 can emit light having a wavelength within a specific range. Accordingly, the shape and number of the concave pattern CP can be changed according to the wavelengths of the light beams emitted from the red light-emitting element, the green light-emitting element, and the blue light-emitting element.

[0063] Figures 2A to 2G is a process diagram for explaining a method of manufacturing a light-emitting element according to an embodiment of the present specification.

[0064] Referring to Figure 2A , the first semiconductor layer 121, the light-emitting layer 122, the second semiconductor layer 123, and the second electrode 125 are disposed on a wafer WA. The light-emitting layer 122 and the second semiconductor layer 123 may each be in a state where a partial region thereof is patterned by mesa etching. In this case, the mesa etching may refer to a process of defining a light-emitting region of the light-emitting element ED1. The mesa etching may refer to the following process: etching the light-emitting layer 122 and the second semiconductor layer 123 disposed in a region corresponding to a non-light-emitting region of the light-emitting element ED1 while keeping the light-emitting layer 122 and the second semiconductor layer 123 only in a region corresponding to a light-emitting region of the light-emitting element ED1 on the wafer WA. In this case, in the mesa etching, a partial region of the first semiconductor layer 121 may also be etched. Accordingly, the thickness of the portion of the first semiconductor layer 121 disposed outside the light-emitting layer 122 and the second semiconductor layer 123 may be smaller than the thickness of the portion of the first semiconductor layer 121 in a region overlapping the light-emitting layer 122 and the second semiconductor layer 123.

[0065] Thereafter, a first cover layer 191 covers the mesa region. The first cover layer 191 may extend from the top surfaces of the second electrode 125 and the second semiconductor layer 123 and cover the second semiconductor layer 123, the side surfaces of the light-emitting layer 122, and a part of the side surface of the first semiconductor layer 121.

[0066] Next, referring to Figure 2B, an etching process is performed. The first cover layer 191 serves as a mask, and the first semiconductor layer 121 is etched in the regions not covered by the first cover layer 191. In this case, the etching process is carried out by wet etching. Therefore, due to the isotropic nature of wet etching, the regions exposed to the first cover layer 191 are etched in all directions without being restricted by the direction. Thus, a concave pattern CP is formed in the first semiconductor layer 121 disposed under the first cover layer 191, and the concave pattern CP can be formed to have an inclined surface or a circular shape. At the same time, the size of the concave pattern CP can be adjusted according to the etching process conditions. That is to say, the concave pattern CP can be formed inside the side surfaces of the second semiconductor layer 123 and the side surfaces of the light-emitting layer 122.

[0067] Next, an isolation process for separating the individual light-emitting elements ED1 from the wafer WA is performed. Refer to Figure 2C , the second cover layer 192 covers a part of the light-emitting layer 122, a part of the second semiconductor layer 123, a part of the second electrode 125, and a part of the first semiconductor layer 121. In this case, the second cover layer 192 covers the concave pattern CP exposed by the etching process. Therefore, the second cover layer 192 serves as a mask, and the first semiconductor layer 121 is etched in the regions covered by the second cover layer 192.

[0068] After that, refer to Figure 2D , the first electrode 124 is formed after the isolation process. After removing the second cover layer 192, the first electrode 124 is formed on the first semiconductor layer 121 and on the top surface of the first semiconductor layer 121 formed by the etching process. The first electrode 124 can be provided to protrude on the first semiconductor layer 121 outside the second semiconductor layer 123 and the light-emitting layer 122. The first electrode 124 can extend from the top surface of the first semiconductor layer 121 and cover the side surface of the first semiconductor layer 121.

[0069] Next, refer to Figure 2E , a third cover layer 193 is formed on the light-emitting element ED1. The third cover layer 193 only covers a partial region of the first semiconductor layer 121. For example, the third cover layer 193 is formed under the second electrode 125, the second semiconductor layer 123, and the light-emitting layer 122. Therefore, the third cover layer 193 only covers the concave pattern CP, the lower region of the concave pattern CP, and the first electrode 124, while the upper part of the first semiconductor layer 121, the second electrode 125, the second semiconductor layer 123, and the light-emitting layer 122 are exposed and not covered by the third cover layer 193.

[0070] Next, refer to Figure 2F, an encapsulation layer 126 is formed on the third cover layer 193. Accordingly, the portions of the upper side of the first semiconductor layer 121, the second electrode 125, the second semiconductor layer 123, and the light-emitting layer 122 that are exposed to the third cover layer 193 are covered by the encapsulation layer 126.

[0071] Next, referring to Figure 2G , the third cover layer 193 is removed. Accordingly, the portions of the upper side of the first semiconductor layer 121, the second electrode 125, the second semiconductor layer 123, and the light-emitting layer 122 that are not covered by the third cover layer 193 remain covered by the encapsulation layer 126. The concave pattern CP of the first semiconductor layer 121, the lower region of the concave pattern CP, and the first electrode 124 that have been covered by the third cover layer 193 are exposed through the encapsulation layer 126.

[0072] In a display device, depending on the shape of the light-emitting element and component tolerances, brightness deviation according to the viewing angle may occur. In the case where a micro light-emitting diode (micro LED) is used as the light-emitting element, the side brightness may be higher than the front brightness. For example, the brightness may increase in the direction of 50 degrees to 70 degrees, and the maximum brightness may occur in the direction of about 60 degrees. Accordingly, the graph of the brightness distribution according to the viewing angle may have an "M" shape, and a non-uniformity (Mura) phenomenon may occur.

[0073] Accordingly, the concave pattern CP is provided on the side surface of the light-emitting element ED1 according to an embodiment of the present specification. Accordingly, among the light beams generated by the light-emitting layer 122 of the light-emitting element ED1, the light beams that enter the concave pattern CP at an angle equal to or smaller than the threshold angle can be extracted to the outside of the light-emitting element ED1. In this case, the propagation direction of the light extracted from the concave pattern CP can be changed by the surface of the concave pattern CP, and the light can propagate along the direction toward the front surface. Accordingly, in the light-emitting element ED1 according to an embodiment of the present specification, the concave pattern CP can be provided on the side surface of the light-emitting element ED1 to improve the light extraction efficiency, and the direction of the optical path can be changed from the direction toward the side surface to the direction toward the front surface to reduce the deviation of the viewing angle.

[0074] In addition, in the light-emitting element ED1 according to an embodiment of the present specification, the first electrode 124 is provided on the first portion 121-1 exposed through the second portion 121-2. Accordingly, the light-emitting element ED1 can be implemented as having a lateral structure, and the bonding metal forming process and the thermocompression process performed to connect a vertical light-emitting element to a display panel may not be included. Accordingly, in the light-emitting element ED1 according to an embodiment of the present specification, since the light-emitting element ED1 can be connected to the display panel without performing the bonding metal forming process and the thermocompression process, process optimization can be achieved.

[0075] In addition, the light-emitting element ED1 according to an embodiment of the present specification may include a concave pattern CP having a shape that changes according to the wavelength of light to be emitted. For example, the shape and number of the concave pattern CP may be adjusted according to the wavelength of light emitted from the light-emitting element ED1, so that the light-emitting element ED1 can emit light having a wavelength within a specific range.

[0076] Hereinafter, the tilt angle of the concave pattern CP will be described with reference to Figures 3A to 4D FIG.

[0077] Figures 3A to 3D are cross-sectional views of light-emitting elements according to comparative and exemplary embodiments of the present specification. Figures 4A to 4D is for explaining Figures 3A to 3D the effects of the light-emitting elements in

[0078] Figures 3B to 3D The various embodiments in Figure 1 relate to the light-emitting element ED1 according to an embodiment of the present specification. Figure 3B In Exemplary Embodiment 1 in Figure 3C the width W and height H of the concave pattern CP are each 1 μm, Figure 3D in Exemplary Embodiment 2 in Figure 3A the width W and height H of the concave pattern CP are each 2 μm, and Figures 3B to 3D in Exemplary Embodiment 3 in

[0079] Figure 4A the width W and height H of the concave pattern CP are each 3 μm. In this case, all the concave patterns CP in Exemplary Embodiments 1 to 3 have an inclination of 73°. Figure 3A The comparative embodiment in Figure 4B differs from the various exemplary embodiments in Figure 3B in that the concave pattern CP is not provided. Figure 4C Figure 3C Figure 4D Figure 3D Figures 4A to 4D Figures 4A to 4D

[0080] Figures 4A to 4D In the graph in Figures 4A to 4D the X-axis indicates the viewing angle.

[0080] With reference to Figures 4A to 4D, in the comparative embodiment and various exemplary embodiments, the brightness in the direction toward the side surface at 50° to 70° is higher than the brightness in the direction toward the front surface, and the maximum brightness is achieved at about 60°.

[0081] According to Figures 4A to 4D The results of the graph in are shown in Table 1 below.

[0082] [Table 1]

[0083] Viewing angle - luminance ratio Increase ratio of central luminance Comparative implementation 36％ 100％ Exemplary implementation 1 21％ 113％ Exemplary implementation 2 13％ 119％ Exemplary implementation 3 9％ 121％

[0084] The viewing angle - brightness ratio refers to the ratio of the maximum brightness measured in the direction toward the side surface to the front - surface brightness in the comparative embodiment and exemplary embodiments 1 to 3.

[0085] The increase ratio of the center brightness refers to the ratio of the front - surface brightness measured in exemplary embodiments 1 to 3 when the brightness at a viewing angle of 0° in the comparative embodiment is 100%.

[0086] Referring to Figure 4A and Table 1, in the comparative embodiment, the viewing angle - brightness ratio is approximately 36%. Next, referring to Figures 4B to 4D and Table 1, the viewing angle - brightness ratio in exemplary embodiment 1 is approximately 21%, the viewing angle - brightness ratio in exemplary embodiment 2 is approximately 13%, and the viewing angle - brightness ratio in exemplary embodiment 3 is approximately 9%. Therefore, it can be determined that, compared with the comparative embodiment without the concave pattern CP, the viewing angle - brightness ratio decreases, and in exemplary embodiments 1 to 3 provided with the concave pattern CP, the change in brightness according to the viewing angle decreases. In addition, it can be determined that the viewing angle - brightness ratio decreases in the order of exemplary embodiment 1, exemplary embodiment 2, and exemplary embodiment 3 in which the size of the concave pattern CP relatively increases.

[0087] In addition, referring to Figures 4B to 4D and Table 1, the increase ratio of the center brightness in exemplary embodiment 1 is approximately 113%, the increase ratio of the center brightness in exemplary embodiment 2 is approximately 119%, and the increase ratio of the center brightness in exemplary embodiment 3 is approximately 121%. Therefore, it can be determined that the increase ratio of the center brightness increases in the order of exemplary embodiment 1, exemplary embodiment 2, and exemplary embodiment 3 in which the size of the concave pattern CP relatively increases.

[0088] Figure 5 is a schematic cross - sectional view of a light - emitting element according to another embodiment of the present specification. Except that a plurality of light extraction patterns P are provided on the concave pattern CP of the light - emitting element ED2, Figure 5 the light - emitting element ED2 in Figures 1 to 2Gis substantially the same as the light-emitting element ED1. Therefore, repeated descriptions will be omitted.

[0089] The light-emitting element ED2 may include a plurality of light extraction patterns P. The plurality of light extraction patterns P are provided on a side surface of the light-emitting element ED2. For example, the plurality of light extraction patterns P are provided along a concave pattern CP of the first semiconductor layer 221, and are also provided on a top surface of a first portion 221-1 of the first semiconductor layer 221 exposed through the concave pattern CP and a bottom surface of a third portion 221-3. Meanwhile, in the light extraction pattern P, the surface roughness of the light-emitting element ED2 may be increased. For example, the surface roughness in the light extraction pattern P may be higher than the roughness of the side surfaces of the first portion 221-1 and the third portion 221-3. Meanwhile, the cross-sectional shape of the plurality of light extraction patterns P is not limited to Figure 5 the cross-sectional shape in.

[0090] In this case, the light extraction pattern P may be formed in a crystal direction. For example, when the angle of the crystal surface of the material constituting the first semiconductor layer 121 is 73°, the light extraction pattern P may have an inclination angle of 73°. However, the present disclosure is not limited thereto.

[0091] Meanwhile, the light-emitting element ED2 may include light-emitting elements configured to emit light beams of different colors. For example, the light-emitting element ED2 may include a red light-emitting element, a blue light-emitting element, and a green light-emitting element.

[0092] The red light-emitting element, the green light-emitting element, and the blue light-emitting element may commonly include a first semiconductor layer 221, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and a packaging layer 126, but have concave patterns CP with different shapes and numbers. In addition, the shape of the light extraction pattern P may also be changed.

[0093] The spectrum emitted from the light-emitting element ED2 may be adjusted according to the area, angle, and size of the concave pattern CP and the light extraction pattern P. Therefore, the shape and number of the concave pattern CP may be adjusted according to the wavelength of the light emitted from the light-emitting element ED2 so that the light-emitting element ED2 can emit light having a wavelength within a specific range. In addition, the angle and surface roughness of the light extraction pattern P may be adjusted according to the wavelength of the light emitted from the light-emitting element ED2 so that the light-emitting element ED2 can emit light having a wavelength within a specific range. Therefore, the shape and number of the concave pattern CP and the light extraction pattern P may be changed according to the wavelengths of the light beams emitted from the red light-emitting element, the green light-emitting element, and the blue light-emitting element.

[0094] The concave pattern CP is provided on the side surface of the light-emitting element ED2 according to another embodiment of the present specification. Therefore, the light-emitting element ED2 according to the embodiment of the present specification can improve the light extraction efficiency, and the direction of the optical path can be changed from the direction toward the side surface to the direction toward the front surface to reduce the deviation of the viewing angle.

[0095] In addition, in the light-emitting element ED2 according to another embodiment of the present specification, since the light-emitting element ED2 can be connected to the display panel without performing the bonding metal forming process and the thermocompression process, process optimization can be achieved.

[0096] A plurality of light extraction patterns P are provided on the concave pattern CP of the light-emitting element ED2 according to another embodiment of the present specification. Therefore, by using the plurality of light extraction patterns P, the roughness of the light-emitting element ED2 can be increased, the light extraction efficiency can be improved, and the front surface brightness can be increased.

[0097] In addition, a plurality of light extraction patterns P are provided on the side surface portion of the light-emitting element ED2 according to another embodiment, so that the light-emitting element ED2 can be stably fixed to the substrate 110. When a plurality of light extraction patterns are formed on the bottom surface of the light-emitting element to reduce the brightness deviation according to the viewing angle, since the flatness of the bottom surface of the light-emitting element is low, it may be difficult to stably fix the light-emitting element to the substrate. Therefore, in the light-emitting element ED2 according to another embodiment of the present specification, a plurality of light extraction patterns P are provided on the side surface portion of the light-emitting element ED2 so that the light-emitting element ED2 can be stably fixed to the substrate 110.

[0098] In addition, the light-emitting element ED2 according to another embodiment may include a concave pattern CP and a light extraction pattern P, and each of the concave pattern CP and the light extraction pattern P has a shape that changes according to the wavelength of the light to be emitted. For example, the shape and number of the concave pattern CP can be adjusted according to the wavelength of the light emitted from the light-emitting element ED2 so that the light-emitting element ED2 can emit light having a wavelength within a specific range. In addition, the angle and surface roughness of the light extraction pattern P can be adjusted according to the wavelength of the light emitted from the light-emitting element ED2 so that the light-emitting element ED2 can emit light having a wavelength within a specific range.

[0099] Figure 6 is a schematic configuration diagram of a display device according to an embodiment of the present specification. For ease of description, Figure 6 only the display panel PN, the gate driving unit GD, the data driving unit DD, and the timing controller TC among the various components of the display device 1000 are shown.

[0100] Refer to Figure 6, the display device 1000 includes: a display panel PN including a plurality of sub-pixels SP; a gate driving unit GD and a data driving unit DD configured to supply various types of signals to the display panel PN; and a timing controller TC configured to control the data driving unit DD and the gate driving unit GD.

[0101] The gate driving unit GD supplies a plurality of scan signals to a plurality of scan lines SL in response to a plurality of gate control signals provided from the timing controller TC. Figure 6 It is shown that a single gate driving unit GD is provided to be spaced apart from one side of the display panel PN. However, the number and arrangement of the gate driving units GD are not limited thereto.

[0102] The data driving unit DD converts the image data input from the timing controller TC into a data voltage by using a reference gamma voltage in response to a plurality of data control signals provided from the timing controller TC. The data driving unit DD may supply the converted data voltage to a plurality of data lines DL.

[0103] The timing controller TC aligns the image data input from the outside and supplies the image data to the data driving unit DD. The timing controller TC may generate gate control signals and data control signals by using the synchronization signals input from the outside (i.e., dot clock signal, data enable signal, and horizontal / vertical synchronization signals). In addition, the timing controller TC may control the gate driving unit GD and the data driving unit DD by supplying the generated gate control signals and data control signals to the gate driving unit GD and the data driving unit DD.

[0104] The display panel PN is configured to display an image to a user and includes a plurality of sub-pixels SP.

[0105] The display panel PN may have a display area AA and a non-display area NA configured to surround the display area AA.

[0106] The display area AA is an area where the display device 1000 displays an image. The display area AA may include a plurality of sub-pixels SP constituting a plurality of pixels, and a circuit configured to operate the plurality of sub-pixels SP. The plurality of sub-pixels SP are the smallest units constituting the display area AA. n sub-pixels SP may constitute a single pixel. A light-emitting element, a thin-film transistor for operating the light-emitting element, etc. may be provided in each of the plurality of sub-pixels SP. The plurality of light-emitting elements may be defined differently according to the type of the display panel PN. For example, in the case where the display panel PN is an inorganic light-emitting display panel, the light-emitting element may be a light-emitting diode (LED) or a micro light-emitting diode (micro LED).

[0107] In a display region AA, a plurality of lines are provided for transmitting various types of signals to a plurality of sub-pixels SP. For example, the plurality of lines may include a plurality of data lines DL for supplying data voltages to the plurality of sub-pixels SP and a plurality of scan lines SL for supplying scan signals to the plurality of sub-pixels SP. The plurality of scan lines SL may extend in one direction in the display region AA and may be connected to the plurality of sub-pixels SP. The plurality of data lines DL may extend in a direction different from the one direction in the display region AA and may be connected to the plurality of sub-pixels SP. Additionally, a low-potential power line, a high-potential power line, etc. may also be provided in the display region AA. However, the present disclosure is not limited thereto.

[0108] A non-display region NA may be defined as a region where an image is not displayed, that is, a region extending from the display region AA. The non-display region NA may include link lines and pad electrodes for transmitting signals to the sub-pixels SP in the display region AA. Alternatively, the non-display region NA may include a driving IC, such as a gate driver IC and a data driver IC.

[0109] However, the non-display region NA may be located on the rear surface of the display panel PN - that is, on the surface where no sub-pixels SP exist. Alternatively, the non-display region NA may not be included. However, the present disclosure is not limited to the configurations shown in the figures.

[0110] Meanwhile, driving units such as a gate driving unit GD, a data driving unit DD, and a timing controller TC may be connected to the display panel PN in various ways. For example, the gate driving unit GD may be installed in the non-display region NA by an in-panel gate (GIP) method or between a plurality of sub-pixels SP in the display region AA by an in-active-region gate (GIA) method. For example, the data driving unit DD and the timing controller TC may be formed on separate flexible films and printed circuit boards PCB. The data driving unit DD and the timing controller TC may be electrically connected to the display panel PN by bonding the flexible films and the printed circuit boards PCB to pad electrodes formed in the non-display region NA of the display panel PN.

[0111] In the case where the gate driving unit GD is installed by the GIP method and the data driving unit DD and the timing controller TC transmit signals to the display panel PN through the pad electrodes in the non-display region NA, it is necessary to ensure that the area of the non-display region NA is at a predetermined level or higher to set the gate driving unit GD and the pad electrodes, which may increase the bezel.

[0112] Alternatively, when the gate driving unit GD is installed in the display area AA by the GIA method, and side lines are formed to connect signal lines on the front surface of the display panel PN to pad electrodes on the rear surface of the display panel PN to bond the flexible film and the printed circuit board to the rear surface of the display panel PN, the non-display area NA on the front surface of the display panel PN can be minimized. That is, when the gate driving unit GD, the data driving unit DD, and the timing controller TC are connected to the display panel PN by the above-mentioned method, a zero bezel with substantially no bezel can be achieved.

[0113] Figure 7 is a cross-sectional view of a pixel region of a display device according to an embodiment of the present specification.

[0114] Referring to Figure 7 , the display device 1000 includes a substrate 110, a light blocking layer LS, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113, a first passivation layer 114, a first planarization layer 115, a second passivation layer 116, a third passivation layer 117, a second planarization layer 118, a third planarization layer 119, an assembly electrode 160, a connection electrode 150, a light emitting element ED1, and a storage capacitor Cst.

[0115] Referring to Figure 7 , the display device 1000 includes a substrate 110. The substrate 110 may be an insulating substrate configured to support components disposed on the upper side of the display device 1000. A plurality of pixels SP may be formed on the substrate 110 such that an image can be displayed. For example, the substrate 110 may be made of glass, resin, etc. Additionally, the substrate 110 may include a polymer or plastic. In some embodiments, the substrate 110 may be made of a flexible plastic material.

[0116] A plurality of sub-pixels SP may be arranged in a plurality of rows and a plurality of columns on the substrate 110. The plurality of sub-pixels SP may each include a light emitting element ED1 and a pixel circuit, and emit light independently.

[0117] The plurality of sub-pixels SP may include a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light beams of different colors. For example, the first sub-pixel may be a red sub-pixel, the second sub-pixel may be a green sub-pixel, and the third sub-pixel may be a blue sub-pixel. However, the present disclosure is not limited thereto.

[0118] A first light-emitting element may be provided on the first sub-pixel, a second light-emitting element may be provided on the second sub-pixel, and a third light-emitting element may be provided on the third sub-pixel. For example, the first light-emitting element may be a red light-emitting element, the second light-emitting element may be a green light-emitting element, and the third light-emitting element may be a blue light-emitting element. However, the present disclosure is not limited thereto.

[0119] A plurality of lines for transmitting various types of signals to the plurality of sub-pixels SP are provided on the substrate 110. For example, a plurality of data lines DL, a plurality of high-potential power lines VDD, and a plurality of low-potential power lines may be provided on the substrate 110 and extend in the column direction. For example, a plurality of light-emission control signal lines, a plurality of auxiliary high-potential power lines, a plurality of auxiliary low-potential power lines, and a plurality of scan lines may be provided on the substrate 110 and extend in the row direction. In addition, the high-potential power line VDD extending in the column direction and the auxiliary high-potential power line extending in the row direction may be electrically connected to each other through a contact hole. In this case, the light-emission control signal line transmits a light-emission control signal to the pixel circuits of the plurality of sub-pixels SP to control the light-emission timing of the plurality of sub-pixels SP.

[0120] A pixel circuit for operating the light-emitting element ED1 is provided in each of the plurality of sub-pixels SP on the substrate 110. The pixel circuit may include a plurality of thin-film transistors and a plurality of capacitors. For ease of description, Figure 7 only the driving transistor DT and the storage capacitor Cst among the components of the pixel circuit are shown. However, the pixel circuit may further include a switching transistor, a sensing transistor, a light-emission control transistor, etc. However, the present disclosure is not limited thereto.

[0121] A light-blocking layer LS is provided on each of the plurality of sub-pixels SP, and the light-blocking layer LS is provided on the substrate 110. The light-blocking layer LS may block the light entering the transistor from the lower side of the substrate 110 and minimize the leakage current. For example, the light-blocking layer LS may block the light entering the active layer ACT.

[0122] A first capacitor electrode SC1 is provided on each of the plurality of sub-pixels SP, and the first capacitor electrode SC1 is provided on the substrate 110. The first capacitor electrode SC1 together with other capacitor electrodes may constitute the storage capacitor Cst. The first capacitor electrode SC1 may be integrated with the light-blocking layer LS.

[0123] A buffer layer 111 is disposed on the light blocking layer LS and the first capacitor electrode SC1. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. For example, the buffer layer 111 can be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto. However, depending on the type of the substrate 110 or the type of the transistor, the buffer layer 111 may not be included. However, the present disclosure is not limited thereto.

[0124] A driving transistor DT is disposed on the buffer layer 111 in each of the plurality of sub-pixels SP. The driving transistor DT is a transistor that supplies a driving current to the light emitting element ED1. The driving transistor DT can be turned on and control the driving current flowing to the light emitting element ED1.

[0125] The driving transistor DT includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0126] The active layer ACT is disposed on the buffer layer 111. The active layer ACT can be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon. However, the present disclosure is not limited thereto.

[0127] A gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer for insulating the active layer ACT and the gate electrode GE. The gate insulating layer 112 can be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto. Meanwhile, Figure 7 It is shown that the gate insulating layer 112 is only disposed in the region overlapping with the gate electrode GE and the second capacitor electrode SC2. However, the present disclosure is not limited thereto.

[0128] The gate electrode GE is disposed on the gate insulating layer 112. The gate electrode GE can be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.

[0129] A first interlayer insulating layer 113 is disposed on the gate electrode GE. Contact holes are formed in the first interlayer insulating layer 113, and the source electrode SE and the drain electrode DE are connected to the active layer ACT through the contact holes. The first interlayer insulating layer 113 is an insulating layer for protecting the components disposed below the first interlayer insulating layer 113. The first interlayer insulating layer 113 can be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.

[0130] The source electrode SE and the drain electrode DE are disposed on the first interlayer insulating layer 113 and are electrically connected to the active layer ACT. The drain electrode DE can be electrically connected to the active layer ACT and the high-potential power line, and the source electrode SE can be electrically connected to the active layer ACT and the light-emitting element ED1. The source electrode SE and the drain electrode DE can each be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.

[0131] A second capacitor electrode SC2 is disposed on the gate insulating layer 112. The second capacitor electrode SC2 can be one of the electrodes constituting the storage capacitor Cst. The second capacitor electrode SC2 can be disposed to overlap the first capacitor electrode SC1. Although not shown in the figure, the second capacitor electrode SC2 can be integrated with the gate electrode GE of the driving transistor DT and electrically connected to the gate electrode GE. However, the present disclosure is not limited thereto. The first capacitor electrode SC1 and the second capacitor electrode SC2 can be disposed to be spaced apart from each other, with the buffer layer 111 and the gate insulating layer 112 inserted between the first capacitor electrode SC1 and the second capacitor electrode SC2.

[0132] A third capacitor electrode SC3 is disposed on the first interlayer insulating layer 113. The third capacitor electrode SC3 can be an electrode constituting the storage capacitor Cst. The third capacitor electrode SC3 can be disposed to overlap the first capacitor electrode SC1 and the second capacitor electrode SC2. The third capacitor electrode SC3 can be integrated with the source electrode SE of the driving transistor DT and electrically connected to the source electrode SE. In addition, the source electrode SE can also be electrically connected to the first capacitor electrode SC1 through a contact hole formed in the interlayer insulating layer 113 and the buffer layer 111. Therefore, the first capacitor electrode SC1 and the third capacitor electrode SC3 can be electrically connected to the source electrode SE of the driving transistor DT.

[0133] The storage capacitor Cst can store the potential difference between the gate electrode GE and the source electrode SE of the driving transistor DT while the light-emitting element ED1 emits light, so that a constant current can be supplied to the light-emitting element ED1. The storage capacitor Cst includes a first capacitor electrode SC1 formed on the substrate 110 and connected to the source electrode SE, a second capacitor electrode SC2 formed on the buffer layer 111 and the gate insulating layer 112, and a third capacitor electrode SC3 formed on the first interlayer insulating layer 113 and connected to the source electrode SE. The storage capacitor Cst can store the voltage between the gate electrode GE and the source electrode SE of the driving transistor DT.

[0134] A first passivation layer 114 is provided over the driving transistor DT and the storage capacitor Cst. The first passivation layer 114 may be an insulating layer for protecting components disposed below the first passivation layer 114. The first passivation layer 114 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.

[0135] A first planarization layer 115 is provided over the first passivation layer 114. The first planarization layer 115 may planarize the upper portion of the substrate 110 on which the driving transistor DT and the storage capacitor Cst are disposed. The first planarization layer 115 may be configured as a single layer or multiple layers and may be made of, for example, photoresist or an acrylic-based organic material. However, the present disclosure is not limited thereto.

[0136] A second passivation layer 116 is provided over the first planarization layer 115. The second passivation layer 116 may be an insulating layer for protecting components disposed below the second passivation layer 116. The second passivation layer 116 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.

[0137] A connection electrode 150 and a plurality of assembly electrodes 160 are provided over the second passivation layer 116.

[0138] The connection electrode 150 is an electrode that electrically connects the driving transistor DT and the second connection electrode CE2. The connection electrode 150 may be electrically connected to the source electrode SE and the third capacitor electrode SC3 through contact holes formed in the second passivation layer 116, the first planarization layer 115, and the first passivation layer 114.

[0139] The connection electrode 150 may have a multi-layer structure including a first connection layer 150a and a second connection layer 150b. The first connection layer 150a is provided over the second passivation layer 116, and the second connection layer 150b is provided to cover the first connection layer 150a. The second connection layer 150b may be provided to surround both the top surface and the side surface of the first connection layer 150a.

[0140] The second connection layer 150b may be made of a material more corrosion-resistant than the material of the first connection layer 150a. Thus, during the process of manufacturing the display device 1000, short-circuit defects caused by migration between lines adjacent to the first connection layer 150a can be minimized. For example, the first connection layer 150a may be made of a conductive material such as copper (Cu) and chromium (Cr). The second connection layer 150b may be made of molybdenum (Mo) and molybdenum titanium (MoTi). However, the present disclosure is not limited thereto.

[0141] A plurality of assembly electrodes 160 are provided over the second passivation layer 116.

[0142] The assembled electrode 160 includes a first assembled electrode 162 and a second assembled electrode 163.

[0143] A plurality of first assembled electrodes 162 and a plurality of second assembled electrodes 163 may extend in the column direction in a plurality of sub-pixels SP and may be arranged to be spaced apart from each other at a predetermined interval.

[0144] The first assembled electrode 162 and the second assembled electrode 163 may be arranged to overlap with the light-emitting element ED1. First, the first assembled electrode 162 may be arranged in a region corresponding to one side of the light-emitting element ED1. In the assembled electrode 160, the first assembled electrode 162 may be arranged in a region overlapping with the low-potential power line and may be electrically connected to the low-potential power line. The low-potential power line is a line for transmitting a low-potential power voltage to the light-emitting element ED1. The low-potential power line may extend in the column direction in each of the plurality of sub-pixels SP. For example, the low-potential power line may be arranged in each of the plurality of sub-pixels SP.

[0145] The second assembled electrode 163 may be spaced apart from the first assembled electrode 162 and arranged in a region corresponding to the other side of the light-emitting element ED1.

[0146] Each of the plurality of assembled electrodes 160 includes a conductive layer 162a and 163a provided on the second passivation layer 116, and a coating layer 162b and 163b provided on the conductive layer 162a and 163a and configured to cover all top surfaces and side surfaces of the conductive layer 162a and 163a.

[0147] The first assembled electrode 162 includes a first conductive layer 162a and a first coating layer 162b, and the second assembled electrode 163 includes a second conductive layer 163a and a second coating layer 163b.

[0148] The first conductive layer 162a and the second conductive layer 163a may not overlap with the light-emitting element ED1. That is, the ends of the first conductive layer 162a and the ends of the second conductive layer 163a may be arranged outside the light-emitting element ED1.

[0149] The first coating layer 162b of the first assembled electrode 162 may be arranged to cover the top surface and side surface of the first conductive layer 162a. In this case, the first coating layer 162b and the second coating layer 163b may extend from the ends of the first conductive layer 162a and the ends of the second conductive layer 163a toward the central portion of the light-emitting element ED1 and overlap with the light-emitting element ED1.

[0150] The first conductive layer 162a and the second conductive layer 163a can be formed by the same process as the first connection layer 150a of the connection electrode 150 and made of the same material as the first connection layer 150a of the connection electrode 150. For example, the first conductive layer 162a and the second conductive layer 163a can be made of conductive materials such as copper (Cu) and chromium (Cr). In addition, the first coating layer 162b and the second coating layer 163b can be formed by the same process as the second connection layer 150b of the connection electrode 150 and made of the same material as the second connection layer 150b of the connection electrode 150. For example, each of the first coating layer 162b and the second coating layer 163b can be made of a material more corrosion-resistant than the materials of the first conductive layer 162a and the second conductive layer 163b. For example, each of the first coating layer 162b and the second coating layer 163b can be made of molybdenum (Mo), molybdenum titanium (MoTi), etc. However, the present disclosure is not limited thereto.

[0151] A third passivation layer 117 is provided on the connection electrode 150 and the assembly electrode 160. The third passivation layer 117 can be an insulating layer for protecting the components disposed below the third passivation layer 117. The third passivation layer 117 can be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.

[0152] A plurality of light-emitting elements ED1 are provided on the third passivation layer 117.

[0153] Portions of the third passivation layer 117 can be opened in regions adjacent to the plurality of light-emitting elements ED1. For example, regions of the third passivation layer 117 adjacent to one side surface of each of the two opposite surfaces of each of the plurality of light-emitting elements ED1 can be opened. For example, the third passivation layer 117 can expose a part of the top surface of the first assembly electrode 162 in a region adjacent to one side surface of each of the plurality of light-emitting elements ED1.

[0154] One or more light-emitting elements ED1 are provided on the third passivation layer 117 in one sub-pixel SP. The light-emitting element ED1 is an element that emits light by receiving current. The light-emitting element ED1 can include light-emitting elements ED1 configured to emit red light, green light, blue light, etc. The light-emitting element ED1 can use a combination of red light, green light, blue light, etc. to achieve light having various colors including white. Additionally, a light beam having various colors can be achieved by using a light-emitting element ED1 that emits light having a specific color and a light conversion member that converts the light from the light-emitting element ED1 into light having a color different from the specific color.

[0155] The light-emitting element ED1 can emit light by receiving a driving current from the driving transistor DT. The size of the light-emitting element ED1 can vary according to the type of the light-emitting element ED1. In this case, since the type of the light-emitting element ED1 means the type of light to be emitted, the size of the light-emitting element ED1 can vary depending on whether the light-emitting element ED1 is a red light-emitting element, a green light-emitting element, or a blue light-emitting element. The light-emitting element can exhibit different types of luminous efficiency according to the color of the light to be emitted. Therefore, the size of the light-emitting element ED1 can be determined according to the efficiency of the light-emitting element ED1 so that the light-emitting elements emitting light beams of different colors emit light beams of the same brightness.

[0156] For example, in the case where the luminous efficiency of a light-emitting element emitting light of a specific color is relatively low, the light-emitting element can be formed to have a larger size than other light-emitting elements to emit light of the same brightness as other light-emitting elements. However, the present disclosure is not limited thereto.

[0157] Referring to Figure 7 , the light-emitting element ED1 includes a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and a encapsulation layer 126. Hereinafter, a description will be made on the assumption that a plurality of light-emitting elements ED1 have a lateral structure. However, the type of the plurality of light-emitting elements ED1 is not limited thereto. In addition, in Figure 7 , the plurality of light-emitting elements ED1 are described as adopting the light-emitting element ED1 described with reference to Figures 1 to 2G . However, the present disclosure is not limited thereto. All the light-emitting elements ED2 according to another embodiment of the present specification described with reference to Figure 5 can be applied. Since the plurality of light-emitting elements ED1 have been described in detail with reference to Figures 1 to 2G , a repeated description will be omitted.

[0158] A bonding layer AD can be provided between the plurality of light-emitting elements ED1, the third passivation layer 117, and the assembly electrode 160. The bonding layer AD can be an organic film that temporarily fixes the light-emitting element ED1 during the self-assembly process of the light-emitting element ED1. When an organic film is formed to cover the light-emitting element ED1 during the manufacturing process of the display device 1000, a part of the organic film fills the space between the light-emitting element ED1, the third passivation layer 117, and the assembly electrode 160, so that the organic film can temporarily fix the light-emitting element ED1 to the third passivation layer 117 and the assembly electrode 160. Thereafter, even if the organic film is removed, the part of the organic film that penetrates into the lower part of the light-emitting element ED1 can remain without being removed, thereby defining the bonding layer. The bonding layer AD can be made of a photoresist or an organic material such as an acrylic-based organic material. However, the present disclosure is not limited thereto.

[0159] A second planarization layer 118 is disposed on the third passivation layer 117. The second planarization layer 118 may be configured as a single layer or multiple layers, and is made of, for example, photoresist or acrylic-based organic material. However, the present disclosure is not limited thereto.

[0160] In addition, the second planarization layer 118 may be disposed to surround a part of the side surface portion of each of the plurality of light-emitting elements ED1. For example, the second planarization layer 118 may be disposed to extend from the bottom surface of the first semiconductor layer 121 of each of the plurality of light-emitting elements ED1 on the third passivation layer 117 and the assembly electrode 160, surrounding the lower side surface of the first semiconductor layer 121. In this case, the bottom surface of the second planarization layer 118 may be disposed below the top surface of the first electrode 124 of each of the plurality of light-emitting elements ED1. However, the present disclosure is not limited thereto.

[0161] A first connection electrode CE1 is disposed on the second planarization layer 118. The first connection electrode CE1 may be disposed on the side surface of the light-emitting element ED1 and electrically connect the light-emitting element ED1 and the assembly electrode 160. The first connection electrode CE1 may be disposed in a region overlapping with the first assembly electrode 162 and surround at least a part of the first semiconductor layer 121 and at least a part of the first electrode 124 of the light-emitting element ED1. The first connection electrode CE1 may be disposed to overlap with a part of the concave pattern CP of the light-emitting element ED1 and connect to the first electrode 124 of the light-emitting element ED1.

[0162] In this case, the first connection electrode CE1 may be electrically connected to the first assembly electrode 162 exposed through the third passivation layer 117 in the region where the third passivation layer 117 is opened. In addition, the first connection electrode CE1 may be disposed on the first electrode 124 of the first light-emitting element ED1 and extend to the upper side of the second planarization layer 118.

[0163] Meanwhile, the first electrode 124 of the first light-emitting element ED1 may be electrically connected to the first assembly electrode 162 without being connected to the second assembly electrode 163, such that the first electrode 124 of the first light-emitting element ED1 may be in a state of being directly insulated from the second assembly electrode 163. However, the present disclosure is not limited thereto. For example, Figure 7 It is shown that the first connection electrode CE1 is not disposed on the other side surface of the light-emitting element ED1. However, the present disclosure is not limited thereto. The first connection electrode CE1 may be disposed to surround the side surface of the light-emitting element ED1. Therefore, the first connection electrode CE1 may be electrically connected to both the first assembly electrode 162 and the second assembly electrode 163. However, the present disclosure is not limited thereto.

[0164] A third planarization layer 119 is provided on the light-emitting element ED1 and the first connection electrode CE1. The third planarization layer 119 can planarize the upper portion of the substrate 110 on which the light-emitting element ED1 is provided. The third planarization layer 119 can fix the light-emitting element ED1 to the substrate 110 together with the bonding layer AD.

[0165] Therefore, the third planarization layer 119 can be provided on one side surface of the light-emitting element ED1 and adjacent to the first connection electrode CE1, and the third planarization layer 119 can be provided on the other side surface of the light-emitting element ED1 and adjacent to the other side surface of the light-emitting element. Meanwhile, the concave pattern CP of the light-emitting element ED1 can be filled with the third planarization layer 119. However, the present disclosure is not limited thereto.

[0166] Meanwhile, the drawings show that the third planarization layer 119 is a single layer. However, the present disclosure is not limited thereto. The third planarization layer 119 can be configured as a single layer or multiple layers, and is made of, for example, a photoresist or an acrylic-based organic material. However, the present disclosure is not limited thereto.

[0167] A second connection electrode CE2 is provided on the third planarization layer 119.

[0168] The second connection electrode CE2 is an electrode that electrically connects the plurality of light-emitting elements ED1 and the connection electrode 150. Referring to Figure 7 , the second connection electrode CE2 can be electrically connected to the connection electrode 150 and the driving transistor DT through contact holes formed in the second planarization layer 118.

[0169] The second connection electrode CE2 can be made of a conductive material such as a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, the present disclosure is not limited thereto.

[0170] Hereinafter, a method of manufacturing the display device 1000 according to an embodiment of the present specification will be described with reference to Figure 8A and Figure 8B .

[0171] Figure 8A and Figure 8B are cross-sectional views for explaining the process of manufacturing the display device according to an embodiment of the present specification.

[0172] Referring to Figure 8A , the light-emitting element ED1 is loaded into a chamber CB filled with a fluid WT. The fluid WT can include water or the like, and the chamber CB filled with the fluid WT can have a shape that is open at its upper side.

[0173] Next, the mother substrate 10 can be positioned on the chamber CB filled with the light-emitting elements ED1. The mother substrate 10 is a substrate including a plurality of substrates 110 constituting the display device 1000, and the mother substrate 10 can then be cut and divided into a plurality of substrates 110. In order to self-assemble the plurality of light-emitting elements ED1, the mother substrate 10 having an organic layer OL additionally formed on the plurality of low-potential power lines and the third passivation layer 117 can be used.

[0174] Specifically, referring to Figure 8B , a buffer layer 111, a first interlayer insulating layer 113, a first passivation layer 114, a first planarization layer 115, and a second passivation layer 116 are sequentially formed on the substrate together with the plurality of lines and pixel circuits, and an assembly electrode 160 is formed on the second passivation layer 116.

[0175] After the display device 1000 is completely manufactured, the assembly electrode 160 can be used as a pair of low-potential power lines. During the process of manufacturing the display device 1000, different voltages can be applied to two adjacent assembly electrodes 160. After the process of manufacturing the display device 1000 is completed, the same low-potential power voltage can be applied to two adjacent assembly electrodes 160.

[0176] The assembly electrode 160 includes a first assembly electrode 162 and a second assembly electrode 163.

[0177] The first assembly electrode 162 is disposed on the second passivation layer 116. The first assembly electrode 162 includes a first conductive layer 162a and a first coating layer 162b configured to cover the first conductive layer 162a.

[0178] The second assembly electrode 163 is disposed on the second passivation layer 116. The second assembly electrode 163 includes a second conductive layer 163a and a second coating layer 163b configured to cover the second conductive layer 163a.

[0179] Next, a third passivation layer 117 is formed on the assembly electrode 160, and an organic layer OL having an opening portion OLH is formed on the third passivation layer 117. The opening portion OLH of the organic layer OL can correspond to the region where the light-emitting elements ED1 are self-assembled. The opening portion OLH of the organic layer OL can overlap with the assembly electrode 160. The organic layer OL is removed after the light-emitting elements ED1 are self-assembled, and when the manufacturing process is completed, the organic layer OL does not exist in the display device 1000.

[0180] Therefore, it can be formed to Figure 8BA plurality of light-emitting elements ED1 of the organic layer OL shown and the substrate 110 are loaded into a chamber CB filled with a fluid WT, and an electric field can be formed by applying an alternating voltage to the assembly electrode 160. Accordingly, an electric field can be formed between the first assembly electrode 162 and the second assembly electrode 163.

[0181] The light-emitting element ED1 can have a polarity by being polarized through the mediation of the electric field. In addition, the polarized light-emitting element ED1 can be fixed or moved in a specific direction by dielectrophoresis (DEP), that is, an electric field. Accordingly, dielectrophoresis can be used to self-assemble a plurality of light-emitting elements ED1 onto the assembly electrode 160.

[0182] Finally, when the light-emitting elements ED1 are completely self-assembled, the organic layer OL is removed, and other components such as a bonding layer AD, a first connection electrode CE1, a second connection electrode CE2, a second planarization layer 118, and a third planarization layer 119 are formed, so that the process of manufacturing the display device 1000 can be completed.

[0183] Figure 9 is a cross-sectional view of a pixel region of a display device according to another embodiment of the present specification.

[0184] Referring to Figure 9 , in each of a plurality of sub-pixels SP of a display device 1100 according to another embodiment of the present specification, a substrate 110, a buffer layer 111, a gate insulating layer 1112, a first interlayer insulating layer 1113, a second interlayer insulating layer 1114, a first planarization layer 1115, a bonding layer AD, a second planarization layer 1118, a third planarization layer 1119, a driving transistor DT, a light-emitting element ED1, a plurality of reflection electrodes RE, a plurality of connection electrodes CE, a light-blocking layer LS, and an auxiliary electrode LE are provided.

[0185] A light-blocking layer LS and a buffer layer 111 are provided on the substrate 110 in each of the plurality of sub-pixels SP, and a driving transistor DT is provided on the buffer layer 111. The driving transistor DT includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0186] The active layer ACT is provided on the buffer layer 111. The active layer ACT can be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon. However, the present disclosure is not limited thereto.

[0187] A gate insulating layer 1112 is provided on the active layer ACT. Figure 9 It shows that the gate insulating layer 1112 is provided on the front surface of the substrate 110. However, the present disclosure is not limited thereto. The gate insulating layer 1112 can be provided to overlap only with the gate electrode GE.

[0188] A gate electrode GE is provided on the gate insulating layer 1112.

[0189] A first interlayer insulating layer 1113 and a second interlayer insulating layer 1114 are provided on the gate electrode GE. Contact holes are formed in the first interlayer insulating layer 1113 and the second interlayer insulating layer 1114, and the active electrode SE and the drain electrode DE are connected to the active layer ACT through the contact holes.

[0190] A source electrode SE and a drain electrode DE are provided on the second interlayer insulating layer 1114, and the source electrode SE and the drain electrode DE are electrically connected to the active layer ACT.

[0191] Meanwhile, in the present specification, a configuration has been described in which the first interlayer insulating layer 1113 and the second interlayer insulating layer 1114 (i.e., a plurality of insulating layers) are provided between the gate electrode GE, the source electrode SE, and the drain electrode DE. However, a single insulating layer may be provided between the gate electrode GE, the source electrode SE, and the drain electrode DE. However, the present disclosure is not limited thereto.

[0192] In addition, as Figure 9 shown, in the case where a plurality of insulating layers such as the first interlayer insulating layer 1113 and the second interlayer insulating layer 1114 are provided between the gate electrode GE, the source electrode SE, and the drain electrode DE, an electrode may be additionally formed between the first interlayer insulating layer 1113 and the second interlayer insulating layer 1114. The additionally formed electrode may define a capacitor together with other components provided on the lower part of the first interlayer insulating layer 1113 or the upper part of the second interlayer insulating layer 1114.

[0193] An auxiliary electrode LE is provided on the gate insulating layer 1112. The auxiliary electrode LE is an electrode that electrically connects the light blocking layer LS provided below the buffer layer 111 to any one of the source electrode SE and the drain electrode DE on the second interlayer insulating layer 114. For example, the light blocking layer LS may be electrically connected to any one of the source electrode SE or the drain electrode DE through the auxiliary electrode LE so as not to operate as a floating gate, thereby minimizing the change in the threshold voltage of the driving transistor DT caused by the floating light blocking layer LS. In the drawings, the light blocking layer LS is shown connected to the drain electrode DE. However, the light blocking layer LS may be connected to the source electrode SE. However, the present disclosure is not limited thereto.

[0194] A power line VDD is provided on the second interlayer insulating layer 1114. The power line VDD may be electrically connected to the light emitting element ED1 together with the driving transistor DT and enable the light emitting element ED1 to emit light. The power line VDD may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.

[0195] A first planarization layer 1115 is provided on the driving transistor DT and the power line VDD. The first planarization layer 1115 can planarize the upper portion of the substrate 110 where the driving transistor DT is provided.

[0196] A plurality of reflective electrodes RE spaced apart from each other are provided on the first planarization layer 1115. The plurality of reflective electrodes RE can be used to electrically connect the light-emitting element ED1 to the power line VDD and the driving transistor DT, and can serve as a reflector for reflecting the light emitted from the light-emitting element ED1 to the upper portion of the light-emitting element ED1. The plurality of reflective electrodes RE can each be made of a conductive material having excellent reflection performance, and can reflect the light emitted from the light-emitting element ED1 toward the upper portion of the light-emitting element ED1. For example, the plurality of reflective electrodes RE can be formed by using an opaque conductive layer made of silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), or an alloy thereof together with a transparent conductive layer made of indium tin oxide (ITO). However, the structure of the reflector RF is not limited thereto.

[0197] The plurality of reflective electrodes RE include a first reflective electrode RE1 and a second reflective electrode RE2. The first reflective electrode RE1 can electrically connect the driving transistor DT and the light-emitting element ED1. The first reflective electrode RE1 can be connected to the source electrode SE or the drain electrode DE of the driving transistor DT through a contact hole CH1 formed in the first planarization layer 1115. In addition, the first reflective electrode RE1 can be electrically connected to the first electrode 124 and the first semiconductor layer 121 of the light-emitting element ED1 through a first connection electrode CE1 to be described below.

[0198] The second reflective electrode RE2 can electrically connect the power line VDD and the light-emitting element ED1. The second reflective electrode RE2 can be connected to the power line VDD through a contact hole CH2 formed in the first planarization layer 1115, and can be electrically connected to the second electrode 125 and the second semiconductor layer 123 of the light-emitting element ED1 through a second connection electrode CE2 to be described below.

[0199] A bonding layer AD is provided on the plurality of reflective electrodes RE. A third contact hole CH3 is provided in the bonding layer AD, and the first connection electrode CE1 is connected to the first reflective electrode RE1 through the third contact hole CH3. A fourth contact hole CH4 is provided in the bonding layer AD, and the second connection electrode CE2 is connected to the second reflective electrode RE2 through the fourth contact hole CH4. The front surface of the substrate 110 can be coated with the bonding layer AD, and the bonding layer AD can fix the light-emitting element ED1 provided on the bonding layer AD.

[0200] A plurality of light-emitting elements ED1 are provided on the bonding layer AD in each of the plurality of sub-pixels SP.

[0201] Reference Figure 9 , the light-emitting element ED1 includes a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and a packaging layer 126. Hereinafter, a description will be made on the assumption that a plurality of light-emitting elements ED1 have a lateral structure. However, the type of the plurality of light-emitting elements ED1 is not limited thereto. In addition, in Figure 9 , a plurality of light-emitting elements ED1 are described as adopting the light-emitting element ED1 described with reference to Figures 1 to 2G . However, the present disclosure is not limited thereto. All light-emitting elements ED2 according to another embodiment of the present specification described with reference to Figure 5 can be applied. Since the light-emitting element ED1 has been described in detail with reference to Figures 1 to 2G , a repeated description will be omitted.

[0202] Meanwhile, the light-emitting elements ED1 provided in different sub-pixels SP may have different shapes. For example, in the case where a first light-emitting element is provided in a first sub-pixel, a second light-emitting element is provided in a second sub-pixel, and a third light-emitting element is provided in a third sub-pixel, the first light-emitting element, the second light-emitting element, and the third light-emitting element may have different shapes.

[0203] For example, the planar shape of the first semiconductor layer 121 of the first light-emitting element may be circular. The planar shape of the first semiconductor layer 121 of the second light-emitting element may be oval. The planar shape of the first semiconductor layer 121 of the third light-emitting element may be oval. In this case, the ratio between the major axis and the minor axis of the third light-emitting element may be different from the ratio between the major axis and the minor axis of the second light-emitting element. The major axis of the third light-emitting element may be longer than the major axis of the second light-emitting element, and the minor axis of the third light-emitting element may be shorter than the minor axis of the second light-emitting element. However, the present disclosure is not limited thereto.

[0204] In a display device 1100 according to another embodiment of the present specification, the first light-emitting element is configured as a circular light-emitting element, the second light-emitting element is configured as a first oval light-emitting element, and the third light-emitting element is configured as a second oval light-emitting element having a planar shape different from that of the second light-emitting element, so that a plurality of light-emitting elements ED1 can be distinguished. For example, during the process of self-assembling the light-emitting elements ED1, a plurality of light-emitting elements ED1 may be formed in different shapes so that a plurality of light-emitting elements ED1 can be self-assembled at positions corresponding to a plurality of sub-pixels SP respectively. However, the shapes of the plurality of light-emitting elements ED1 are exemplary, and the present disclosure is not limited thereto.

[0205] A second planarization layer 1118 and a third planarization layer 1119 are provided on the bonding layer AD. The second planarization layer 1118 may partially overlap the side surfaces of the plurality of light-emitting elements ED1 and may fix and protect the plurality of light-emitting elements ED1.

[0206] In addition, a first connection electrode CE1 is provided on the second planarization layer 1118. The first connection electrode CE1 may be connected to the first reflective electrode RE1 through a third contact hole CH3 formed in the second planarization layer 1118 and the bonding layer AD. Accordingly, the first connection electrode CE1 may be electrically connected to either the source electrode SE or the drain electrode DE of the driving transistor DT through the first reflective electrode RE1. In addition, the first connection electrode CE1 may be connected to the first electrode 124 of each of the plurality of light-emitting elements ED1.

[0207] The first connection electrode CE1 may be arranged to surround the side surface of each of the plurality of light-emitting elements ED1.

[0208] The third planarization layer 1119 is provided on the first connection electrode CE1 and the plurality of light-emitting elements ED1. The concave pattern CP of the light-emitting element ED1 may be filled with the third planarization layer 1119. However, the present disclosure is not limited thereto.

[0209] A second connection electrode CE2 is provided on the third planarization layer 1119. The second connection electrode CE2 is an electrode that electrically connects the light-emitting element ED1 and the power line VDD. The second connection electrode CE2 may be connected to the second reflective electrode RE2 through a fourth contact hole CH4 formed in the third planarization layer 1119, the second planarization layer 1118, and the bonding layer AD. Accordingly, the second connection electrode CE2 may be electrically connected to the power line VDD through the second reflective electrode RE2. In addition, the second connection electrode CE2 may be connected to the second electrode 125 of each of the plurality of light-emitting elements ED1. Accordingly, the second connection electrode CE2 may electrically connect the power line VDD to the second electrode 125 of each of the plurality of light-emitting elements ED1 and the second semiconductor layer 123.

[0210] Hereinafter, reference will be made to Figures 10A to 10F a method of manufacturing a display device 1100 according to another embodiment of the present specification will be described.

[0211] Figures 10A to 10F is a process diagram for explaining a method of manufacturing a display device according to another embodiment of the present specification. Figure 10A and Figure 10B are views for explaining a process of self-assembling the light-emitting element ED1 onto the assembly substrate 2000. Figure 10C is a view for explaining a process of transferring the light-emitting element ED1 on the assembly substrate 2000 to the donor 3000.Figure 10D And Figure 10E is a view for explaining the process of transferring the light-emitting element ED1 on the donor 3000 to the display panel PN. Figure 10F is a cross-sectional view of the display device 1100 for explaining the process of forming the first connection electrode CE1 and the second connection electrode CE2.

[0212] Referring to Figure 10A , a plurality of light-emitting elements ED1 are self-assembled onto the assembly substrate 2000.

[0213] First, a plurality of light-emitting elements ED1 grown on a wafer are loaded into a chamber CB filled with a fluid WT. The fluid WT may include water or the like, and the chamber CB filled with the fluid WT may have a shape that is open at its upper side.

[0214] Next, the assembly substrate 2000 can be positioned on the chamber CB filled with the light-emitting elements ED1. The assembly substrate 2000 can be arranged such that the organic layer OL having a plurality of opening portions OLH of the assembly substrate 2000 faces the chamber CB.

[0215] Next, a magnet MG can be positioned on the assembly substrate 2000. The light-emitting elements ED1 immersed or suspended on the bottom of the chamber CB can be moved toward the assembly substrate 2000 by the magnetic force of the magnet MG.

[0216] In this case, the light-emitting element ED1 may include a magnetic element such that the light-emitting element ED1 can be moved by a magnetic field. For example, either the first electrode 124 or the second electrode 125 of the light-emitting element ED1 may include a ferromagnetic material such as iron (Fe), cobalt (Co), or nickel (Ni) such that the direction in which the light-emitting element ED1 is guided by the magnet MG can be aligned.

[0217] Next, referring to Figure 10B , the light-emitting elements ED1 that have been moved toward the assembly substrate 2000 by the magnet MG can be self-assembled onto the assembly substrate 2000 by an electric field formed between a plurality of assembly electrodes AE.

[0218] Referring to Figure 10B , the assembly substrate 2000 includes an assembly substrate 210, an organic layer OL, a plurality of assembly electrodes AE, and an assembly insulating layer IL.

[0219] Specifically, multiple light-emitting elements ED1 can be self-assembled into the opening portion OLH of the organic layer OL by applying a voltage to multiple assembly electrodes AE. For example, an electric field can be formed by applying different alternating voltages to the multiple first assembly electrodes AE1 and the multiple second assembly electrodes AE2. The light-emitting element ED1 can have a polarity by being polarized through the mediation of the electric field. In addition, the polarized light-emitting element ED1 can be fixed or moved in a specific direction by dielectrophoresis (DEP), i.e., an electric field. Therefore, multiple light-emitting elements ED1 can be temporarily self-assembled inside the opening portion OLH of the assembly substrate 2000 by using dielectrophoresis.

[0220] Meanwhile, the organic layer OL includes a first organic layer OL1 and a second organic layer OL2. The thickness of the organic layer OL that can be formed by one kind of treatment is limited. If the thickness of the organic layer OL is at a predetermined level or lower, the light-emitting element ED1 self-assembled in the opening portion OLH of the organic layer OL may not be properly placed in the opening portion OLH. On the contrary, in the case where the thickness of the organic layer OL is too large, it may be difficult to attach the light-emitting element ED1 self-assembled inside the opening portion OLH of the organic layer OL to the donor 3000. Therefore, the thickness of the organic layer OL can be adjusted by forming the organic layer OL into multiple layers.

[0221] The organic layer OL includes multiple opening portions OLH. Each of the multiple opening portions OLH formed by opening a part of the organic layer OL can be an area where multiple light-emitting elements ED1 are self-assembled. Thereafter, the multiple opening portions OLH can be respectively formed at positions corresponding to multiple sub-pixels SP of the display device 1100. The multiple opening portions OLH can be configured to respectively correspond to the multiple sub-pixels SP in a one-to-one manner. The light-emitting elements ED1 self-assembled in the multiple opening portions OLH can be completely transferred to the multiple sub-pixels SP.

[0222] An assembly insulating layer IL can be provided on the organic layer OL, and the assembly insulating layer IL can protect the multiple assembly lines AL, the multiple assembly electrodes AE, and the organic layer OL from the influence of the fluid WT, thereby suppressing defects such as corrosion of the multiple assembly lines AL.

[0223] After the self-assembly is completed, the fluid WT can evaporate from the assembly substrate 2000. In this case, the light-emitting element ED1 can be fixed to the inside of the opening portion OLH by forming an electric field between the assembly electrodes AE until the fluid WT completely evaporates. In addition, the electric field can be removed after the assembly substrate 2000 is completely dried. In this case, even after the electric field is removed, the light-emitting element ED1 can be temporarily fixed to the assembly substrate 2000 by van der Waals forces.

[0224] Next, refer to Figure 10C, transfer a plurality of light-emitting elements ED1 of the assembled substrate 2000 to the donor 3000.

[0225] First, refer to Figure 10C , align the assembled substrate 2000 and the donor 3000 such that the plurality of light-emitting elements ED1 and the donor 3000 face each other. For example, the assembled substrate 2000 and the donor 3000 can be aligned such that a first alignment pattern of the assembled substrate 2000 and a second alignment pattern of the donor 3000 overlap each other.

[0226] After aligning the assembled substrate 2000 and the donor 3000, the assembled substrate 2000 and the donor 3000 can be bonded such that the upper portions of the light-emitting elements ED1 can contact the donor 3000. In this case, the donor 3000 is made of a material having an adhesive force such that the upper portions of the plurality of light-emitting elements ED1 can be bonded to the donor 3000 and move from the assembled substrate 2000 to the donor 3000.

[0227] Next, refer to Figure 10D , transfer the plurality of light-emitting elements ED1 on the donor 3000 to the bonding layer AD of the display panel PN.

[0228] First, align the donor 3000 and the display panel PN formed with the bonding layer AD. The display panel PN and the donor 3000 can be aligned after the donor 3000 is set such that the plurality of light-emitting elements ED1 of the donor 3000 and the bonding layer AD of the display panel PN face each other. When the display panel PN and the donor 3000 are aligned, align the alignment key AK temporarily attached to the donor 3000 with a third alignment pattern AP3 of the display panel PN such that the donor 3000 and the display panel PN can be aligned. The third alignment pattern AP3 can be a pattern provided in a non-display area NA of the display panel PN. The third alignment pattern AP3 can be made of the same material as any one of a plurality of electrodes or a plurality of lines provided on the display panel PN. For example, the third alignment pattern AP3 can have a quadrilateral provided with an X-shaped pattern. Thus, the donor 3000 and the display panel PN can be aligned such that the alignment key AK is provided at the center of the X-shaped portion of the third alignment pattern AP3.

[0229] In addition, refer to Figure 10D and Figure 10E, the donor 3000 and the display device 1100 can be joined such that the light-emitting elements ED1 on the donor 3000 can be transferred onto the bonding layer AD. The plurality of light-emitting elements ED1 provided on the donor 3000 are arranged corresponding to the plurality of sub-pixels SP such that all the light-emitting elements ED1 on the donor 3000 can be transferred onto the display panel PN at once without selectively transferring the light-emitting elements ED1. The plurality of light-emitting elements ED1 transferred onto the display panel PN can be temporarily fixed by being attached to the bonding layer AD.

[0230] In addition, the alignment keys AK can be transferred together with the plurality of light-emitting elements ED1. The alignment keys AK can be transferred onto a third alignment pattern AP3 in the non-display area NA. However, since the alignment keys AK transferred onto the display panel PN are not connected to separate connection electrodes CE, they do not emit light.

[0231] Next, referring to Figure 10F , the light-emitting elements ED1 are transferred onto the bonding layer AD of the display device 1100, and then a first connection electrode CE1 and a second connection electrode CE2 are formed such that the light-emitting elements ED1 can be electrically connected to the driving transistor DT and the power line VDD.

[0232] First, a second planarization layer 1118 and a third planarization layer 1119 covering the plurality of light-emitting elements ED1 are formed. In addition, contact holes through which the first electrode 124 and the second electrode 125 of each of the plurality of light-emitting elements ED1 are exposed can be formed in the third planarization layer 1119. Contact holes through which the first reflective electrode RE1 and the second reflective electrode RE2 are exposed can be formed in the third planarization layer 1119, the second planarization layer 1118, and the bonding layer AD.

[0233] Then, the first connection electrode CE1 can be formed on the second planarization layer 1118 and the second connection electrode CE2 can be formed on the third planarization layer 1119. In addition, a conductive material layer can be formed on the front surface of the substrate 110, and the first connection electrode CE1 and the second connection electrode CE2 can be formed by patterning the conductive material layer.

[0234] Thus, in a display device 1100 and a method of manufacturing the display device 1100 according to another embodiment of the present specification, a plurality of light-emitting elements ED1 can be self-assembled onto an assembly substrate 2000 in an arrangement corresponding to a plurality of sub-pixels SP, and then the plurality of light-emitting elements ED1 on the assembly substrate 2000 can be transferred to a display panel PN by using a donor 3000. In the case of self-assembling the light-emitting elements ED1 by using an electric field, the process of aligning the plurality of light-emitting elements ED1 to correspond to the intervals between the plurality of sub-pixels SP and then transferring the plurality of light-emitting elements ED1 from a wafer to the donor 3000 can be excluded. Additionally, by using an electric field and a plurality of opening portions OLH, the light-emitting elements ED1 can be easily self-assembled at precise positions, which can minimize alignment errors. Therefore, the plurality of light-emitting elements ED1 can be self-assembled in an arrangement corresponding to the sub-pixels SP by using the assembly substrate 2000, and the plurality of light-emitting elements ED1 can be transferred to the display panel PN in a complete manner, which can minimize the alignment errors of the plurality of light-emitting elements ED1 and simplify the transfer process.

[0235] Exemplary embodiments of the present disclosure may also be described as follows:

[0236] According to an aspect of the present disclosure, a light-emitting element is provided. The light-emitting element includes: a first semiconductor layer; a light-emitting layer on the first semiconductor layer; a second semiconductor layer on the light-emitting layer; a second electrode on the second semiconductor layer; and a first electrode on the first semiconductor layer and spaced apart from the light-emitting layer and the second semiconductor layer, wherein the first semiconductor layer includes one or more concave patterns between the first electrode and the second electrode.

[0237] The width of the first semiconductor layer above the concave pattern may increase in a downward direction.

[0238] The minimum width of the first semiconductor layer in the concave pattern may be smaller than the width of the top surface of the first semiconductor layer and the width of the bottom surface of the first semiconductor layer.

[0239] At least a portion of the first electrode may be disposed outside the light-emitting layer, the second semiconductor layer, and the second electrode.

[0240] The first electrode may be disposed on a flat top surface of the first semiconductor layer extending from the concave pattern.

[0241] The first semiconductor layer may further include a plurality of light extraction patterns disposed along the concave pattern.

[0242] The plurality of light extraction patterns may have an inclination of 73 degrees.

[0243] The light-emitting element may further include a packaging layer configured to cover the top surface and the side surface of the light-emitting element, wherein the packaging layer may be provided only above the concave pattern.

[0244] A plurality of light extraction patterns may be provided on the surface of the concave pattern.

[0245] The concave pattern may be formed along the crystal direction of the first semiconductor layer.

[0246] According to an aspect of the present disclosure, a display device is provided. The display device includes: a substrate including a plurality of sub-pixels; a plurality of light-emitting elements provided in the plurality of sub-pixels on the substrate; a plurality of transistors provided on the substrate; and a connection electrode configured to connect the plurality of transistors and the plurality of light-emitting elements, wherein each of the plurality of light-emitting elements includes at least one concave pattern provided on the side surface of the plurality of light-emitting elements, and wherein the connection electrode is provided to overlap a part of the concave pattern.

[0247] Each of the plurality of light-emitting elements may include: a first semiconductor layer; a light-emitting layer on the first semiconductor layer; a second semiconductor layer on the light-emitting layer; a second electrode on the second semiconductor layer; and a first electrode on the first semiconductor layer and spaced apart from the light-emitting layer and the second semiconductor layer, and wherein the concave pattern may be provided on the first semiconductor layer.

[0248] The first semiconductor layer may include: a first portion below the concave pattern; a second portion above the first portion and including the concave pattern; and a third portion on the second portion, and wherein the first electrode may be provided on the top surface of the first portion exposed through the second portion.

[0249] The display device may further include: a planarization layer configured to surround the side surfaces of the plurality of light-emitting elements, wherein the planarization layer may fill the concave pattern.

[0250] The display device may further include: a plurality of assembly electrodes on the substrate and configured to overlap the plurality of light-emitting elements.

[0251] The plurality of assembly electrodes and the plurality of light-emitting elements may be electrically connected.

[0252] The display device may further include: a plurality of reflective electrodes on the substrate and configured to overlap the plurality of light-emitting elements; and a bonding layer on the substrate and bonded to the plurality of light-emitting elements.

[0253] The plurality of light-emitting elements may include a first light-emitting element, a second light-emitting element, and a third light-emitting element that may have different planar shapes.

[0254] A plurality of light-emitting elements may have a concave pattern, and the concave pattern has a shape that varies according to the wavelength of light to be emitted.

[0255] According to one aspect of the present disclosure, a method of manufacturing a light-emitting element is provided. The method includes: disposing a first semiconductor layer, a light-emitting layer, a second semiconductor layer, and a second electrode on a wafer; performing mesa etching on partial regions of the light-emitting layer and the second semiconductor layer to form mesa regions; forming a first cover layer covering the mesa regions; etching the first semiconductor layer in regions not covered by the first cover layer to form a concave pattern; forming a second cover layer; etching the first semiconductor layer in regions covered by the second cover layer and removing the second cover layer to form a first electrode on the first semiconductor layer; forming a third cover layer that only covers the concave pattern, the lower region of the concave pattern, and the first electrode; forming a packaging layer on the third cover layer; and removing the third cover layer.

[0256] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-described exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. The protection scope of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope should be interpreted as falling within the scope of the present disclosure.

Claims

1. A light emitting element, comprising: a first semiconductor layer; a light emitting layer on the first semiconductor layer; a second semiconductor layer on the light emitting layer; a second electrode on the second semiconductor layer; as well as a first electrode, the first electrode being disposed on the first semiconductor layer and spaced apart from the light emitting layer and the second semiconductor layer; The first semiconductor layer includes one or more concave patterns between the first electrode and the second electrode.

2. The light-emitting element according to claim 1, wherein The width of the first semiconductor layer above the concave pattern increases in a downward direction.

3. The light-emitting element according to claim 1, wherein A minimum width of the first semiconductor layer in the concave pattern is smaller than a width of a top surface of the first semiconductor layer and a width of a bottom surface of the first semiconductor layer.

4. The light-emitting element according to claim 3, wherein At least a portion of the first electrode is disposed outside the light emitting layer, the second semiconductor layer, and the second electrode.

5. The light emitting element according to claim 4, wherein The first electrode is disposed on a flat top surface of the first semiconductor layer extending from the concave pattern.

6. The light-emitting element according to claim 1, wherein The first semiconductor layer further includes a plurality of light extraction patterns disposed along the concave pattern.

7. The light-emitting element according to claim 6, wherein The plurality of light extraction patterns have an inclination of 73 degrees.

8. The light emitting element according to claim 1, further comprising: an encapsulation layer, the encapsulation layer being configured to cover a top surface of the light emitting element and a side surface of the light emitting element, Wherein, the encapsulation layer is only arranged above the concave pattern.

9. The light-emitting element according to claim 1, wherein The concave pattern is formed along a crystal direction of the first semiconductor layer.

10. A display device, comprising: a substrate, the substrate comprising a plurality of sub-pixels; a plurality of light emitting elements, wherein the plurality of light emitting elements are arranged in the plurality of sub-pixels on the substrate; a plurality of transistors, wherein the plurality of transistors are disposed on the substrate; as well as a connecting electrode configured to connect the plurality of transistors and the plurality of light emitting elements, wherein each of the plurality of light emitting elements comprises at least one concave pattern disposed on a side surface of the plurality of light emitting elements, and Wherein, the connecting electrode is arranged to overlap with a portion of the concave pattern.

11. The display device according to claim 10, wherein: A plurality of light extraction patterns are disposed on a surface of the concave pattern.

12. The display device according to claim 10, wherein: Each of the plurality of light emitting elements comprises: a first semiconductor layer; a light emitting layer on the first semiconductor layer; a second semiconductor layer on the light emitting layer; a second electrode on the second semiconductor layer; and a first electrode disposed on the first semiconductor layer and spaced apart from the light emitting layer and the second semiconductor layer, and Wherein, the concave pattern is arranged on the first semiconductor layer.

13. The display device according to claim 12, wherein: The first semiconductor layer comprises: a first portion below the concave pattern; a second portion disposed above the first portion and including the concave pattern; and a third portion on the second portion, and Wherein, the first electrode is disposed on a top surface of the first portion exposed by the second portion.

14. The display device according to claim 10, further comprising: a planarization layer configured to surround side surfaces of the plurality of light emitting elements, Wherein, the planarization layer fills the concave pattern.

15. The display device according to claim 10, further comprising: A plurality of assembly electrodes are disposed on the substrate and configured to overlap with the plurality of light emitting elements.

16. The display device according to claim 15, wherein: The plurality of assembly electrodes and the plurality of light emitting elements are electrically connected.

17. The display device according to claim 10, further comprising: a plurality of reflective electrodes, the plurality of reflective electrodes being disposed on the substrate and configured to overlap with the plurality of light emitting elements; as well as A bonding layer is provided on the substrate and bonded to the plurality of light emitting elements.

18. The display device according to claim 17, wherein: The plurality of light emitting elements include a first light emitting element, a second light emitting element, and a third light emitting element having different planar shapes.

19. The display device according to claim 17, wherein: The concave patterns of the plurality of light emitting elements have shapes that vary according to a wavelength of light to be emitted.

20. A method for manufacturing a light emitting element, comprising: Disposing a first semiconductor layer, a light emitting layer, a second semiconductor layer and a second electrode on a wafer; Performing mesa etching on a portion of the light emitting layer and the second semiconductor layer to form a mesa region; forming a first covering layer covering the mesa area; etching the first semiconductor layer in a region not covered by the first covering layer to form a concave pattern; forming a second covering layer; Etching the first semiconductor layer in a region covered by the second covering layer and removing the second covering layer to form a first electrode on the first semiconductor layer; forming a third covering layer, wherein the third covering layer only covers the concave pattern, a lower region of the concave pattern, and the first electrode; forming an encapsulation layer on the third covering layer; as well as The third covering layer is removed.

Images