Display device

Abstract

The invention discloses a display device which comprises a substrate, an insulating layer, a plurality of first chip connecting line structures, a plurality of light-emitting elements, a failure microchip and a repair microchip. The insulating layer is located on the substrate. The first chip connecting line structure is located on the insulating layer and extends from the chip placing area to a plurality of pixel areas around the chip placing area. The light-emitting elements are respectively arranged in the pixel areas. And the failed microchip is positioned in the chip placement area. The insulating layer laterally surrounds the failed microchip. The failed microchip is at least partially connected to the first chip connection line structure. The repair microchip is located in the chip placement area. The repair microchip is electrically connected to the light-emitting element through the first chip connection line structure.

Description

Technical Field

[0001] The present invention relates to a display device, and particularly to a display device including a repair microchip. Background Art

[0002] A micro light emitting diode (μLED) display panel is a display technology composed of tens of thousands of micro light emitting diodes. These micro light emitting diodes serve as the light sources for each pixel, and have higher brightness, lower power consumption, and longer lifespan compared to traditional organic light emitting diode display panels or liquid crystal display panels.

[0003] In a micro light emitting diode display panel, the driving method of micro light emitting diodes is a key challenge because each micro light emitting diode requires precise signal control. Using microchip technology, micro control chips can be disposed in the display area of the display panel, and these microchips directly provide signals to the micro light emitting diodes to achieve the driving and control of pixels. This technology greatly improves the accuracy and efficiency of signal transmission, while reducing the layout complexity of the driving circuit, which is beneficial to the realization of miniaturized and high-resolution display panels. Summary of the Invention

[0004] The present invention provides a display device that can repair failed microchips.

[0005] At least one embodiment of the present invention provides a display device, which includes a substrate, an insulating layer, a plurality of first chip connection line structures, a plurality of light emitting elements, a failed microchip, and a repair microchip. The insulating layer is located on the substrate. The first chip connection line structures are located on the insulating layer and extend from the chip placement area to a plurality of pixel areas around the chip placement area. The light emitting elements are respectively disposed in the pixel areas. The failed microchip is located in the chip placement area. The insulating layer laterally surrounds the failed microchip. The failed microchip is at least partially connected to the first chip connection line structures. The repair microchip is located in the chip placement area. The repair microchip is electrically connected to the light emitting elements through the first chip connection line structures. Description of the Drawings

[0006] Figure 1A 、 Figure 2A 、 Figure 3A and Figure 4A are top view schematic diagrams of various stages of manufacturing a display device according to an embodiment of the present invention;

[0007] Figure 1B 、 Figure 2B 、 Figure 3B and Figure 4B are respectively Figure 1A 、 Figure 2A 、 Figure 3Aand Figure 4A Schematic cross-sectional view of line A-A' and line B-B';

[0008] Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 and Figure 9A are top views of various stages of manufacturing a display device according to another embodiment of the present invention;

[0009] Figure 9B is Figure 9A Schematic cross-sectional view of line C-C';

[0010] Figure 10 is a top view of manufacturing a display device according to yet another embodiment of the present invention;

[0011] Figure 11 is a top view of manufacturing a display device according to still another embodiment of the present invention;

[0012] Figure 12A 、 Figure 12B 、 Figure 12C and Figure 12D are respectively top views of repairing the second chip pads of microchips according to some embodiments of the present invention;

[0013] Figure 13A is a top view of a display device according to an embodiment of the present invention;

[0014] Figure 13B is Figure 13A Schematic cross-sectional views of line A-A' and line C-C';

[0015] Figure 13C is Figure 13A Top view of the microchip;

[0016] Symbol Description

[0017] 10A, 10B, 10C, 10D, 10E: Display device

[0018] 100: Substrate

[0019] 102: Adhesive layer

[0020] 110A, 110B: First microchip

[0021] 112, 212: Active surface

[0022] 112a, 112c: First long side

[0023] 112b, 112d: First short side

[0024] 113: First chip pad

[0025] 120A, 120D, 120E: First chip connection line structure

[0026] 122A, 122D, 122E: First chip connection pad

[0027] 123A, 123D, 123E: First connection line

[0028] 124A, 124D, 124E: First repair pad

[0029] 125A, 125D, 125E: Signal output line

[0030] 120B, 120C: Second chip connection line structure

[0031] 122B, 122C: Second chip connection pad

[0032] 123B, 123C: Second connection line

[0033] 124B, 124C: Second repair pad

[0034] 125B, 125C: Signal input line

[0035] 126C, 126D: Bridge connection line

[0036] 130: Insulating layer

[0037] 132: First light-emitting diode bonding pad

[0038] 134: Second light-emitting diode bonding pad

[0039] 210: Repair microchip

[0040] 212a, 212c: Second long side

[0041] 212b, 212d: Second short side

[0042] 213: Second chip pad

[0043] 215: Connection structure

[0044] CA: Chip placement area

[0045] D1, D2, D3: Light-emitting element

[0046] DR1: First direction

[0047] DR2: Second direction

[0048] L1, L2: Connection lines

[0049] LC1, LC3: Signal disconnection parts

[0050] LC2, LC4: Signal connection parts

[0051] ND: Direction

[0052] PA: Pixel area

[0053] Y1, Y2: Lengths Detailed implementation manners

[0054] Figure 1A 、 Figure 2A 、 Figure 3A And Figure 4A are top - view schematic diagrams of each stage of manufacturing a display device 10A according to an embodiment of the present invention. Figure 1B 、 Figure 2B 、 Figure 3B And Figure 4B are respectively Figure 1A 、 Figure 2A 、 Figure 3A And Figure 4A are cross - sectional schematic diagrams, where Figure 1B 、 Figure 2B 、 Figure 3B And Figure 4B respectively correspond to Figure 1A 、 Figure 2A 、 Figure 3A And Figure 4A for lines A - A' and line B - B'. Please refer to Figure 1A And Figure 1B , and the first microchips 110A, 110B are disposed on the substrate 100. For example, the first microchips 110A, 110B are attached to the substrate 100 through the adhesive layer 102.

[0055] In some embodiments, the substrate 100 is, for example, a rigid substrate, and its material can be glass, quartz, organic polymer, or light-blocking / reflection material (e.g., conductive material, metal, wafer, ceramic, or other applicable materials) or other applicable materials. However, the present invention is not limited thereto. In other embodiments, the substrate 100 can also be a flexible substrate or a stretchable substrate. For example, the materials of the flexible substrate and the stretchable substrate include polyimide (PI), polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyurethane (PU), or other suitable materials. In some embodiments, the substrate 100 is a transparent substrate, which is applicable to a transparent display device.

[0056] Above the substrate 100, there are multiple chip placement areas CA and multiple pixel areas PA. The first microchips 110A and 110B are respectively disposed in different chip placement areas CA, and the pixel areas PA are respectively located around the corresponding chip placement areas CA. In some embodiments, both the chip placement areas CA and the pixel areas PA are disposed in the display area of the display device. By disposing the chip placement areas CA in the display area, it helps to reduce the border size of the display device. The pixel area PA is an area for disposing light-emitting elements in subsequent manufacturing processes.

[0057] In this embodiment, the first microchips 110A and 110B are attached to the top surface of the substrate 100 through the adhesive layer 102, but the present invention is not limited thereto. In other embodiments, there are circuit structures (not shown) on the top surface of the substrate 100, and the first microchips 110A and 110B are attached to the aforementioned circuit structures through the adhesive layer 102.

[0058] In this embodiment, a whole adhesive layer 102 is formed on the substrate 100, and a part of the adhesive layer 102 does not overlap with the first microchips 110A and 110B, but the present invention is not limited thereto. In other embodiments, multiple separated adhesive layers 102 respectively attach the first microchips 110A and 110B to the substrate 100. In some embodiments, the first microchips 110A and 110B include drive circuits.

[0059] In this embodiment, the first microchips 110A and 110B are both disposed in the chip placement area CA with their active surfaces 112 facing upward. Each of the first microchips 110A and 110B includes a plurality of first chip pads 113. In some embodiments, the first chip pads 113 include a metal bump structure. For example, the first chip pads 113 include gold, copper, tin, silver, lead, indium, or other metal materials or combinations of the above materials. The first chip pads 113 are disposed on the active surface 112. In some embodiments, the active surface 112 includes two opposite first short sides 112b and 112d and two opposite first long sides 112a and 112c, wherein the centers of the respective first chip pads 113 are offset from the midpoint connection line L1 between the two opposite first short sides 112b and 112d. The connection line L1 is a virtual line segment and does not actually exist. In this embodiment, the midpoints of all the first chip pads 113 are located between the connection line L1 and the first long side 112a, but the present invention is not limited thereto. In other embodiments, the midpoints of some of the first chip pads 113 are located between the connection line L1 and the first long side 112a, while the midpoints of another part of the first chip pads 113 are located between the connection line L1 and the first long side 112c. In some embodiments, each of the first microchips 110A and 110B includes a row of first chip pads 113. Compared with designing the first chip pads 113 into multiple rows, the probability that a single row of first chip pads 113 contacts the wrong trace due to offset is lower.

[0060] Please refer to Figure 2A and Figure 2B , an insulating layer 130 is formed on the substrate 100. The insulating layer 130 laterally surrounds the first microchips 110A and 110B. The first chip pads 113 of the first microchips 110A and 110B are exposed by the insulating layer 130.

[0061] A plurality of first chip connection line structures 120A and a plurality of second chip connection line structures 120B are formed on the insulating layer 130. The first chip connection line structures 120A extend from the chip placement area CA to a plurality of pixel areas PA around the chip placement area CA, while the second chip connection line structures 120B extend from the chip placement area CA to a signal source area (not shown). In some embodiments, the signal source area is disposed in the border area of the display device, but the present invention is not limited thereto.

[0062] In some embodiments, the first chip connection line structure 120A includes a first chip connection pad 122A, a first connection line 123A, a first repair pad 124A, and a signal output line 125A. The first chip connection pad 122A, the first connection line 123A, and the first repair pad 124A are disposed in the chip placement area CA. The first chip connection pad 122A is configured to connect a portion of the first chip pad 113. In this embodiment, the first chip connection pad 122A of the first chip connection line structure 120A is directly formed on the first chip pad 113 and directly contacts at least a portion of the first chip pad 113. The first connection line 123A connects the first chip connection pad 122A and the first repair pad 124A. The signal output line 125A connects the first repair pad 124A and extends from the first repair pad 124A to the pixel area PA. In some embodiments, the signal output line 125A is connected to the first light-emitting diode bonding pad 132 in the pixel area PA. In some embodiments, the pixel area PA further includes one or more second light-emitting diode bonding pads 134. In some embodiments, the plurality of second light-emitting diode bonding pads 134 are connected to each other and electrically connected to a common voltage.

[0063] In some embodiments, the second chip connection line structure 120B includes a second chip connection pad 122B, a second connection line 123B, a second repair pad 124B, and a signal input line 125B. The second chip connection pad 122B, the second connection line 123B, and the second repair pad 124B are disposed in the chip placement area CA. The second chip connection pad 122B is configured to connect another portion of the first chip pad 113. In this embodiment, the second chip connection pad 122B of the second chip connection line structure 120B is directly formed on the first chip pad 113 and directly contacts at least a portion of the first chip pad 113. The second connection line 123B connects the second chip connection pad 122B and the second repair pad 124B. The signal input line 125B connects the second repair pad 124B and extends from the second repair pad 124B to the signal source area (not shown). In some embodiments, the signal source provides a signal to the first microchips 110A, 110B through the second chip connection line structure 120B.

[0064] Please refer to Figure 3A and Figure 3B, the light-emitting elements D1, D2, and D3 are respectively disposed in the pixel region PA. The light-emitting elements D1, D2, and D3 are located above the insulating layer 130, and the light-emitting elements D1, D2, and D3 are respectively bonded to the first light-emitting diode bonding pad 132 and the second light-emitting diode bonding pad 134. In some embodiments, the light-emitting elements D1, D2, and D3 include micro light-emitting diodes. For example, the light-emitting elements D1, D2, and D3 are a red micro light-emitting diode, a green micro light-emitting diode, and a blue micro light-emitting diode, respectively.

[0065] Before or after the light-emitting elements D1, D2, and D3 are disposed in the pixel region PA, the first microchips 110A and 110B are tested to confirm whether the first microchips 110A and 110B can operate normally. In this embodiment, the first microchip 110A cannot operate normally, while the first microchip 110B can operate normally. For example, the first microchip 110A cannot output and / or receive the expected signals because of an offset when placed on the substrate 100 or a defect inside itself. The first microchip 110A can also be referred to as a failed microchip. In this embodiment, the failed microchip (i.e., the first microchip 110A) is located in the chip placement area CA. The insulating layer 130 laterally surrounds the failed microchip, and the failed microchip is at least partially connected to the first chip connection line structure 120A and the second chip connection line structure 120B. In some embodiments, because of the offset of the failed microchip during placement, a part of the first chip pad 113 of the failed microchip is not bonded to the first chip connection line structure 120A and the second chip connection line structure 120B.

[0066] Please refer to Figure 4A and Figure 4B , after confirming that the first microchip 110A is a failed microchip, a repair manufacturing process is performed. Specifically, the repair microchip 210 is disposed in the chip placement area CA corresponding to the failed microchip. The repair microchip 210 is not disposed in the chip placement area CA corresponding to the first microchip 110B that can operate normally. In some embodiments, the repair microchip 210 has the same structural design as the first microchips 110A and 110B. Therefore, it is not necessary to redesign the microchip for the repair manufacturing process. For example, the relative positions of the second chip pads 213 on the repair microchip 210 are equal to the relative positions of the first chip pads 113 of the first microchips 110A and 110B, respectively. In some embodiments, the second chip pads 213 include a metal bump structure. For example, the second chip pads 213 include gold, copper, tin, silver, lead, indium, or other metal materials or a combination of the above materials.

[0067] The repair microchip 210 is located above the insulating layer 130 and is joined to the corresponding first chip connection line structure 120A and second chip connection line structure 120B through the connection structure 215. Specifically, the second chip pad 213 of the repair microchip 210 is joined to the first repair pad 124A of the corresponding first chip connection line structure 120A and the second repair pad 124B of the corresponding second chip connection line structure 120B through the connection structure 215. The connection structure 215 includes, for example, solder (such as indium, tin, or other suitable metal materials or a combination of the above materials), conductive adhesive, or other conductive connection materials. The repair microchip 210 is electrically connected to the light-emitting elements D1, D2, D3 through the first chip connection line structure 120A corresponding to the failed microchip; at the same time, the repair microchip 210 is electrically connected to the signal source through the second chip connection line structure 120B corresponding to the failed microchip. For example, the first chip connection line structure 120A is configured to provide data signals from the microchip to the light-emitting elements D1, D2, D3, and the second chip connection line structure 120B is configured to provide input signals to the microchip.

[0068] In this embodiment, the repair microchip 210 is disposed in the chip placement area CA with the active surface 212 facing downwards. The second chip pads 213 of the repair microchip 210 are disposed on the active surface 212. In some embodiments, the active surface 212 includes two opposite second short sides 212b, 212d and two opposite second long sides 212a, 212c, wherein the centers of the respective second chip pads 213 deviate from the line L2 connecting the midpoints of the two opposite second short sides 212b, 212d. In this embodiment, the midpoints of all the second chip pads 213 are located between the line L2 and the second long side 212c, but the present invention is not limited thereto. In other embodiments, the midpoints of some of the second chip pads 213 are located between the line L2 and the second long side 212c, while the midpoints of another part of the second chip pads 213 are located between the line L2 and the second long side 212d. In some embodiments, the repair microchip 210 includes second chip pads 213 arranged in a single row. Compared with designing the second chip pads 213 in multiple rows, the probability of the single-row second chip pads 213 contacting the wrong traces due to offset is lower.

[0069] In some embodiments, the failed microchip (i.e., the first microchip 110A) at least partially overlaps the repair microchip 210 in the direction ND perpendicular to the top surface of the substrate 100. Therefore, the impact of the repair microchip 210 on the display area can be reduced. In some embodiments, when the display device 10A is a transparent display device, the transmittance of the display device 10A can be improved by overlapping the repair microchip 210 with the failed microchip. In some embodiments, the active surface 112 of the failed microchip (i.e., the first microchip 110A) faces the active surface 212 of the repair microchip 210, however, the first chip pad 113 does not overlap the second chip pad 213 in the direction ND perpendicular to the top surface of the substrate 100.

[0070] In some embodiments, the second repair pad 124B is disposed between the second chip connection pad 122B and the signal input line 125B. Such a design allows the second connection line 123B between the second repair pad 124B and the second chip connection pad 122B to be cut off by a cutting process (such as laser cutting or other suitable cutting methods) before installing the repair microchip 210. This ensures that the first microchip 110A no longer receives input signals through the second chip connection line structure 120B, while the repair microchip 210 can still receive input signals from the signal source through the second repair pad 124B and the signal input line 125B. Similarly, the first repair pad 124A is located between the first chip connection pad 122A and the signal output line 125A. The first connection line 123A between the first repair pad 124A and the first chip connection pad 122A is cut off through a cutting process to ensure that the first microchip 110A no longer outputs signals to the light-emitting elements D1, D2, D3. At the same time, the repair microchip 210 can still output signals to the light-emitting elements D1, D2, D3 through the first repair pad 124A and the signal output line 125A.

[0071] In other embodiments, when the repair process does not require cutting the first connection line 123A and the second connection line 123B, the position of the first repair pad 124A and the position of the first chip connection pad 122A can be swapped, and the position of the second repair pad 124B and the position of the second chip connection pad 122B can also be swapped.

[0072] Figure 5 , Figure 6 , Figure 7 , Figure 8 as well as Figure 9A is a schematic top view of various stages of manufacturing a display device 10B according to another embodiment of the present invention. Figure 9B yes Figure 9A Please refer to the cross-sectional diagram of the line C-C'. Figure 5, the first microchips 110A and 110B are both disposed in the chip placement area CA with their active surfaces 112 facing upward. In this embodiment, the first chip pads 113 of the first microchips 110A and 110B are arranged in a staggered manner along the first direction DR1. Specifically, the midpoints of some of the first chip pads 113 are located between the connecting line L1 and the first long side 112a, while the midpoints of the other part of the first chip pads 113 are located between the connecting line L1 and the first long side 112c. In some embodiments, the first microchips 110A and 110B each include first chip pads 113 arranged in a column along the first direction DR1. In this embodiment, being arranged in a column along the first direction DR1 means that the first chip pads 113 do not overlap with each other in the second direction DR2 perpendicular to the first direction DR1. Compared with designing the first chip pads 113 into multiple columns, the probability that a single column of the first chip pads 113 contacts the wrong trace due to offset is lower.

[0073] Please refer to Figure 5 and Figure 6 , an insulating layer 130 is formed on the substrate 100. The insulating layer 130 laterally surrounds the first microchips 110A and 110B. The first chip pads 113 of the first microchips 110A and 110B are exposed by the insulating layer 130.

[0074] A plurality of first chip connection line structures 120A and a plurality of second chip connection line structures 120C are formed on the insulating layer 130. The first chip connection line structures 120A extend from the chip placement area CA to a plurality of pixel areas PA around the chip placement area CA, and the second chip connection line structures 120C extend from the chip placement area CA to a signal source area (not shown). In some embodiments, the signal source area is disposed in the border area of the display device, but the present invention is not limited thereto.

[0075] In some embodiments, the second chip connection line structure 120C includes a second chip connection pad 122C, a second connection line 123C, a second repair pad 124C, a signal input line 125C, and a bridging line 126C. The second chip connection pad 122C, the second connection line 123C, the second repair pad 124C, and the bridging line 126C are disposed in the chip placement area CA. The first chip connection pad 122A is configured to connect a part of the first chip pad 113, and the second chip connection pad 122C is configured to connect another part of the first chip pad 113. In this embodiment, the second chip connection pad 122C of the second chip connection line structure 120C is directly formed on the first chip pad 113 and directly contacts at least a part of the first chip pad 113. The second connection line 123C connects the second chip connection pad 122C and the second repair pad 124C. The signal input line 125C is connected to the second connection line 123C through the bridging line 126C and extends to a signal source area (not shown). In some embodiments, a signal source provides a signal to the first microchips 110A, 110B through the second chip connection line structure 120C.

[0076] Please refer to Figure 6 With Figure 7 , the light-emitting elements D1, D2, D3 are respectively disposed in the pixel area PA. The light-emitting elements D1, D2, D3 are located above the insulating layer 130 and are bonded to the first light-emitting diode bonding pad 132 and the second light-emitting diode bonding pad 134.

[0077] Before or after the light-emitting elements D1, D2, D3 are disposed in the pixel area PA, the first microchips 110A, 110B are tested to confirm whether the first microchips 110A, 110B can operate properly. In this embodiment, the first microchip 110A cannot operate properly, while the first microchip 110B can operate properly. For example, the first microchip 110A cannot output and / or receive an expected signal because it is offset when placed on the substrate 100 or has a defect inside itself. The first microchip 110A can also be referred to as a failed microchip.

[0078] Please refer to Figure 8, after confirming that the first microchip 110A is a failed microchip, the second connection line 123C between the second repair pad 124C and the second chip connection pad 122C is truncated by a cutting manufacturing process (such as laser cutting or other suitable cutting methods). For example, at least one of the second chip connection line structures 120C is cut to have a signal disconnection portion LC1 (for example, including the second chip connection pad 122C and a part of the second connection line 123C connecting the second chip connection pad 122C) and a signal connection portion LC2 (for example, including the second repair pad 124C, a part of the second connection line 123C connecting the second repair pad 124C, the bridge connection line 126C, and the signal input line 125C) that are separated from each other. The failed microchip (i.e., the first microchip 110A) is electrically connected to the signal disconnection portion LC1, while the repair microchip 210 is electrically connected to the signal connection portion LC2.

[0079] Please refer to Figure 9A and Figure 9B , the repair microchip 210 is disposed in the chip placement area CA corresponding to the failed microchip (i.e., the first microchip 110A). The repair microchip 210 is not disposed in the chip placement area CA corresponding to the first microchip 110B that can operate normally.

[0080] The repair microchip 210 is located above the insulating layer 130 and is bonded to the corresponding first chip connection line structure 120A and second chip connection line structure 120C through the connection structure 215. Specifically, the second chip pad 213 of the repair microchip 210 is bonded to the first repair pad 124A of the corresponding first chip connection line structure 120A and the second repair pad 124C of the second chip connection line structure 120C through the connection structure 215. The repair microchip 210 is electrically connected to the light-emitting elements D1, D2, D3 through the corresponding first chip connection line structure 120A; at the same time, the repair microchip 210 is electrically connected to the signal source through the corresponding second chip connection line structure 120C. For example, the first chip connection line structure 120A is configured to provide data signals from the repair microchip 210 to the light-emitting elements D1, D2, D3, while the second chip connection line structure 120C is configured to provide input signals to the repair microchip 210. In addition, since the second connection line 123C has been truncated, it can be ensured that the first microchip 110A cannot receive input signals through the signal input line 125C.

[0081] In Figure 9A and Figure 9B , the failed microchip (i.e., the first microchip 110A) does not overlap the repair microchip 210 in the direction ND perpendicular to the top surface of the substrate 100, but the present invention is not limited thereto. In other embodiments, the failed microchip at least partially overlaps the repair microchip 210.

[0082] Figure 10 It is a top view schematic diagram of manufacturing a display device 10C according to another embodiment of the present invention. It should be noted here that Figure 10 The embodiment of Figures 5 to 9B adopts the component numbers and partial contents of the embodiment of

[0083] Figure 10 The display device 10C of Figure 9A differs from the display device 10B of Figure 10 in that: in the display device 10B, the first chip pads 113 are arranged in a staggered manner in groups of two along the first direction DR1, and the second chip pads 213 are also arranged in the same way, that is, in groups of two, along the first direction DR1 in a staggered manner. In contrast, in the display device 10C, the first chip pads 113 (the pads to which the first microchips 110A and 110B are bonded to the first chip connection pads 122A and the second chip connection pads 122C, Figure 10 not shown) are arranged in a staggered manner along the first direction DR1 in units of a single one, and the second chip pads 213 (the pads to which the repair microchip 210 is bonded to the first repair pad 124A and the second repair pad 124C, Figure 10 not shown) are also arranged in a staggered manner along the first direction DR1 in units of a single one.

[0084] Figure 11 It is a top view schematic diagram of manufacturing a display device 10D according to yet another embodiment of the present invention. It should be noted here that Figure 11 The embodiment of Figures 5 to 9B adopts the component numbers and partial contents of the embodiment of

[0085] Figure 11 The display device 10D of Figure 9A differs from the display device 10B of

[0086] The first chip connection pad 122D, the first connection line 123D, the first repair pad 124D, and the bridge connection line 126D are disposed in the chip placement area CA. The first chip connection pad 122D is configured to connect to the first chip pad of a part of the first microchip 110A, and the second chip connection pad 122C is configured to connect to the first chip pad of another part of the first microchip 110A. In this embodiment, the first chip connection pad 122D of the first chip connection line structure 120D is directly formed on the first chip pad of the first microchip 110A and directly contacts at least part of the first chip pad of the first microchip 110A. The first connection line 123D connects the first chip connection pad 122D and the first repair pad 124D before the cutting manufacturing process. The signal output line 125D is connected to the first connection line 123D through the bridge connection line 126D. The signal output line 125D extends to the pixel area PA. In some embodiments, the signal output line 125D is connected to the first light-emitting diode bonding pad in the pixel area PA. In some embodiments, the pixel area PA further includes one or more second light-emitting diode bonding pads. The light-emitting elements D1, D2, D3 are bonded to the first light-emitting diode bonding pad and the second light-emitting diode bonding pad.

[0087] In this embodiment, after confirming that the first microchip 110A is a failed microchip, in addition to truncating the second connection line 123C between the second repair pad 124C and the second chip connection pad 122C through the cutting manufacturing process, the first connection line 123D between the first repair pad 124D and the first chip connection pad 122D is also truncated through the cutting manufacturing process to ensure that the first microchip 110A no longer outputs signals to the light-emitting elements D1, D2, D3.

[0088] For example, at least one of the first chip connection line structures 120D is cut to have a signal disconnection portion LC3 (e.g., including the second chip connection pad 122D and a part of the second connection line 123D connecting the second chip connection pad 122D) and a signal connection portion LC4 (e.g., including the second repair pad 124D, a part of the second connection line 123D connecting the second repair pad 124D, the bridge connection line 126D, and the signal input line 125D) that are separated from each other. Similarly, at least one of the second chip connection line structures 120C is cut to have a signal disconnection portion LC1 (e.g., including the second chip connection pad 122C and a part of the second connection line 123C connecting the second chip connection pad 122C) and a signal connection portion LC2 (e.g., including the second repair pad 124C, a part of the second connection line 123C connecting the second repair pad 124C, the bridge connection line 126C, and the signal input line 125C) that are separated from each other. The failed microchip (i.e., the first microchip 110A) is electrically connected to the signal disconnection portion LC1 and the signal disconnection portion LC3, while the repair microchip 210 is electrically connected to the signal connection portion LC2 and the signal connection portion LC4.

[0089] Figure 12A , Figure 12B , Figure 12C and Figure 12D are respectively top view schematic diagrams of the second chip pads of the repair microchip according to some embodiments of the present invention. Please refer to Figure 12A , in some embodiments, the second chip pads 213 of the repair microchip 210 have the same length Y1, but the present invention is not limited thereto. In other embodiments, the second chip pads 213 have two or more lengths, such as length Y1 and length Y2, as shown in Figure 12B , Figure 12C and Figure 12D wherein length Y2 is greater than length Y1. The arrangement of the second chip pads 213 having length Y1 and the second chip pads 213 having length Y2 can be adjusted according to actual needs. By introducing the second chip pads 213 with different lengths, the problem that the repair microchip 210 is prone to tipping when pressed onto the chip connection line structure can be improved.

[0090] Figure 13A is a top view schematic diagram of a display device according to an embodiment of the present invention. Figure 13B is Figure 13A a cross-sectional schematic diagram of lines A - A' and C - C' of Figure 13C is Figure 13A a top view schematic diagram of the microchip of Figure 13C wherein the first microchips 110A, 110B have the same top view shape, so only a single microchip is schematically shown in Figures 13A to 13CThe embodiments follow the component numbers and some content of the previous embodiments, where the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, reference can be made to the previous embodiments and will not be elaborated here.

[0091] Please refer to Figures 13A to 13C , a first chip connection line structure 120E and a plurality of second chip connection line structures 120B are on the insulating layer 130. The first chip connection line structure 120E extends from the chip placement area CA to a plurality of pixel areas PA around the chip placement area CA, while the second chip connection line structure 120B extends from the chip placement area CA to a signal source area (not shown). In Figure 13A , some of the pixel areas PA are located above the corresponding chip placement area CA, while another part of the pixel areas PA are located below the corresponding chip placement area CA.

[0092] In some embodiments, the first chip connection line structure 120E includes a first chip connection pad 122E, a first connection line 123E, a first repair pad 124E, and a signal output line 125E. The first chip connection pad 122E, the first connection line 123E, and the first repair pad 124E are disposed in the chip placement area CA. The first chip connection pad 122E is configured to connect a part of the first chip pads 113. In this embodiment, the first chip connection pad 122E of the first chip connection line structure 120E is directly formed on the first chip pad 113 and directly contacts at least a part of the first chip pad 113. The first connection line 123E connects the first chip connection pad 122E and the first repair pad 124E. The signal output line 125E connects the first repair pad 124E. In some embodiments, the signal output line 125E is connected to the first light-emitting diode bonding pad 132 in the pixel area PA and is electrically connected to the light-emitting elements D1, D2, D3 through the first light-emitting diode bonding pad 132.

[0093] In this embodiment, in the same first chip connection line structure 120E, the first repair pad 124E is closer to the corresponding light-emitting elements D1, D2, D3 than the first chip connection pad 122E. Such a design allows the first connection line 123E between the first repair pad 124E and the first chip connection pad 122 to be truncated by a cutting manufacturing process (such as laser cutting or other suitable cutting methods) before installing the repair microchip 210. Even if the first connection line 123E is truncated, the repair microchip 210 on the first repair pad 124E can still be electrically connected to the light-emitting elements D1, D2, D3 through the first repair pad 124E and the signal output line 125E.

[0094] In some embodiments, the second chip connection line structure 120B includes a second chip connection pad 122B, a second connection line 123B, a second repair pad 124B, and a signal input line 125B. The second chip connection pad 122B, the second connection line 123B, and the second repair pad 124B are disposed in the chip placement area CA. The second chip connection pad 122B is configured to connect to a first chip pad 113 of another part. In this embodiment, the second chip connection pad 122B of the second chip connection line structure 120B is directly formed on the first chip pad 113 and directly contacts at least a part of the first chip pad 113. The second connection line 123B connects the second chip connection pad 122B and the second repair pad 124B. The signal input line 125B connects to the second repair pad 124B and extends from the second repair pad 124B to a signal source area (not shown). In some embodiments, a signal source provides a signal to the first microchips 110A, 110B through the second chip connection line structure 120B.

[0095] In some embodiments, the second repair pad 124B is disposed between the second chip connection pad 122B and the signal input line 125B. Such a design allows, before installing the repair microchip 210, the second connection line 123B between the second repair pad 124B and the second chip connection pad 122B to be truncated by a cutting manufacturing process (such as laser cutting or other suitable cutting methods). This ensures that the first microchips 110A no longer receive input signals through the second chip connection line structure 120B, while the repair microchip 210 can still receive input signals from the signal source through the second repair pad 124B and the signal input line 125B.

[0096] In this embodiment, the repair microchip 210 has the same structural design as the first microchips 110A, 110B. Therefore, it is not necessary to redesign the microchip for the repair manufacturing process. For example, the relative positions of the second chip pads 213 on the repair microchip 210 with respect to each other are equal to the relative positions of the first chip pads 113 of the first microchips 110A, 110B with respect to each other. In some embodiments, the second chip pads 213 include a metal bump structure. For example, the second chip pads 213 include gold, copper, tin, silver, lead, indium, or other metal materials or combinations of the above materials.

[0097] In summary, in the display device of the present invention, the repair microchip can replace the failed microchip to output signals to the light-emitting elements, thereby improving the yield of the display device.

Claims

1. A display device, comprising: substrate; an insulating layer, located on the substrate; A plurality of first chip connection line structures are located on the insulating layer and extend from the chip placement area to a plurality of pixel areas around the chip placement area; A plurality of light emitting elements are respectively disposed in the pixel areas; a failed microchip located in the chip placement area, wherein the insulating layer laterally surrounds the failed microchip, and the failed microchip is at least partially connected to the first chip connection line structures; and The repair microchip is located in the chip placement area, wherein the repair microchip is electrically connected to the light emitting elements through the first chip connection line structures. 2 . The display device as claimed in claim 1 , wherein the failed microchip at least partially overlaps the repaired microchip in a direction perpendicular to the top surface of the substrate. The display device as claimed in claim 1 , wherein the repair microchip is located above the insulating layer.

4. The display device as claimed in claim 1, wherein at least one of the first chip connection line structures is cut to have a first signal disconnecting portion and a first signal connecting portion separated from each other, wherein the failed microchip is electrically connected to the first signal disconnecting portion, and the repaired microchip is electrically connected to the first signal connecting portion.

5. The display device according to claim 1, further comprising: A plurality of second chip connection line structures, wherein at least one of the second chip connection line structures is cut to have a second signal disconnection portion and a second signal connection portion separated from each other, wherein the failed microchip is electrically connected to the second signal disconnection portion, and the repair microchip is electrically connected to the second signal connection portion, wherein the first chip connection line structures are configured to provide data signals from the repair microchip to the light-emitting elements, and the second chip connection line structures are configured to provide input signals to the repair microchip. 6 . The display device as claimed in claim 1 , wherein the active surface of the failed microchip faces the active surface of the repaired microchip.

7. A display device as described in claim 1, wherein the failed microchip includes a plurality of first chip pads, which are arranged on the active surface of the failed microchip, wherein the active surface of the failed microchip includes two opposite first short sides and two opposite first long sides, wherein the center of each of the first chip pads deviates from the line connecting the midpoints of the two opposite first short sides, wherein the repair microchip includes a plurality of second chip pads, which are arranged on the active surface of the repair microchip, wherein the active surface of the repair microchip includes two opposite second short sides and two opposite second long sides, wherein the center of each of the second chip pads deviates from the line connecting the midpoints of the two opposite second short sides. 8 . The display device as claimed in claim 7 , wherein the first chip pads do not overlap the second chip pads in a direction perpendicular to the top surface of the substrate.

9. The display device as claimed in claim 1, wherein the failed microchip includes a plurality of first chip pads, and the first chip connection line structures directly contact at least a portion of the first chip pads, and wherein the repair microchip is bonded to the first chip connection line structures through a plurality of connection structures. 10 . The display device as claimed in claim 9 , wherein the connection structures comprise solder or conductive adhesive.

11. The display device as claimed in claim 1, wherein the failed microchip comprises a plurality of first chip pads arranged in a row, and the repaired microchip comprises a plurality of second chip pads arranged in a row. 12 . The display device as claimed in claim 1 , wherein the repair microchip comprises a plurality of second chip pads, and the chip pads have two or more lengths.

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