Assembly substrate, display device and manufacturing method thereof

Abstract

According to another aspect of the present disclosure, a manufacturing method of a display device includes: self-assembling a plurality of light emitting diodes on an assembly substrate; transferring the plurality of light emitting diodes self-assembled on the assembly substrate onto a donor; and transferring the plurality of light emitting diodes on the donor onto the adhesive layer of the display panel, wherein the step of self-assembling the plurality of light emitting diodes is a step of applying a voltage to the plurality of assembly electrodes to form an electric field and self-assembling the plurality of light emitting diodes on the plurality of assembly electrodes by using the electric field.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0165978, filed with the Korean Intellectual Property Office on November 24, 2023, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a method of manufacturing the same, and more particularly, to a display device using light - emitting diodes (LEDs) and a method of manufacturing the display device. Background Art

[0004] As display devices for displays of computers, televisions, cellular phones, etc., there are organic light - emitting display (OLED) devices that are self - emitting devices, liquid crystal display (LCD) devices that require a separate light source, etc.

[0005] The application scope of display devices is diverse, including personal digital assistants and displays of computers and televisions, and display devices with a large display area and reduced volume and weight are being studied.

[0006] In addition, recently, display devices including light - emitting diodes (LEDs) have been attracting attention as next - generation display devices. Since LEDs are formed of inorganic materials rather than organic materials, they have excellent reliability, so that their lifespan is longer than that of liquid crystal display devices or organic light - emitting display devices. In addition, LEDs have a fast lighting speed, excellent luminous efficiency, and strong impact resistance, so that they have excellent stability and can display images with high brightness. Summary of the Invention

[0007] One object to be achieved by the present disclosure is to provide a display device that minimizes brightness deviation according to viewing angles and a method of manufacturing a display device.

[0008] Another object to be achieved by the present disclosure is to provide a display device with improved brightness and a method of manufacturing a display device.

[0009] Still another object to be achieved by the present disclosure is to provide a display device that suppresses the transfer of defective light - emitting diodes and a method of manufacturing a display device.

[0010] Yet another object to be achieved by the present disclosure is to provide a display device in which light - emitting diodes and electrodes can be connected in all directions and a method of manufacturing a display device.

[0011] The objects of the present disclosure are not limited to the above - mentioned objects, and other objects not mentioned above can be clearly understood by those of ordinary skill in the art from the following description.

[0012] According to one aspect of the present disclosure, an assembling substrate includes: an assembly substrate; a plurality of first assembly lines disposed on the assembly substrate; a plurality of second assembly lines disposed on the assembly substrate and alternately disposed with the plurality of first assembly lines; and an organic layer disposed on the plurality of first assembly lines and the plurality of second assembly lines and including a plurality of openings, the plurality of openings including a plurality of first oval openings and a plurality of second oval openings having a different planar shape from the plurality of first oval openings, a plurality of unit areas formed by the plurality of first oval openings and the plurality of second oval openings are defined on the assembly substrate, and in the plurality of unit areas, the major axis directions of the plurality of openings in at least one unit area are different from those in adjacent unit areas.

[0013] According to another aspect of the present disclosure, a method of manufacturing a display device includes: self-assembling a plurality of light-emitting diodes on an assembling substrate; transferring the plurality of light-emitting diodes self-assembled on the assembling substrate to a donor; and transferring the plurality of light-emitting diodes on the donor to an adhesive layer of a display panel, and the self-assembling of the plurality of light-emitting diodes is performed by applying a voltage to a plurality of assembly electrodes to form an electric field and using the electric field to self-assemble the plurality of light-emitting diodes on the plurality of assembly electrodes. The plurality of light-emitting diodes includes a plurality of first oval light-emitting diodes and second oval light-emitting diodes having a different planar shape from the plurality of first oval light-emitting diodes, and self-assembling the plurality of light-emitting diodes on the assembling substrate includes assembling at least a part of the first oval light-emitting diodes in a direction different from that of adjacent first oval light-emitting diodes, and assembling at least a part of the second oval light-emitting diodes in a direction different from that of adjacent second oval light-emitting diodes.

[0014] According to one aspect of the present disclosure, a display device includes: a substrate on which a plurality of pixels including a plurality of sub-pixels are defined; and a plurality of light-emitting diodes disposed in the plurality of pixels, the plurality of light-emitting diodes including a plurality of oval light-emitting diodes, and in at least one of the plurality of pixels, the major axes of the plurality of oval light-emitting diodes can be disposed in a direction different from that of the plurality of oval light-emitting diodes disposed on an adjacent pixel. Accordingly, the plurality of light-emitting diodes are disposed in various directions to minimize the visibility of color and brightness stains visible from the display panel.

[0015] Other details of the exemplary embodiments are included in the detailed description and the drawings.

[0016] According to the present disclosure, the light-emitting area of the light-emitting diodes can be enlarged.

[0017] According to the present disclosure, only the undamaged light-emitting diodes are transferred to improve production efficiency.

[0018] According to the present disclosure, during self-assembly, even if multiple light-emitting diodes are self-assembled in various directions, the electrodes can be easily connected.

[0019] According to the present disclosure, during self-assembly, multiple light-emitting diodes are self-assembled in various directions, so that the visibility of color and brightness stains in the display panel can be minimized.

[0020] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in this specification. Description of the Drawings

[0021] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the drawings, in which:

[0022] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0023] Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0024] Figure 2B is a perspective view of a tiled display device according to an exemplary embodiment of the present disclosure;

[0025] Figure 3 is an enlarged plan view of a display device according to an exemplary embodiment of the present disclosure;

[0026] Figure 4 is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0027] Figures 5A to 5C is a view for explaining multiple light-emitting diodes of a display device according to an exemplary embodiment of the present disclosure;

[0028] Figure 6 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure;

[0029] Figures 7A to 7C is a view for explaining multiple light-emitting diodes of a display device according to another exemplary embodiment of the present disclosure;

[0030] Figures 8A to 8C is a view for explaining multiple light-emitting diodes of a display device according to still another exemplary embodiment of the present disclosure;

[0031] Figure 9 is a plan view of an assembly substrate according to an exemplary embodiment of the present disclosure;

[0032] Figure 10A is an enlarged plan view of an assembly substrate of a display device according to an exemplary embodiment of the present disclosure;

[0033] Figure 10B is a cross-sectional view of a display device taken along Figure 10A Xb-Xb' thereof;

[0034] Figures 11A to 11H is a process diagram for explaining a method of manufacturing a display device according to an exemplary embodiment of the present disclosure;

[0035] Figure 12 is a plan view of an assembly substrate according to another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] Advantages and features of the present disclosure and methods of achieving these advantages and features will be apparent by referring to exemplary embodiments described in detail below together with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure content of the present disclosure and the scope of the present disclosure.

[0037] Shapes, dimensions, ratios, angles, quantities, etc. illustrated in the drawings for describing exemplary embodiments of the present disclosure are only examples, and the present disclosure is not limited thereto. The same reference numerals generally denote the same elements throughout the specification. Additionally, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "comprising", "having", "consisting of" used herein generally intend to allow the addition of other components, unless the term is used together with the term "only". Any reference to the singular may include the plural, unless otherwise explicitly stated.

[0038] Even without explicit specification, components are construed to include a normal error range.

[0039] When describing the positional relationship between two parts using terms such as "on", "above", "below", "adjacent", one or more parts may be located between the two parts, unless the term is used together with the term "immediately" or "directly".

[0040] When an element or layer is disposed "on" another element or layer, yet another element or layer may be directly interposed on the other element or between the two.

[0041] Although terms such as "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Thus, the first component to be mentioned below may be the second component in the technical concept of the present disclosure.

[0042] Throughout the specification, the same reference numerals generally denote the same elements.

[0043] The sizes and thicknesses of the components illustrated in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the sizes and thicknesses of the illustrated components.

[0044] The features of the various embodiments of the present disclosure may be partially or wholly combined or incorporated with each other, may be associated and operated in various ways technically, and the embodiments may be implemented independently of each other or implemented in association with each other.

[0045] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the drawings.

[0046] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. In Figure 1 for convenience of description, among the various components of the display device 100, only the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC are illustrated.

[0047] Referring to Figure 1 , the display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD that supply various signals to the display panel PN, and a timing controller TC that controls the gate driver GD and the data driver DD.

[0048] The gate driver GD supplies a plurality of scan signals to a plurality of scan lines SL according to a plurality of gate control signals supplied from the timing controller TC. Even in Figure 1 it is illustrated that one gate driver GD is provided to be spaced apart from one side of the display panel PN, the number and arrangement of the gate drivers GD are not limited thereto.

[0049] The data driver DD converts the image data input from the timing controller TC into a data voltage using a reference gamma voltage according to a plurality of data control signals supplied from the timing controller TC. The data driver DD may supply the converted data voltage to a plurality of data lines DL.

[0050] The timing controller TC aligns the image data input from the outside to supply the image data to the data driver DD. The timing controller TC may use the synchronization signals (e.g., dot clock signal, data enable signal, and horizontal / vertical synchronization signal) input from the outside to generate a gate control signal and a data control signal. The timing controller TC supplies the generated gate control signal and data control signal to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0051] The display panel PN is configured to display an image to a user and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL cross each other, and the plurality of sub-pixels SP are respectively connected to the scan lines SL and the data lines DL. In addition, even if not illustrated in the drawings, each of the plurality of sub-pixels SP may be connected to a high potential power supply line, a low potential power supply line, a reference line, etc.

[0052] In the display panel PN, an active area AA and a non-active area NA surrounding the active area AA may be defined.

[0053] The active area AA is an area where an image is displayed in the display device 100. In the active area AA, a plurality of sub-pixels SP constituting a plurality of pixels PX and a circuit for driving the plurality of sub-pixels SP may be provided. The plurality of sub-pixels SP are the minimum units constituting the active area AA, and n sub-pixels SP may form one pixel PX. In each of the plurality of sub-pixels SP, a light emitting diode, a thin film transistor for driving the light emitting diode, etc. may be provided. The plurality of light emitting diodes may be defined in different ways according to the type of the display panel PN. For example, when the display panel PN is an inorganic light emitting display panel, the light emitting diode may be a light emitting diode (LED) or a micro light emitting diode (micro-LED).

[0054] In the active area AA, a plurality of signal lines for transmitting various signals to the plurality of sub-pixels SP are provided. For example, the plurality of signal lines include a plurality of data lines DL for supplying data voltages to each of the plurality of sub-pixels SP, a plurality of scan lines for supplying gate voltages to each of the plurality of sub-pixels SP, etc. The plurality of scan lines SL extend in one direction in the active area AA and are connected to the plurality of sub-pixels SP, and the plurality of data lines DL extend in a direction different from the one direction in the active area AA and are connected to the plurality of sub-pixels SP. In addition, in the active area AA, a low potential power supply line, a high potential power supply line, etc. may be further provided, but are not limited thereto.

[0055] The non-active region NA is a region where an image is not displayed, such that the non-active region NA can be defined as a region extending from the active region AA. In the non-active region NA, link lines, pad electrodes, or driving ICs (e.g., a gate driving IC or a data driving IC) that transmit signals to the sub-pixels SP of the active region AA can be provided. The non-active region NA can be located on the rear surface of the display panel PN (i.e., the surface on which the sub-pixels SP are not provided), or can be omitted, and is not limited by what is shown in the drawings.

[0056] Meanwhile, the drivers (e.g., the gate driver GD, the data driver DD, and the timing controller TC) can be connected to the display panel PN in various ways. For example, the gate driver GD can be mounted in the non-active region NA in a gate-in-panel (GIP) manner or between a plurality of sub-pixels SP in the active region AA in a gate-in-active (GIA) manner. For example, the data driver DD and the timing controller TC are formed in separate flexible films and printed circuit boards, and can be electrically connected to the display panel PN by bonding the flexible films and the printed circuit boards to the pad electrodes formed in the non-active region NA of the display panel PN. If the gate driver GD is mounted in the GIP manner and the data driver DD and the timing controller TC transmit signals to the display panel PN through the pad electrodes of the non-active region NA, it is necessary to ensure the area of the non-active region NA for setting the gate driver GD and the pad electrodes. Thus, the bezel may be increased.

[0057] On the contrary, when the gate driver GD is mounted in the GIA manner in the active region AA and the side line SRL that connects the signal lines on the front surface of the display panel PN to the pad electrodes on the rear surface of the display panel PN is formed to bond the flexible film and the printed circuit board to the rear surface of the display panel PN, the non-active region NA can be minimized on the front surface of the display panel PN. That is, when the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN as described above, a zero bezel without a bezel can be substantially achieved, which will be described in more detail with reference to Figure 2A and Figure 2B more specifically.

[0058] Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 2B is a perspective view of a tiled display device according to an exemplary embodiment of the present disclosure.

[0059] In the non-active region NA of the display panel PN, a plurality of pad electrodes are provided for transmitting various signals to a plurality of sub-pixels SP. For example, in the non-active region NA on the front surface of the display panel PN, a first pad electrode PAD1 for transmitting signals to the plurality of sub-pixels SP is provided. In the non-active region NA on the rear surface of the display panel PN, a second pad electrode PAD2 electrically connected to a driving component (such as a flexible film and a printed circuit board) is provided.

[0060] In this case, even if not illustrated in the drawings, various signal lines (such as a scan line SL or a data line DL) connected to the plurality of sub-pixels SP extend from the active region AA to the non-active region NA to be electrically connected to the first pad electrode PAD1.

[0061] Side lines SRL are provided along the side surfaces of the display panel PN. The side lines SRL can electrically connect the first pad electrode PAD1 on the front surface of the display panel PN and the second pad electrode PAD2 on the rear surface of the display panel PN. Therefore, signals from the driving component on the rear surface of the display panel PN can be transmitted to the plurality of sub-pixels SP through the second pad electrode PAD2, the side lines SRL, and the first pad electrode PAD1. Accordingly, a signal transmission path from the front surface to the side surfaces and the rear surface of the display panel PN is formed to minimize the area of the non-active region NA of the display panel PN.

[0062] Referring to Figure 2B , a tiled display device TD having a large screen size can be realized by connecting a plurality of display devices 100. At this time, as Figure 2A shows, when the tiled display device TD is realized using the display device 100 with a minimized bezel, the seam region where no image is displayed between the display devices 100 is minimized, thereby improving the display quality.

[0063] For example, a plurality of sub-pixels SP can form one pixel PX and the distance D1 between the outermost pixel PX of one display device 100 and the outermost pixel PX of another adjacent display device 100 can be made equal to the distance D1 between the pixels PX in one display device 100. Accordingly, the distance between the pixels PX between the display devices 100 is constantly configured to minimize the seam region.

[0064] However, Figure 2A and Figure 2B are illustrative, and thus the display device 100 according to an exemplary embodiment of the present disclosure can be a general display device with a bezel, but is not limited thereto.

[0065] Figure 3 is a schematic enlarged plan view of a display device according to an exemplary embodiment of the present disclosure. Figure 4It is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figures 5A to 5C It is a view for explaining a plurality of light-emitting diodes of a display device according to an exemplary embodiment of the present disclosure. For ease of explanation, Figure 3 the hatching of the second connection electrode CE2 is omitted.

[0066] First, refer to Figure 3 , the display panel PN includes a plurality of pixels PX formed of a plurality of sub-pixels SP. Each of the plurality of sub-pixels SP includes a light-emitting diode LED and a pixel circuit to emit light independently. One pixel PX may include one or more first sub-pixels SP1, one or more second sub-pixels SP2, and one or more third sub-pixels SP3. For example, one pixel PX may include two first sub-pixels SP1, two second sub-pixels SP2, and two third sub-pixels SP3. At this time, the first sub-pixel SP1 is a red sub-pixel, the second sub-pixel SP2 is a green sub-pixel, and the third sub-pixel SP3 is a blue sub-pixel, but they are not limited thereto.

[0067] Referring jointly to Figures 5A to 5C , the plurality of light-emitting diodes LED include a first light-emitting diode 120, a second light-emitting diode 130, and a third light-emitting diode 140. The first light-emitting diode 120 may be disposed in the first sub-pixel SP1, the second light-emitting diode 130 may be disposed in the second sub-pixel SP2, and the third light-emitting diode 140 may be disposed in the third sub-pixel SP3. For example, the first light-emitting diode 120 may be a red light-emitting diode, the second light-emitting diode 130 may be a green light-emitting diode, and the third light-emitting diode 140 may be a blue light-emitting diode, but the present disclosure is not limited thereto.

[0068] Referring to Figure 3 , the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 in which the first light-emitting diode 120, the second light-emitting diode 130, and the third light-emitting diode 140 are disposed may form one pixel PX. At this time, a pair of first sub-pixels SP1 in which a pair of first light-emitting diodes 120 are disposed, a pair of second sub-pixels SP2 in which a pair of second light-emitting diodes 130 are disposed, and a pair of third sub-pixels SP3 in which a pair of third light-emitting diodes 140 are disposed may constitute one pixel PX. However, the present disclosure is not limited thereto.

[0069] Meanwhile, each of the plurality of second light-emitting diodes 130 and the plurality of third light-emitting diodes 140 can be arranged on the display panel PN in various directions, for example, can be arranged in a random direction. For example, in one pixel PX, the major axes of the plurality of second light-emitting diodes 130 and the plurality of third light-emitting diodes 140 can be arranged in the row direction. In another pixel PX, the major axes of the plurality of second light-emitting diodes 130 and the plurality of third light-emitting diodes 140 can be arranged in the column direction. Additionally, in yet another pixel PX, the major axes of the plurality of second light-emitting diodes 130 and the plurality of third light-emitting diodes 140 can be arranged in a direction between the row direction and the column direction. Accordingly, in one pixel PX, the major axis of each of the second light-emitting diodes 130 and the third light-emitting diodes 140 can be arranged in a direction different from the major axis of each of the second light-emitting diodes 130 and the third light-emitting diodes 140 arranged in an adjacent pixel PX. Meanwhile, Figure 3 The arrangement of the plurality of light-emitting diodes LED shown in is illustrated for ease of explanation, but the present disclosure is not limited thereto. The major axes of the plurality of second light-emitting diodes 130 and the plurality of third light-emitting diodes 140 can be arranged in various directions, and in one pixel PX, the major axes of the plurality of second light-emitting diodes 130 and the plurality of third light-emitting diodes 140 can also be arranged in different directions.

[0070] will be described in detail below with reference to Figures 9 to 11G the arrangement of the plurality of light-emitting diodes LED.

[0071] Next, with reference to Figure 4 Together, in each of the plurality of sub-pixels SP of the display panel PN of the display device 100 according to an exemplary embodiment of the present disclosure, a substrate 110, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113, a second interlayer insulating layer 114, a first planarization layer 115, a passivation layer 116, an adhesive layer AD, a second planarization layer 117, a third planarization layer 118, a driving transistor DT, a light-emitting diode LED, a plurality of reflective electrodes RE, a plurality of connection electrodes CE, a light-shielding layer LS, and an auxiliary electrode LE are provided.

[0072] First, the substrate 110 is a component for supporting various components included in the display device 100 and can be formed of an insulating material. For example, the substrate 110 can be formed of glass or resin. Additionally, the substrate 110 can be configured to include a polymer or plastic or can be formed of a flexible material.

[0073] The light-shielding layer LS is disposed in each of a plurality of sub-pixels SP on the substrate 110. The light-shielding layer LS blocks light incident on the active layer ACT of the driving transistor DT, which will be described below, from below the substrate 110. The light incident on the active layer ACT of the driving transistor DT is blocked by the light-shielding layer LS to minimize leakage current.

[0074] A buffer layer 111 is disposed on the substrate 110 and the light-shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. For example, the buffer layer 111 may be composed of a single layer or a double layer of silicon oxide (SiO x ) or silicon nitride (SiN x ), but is not limited thereto. However, depending on the type of the substrate 110 or the type of the transistor, the buffer layer 111 may be omitted, but is not limited thereto.

[0075] The driving transistor DT is disposed on the buffer layer 111. The driving transistor DT includes an active layer ACT, a gate GE, a source SE, and a drain DE.

[0076] The active layer ACT is disposed on the buffer layer 111. The active layer ACT may be formed of a semiconductor material (e.g., an oxide semiconductor, amorphous silicon, or polysilicon), but is not limited thereto.

[0077] A gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer that insulates the active layer from the gate GE, and may be composed of a single layer or a double layer of silicon oxide (SiO x ) or silicon nitride (SiN x ), but is not limited thereto.

[0078] The gate GE is disposed on the gate insulating layer 112. The gate GE may be composed of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof), but is not limited thereto.

[0079] A first interlayer insulating layer 113 and a second interlayer insulating layer 114 are disposed on the gate GE. In the first interlayer insulating layer 113 and the second interlayer insulating layer 114, contact holes are formed through which the source SE and the drain DE are respectively connected to the active layer ACT. The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are insulating layers for protecting the components below the first interlayer insulating layer 113 and the second interlayer insulating layer 114, and may be composed of a single layer or a double layer of silicon oxide (SiO x ) or silicon nitride (SiN x ), but is not limited thereto.

[0080] The source SE and the drain DE electrically connected to the active layer ACT are disposed on the second interlayer insulating layer 114. The source SE and the drain DE may be made of a conductive material (such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof), but are not limited thereto.

[0081] Meanwhile, in the present disclosure, the first interlayer insulating layer 113 and the second interlayer insulating layer 114 are described, that is, a plurality of insulating layers are disposed between the gate GE and the source SE and the drain DE. However, only one insulating layer may be disposed between the gate GE and the source SE and the drain DE, but is not limited thereto.

[0082] As shown in the drawings, when a plurality of insulating layers (such as the first interlayer insulating layer 113 and the second interlayer insulating layer 114) are disposed between the gate GE and the source SE and the drain DE, an electrode may be further formed between the first interlayer insulating layer 113 and the second interlayer insulating layer 114. The additionally formed electrode may form a capacitor with other configurations disposed below the first interlayer insulating layer 113 or above the second interlayer insulating layer 114.

[0083] The auxiliary electrode LE is disposed on the gate insulating layer 112. The auxiliary electrode LE is an electrode that electrically connects the light-shielding layer LS below the buffer layer 111 to any one of the source SE and the drain DE on the second interlayer insulating layer 114. For example, the light-shielding layer LS is electrically connected to any one of the source SE and the drain DE through the auxiliary electrode LE so as not to operate as a floating gate. Therefore, the fluctuation of the threshold voltage of the driving transistor DT caused by the floating light-shielding layer LS can be minimized. Even if the light-shielding layer LS is described as being connected to the source SE in the drawings, the light-shielding layer LS may be connected to the drain DE, but is not limited thereto.

[0084] The power supply line VDD is disposed on the second interlayer insulating layer 114. The power supply line VDD is electrically connected to the light-emitting diode LED together with the driving transistor DT to cause the light-emitting diode LED to emit light. The power supply line VDD may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0085] The first planarization layer 115 is disposed on the driving transistor DT and the power supply line VDD. The first planarization layer 115 may planarize the upper portion of the substrate 110 on which the driving transistor DT is disposed. The first planarization layer 115 may be composed of a single layer or a double layer, and may be formed of, for example, a photoresist or an acrylic organic material, but is not limited thereto.

[0086] A plurality of reflection electrodes RE spaced apart from each other are provided on the first planarization layer 115. The plurality of reflection electrodes RE electrically connect the light-emitting diode LED to the power supply line VDD and the driving transistor DT, and at the same time, can be used as a reflector for reflecting the light emitted from the light-emitting diode LED to the upper part of the light-emitting diode LED. The plurality of reflection electrodes RE are formed of a conductive material having excellent reflectivity for reflecting the light emitted from the light-emitting diode LED toward the upper part of the light-emitting diode LED.

[0087] The plurality of reflection electrodes RE include a first reflection electrode RE1 and a second reflection electrode RE2. The first reflection electrode RE1 can electrically connect the driving transistor DT and the light-emitting diode LED. The first reflection electrode RE1 can be connected to the source SE or the drain DE of the driving transistor DT through a first contact hole CH1 formed in the first planarization layer 115. The first reflection electrode RE1 can be electrically connected to the first electrode and the first semiconductor layer of the light-emitting diode LED through a first connection electrode CE1 to be described below.

[0088] The second reflection electrode RE2 can electrically connect the power supply line VDD and the light-emitting diode LED. The second reflection electrode RE2 can be connected to the power supply line VDD through a second contact hole CH2 formed in the first planarization layer 115 and can be electrically connected to the p-type electrodes 125, 135, and 145 and the p-type semiconductor layers 123, 133, and 143 of the light-emitting diode LED through a second connection electrode CE2 to be described below.

[0089] A passivation layer 116 is provided on the plurality of reflection electrodes RE. In the passivation layer 116, a third contact hole CH3 through which the first connection electrode CE1 is connected to the first reflection electrode RE1 and a fourth contact hole CH4 through which the second connection electrode CE2 is connected to the second reflection electrode RE2 are provided. The passivation layer 116 is an insulating layer that protects the components below the passivation layer 116 and can be composed of a single layer or a double layer of silicon oxide (SiO x ) or silicon nitride (SiN x ), but is not limited thereto.

[0090] An adhesion layer AD is provided on the plurality of reflection electrodes RE. The adhesion layer AD is coated on the entire substrate 110 to fix the light-emitting diode LED provided on the adhesion layer AD. For example, the adhesion layer AD can be selected from any one of an adhesive polymer, an epoxy resist, a UV resin, a polyimide, an acrylate, a urethane, and polydimethylsiloxane (PDMS), but is not limited thereto.

[0091] A plurality of light-emitting diodes (LEDs) are disposed in each of a plurality of sub-pixels (SP) on an adhesive layer (AD). The plurality of light-emitting diodes (LEDs) are elements that emit light when an electric current is applied, and may include light-emitting diodes (LEDs) that emit red, green, blue, etc., and various colored lights including white can be achieved through their combination. For example, the plurality of light-emitting diodes (LEDs) may be light-emitting diodes (LEDs) or micro LEDs, but are not limited thereto.

[0092] Referring to Figure 4 and Figure 5A , the first light-emitting diode (120) includes a first n-type semiconductor layer (121), a first light-emitting layer (122), a first p-type semiconductor layer (123), a first n-type electrode (124), a first p-type electrode (125), and a first encapsulation layer (126).

[0093] The first n-type semiconductor layer (121) is disposed on the adhesive layer (AD), and the first p-type semiconductor layer (123) is disposed on the first n-type semiconductor layer (121). The first n-type semiconductor layer (121) and the first p-type semiconductor layer (123) can be formed by doping n-type impurities and p-type impurities into a specific material. For example, the first n-type semiconductor layer (121) and the first p-type semiconductor layer (123) may be layers in which n-type impurities and p-type impurities are doped into materials such as gallium nitride (GaN), aluminum indium phosphide (InAlP), or gallium arsenide (GaAs). The p-type impurities may be magnesium (Mg), zinc (Zn), beryllium (Be), etc., and the n-type impurities may be silicon (Si), germanium, tin (Sn), etc., but are not limited thereto.

[0094] The first light-emitting layer (122) is disposed between the first n-type semiconductor layer (121) and the first p-type semiconductor layer (123). The first light-emitting layer (122) is supplied with holes and electrons from the first n-type semiconductor layer (121) and the first p-type semiconductor layer (123) to emit light. The first light-emitting layer (122) may be formed of a single layer or a multi-quantum well (MQW) structure, and may be formed of indium gallium nitride (InGaN) or gallium nitride (GaN), for example, but is not limited thereto.

[0095] Referring to Figure 5A , the first light-emitting layer (122) and the first p-type semiconductor layer (123) are disposed at a distance from the first n-type electrode (124). At this time, a portion of the first light-emitting layer (122) and the first p-type semiconductor layer (123) opposite to the first n-type electrode (124) may be disposed along the periphery of the first n-type electrode (124). For example, as Figure 5AAs shown, when the circular first n-type electrode 124 is disposed at both ends of the first n-type semiconductor layer 121, the first light-emitting layer 122 and the first p-type semiconductor layer 123 may have a concave curved pattern corresponding to the first n-type electrode 124 at both ends of the first n-type semiconductor layer 121. At the same time, at the end of the first n-type semiconductor layer 121 where the first n-type electrode 124 is not disposed, the first light-emitting layer 122 and the first p-type semiconductor layer 123 may be disposed along the periphery of the first n-type semiconductor layer 121. Therefore, in a region other than the concave curved pattern of the first light-emitting layer 122 and the first p-type semiconductor layer 123, the first light-emitting layer 122 and the first p-type semiconductor layer 123 may have a convex curved shape along the periphery of the first n-type semiconductor layer 121.

[0096] More than two first n-type electrodes 124 are disposed on the first n-type semiconductor layer 121. The first n-type electrode 124 is an electrode that electrically connects the driving transistor DT and the first n-type semiconductor layer 121. The first n-type electrode 124 may be disposed on the top surface of the first n-type semiconductor layer 121 exposed from the first light-emitting layer 122 and the first p-type semiconductor layer 123. For example, the first n-type electrode 124 may be disposed adjacent to both ends of the top surface of the first n-type semiconductor layer 121 having a circular planar shape. The planar shape of the first n-type electrode 124 may be circular and / or elliptical. The first n-type electrode 124 may be made of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0097] The first p-type electrode 125 is disposed on the first p-type semiconductor layer 123. The first p-type electrode 125 may be disposed on the top surface of the first p-type semiconductor layer 123. The planar shape of the first p-type electrode 125 may be circular and / or elliptical. The first p-type electrode 125 is an electrode that electrically connects the power supply line VDD and the first p-type semiconductor layer 123. The first p-type electrode 125 may be made of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0098] Next, a first encapsulation layer 126 that surrounds the first n-type semiconductor layer 121, the first light-emitting layer 122, the first p-type semiconductor layer 123, the first n-type electrode 124, and the first p-type electrode 125 is provided. The first encapsulation layer 126 is formed of an insulating material to protect the first n-type semiconductor layer 121, the first light-emitting layer 122, and the first p-type semiconductor layer 123. In the first encapsulation layer 126, contact holes that expose the first n-type electrode 124 and the first p-type electrode 125 are formed to electrically connect the first connection electrode CE1 and the second connection layer CE2 to the first n-type electrode 124 and the first p-type electrode 125.

[0099] Referring to Figure 5B , the second light-emitting diode 130 includes a second n-type semiconductor layer 131, a second light-emitting layer 132, a second p-type semiconductor layer 133, a second n-type electrode 134, a second p-type electrode 135, and a second encapsulation layer 136.

[0100] The second n-type semiconductor layer 131 is disposed on the adhesive layer AD and the second p-type semiconductor layer 133 is disposed on the second n-type semiconductor layer 131. The second n-type semiconductor layer 131 and the second p-type semiconductor layer 133 may be formed by doping n-type and p-type impurities into a specific material. For example, the second n-type semiconductor layer 131 and the second p-type semiconductor layer 133 may be layers in which n-type and p-type impurities are doped into a material such as gallium nitride (GaN), aluminum indium phosphide (InAlP), or gallium arsenide (GaAs). The p-type impurity may be magnesium (Mg), zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium, tin (Sn), etc., but is not limited thereto.

[0101] The second light-emitting layer 132 is disposed between the second n-type semiconductor layer 131 and the second p-type semiconductor layer 133. The second light-emitting layer 132 is supplied with holes and electrons from the second n-type semiconductor layer 131 and the second p-type semiconductor layer 133 to emit light. The second light-emitting layer 132 may be formed of a single layer or a multi-quantum well (MQW) structure, and may be formed of indium gallium nitride (InGaN), gallium nitride (GaN), etc., but is not limited thereto.

[0102] Referring to Figure 5B , the second light-emitting layer 132 and the second p-type semiconductor layer 133 are disposed to be spaced apart from the second n-type electrode 134. At this time, a part of the side surface of the second light-emitting layer 132 and the side surface of the second p-type semiconductor layer 133 that faces the second n-type electrode 134 may be disposed along the periphery of the second n-type electrode 134. For example, as Figure 5BAs shown, when the circular second n-type electrode 134 is disposed at both ends of the second n-type semiconductor layer 131, the second light-emitting layer 132 and the second p-type semiconductor layer 133 may have a concave curved pattern corresponding to the second n-type electrode 134 at both ends of the second n-type semiconductor layer 131. At the same time, at the end of the second n-type semiconductor layer 131 where the second n-type electrode 134 is not disposed, the second light-emitting layer 132 and the second p-type semiconductor layer 133 may be disposed along the periphery of the second n-type semiconductor layer 131. Therefore, in a region other than the concave curved pattern of the second light-emitting layer 132 and the concave curved pattern of the second p-type semiconductor layer 133, the second light-emitting layer 132 and the second p-type semiconductor layer 133 may have a convex curved shape along the periphery of the second n-type semiconductor layer 131.

[0103] More than two second n-type electrodes 134 are disposed on the second n-type semiconductor layer 131. The second n-type electrode 134 is an electrode that electrically connects the driving transistor DT and the second n-type semiconductor layer 131. The second n-type electrode 134 may be disposed on the top surface of the second n-type semiconductor layer 131 exposed from the second light-emitting layer 132 and the second p-type semiconductor layer 133. For example, on the top surface of the second n-type semiconductor layer 131 formed in an oval shape in a plan view, the second n-type electrode 134 may be disposed adjacent to both ends of the top surface of the second n-type semiconductor layer 131 in the major axis direction. The planar shape of the second n-type electrode 134 may be circular and / or oval. The second n-type electrode 134 may be made of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0104] The second p-type electrode 135 is disposed on the second p-type semiconductor layer 133. The second p-type electrode 135 may be disposed on the top surface of the second p-type semiconductor layer 133. The planar shape of the second p-type electrode 135 may be circular and / or oval. The second p-type electrode 135 is an electrode that electrically connects the power supply line VDD and the second p-type semiconductor layer 133. The second p-type electrode 135 may be made of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0105] Next, a second encapsulation layer 136 that surrounds the second n-type semiconductor layer 131, the second light-emitting layer 132, the second p-type semiconductor layer 133, the second n-type electrode 134, and the second p-type electrode 135 is provided. The second encapsulation layer 136 is formed of an insulating material to protect the second n-type semiconductor layer 131, the second light-emitting layer 132, and the second p-type semiconductor layer 133. In the second encapsulation layer 136, contact holes that expose the second n-type electrode 134 and the second p-type electrode 135 are formed to electrically connect the first connection electrode CE1 and the second connection electrode CE2 to the second n-type electrode 134 and the second p-type electrode 135.

[0106] Referring to Figure 5C , the third light-emitting diode 140 includes a third n-type semiconductor layer 141, a third light-emitting layer 142, a third p-type semiconductor layer 143, a third n-type electrode 144, a third p-type electrode 145, and a third encapsulation layer 146.

[0107] The third n-type semiconductor layer 141 is disposed on the adhesive layer AD and the third p-type semiconductor layer 143 is disposed on the third n-type semiconductor layer 141. The third n-type semiconductor layer 141 and the third p-type semiconductor layer 143 can be formed by doping n-type and p-type impurities into a specific material. For example, the third n-type semiconductor layer 141 and the third p-type semiconductor layer 143 can be layers in which n-type impurities and p-type impurities are doped into a material such as gallium nitride (GaN), aluminum indium phosphide (InAlP), or gallium arsenide (GaAs). The p-type impurities can be magnesium (Mg), zinc (Zn), beryllium (Be), etc., and the n-type impurities can be silicon (Si), germanium, tin (Sn), etc., but are not limited thereto.

[0108] The third light-emitting layer 142 is disposed between the third n-type semiconductor layer 141 and the third p-type semiconductor layer 143. The third light-emitting layer 142 is supplied with holes and electrons from the third n-type semiconductor layer 141 and the third p-type semiconductor layer 143 to emit light. The third light-emitting layer 142 can be formed of a single layer or a multi-quantum well (MQW) structure, and for example, can be formed of indium gallium nitride (InGaN), gallium nitride (GaN), etc., but is not limited thereto.

[0109] Referring to Figure 5C , the third light-emitting layer 142 and the third p-type semiconductor layer 143 are disposed to be spaced apart from the third n-type electrode 134. At this time, a part of the side surface of the third light-emitting layer 142 and the side surface of the third p-type semiconductor layer 143 that faces the third n-type electrode 144 can be disposed along the periphery of the third n-type electrode 144. For example, as Figure 5CAs shown, when the circular third n-type electrode 144 is disposed at both ends of the third n-type semiconductor layer 141, the third light-emitting layer 142 and the third p-type semiconductor layer 143 may have concave curved patterns corresponding to the third n-type electrode 144 at both ends of the third n-type semiconductor layer 141. At the same time, at the end of the third n-type semiconductor layer 141 where the third n-type electrode 144 is not disposed, the third light-emitting layer 142 and the third p-type semiconductor layer 143 may be disposed along the periphery of the third n-type semiconductor layer 141. Therefore, in a region other than the concave curved pattern of the third light-emitting layer 142 and the concave curved pattern of the third p-type semiconductor layer 143, the third light-emitting layer 142 and the third p-type semiconductor layer 143 may have a convex curved shape along the periphery of the third n-type semiconductor layer 141.

[0110] The third n-type electrode 144 is disposed on the third n-type semiconductor layer 141. The third n-type electrode 144 is an electrode that electrically connects the driving transistor DT and the third n-type semiconductor layer 141. The third n-type electrode 144 may be disposed on the top surface of the third n-type semiconductor layer 141 exposed from the third light-emitting layer 142 and the third p-type semiconductor layer 143. For example, on the top surface of the third n-type semiconductor layer 141 formed in an elliptical planar shape, the third n-type electrode 144 may be disposed adjacent to two ends of the top surface of the third n-type semiconductor layer 141 in the major axis direction. The planar shape of the third n-type electrode 144 may be circular and / or elliptical. The third n-type electrode 144 may be made of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0111] The third p-type electrode 145 is disposed on the third p-type semiconductor layer 143. The third p-type electrode 145 may be disposed on the top surface of the third p-type semiconductor layer 143. The planar shape of the third p-type electrode 145 may be circular and / or elliptical. The third p-type electrode 145 is an electrode that electrically connects the power supply line VDD and the third p-type semiconductor layer 143. The third p-type electrode 145 may be made of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0112] Next, a third encapsulation layer 146 surrounding the third n-type semiconductor layer 141, the third light-emitting layer 142, the third p-type semiconductor layer 143, the third n-type electrode 144, and the third p-type electrode 145 is provided. The third encapsulation layer 146 is formed of an insulating material to protect the third n-type semiconductor layer 141, the third light-emitting layer 142, and the third p-type semiconductor layer 143. In the third encapsulation layer 146, contact holes exposing the third n-type electrode 144 and the third p-type electrode 145 are formed to electrically connect the first connection electrode CE1 and the second connection layer CE2 to the third n-type electrode 144 and the third p-type electrode 145.

[0113] Meanwhile, the first light-emitting diode 120, the second light-emitting diode 130, and the third light-emitting diode 140 may be formed in different shapes. Each of the plurality of light-emitting diodes LED generally includes an n-type semiconductor layer 121, 131, and 141, a light-emitting layer 122, 132, and 142, a p-type semiconductor layer 123, 133, and 143, an n-type electrode 124, 134, and 144, a p-type electrode 125, 135, and 145, and an encapsulation layer 126, 136, and 146. However, some components may have different shapes.

[0114] For example, the planar shape of the first n-type semiconductor layer 121 of the first light-emitting diode 120 may be a circular shape. The planar shape of the second n-type semiconductor layer 131 of the second light-emitting diode 130 may be an elliptical shape. The planar shape of the third n-type semiconductor layer 141 of the third light-emitting diode 140 may be an elliptical shape. For example, the ratio of the major axis to the minor axis of the third light-emitting diode 140 may be different from the ratio of the major axis to the minor axis of the second light-emitting diode 130. The major axis of the third light-emitting diode 140 may be longer than the major axis of the second light-emitting diode 130 and the minor axis of the third light-emitting diode 140 may be shorter than the minor axis of the second light-emitting diode 130, but the present disclosure is not limited thereto.

[0115] In the display device 100 according to an exemplary embodiment of the present disclosure, to distinguish the plurality of light-emitting diodes LED, the first light-emitting diode 120 is configured as a circular light-emitting diode, the second light-emitting diode 130 is configured as a first elliptical light-emitting diode, and the third light-emitting diode 140 is configured as a second elliptical light-emitting diode having a planar shape different from that of the second light-emitting diode 130. For example, when the light-emitting diodes LED are self-assembled, the plurality of light-emitting diodes LED are formed in different shapes to be self-assembled at positions corresponding to each of the plurality of sub-pixels SP. However, the shapes of the plurality of light-emitting diodes LED are illustrative and thus not limited thereto.

[0116] Multiple light-emitting diodes (LEDs) can be arranged in various directions on the display panel (PN). For example, the major axis direction of the second light-emitting diode 130 in one pixel (PX) can be different from that of the second light-emitting diode 130 in an adjacent pixel (PX). Additionally, the major axis direction of the third light-emitting diode 140 in one pixel (PX) can be different from that of the third light-emitting diode 140 in an adjacent pixel (PX).

[0117] Meanwhile, as Figure 3 shown, the arrangement directions of the multiple first light-emitting diodes 120, multiple second light-emitting diodes 130, and multiple third light-emitting diodes 140 are illustrative only and are not limited thereto. Even though Figure 3 shows that all the major axis directions of the second light-emitting diode 130 and the third light-emitting diode 140 provided in the same pixel (PX) are arranged along the same direction respectively, it is not limited thereto. Therefore, the major axis directions of the second light-emitting diode 130 and the third light-emitting diode 140 can be set differently in the same pixel (PX).

[0118] The second planarization layer 117 and the third planarization layer 118 are provided on the adhesive layer (AD). The second planarization layer 117 overlaps with a part of the side surface portions of the multiple light-emitting diodes (LEDs) to fix and protect the multiple light-emitting diodes (LEDs). Specifically, the thickness of the second planarization layer 117 can be less than the thicknesses of the n-type semiconductor layers 121, 131, and 141 of the multiple light-emitting diodes (LEDs). For example, the top surface of the second planarization layer 117 can be provided below the light-emitting layers 122, 132, and 142.

[0119] The second planarization layer 117 can be arranged to surround the lower side surfaces of the n-type semiconductor layers 121, 131, and 141 extending from the bottom surfaces of the n-type semiconductor layers 121, 131, and 141 of the multiple light-emitting diodes (LEDs) on the adhesive layer (AD).

[0120] Meanwhile, during the process of separating the multiple light-emitting diodes (LEDs) from the wafer, a part of the lower edges of the encapsulation layers 126, 136, and 146 of the multiple light-emitting diodes (LEDs) may be peeled off. Additionally, when the first electrode (CE1) is formed to surround the side surface of the encapsulation layer 126, there may be a failure that the first connection electrode (CE1) is disconnected at the peeled-off portion of the encapsulation layers 126, 136, and 146. Therefore, when the second planarization layer 117 surrounds the lower side surfaces of the multiple light-emitting diodes (LEDs) before forming the first connection electrode (CE1), the lower parts of the multiple light-emitting diodes (LEDs) can be spaced apart from the first connection electrode (CE1) and the disconnection of the first connection electrode (CE1) can be minimized.

[0121] The first connection electrode CE1 is disposed on the second planarization layer 117. The first connection electrode CE1 is an electrode disposed in each of the plurality of sub-pixels SP to electrically connect the light-emitting diode LED and the driving transistor DT. The first connection electrode CE1 can be connected to the first reflective electrode RE1 through a third contact hole CH3 formed in the second planarization layer 117, the adhesive layer AD, and the passivation layer 116. Therefore, the first connection electrode CE1 can be electrically connected to either the source SE or the drain DE of the driving transistor DT through the first reflective electrode RE1. The first connection electrode CE1 can be connected to the n-type electrodes 124, 134, and 144 of each of the plurality of light-emitting diodes LED. Therefore, the first connection electrode CE1 can electrically connect the driving transistor DT to the n-type electrodes 124, 134, and 144 of the plurality of light-emitting diodes LED and the n-type semiconductor layers 121, 131, and 141.

[0122] The first connection electrode CE1 can be arranged to surround the side surfaces of the plurality of light-emitting diodes LED. When manufacturing the display device 100, even if the second light-emitting diode 130 and the third light-emitting diode 140 are arranged in various directions, the first connection electrode CE1 can be connected to the n-type electrodes 124, 134, and 144 through the second planarization layer 117.

[0123] The third planarization layer 118 is disposed on the first connection electrode CE1 and the plurality of light-emitting diodes LED. The third planarization layer 118 can flatten the upper part of the substrate 110 where the plurality of light-emitting diodes LED are disposed and fix the plurality of light-emitting diodes LED together with the adhesive layer AD to the substrate 110. The second planarization layer 117 and the third planarization layer 118 can be composed of a single layer or a double layer. For example, they can be formed of a photoresist or an acrylic organic material, but are not limited thereto.

[0124] The top surface of the third planarization layer 118 can be arranged to be at least higher than the light-emitting layers 122, 132, and 142 of the plurality of light-emitting diodes LED, and can be arranged to be at the same height as or lower than the top surfaces of the p-type semiconductor layers 123, 133, and 143. For example, the top surface of the third planarization layer 118 corresponding to the plurality of light-emitting diodes LED is disposed between the top surfaces of the light-emitting layers 122, 132, and 142 and the p-type semiconductor layers 123, 133, and 143, or on the same plane as the top surfaces of the p-type semiconductor layers 123, 133, and 143. Therefore, when manufacturing the display device 100, the second connection electrode CE2 can be connected to only the p-type semiconductor layers 123, 133, and 143 using the third planarization layer 118.

[0125] The second planarization layer 117 and the third planarization layer 118 may be composed of a single layer or a double layer, and may be formed of, for example, photoresist or acrylic organic material, but is not limited thereto. Although the second planarization layer 117 and the third planarization layer 118 are described in the present disclosure, the planarization layer may also be formed of a single layer, but the present disclosure is not limited thereto.

[0126] The second connection electrode CE2 is disposed on the third planarization layer 118. The second connection electrode CE2 is an electrode for electrically connecting the light-emitting diode LED and the power supply line VDD. The second connection electrode CE2 may be connected to the second reflective electrode RE2 through a fourth contact hole CH4 formed in the third planarization layer 118, the second planarization layer 117, the adhesive layer AD, and the passivation layer 116. Therefore, the second connection electrode CE2 may be electrically connected to the power supply line VDD through the second reflective electrode RE2. The second connection electrode CE2 may be connected to the p-type electrodes 125, 135, and 145 of the plurality of light-emitting diodes LED through a contact hole formed in the third planarization layer 118. Therefore, the second connection electrode CE2 may electrically connect the power supply line VDD and the p-type electrodes 125, 135, and 145 of the plurality of light-emitting diodes LED and the p-type semiconductor layers 123, 133, and 143.

[0127] Meanwhile, the first connection electrode CE1 that connects the driving transistor DT and the light-emitting diode LED provided in each of the plurality of sub-pixels SP may be separately provided in each of the plurality of sub-pixels SP. The second connection electrode CE2 provided in each of the plurality of sub-pixels SP to connect the power supply line VDD and the light-emitting diode LED may be connected to each other. That is, the power supply voltage of the power supply line VDD is commonly applied to all the plurality of light-emitting diodes LED of the plurality of sub-pixels SP, so that one second connection electrode CE2 may be provided in all the plurality of sub-pixels SP.

[0128] Meanwhile, the display device 100 according to an exemplary embodiment of the present disclosure may be manufactured by transferring a plurality of self-assembled light-emitting diodes LED from the assembly substrate 200 to the display panel PN using a donor 300 after self-assembling the plurality of light-emitting diodes LED on a separate assembly substrate.

[0129] Meanwhile, the viewing angle brightness characteristics of the plurality of light-emitting diodes may be affected by the shape of the light-emitting diodes. For example, viewing angle brightness deviation may be caused according to the shapes of the plurality of electrodes and the plurality of semiconductor layers provided in the plurality of light-emitting diodes. For example, when the angles, positions, widths, and sizes of the plurality of electrodes and the plurality of semiconductor layers are changed, the brightness of each viewing angle may change. Therefore, the viewing angle brightness may change according to the shape deviation of each of the plurality of light-emitting diodes.

[0130] For example, when the light generated from a light-emitting diode travels in the direction of the side surface of the light-emitting diode, the traveling direction of the light may change on the side surface of the light-emitting diode. Specifically, the brightness distribution according to the viewing angle of the light-emitting diode may vary according to the inclination angle of a region (i.e., the side surfaces of the second semiconductor layer and the active layer) of the light-emitting diode called the mesa unit.

[0131] The mesa unit of the light-emitting diode can be formed by a mesa etching process, and the inclined surface of the mesa unit of the light-emitting diode can be formed by a mesa etching process. At the same time, after the mesa etching process, each process for forming the light-emitting diode is performed, and the mesa unit of the light-emitting diode can be exposed during various processes. For example, after the mesa etching process, an isolation process for etching the wafer and the semiconductor layer provided on the wafer to separate the light-emitting diode can be performed. At this time, the isolation process refers to a process of etching a region corresponding to the outer peripheral region of the light-emitting diode to separate the light-emitting diode from the wafer. Therefore, the etching process performed in the isolation process is performed on the region other than the mesa unit. However, when there is a process deviation, the mesa unit may be exposed to the isolation process. For example, when a photoresist is used as a mask, one side of the mesa unit may be covered by the photoresist due to a process error, but the other side of the mesa unit may be exposed due to the difference in the area covered by the photoresist. Therefore, the mesa unit not covered by the photoresist due to the process deviation of the photoresist may be etched together with the wafer and the semiconductor layer provided on the wafer. In this case, the inclination angle of the inclined surface of the mesa unit exposed by the isolation process may be different from the inclination angle of the inclined surface of the mesa unit covered by the photoresist, and there may be a deviation in the inclination angle of the inclined surface of the mesa unit.

[0132] Specifically, in a structure where multiple light-emitting diodes are asymmetric, the variation range of the viewing angle brightness according to the shape deviation of the light-emitting diodes may be more significant. For example, the variation range of the viewing angle brightness according to the inclination angle deviation of the mesa unit in a light-emitting diode with an asymmetric shape may be greater than the variation range of the viewing angle brightness according to the inclination angle deviation of the mesa unit in a light-emitting diode with a symmetric shape.

[0133] In addition, in the case of the same process error, when the light-emitting diode is formed in an asymmetric shape including a major axis and a minor axis, the inclination angle deviation of the mesa unit generated in the major axis direction of the light-emitting diode may be different from the inclination angle deviation of the mesa unit generated in the minor axis direction of the light-emitting diode. Therefore, when multiple light-emitting diodes are formed in an elliptical shape, the viewing angle brightness characteristics in the minor axis direction of the light-emitting diode may be different from the viewing angle brightness characteristics in the major axis direction.

[0134] Meanwhile, on the display panel, all of the plurality of light-emitting diodes can be set to be aligned in the same direction. For example, when the plurality of light-emitting diodes are formed to have an elliptical shape, all of the major axis directions of the plurality of light-emitting diodes can be set along the same direction. Accordingly, on the display panel, the brightness characteristics in a corresponding direction may be different from those in another direction. Therefore, when all of the plurality of light-emitting diodes are aligned in the same direction, due to the brightness asymmetry characteristics of the plurality of light-emitting diodes, the brightness asymmetry characteristics may be visible in the display device.

[0135] Accordingly, in the display device 100 according to an exemplary embodiment of the present disclosure, the plurality of light-emitting diodes LED can be arranged in various directions. For example, the major axes of the second light-emitting diode 130 and the third light-emitting diode 140 can be arranged in different directions in each pixel PX, respectively. Accordingly, even if the plurality of light-emitting diodes LED are formed to have an asymmetrical shape, the plurality of light-emitting diodes LED are arranged in various directions in the display panel PN, such that the viewing angle deviation and the brightness deviation generated in a specific direction can be reduced. Accordingly, in the display device 100 according to an exemplary embodiment of the present disclosure, the plurality of light-emitting diodes LED are aligned in various directions to minimize the color difference and the stain caused by the viewing angle change and to improve the color uniformity.

[0136] Figure 6 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. Figures 7A to 7C is a view for explaining the plurality of light-emitting diodes of a display device according to another exemplary embodiment of the present disclosure. In Figure 6 , Figures 7A to 7C the display device 600, only the plurality of light-emitting diodes LED, the second planarization layer 617, the third planarization layer 618, and the second connection electrode CE2 are different from Figures 1 to 5C the display device 100. Other configurations are substantially the same, and thus redundant descriptions will be omitted.

[0137] With reference to Figure 6 and Figure 7A , the first light-emitting diode 620 includes a first n-type semiconductor layer 621, a first light-emitting layer 622, a first p-type semiconductor layer 623, a first n-type electrode 624, a first p-type electrode 625, and a first encapsulation layer 626.

[0138] The first light-emitting layer 622 and the first p-type semiconductor layer 623 are disposed on the first n-type semiconductor layer 621. The first n-type electrode 624 is disposed at one end of the first n-type semiconductor layer 621 and the first p-type electrode 625 is disposed at the other end of the first n-type semiconductor layer 621.

[0139] All of the planar shapes of the first n-type semiconductor layer 621 of the first light-emitting diode 620 can be circular shapes.

[0140] The planar shape of the first n-type electrode 624 may correspond to a partial shape of a circle. For example, a side surface of the first n-type electrode 624 adjacent to one end of the first n-type semiconductor layer 621 may be formed by a curved surface corresponding to the side surface of the first n-type semiconductor layer 621. In addition, a side surface of the first n-type electrode 624 adjacent to the other end of the first n-type semiconductor layer 621 may be formed by a plane connecting the side surfaces of the curved first n-type electrode 624.

[0141] The first light-emitting layer 622 and the first p-type semiconductor layer 623 are provided to be spaced apart from the first n-type electrode 624. At this time, the first light-emitting layer 622 and the first p-type semiconductor layer 623 may be provided along the periphery of the first n-type electrode 624. For example, as Figure 7A shown, when the semi-circular first n-type electrode 624 is provided at one end of the first n-type semiconductor layer 621, side surfaces of the first light-emitting layer 622 and the first p-type semiconductor layer 623 opposite to the first n-type electrode 624 may be formed by planes. At the same time, at the end of the first n-type semiconductor layer 621 where the first n-type electrode 624 is not provided, the first light-emitting layer 622 and the first p-type semiconductor layer 623 may be provided along the periphery of the first n-type semiconductor layer 621. Therefore, the first light-emitting layer 622 and the first p-type semiconductor layer 623 may include side surfaces formed as curved surfaces along the periphery of the first n-type semiconductor layer 621.

[0142] The first p-type electrode 625 is provided on the first p-type semiconductor layer 623.

[0143] Next, a first encapsulation layer 626 surrounding the first n-type semiconductor layer 621, the first light-emitting layer 622, the first p-type semiconductor layer 623, the first n-type electrode 624, and the first p-type electrode 625 is provided.

[0144] Referring to Figure 7B , the second light-emitting diode 630 includes a second n-type semiconductor layer 631, a second light-emitting layer 632, a second p-type semiconductor layer 633, a second n-type electrode 634, a second p-type electrode 635, and a second encapsulation layer 636.

[0145] The second light-emitting layer 632 and the second p-type semiconductor layer 633 are provided on the second n-type semiconductor layer 631. The second n-type electrode 634 is provided at one end of the second n-type semiconductor layer 631 and the second p-type electrode 635 is provided at the other end of the second n-type semiconductor layer 631.

[0146] The planar shape of the second n-type semiconductor layer 631 of the second light-emitting diode 630 may be an elliptical shape.

[0147] The planar shape of the second n-type electrode 634 may correspond to a partial shape of an ellipse. For example, a side surface of the second n-type electrode 634 adjacent to one end of the second n-type semiconductor layer 631 may be formed by a curved surface corresponding to the side surface of the second n-type semiconductor layer 631. In addition, a side surface of the second n-type electrode 634 adjacent to the other end of the second n-type semiconductor layer 631 may be formed by a plane connecting the side surfaces of the curved second n-type electrode 634.

[0148] At this time, the second light-emitting layer 632 and the second p-type semiconductor layer 633 are spaced apart from the second n-type electrode 634 and may be disposed along the periphery of the second n-type electrode 634. For example, as Figure 7B shown, side surfaces of the second light-emitting layer 632 and the second p-type semiconductor layer 633 opposite to the second n-type electrode 634 may be formed by planes. Meanwhile, at the other end of the second n-type semiconductor layer 631 where the second n-type electrode 634 is not provided, the second light-emitting layer 632 and the second p-type semiconductor layer 633 may be disposed along the periphery of the second n-type semiconductor layer 631. Therefore, the side surfaces of the second light-emitting layer 632 and the second p-type semiconductor layer 633 may be formed as convex curved surfaces along the periphery of the second n-type semiconductor layer 631.

[0149] The second p-type electrode 635 is provided on the second p-type semiconductor layer 633.

[0150] Next, a second encapsulation layer 636 surrounding the second n-type semiconductor layer 631, the second light-emitting layer 632, the second p-type semiconductor layer 633, the second n-type electrode 634, and the second p-type electrode 635 is provided.

[0151] Referring to Figure 7C , the third light-emitting diode 640 includes a third n-type semiconductor layer 641, a third light-emitting layer 642, a third p-type semiconductor layer 643, a third n-type electrode 644, a third p-type electrode 645, and a third encapsulation layer 646.

[0152] The third light-emitting layer 642 and the third p-type semiconductor layer 643 are provided on the third n-type semiconductor layer 641. The third n-type electrode 644 is provided at one end of the third n-type semiconductor layer 641 and the third p-type electrode 645 is provided at the other end of the third n-type semiconductor layer 641.

[0153] The planar shape of the third n-type semiconductor layer 641 of the third light-emitting diode 640 may be formed by an elliptical shape different from the planar shape of the second n-type semiconductor layer 631 of the second light-emitting diode 630.

[0154] The planar shape of the third n-type electrode 644 may correspond to a partial shape of an ellipse. For example, a side surface of the third n-type electrode 644 adjacent to one end of the third n-type semiconductor layer 641 may be formed by a curved surface corresponding to the side surface of the third n-type semiconductor layer 641. In addition, a side surface of the third n-type electrode 644 adjacent to the other end of the third n-type semiconductor layer 641 may be formed by a plane connecting the side surfaces of the curved third n-type electrode 644.

[0155] The third light-emitting layer 642 and the third p-type semiconductor layer 643 are spaced apart from the third n-type electrode 644 and may be disposed along the periphery of the third n-type electrode 644. For example, as Figure 7C shown, side surfaces of the third light-emitting layer 642 and the third p-type semiconductor layer 643 opposite to the third n-type electrode 644 may be formed by planes. Meanwhile, at the other end of the third n-type semiconductor layer 641 where the third n-type electrode 644 is not provided, the third light-emitting layer 642 and the third p-type semiconductor layer 643 may be disposed along the periphery of the third n-type semiconductor layer 641. Accordingly, the side surfaces of the third light-emitting layer 642 and the side surfaces of the third p-type semiconductor layer 643 may be formed as convex curved surfaces along the periphery of the third n-type semiconductor layer 641.

[0156] The third p-type electrode 645 is disposed on the third p-type semiconductor layer 643.

[0157] Next, a third encapsulation layer 646 is provided to surround the third n-type semiconductor layer 641, the third light-emitting layer 642, the third p-type semiconductor layer 643, the third n-type electrode 644, and the third p-type electrode 645.

[0158] The second planarization layer 617 is disposed on the adhesive layer AD and the first connection electrode CE1 is disposed on the second planarization layer 617. The first connection electrode CE1 is disposed on one side of the plurality of light-emitting diodes LED and is connected to the n-type electrodes 624, 634, and 644 of the plurality of light-emitting diodes LED. The first connection electrode CE1 may be electrically connected to the driving transistor DT, the n-type electrodes 624, 634, and 644 of the plurality of light-emitting diodes LED, and the n-type semiconductor layers 621, 631, and 641, respectively.

[0159] The third planarization layer 618 is disposed on the first connection electrode CE1 and the plurality of light-emitting diodes LED.

[0160] In the display device 600 according to another exemplary embodiment of the present disclosure, the plurality of light-emitting diodes LED may be disposed in various directions. Accordingly, color differences and stains caused by a change in the viewing angle of the display panel PN may be minimized and color uniformity may be improved.

[0161] Meanwhile, during the self-assembly process, multiple light-emitting diodes dispersed in a fluid may collide with each other and may collide with the assembly substrate during the assembly process. Therefore, a part of the multiple light-emitting diodes may break due to the impact. For example, when n-type electrodes formed of a magnetic material are provided on both sides of a light-emitting diode, the n-type electrode provided on one side of the light-emitting diode may break at the boundary with the p-type electrode.

[0162] Meanwhile, when a voltage is applied to multiple assembly lines AL and multiple assembly electrodes AE, a part of the broken light-emitting diode containing the magnetic material can be assembled in the opening of the assembly substrate. In addition, when a second light-emitting diode and a third light-emitting diode having a larger size than the first light-emitting diode among the multiple light-emitting diodes break, a part of the broken second light-emitting diode and third light-emitting diode can be assembled in the area where the first light-emitting diode is assembled. Therefore, when a part of the broken light-emitting diode with the n-type electrode and the p-type electrode left is assembled at the position of the light-emitting diode to emit light in different colors, dark spots and / or bright spot failures may occur in the display panel.

[0163] Therefore, in the display device 600 according to another exemplary embodiment of the present disclosure, the n-type electrodes 624, 634, and 644 containing the magnetic material of the multiple light-emitting diodes LED are only provided on one side of the light-emitting diode LED. Therefore, when the multiple light-emitting diodes LED are divided at the boundary between the n-type electrodes 624, 634, and 644 and the p-type electrodes 625, 635, and 645, the p-type electrodes 625, 635, and 645 without magnetism between the n-type electrodes 624, 634, and 644 and the p-type electrodes 625, 635, and 645 may not be provided in the opening. In addition, when a part of the broken light-emitting diode LED only includes the n-type electrodes 624, 634, and 644 having magnetism, the size of the broken light-emitting diode LED is small, so that a magnetic field sufficient to move to the assembly substrate may not be formed. Therefore, a part of the light-emitting diode LED only including the n-type electrodes 624, 634, and 644 does not move to the assembly substrate but may remain in the fluid. Therefore, in the display device 600 according to another exemplary embodiment of the present disclosure, only the normal light-emitting diodes LED that are not broken are assembled on the assembly substrate and the broken light-emitting diodes remain in the fluid, thereby improving the assembly rate.

[0164] Figures 8A to 8C is a view showing multiple light-emitting diodes of a display device according to still another exemplary embodiment of the present disclosure. Only Figures 8A to 8C of the display device 800 and multiple light-emitting diodes LED of Figure 6 、 Figures 7A to 7C of the display device 600 are different, but other configurations are basically the same, so redundant descriptions will be omitted.

[0165] Refer to Figure 8A , the first light-emitting diode 820 includes a first n-type semiconductor layer 821, a first light-emitting layer 822, a first p-type semiconductor layer 823, a first n-type electrode 824, a first p-type electrode 825, and a first encapsulation layer 826.

[0166] The first n-type electrode 824 is disposed at one end of the first n-type semiconductor layer 821 and the first p-type electrode 825 is disposed at the other end of the first n-type semiconductor layer 821.

[0167] All planar shapes of the first n-type semiconductor layer 821 of the first light-emitting diode 820 may be circular shapes.

[0168] The planar shape of the first n-type electrode 824 may correspond to a partial shape of a circle. For example, a side surface of the first n-type electrode 824 adjacent to one end of the first n-type semiconductor layer 821 may be formed by a curved surface corresponding to the side surface of the first n-type semiconductor layer 821. At this time, a side surface of the first n-type electrode 824 opposite to the side surface formed as a curved surface of the first n-type electrode 824 may also be formed as a curved surface. At this time, two side surfaces of the first n-type electrode 824 opposite to each other are curved in the same direction and the planar shape of the first n-type electrode 824 may be a crescent shape.

[0169] The first light-emitting layer 822 and the first p-type semiconductor layer 823 are disposed at a distance from the first n-type electrode 824. At this time, as Figure 8A shown, when the first n-type electrode 824 is bent toward one side of the first n-type semiconductor layer 821, the first light-emitting layer 822 and the first p-type semiconductor layer 823 opposite to the first n-type electrode 824 may protrude along the side surface of the first n-type electrode 824 in one direction. Therefore, side surfaces of the first light-emitting layer 822 and the first p-type semiconductor layer 823 opposite to the first n-type electrode 824 may protrude outward from the first light-emitting diode 820.

[0170] Meanwhile, at an end of the first n-type semiconductor layer 821 where the first n-type electrode 824 is not disposed, the first light-emitting layer 822 and the first p-type semiconductor layer 823 may be disposed along the periphery of the first n-type semiconductor layer 821. Therefore, the first light-emitting layer 822 and the first p-type semiconductor layer 823 may include side surfaces formed as convex curved surfaces along the periphery of the first n-type semiconductor layer 821.

[0171] The first p-type electrode 825 is disposed on the first p-type semiconductor layer 823.

[0172] Next, a first encapsulation layer 826 surrounding the first n-type semiconductor layer 821, the first light-emitting layer 822, the first p-type semiconductor layer 823, the first n-type electrode 824, and the first p-type electrode 825 is provided.

[0173] Referring to Figure 8B , the second light-emitting diode 830 includes a second n-type semiconductor layer 831, a second light-emitting layer 832, a second p-type semiconductor layer 833, a second n-type electrode 834, a second p-type electrode 835, and a second encapsulation layer 836.

[0174] The second n-type electrode 834 is provided at one end of the second n-type semiconductor layer 831 and the second p-type electrode 835 is provided at the other end of the second n-type semiconductor layer 831.

[0175] The planar shape of the second n-type semiconductor layer 831 of the second light-emitting diode 830 may be formed in an elliptical shape.

[0176] The planar shape of the second n-type electrode 834 may correspond to a partial shape of the ellipse. For example, the side surface of the second n-type electrode 834 adjacent to one end of the second n-type semiconductor layer 831 may be formed by a curved surface corresponding to the side surface of the second n-type semiconductor layer 831. At this time, the side surface of the second n-type electrode 834 opposite to the side surface that is the curved surface of the second n-type electrode 834 may also be formed as a curved surface. At this time, the two side surfaces of the second n-type electrode 834 opposite to each other are curved in the same direction and the planar shape of the second n-type electrode 834 may be a crescent shape.

[0177] The second light-emitting layer 832 and the second p-type semiconductor layer 833 are provided at a distance from the second n-type electrode 834. At this time, as Figure 8B shown, when the second n-type electrode 834 is bent toward one side of the second n-type semiconductor layer 831, the second light-emitting layer 832 and the second p-type semiconductor layer 833 opposite to the second n-type electrode 834 may protrude along the side surface of the second n-type electrode 834 in one direction. Therefore, the side surfaces of the second light-emitting layer 832 and the second p-type semiconductor layer 833 opposite to the second n-type electrode 834 may protrude outward from the second light-emitting diode 830.

[0178] Meanwhile, at the end of the second n-type semiconductor layer 831 where the second n-type electrode 834 is not provided, the second light-emitting layer 832 and the second p-type semiconductor layer 833 may be provided along the periphery of the second n-type semiconductor layer 831. Therefore, the second light-emitting layer 832 and the second p-type semiconductor layer 833 may include side surfaces formed as convex curved surfaces along the periphery of the second n-type semiconductor layer 831.

[0179] The second p-type electrode 835 is provided on the second p-type semiconductor layer 833.

[0180] Next, a second encapsulation layer 836 surrounding the second n-type semiconductor layer 831, the second light-emitting layer 832, the second p-type semiconductor layer 833, the second n-type electrode 834, and the second p-type electrode 835 is provided.

[0181] Referring to Figure 8C , the third light-emitting diode 840 includes a third n-type semiconductor layer 841, a third light-emitting layer 842, a second p-type semiconductor layer 843, a third n-type electrode 844, a third p-type electrode 845, and a third encapsulation layer 846.

[0182] The planar shape of the third n-type semiconductor layer 841 of the third light-emitting diode 840 may be formed of an elliptical shape different from the planar shape of the second n-type semiconductor layer 830 of the second light-emitting diode 831.

[0183] The third n-type electrode 844 is provided at one end of the third n-type semiconductor layer 841 and the third p-type electrode 845 is provided at the other end of the third n-type semiconductor layer 841.

[0184] The planar shape of the third n-type semiconductor layer 841 of the third light-emitting diode 840 may be formed as an elliptical shape.

[0185] The planar shape of the third n-type electrode 844 may correspond to a partial shape of an ellipse. For example, the side surface of the third n-type electrode 844 adjacent to one end of the third n-type semiconductor layer 841 may be formed of a curved surface corresponding to the side surface of the third n-type semiconductor layer 841. At this time, the side surface of the third n-type electrode 844 opposite to the side surface of the third n-type electrode 844 that is a curved surface may also be formed as a curved surface. At this time, the two side surfaces of the third n-type electrode 844 opposite to each other are curved in the same direction and the planar shape of the third n-type electrode 844 may be a crescent shape.

[0186] The third light-emitting layer 842 and the third p-type semiconductor layer 843 are provided at a distance from the third n-type electrode 844. At this time, as Figure 8C shown, when the third n-type electrode 844 is bent toward one side of the third n-type semiconductor layer 841, the third light-emitting layer 842 and the third p-type semiconductor layer 843 opposite to the third n-type electrode 844 may protrude along the side surface of the third n-type electrode 844 in one direction. Accordingly, the side surfaces of the third light-emitting layer 842 and the third p-type semiconductor layer 843 opposite to the third n-type electrode 844 may protrude outward from the third light-emitting diode 840.

[0187] Meanwhile, at an end of the third n-type semiconductor layer 841 where the third n-type electrode 844 is not provided, the third light-emitting layer 842 and the third p-type semiconductor layer 843 may be disposed along the periphery of the third n-type semiconductor layer 841. Accordingly, the third light-emitting layer 842 and the third p-type semiconductor layer 843 may include side surfaces formed as convex curved surfaces along the periphery of the third n-type semiconductor layer 841.

[0188] The third p-type electrode 845 is disposed on the third p-type semiconductor layer 843.

[0189] Next, a third encapsulation layer 846 surrounding the third n-type semiconductor layer 841, the third light-emitting layer 842, the third p-type semiconductor layer 843, the third n-type electrode 844, and the third p-type electrode 845 is provided.

[0190] In a display device 800 according to another exemplary embodiment of the present disclosure, a plurality of light-emitting diodes LED are disposed in all directions. Accordingly, color differences and stains caused by a change in the viewing angle of the display panel PN may be minimized and color uniformity may be improved.

[0191] In a display device 800 according to another exemplary embodiment of the present disclosure, n-type electrodes 824, 834, and 844 including a magnetic material of the plurality of light-emitting diodes LED are provided only on one side of the light-emitting diodes LED. Accordingly, only the normal light-emitting diodes LED that are not broken are assembled on the assembly substrate, and the broken light-emitting diodes remain in the fluid, thereby improving the assembly rate.

[0192] In a display device 800 according to another exemplary embodiment of the present disclosure, the n-type electrodes 824, 834, and 844 of the plurality of light-emitting diodes LED are provided to be bent toward one side of the light-emitting diodes LED. Accordingly, the light-emitting layers 822, 832, and 842 and the p-type semiconductor layers 823, 833, and 843 opposite to the n-type electrodes 824, 834, and 844 are formed to protrude outward from the light-emitting diodes LED to increase the areas of the light-emitting layers 822, 832, and 842. Accordingly, the light-emitting efficiency of the light-emitting diodes LED may be improved.

[0193] Hereinafter, after describing the assembly substrate 1000 and the donor 2000 according to the exemplary embodiments of the present disclosure, first, reference will be made to Figures 9 to 11B Describe a method of manufacturing a display device according to each exemplary embodiment of the present disclosure.

[0194] Figure 9 is a plan view of an assembly substrate according to an exemplary embodiment of the present disclosure. Figure 10A is an enlarged plan view of an assembly area of an assembly substrate of a display device according to an exemplary embodiment of the present disclosure. Figure 10B is along Figure 10ACross-sectional view of the display device taken along Xb-Xb'.

[0195] Referring to Figure 9 , the assembly substrate 1000 includes an assembly area 1000A and an outer peripheral area 1000B. The assembly area 1000A is an area where a plurality of light-emitting diodes LED are self-assembled and provided with a plurality of assembly lines AL and a plurality of assembly electrodes AE for self-assembling the light-emitting diodes LED. The outer peripheral area 1000B is the remaining area other than the assembly area 1000A, and a plurality of assembly pads, a plurality of alignment keys, etc. can be provided in the outer peripheral area 1000B.

[0196] Referring to Figures 9 to 10B , the assembly substrate 1000 includes an assembly substrate 1010, a plurality of assembly lines AL, a plurality of assembly electrodes AE, a plurality of assembly pads, an electrode insulating layer EIL, an organic layer OL, and an assembly insulating layer IL.

[0197] First, referring to Figure 10A and Figure 10B , in the assembly area 1000A, a plurality of assembly lines AL and a plurality of assembly electrodes AE are provided on the assembly substrate 1010.

[0198] The plurality of assembly lines AL include a plurality of first assembly lines AL1 and a plurality of second assembly lines AL2. The plurality of first assembly lines AL1 and the plurality of second assembly lines AL2 can be arranged to be spaced apart from each other at a predetermined interval. The plurality of first assembly lines AL1 and the plurality of second assembly lines AL2 can be alternately arranged. Different voltages are applied to the plurality of first assembly lines AL1 and the plurality of second assembly lines AL2 so that an electric field can be formed between the plurality of first assembly lines AL1 and the plurality of second assembly lines AL2. A plurality of light-emitting diodes LED can be self-assembled between the plurality of first assembly lines AL1 and the plurality of second assembly lines AL2 by using the electric field formed between the plurality of first assembly lines AL1 and the plurality of second assembly lines AL2.

[0199] Each of the plurality of first assembly lines AL1 includes a first line portion LP1 and a plurality of first protrusions PP1. The first line portion LP1 is a portion that extends linearly along the first direction DR1 from the assembly area 1000A. The first line portion LP1 extends from the assembly area 1000A to the outer peripheral area 1000B and can be electrically connected to the plurality of assembly pads in the outer peripheral area 1000B.

[0200] A plurality of first protrusions PP1 are connected to a first line portion LP1. The plurality of first protrusions PP1 may extend from a side surface of the first line portion LP1 toward a second assembly line AL2 adjacent thereto. The plurality of first protrusions PP1 may be arranged to self-assemble each of a plurality of first light-emitting diodes 120, a plurality of second light-emitting diodes 130, and a plurality of third light-emitting diodes 140 between a first assembly line AL1 and a second assembly line AL2 adjacent to each other. The plurality of first protrusions PP1 are arranged to alternate with a plurality of second protrusions PP2 of the second assembly line AL2 described below, and may form a plurality of electric fields to self-assemble light-emitting diodes LED corresponding to each of a plurality of first sub-pixels SP1, a plurality of second sub-pixels SP2, and a plurality of third sub-pixels SP3. Accordingly, the plurality of first protrusions PP1 are arranged in a region between the first assembly line AL1 and the second assembly line AL2 and self-assemble the first light-emitting diodes 120, the second light-emitting diodes 130, and the third light-emitting diodes 140 at intervals between the plurality of sub-pixels SP.

[0201] If each of the plurality of first light-emitting diodes 120, the plurality of second light-emitting diodes 130, and the plurality of third light-emitting diodes 140 is self-assembled using different assembly lines AL, all the assembly lines AL for self-assembling the first light-emitting diodes 120, the assembly lines AL for self-assembling the second light-emitting diodes 130, and the assembly lines AL for self-assembling the third light-emitting diodes 140 are required. In this case, the number of the plurality of assembly lines AL increases, making it difficult to ensure a design area. In addition, in the process of forming the assembly lines AL corresponding to the intervals between the sub-pixels SP, the width of the assembly lines AL decreases to increase the resistance, which may lead to a reduction in assembly efficiency.

[0202] Accordingly, in order to self-assemble all of the first light-emitting diodes 120, the second light-emitting diodes 130, and the third light-emitting diodes 140 between a first assembly line AL1 and a second assembly line AL2 adjacent to each other, a plurality of first protrusions PP1 may be connected to a first line portion LP1.

[0203] Each of the plurality of first protrusions PP1 includes a first portion PP1a and a second portion PP1b. The first portion PP1a is a portion extending from the first line portion LP1 toward a second direction DR2. The first portion PP1a may be a connection member for transmitting a voltage to the second portion PP1b. One end of the first portion PP1a may be connected to the first line portion LP1 and the other end may be connected to the second portion PP1b.

[0204] The second part PP1b is connected to the other end of the first part PP1a and extends in the first direction DR1. The second part PP1b can be alternately arranged with the second protrusion PP2 of the second assembly line AL2 while extending in the first direction DR1. The second part PP1b can be arranged in the region between the fourth part PP2b of the second protrusion PP2 of the second assembly line AL2 and the second wire part LP2. The second part PP1b is arranged adjacent to the fourth part PP2b of the second protrusion PP2 and the second wire part LP2 to form an electric field for self-assembling a plurality of first light-emitting diodes 120, a plurality of second light-emitting diodes 130, and a plurality of third light-emitting diodes 140.

[0205] Each of the plurality of second assembly lines AL2 includes a second wire part LP2 and a plurality of second protrusions PP2. The second wire part LP2 is a part that extends linearly in the first direction DR1 from the assembly region 1000A. In the second direction DR2, the second wire part LP2 can be alternately arranged with the first wire part LP1. The second wire part LP2 extends from the assembly region 1000A to the outer peripheral region 1000B and can be electrically connected to a plurality of assembly pads in the outer peripheral region 1000B.

[0206] The plurality of second protrusions PP2 are connected to the second wire part LP2. The plurality of second protrusions PP2 can extend from the other surface of the second wire part LP2 in the second direction DR2. Each of the plurality of second protrusions PP2 includes a third part PP2a and a fourth part PP2b. The third part PP2a is a part that extends from the second wire part LP2 in the second direction DR2. The third part PP2a can be a connection member for transmitting voltage to the fourth part PP2b. One end of the third part PP2a can be connected to the second wire part LP2 and the other end can be connected to the fourth part PP2b. The third part PP2a can be alternately arranged with the first part PP1a of the first assembly line AL1 adjacent to it. Therefore, the third part PP2a and the first part are alternately arranged so that the fourth part PP2b connected to the third part PP2a can be alternately arranged with the second part PP1b connected to the first part PP1a.

[0207] The fourth part PP2b is connected to the other end of the third part PP2a and extends in the first direction DR1. The fourth part PP2b extends in the first direction DR1 and can be alternately arranged with the second part PP1b of the first protrusion PP1 of the first assembly line AL1. The fourth part PP2b can be arranged in the region between the second part PP1b of the first protrusion PP1 of the first assembly line AL1 and the first wire part LP1. In the second direction DR2, the fourth part PP2b of the second assembly line AL2 and the second part PP1b of the first assembly line AL1 can face each other. Therefore, the fourth part PP2b of the second assembly line AL2 can form an electric field to self-assemble the plurality of first light-emitting diodes 120, the plurality of second light-emitting diodes 130, and the plurality of third light-emitting diodes 140 together with the first wire part LP1 and the second part PP1b of the first assembly line AL1 adjacent thereto.

[0208] The plurality of assembly electrodes AE include a plurality of first assembly electrodes AE1 and a plurality of second assembly electrodes AE2. The plurality of first assembly electrodes AE1 can be connected to the plurality of first assembly lines AL1, and the plurality of second assembly electrodes AE2 can be connected to the plurality of second assembly lines AL2. A pair of the first assembly electrode AE1 and the second assembly electrode AE2 are arranged adjacent to each other to form an electric field for self-assembling the light-emitting diode LED. Each of the paired first assembly electrodes AE1 and second assembly electrodes AE2 can be arranged to correspond to the correct position where the light-emitting diode LED is transferred in the plurality of sub-pixels SP.

[0209] A part of the plurality of first assembly electrodes AE1 can be arranged to protrude from one side surface of the first wire part LP1 in the second direction DR2. The other parts of the plurality of first assembly electrodes AE1 can be arranged to protrude from both side surfaces of the second part PP1b of the first protrusion PP1 in the second direction DR2. For example, four first assembly electrodes AE1 can be connected to each of the two side surfaces of one second part PP1b.

[0210] A part of the plurality of second assembly electrodes AE2 can be set to protrude from the other surface of the second wire part LP2 toward the second direction DR2. A part of the second assembly electrodes AE2 connected to the second wire part LP2 can face the first assembly electrode AE1 protruding from the second part PP1b of the adjacent first assembly line AL1. A part of the plurality of second assembly electrodes AE2 can be set to protrude from the two side surfaces of the fourth part PP2b of the second protrusion PP2 toward the second direction DR2. Among these second assembly electrodes AE2, the second assembly electrode AE2 protruding from one side surface of the fourth part PP2b can face the first assembly electrode AE1 protruding from the other surface of the second part PP1b of the adjacent first assembly line AL1. The second assembly electrode AE2 protruding from the other side surface of the fourth part PP2b can face the first assembly electrode AE1 protruding from the first wire part LP1 of the adjacent first assembly line AL1.

[0211] Any one of the first light-emitting diode 120, the second light-emitting diode 130, and the third light-emitting diode 140 can be self-assembled between the first assembly electrode AE1 and the second assembly electrode AE2 facing each other at intervals and arrangements corresponding to each of the plurality of sub-pixels SP. For example, the first light-emitting diode 120 can be self-assembled between the first assembly electrode AE1 of the first wire part LP1 and the second assembly electrode AE2 of the fourth part PP2b facing each other. The second light-emitting diode 130 can be self-assembled between the first assembly electrode AE1 of the second part PP1b and the second assembly electrode AE2 of the fourth part PP2b facing each other. The third light-emitting diode 140 can be self-assembled between the first assembly electrode AE1 of the second part PP1b and the second assembly electrode AE2 of the second wire part LP2 facing each other.

[0212] Therefore, the plurality of first protrusions PP1 and the plurality of second protrusions PP2 are alternately arranged between an adjacent first assembly line AL1 and second assembly line AL2. Thus, the first light-emitting diode 120 of the first sub-pixel SP1, the second light-emitting diode 130 of the second sub-pixel SP2, and the third light-emitting diode 140 of the third sub-pixel SP3 can be self-assembled at one time.

[0213] Meanwhile, referring to Figure 10A , the plurality of first assembly electrodes AE1 and the plurality of second assembly electrodes AE2 are provided in each of the plurality of unit areas UA and are provided at positions corresponding to the plurality of openings OLH. At this time, in the plurality of unit areas UA, all the shapes of the plurality of first assembly electrodes AE1 and the plurality of second assembly electrodes AE2 can be the same. For example, as Figure 10AAs shown, the planar shape of each of the plurality of first assembly electrodes AE1 and the plurality of second assembly electrodes AE2 provided in a unit area UA may be rectangular, but is not limited thereto.

[0214] Refer to together Figure 9 , a plurality of assembly pads are provided in the outer peripheral area 1000B of the assembly substrate 1000. The plurality of assembly pads include a plurality of first assembly pads APAD1 and a plurality of second assembly pads APAD2. A plurality of first assembly lines AL1 and a plurality of first assembly electrodes AE1 are connected to the plurality of first assembly pads APAD1 to apply a voltage. A plurality of second assembly lines AL2 and a plurality of second assembly electrodes AE2 are connected to the plurality of second assembly pads APAD2 to apply a voltage. A part of the plurality of first assembly lines AL1 among the plurality of first assembly lines AL1 may be connected to one first assembly pad APAD1, and a part of the plurality of second assembly lines AL2 among the plurality of second assembly lines AL2 may be connected to one second assembly pad APAD2.

[0215] Next, an electrode insulating layer EIL is disposed on the plurality of assembly lines AL and the plurality of assembly electrodes AE. The electrode insulating layer EIL may be composed of a single layer or a double layer of silicon oxide (SiO x ) or silicon nitride (SiN x ), but is not limited thereto.

[0216] An organic layer OL including a plurality of openings OLH is provided. The organic layer OL includes a first organic layer OL1 and a second organic layer OL2. The first organic layer OL1 is disposed on the plurality of assembly lines AL, and the second organic layer OL2 is disposed on the first organic layer OL1. The thickness of the organic layer OL that can be formed in one process is limited. If the thickness of the organic layer OL is equal to or lower than a predetermined level, the light-emitting diodes LED self-assembled in the openings OLH of the organic layer OL may not be properly placed in the openings OLH. On the contrary, when the thickness of the organic layer OL is too thick, it may be difficult to attach the light-emitting diodes LED self-assembled in the openings OLH of the organic layer OL to the donor 2000. Therefore, the thickness of the organic layer OL can be adjusted by forming a plurality of organic layers OL. The organic layer OL can have at least a thickness less than the height of the light-emitting diodes LED. Even in Figure 10B it is shown that the organic layer OL includes a first organic layer OL1 and a second organic layer OL2, but in addition to the first organic layer OL1 and the second organic layer OL2, the organic layer OL may be formed as a single layer or further include additional organic layers OL. However, it is not limited thereto.

[0217] The organic layer OL includes a plurality of openings OLH. Each of the plurality of openings OLH formed by opening a part of the organic layer OL is an area where a plurality of light-emitting diodes LED are self-assembled. The plurality of openings OLH may be arranged to overlap with the area between the pair of first assembly electrodes AE1 and the second assembly electrodes AE2. Each of the plurality of openings OLH may be formed at a position corresponding to each of the plurality of sub-pixels SP in the display device 100. The plurality of openings OLH may be arranged to correspond one-to-one with the plurality of sub-pixels SP, and the light-emitting diodes LED self-assembled in the plurality of openings OLH may be transferred as they are onto the plurality of sub-pixels SP.

[0218] The plurality of openings OLH includes a plurality of first openings OLH1, a plurality of second openings OLH2, and a plurality of third openings OLH3. Each of the plurality of first openings OLH1, the plurality of second openings OLH2, and the plurality of third openings OLH3 may be arranged to correspond to the plurality of first sub-pixels SP1, the plurality of second sub-pixels SP2, and the plurality of third sub-pixels SP3.

[0219] Meanwhile, the plurality of openings OLH may form a plurality of unit areas UA. The plurality of unit areas UA are areas corresponding to one pixel PX, and each of the plurality of unit areas UA may be formed at a position corresponding to each of the plurality of pixels PX in the display device 100. Each of the plurality of unit areas UA may be arranged to correspond one-to-one with each of the pixels PX, and the light-emitting diodes LED self-assembled in each of the plurality of unit areas UA may be transferred to each of the plurality of pixels PX.

[0220] In Figure 10A it is shown that one unit area UA is formed by a pair of first openings OLH1, a pair of second openings OLH2, and a pair of third openings OLH3, but it is not limited thereto.

[0221] The plurality of first openings OLH1 may have a shape corresponding to the planar shape of the first light-emitting diodes 120. The plurality of second openings OLH2 may have a shape corresponding to the planar shape of the second light-emitting diodes 130. The plurality of third openings OLH3 may have a shape corresponding to the planar shape of the third light-emitting diodes 140. For example, the plurality of first openings OLH1 may be a plurality of circular openings, the plurality of second openings OLH2 may be a plurality of first oval openings, and the plurality of third openings OLH3 may be a plurality of second oval openings. Accordingly, the first openings OLH1 are formed to have a circular shape such that only the first light-emitting diodes 120 can be self-assembled in the first openings OLH1, and the second openings OLH2 are formed to have an oval shape such that only the second light-emitting diodes 130 can be self-assembled in the second openings OLH2. The third openings OLH3 are formed to have an oval shape with a major axis longer than the major axis of the second openings OLH2 such that only the third light-emitting diodes 140 can be self-assembled in the third openings OLH3. Accordingly, the first openings OLH1, the second openings OLH2, and the third openings OLH3 are formed to have shapes corresponding to the first light-emitting diodes 120, the second light-emitting diodes 130, and the third light-emitting diodes 140. Accordingly, only the light-emitting diodes having a specific shape can be self-assembled in each opening OLH.

[0222] Meanwhile, the plurality of openings OLH may be arranged in various directions. For example, in one unit area UA, each of the second openings OLH2 and the third openings OLH3 may be arranged in a direction different from the direction of the second openings OLH2 and the third openings OLH3 provided in an adjacent unit area UA. For example, in one unit area UA, the major axes of the second openings OLH2 and the third openings OLH3 may be arranged along a first direction DR1, and in another unit area UA, the major axes of the second openings OLH2 and the third openings OLH3 may be arranged along a second direction DR2. Additionally, in yet another unit area UA, the major axes of the second openings OLH2 and the third openings OLH3 may be arranged along a direction between the first direction DR1 and the second direction DR2. Accordingly, in at least one unit area UA among the plurality of unit areas UA, the major axis directions of the second openings OLH2 and the third openings OLH3 may be different from the major axis directions of the second openings OLH2 and the third openings OLH3 in an adjacent unit area UA. Meanwhile, as Figure 10A shown, the shapes of the plurality of openings are illustrated for ease of description, and thus the present disclosure is not limited thereto. Accordingly, the major axes of the plurality of openings OLH may be arranged in various directions, and in one unit area UA, the major axes of the second openings OLH2 and the third openings OLH3 may be arranged in random directions.

[0223] Meanwhile, in a plurality of unit regions UA, all of the plurality of first assembly electrodes AE1 and the plurality of second assembly electrodes AE2 are arranged in the same shape and in the same direction. Accordingly, the area where the second opening OLH2 and the third opening OLH3 overlap with the plurality of first assembly electrodes AE1 and the plurality of second assembly electrodes AE2 in one unit region UA may be different from the area where the second opening OLH2 and the third opening OLH3 overlap with the plurality of first assembly electrodes AE1 and the plurality of second assembly electrodes AE2 in an adjacent unit region UA.

[0224] An assembly insulating layer IL is provided on the organic layer OL and the electrode insulating layer EIL. The assembly insulating layer IL can protect the plurality of assembly lines AL, the plurality of assembly electrodes AE, and the organic layer OL from the fluid WT, so as to suppress defects such as corrosion of the plurality of assembly lines AL.

[0225] Meanwhile, referring to Figure 10A and Figure 10B , the assembly insulating layer IL can expose the side surface of the organic layer OL in the outer peripheral region 1000B. In the outer peripheral region 1000B, a first line portion LP1 and a second line portion LP2 extending from the assembly region 1000A are electrically connected to the plurality of assembly pads. Accordingly, in the outer peripheral region 1000B, the assembly insulating layer IL and the organic layer OL are removed together, and the side surface of the organic layer OL can be exposed, but is not limited thereto.

[0226] Referring together to Figure 9 , the outer peripheral region 1000B includes one or more first alignment regions 1000Ba. The first alignment region 1000Ba is a region in which a plurality of first alignment patterns are provided and a plurality of alignment keys are self-assembled. For example, each of the plurality of first alignment regions 1000Ba may be formed adjacent to each of the four corners of the assembly region 1000A.

[0227] In the first alignment region 1000Ba, a plurality of first alignment patterns are provided on the assembly substrate 1000. The plurality of first alignment patterns are marks for aligning a donor 2000 and the assembly substrate 1000, which will be described below. By aligning the plurality of first alignment patterns of the assembly substrate 1000 and the plurality of second alignment patterns of the donor 2000, the assembly substrate 1000 and the donor 2000 can be aligned. For example, the plurality of first alignment patterns may be formed in a donut shape.

[0228] In the first alignment region 1000Ba, the assembly line AL and the assembly electrode AE may be further provided on the assembly substrate 1000. The assembly line AL provided in the first alignment region 1000Ba can apply a voltage to the assembly electrode AE to form an electric field for self-assembling alignment keys in the assembly electrode AE.

[0229] The alignment keys can self-assemble in the region between the assembly electrodes AE of the first alignment region 1000Ba. The alignment keys can be transferred onto the donor 2000 together with a plurality of light-emitting diodes LEDs, and the alignment keys transferred onto the donor 2000 can be used to align the donor 2000 and the display panel PN. That is, the alignment keys are marks for aligning the donor 2000 and the display panel PN. The alignment keys can be formed of at least a part of the same material as the material forming the light-emitting diodes LEDs. For example, the first light-emitting diode 120 can be used as an alignment key. In this case, the first opening OLH1 of the organic layer OL can be formed on the assembly electrode AE to self-assemble only the first light-emitting diode 120 serving as an alignment key.

[0230] Hereinafter, with reference to Figures 11A to 11H a method of manufacturing the display device 100 according to an exemplary embodiment of the present disclosure will be described.

[0231] Figures 11A to 11H is a process diagram for explaining a method of manufacturing a display device according to an exemplary embodiment of the present disclosure. Figure 11A and Figure 11B is a diagram for explaining a process of self-assembling light-emitting diodes LEDs on the assembly substrate 1000. Figure 11C is a diagram for explaining a process of transferring the light-emitting diodes LEDs on the assembly substrate 1000 onto the donor 2000. Figure 11D is a plan view of the first alignment region 1000Ba and the second alignment region 2000Bb when the assembly substrate 1000 and the donor 2000 are joined. Figure 11E is a plan view of the assembly region 1000A and the transfer region 2000A when the assembly substrate 1000 and the donor 2000 are joined. Figure 11F and Figure 11G is a diagram for explaining a process of transferring the light-emitting diodes LEDs on the donor 2000 onto the display panel PN. Figure 11H is a cross-sectional view of the display panel PN for explaining a process of forming the first connection electrode CE1 and the second connection electrode CE2.

[0232] With reference to Figure 11A , a plurality of light-emitting diodes LEDs are self-assembled on the assembly substrate 1000.

[0233] First, the light-emitting diodes LEDs grown on a wafer are input into a chamber CB filled with a fluid WT. The fluid WT can include water or the like, and the top of the chamber CB filled with the fluid WT can be open.

[0234] Next, the assembly substrate 1000 can be positioned over the chamber CB filled with light-emitting diodes LED. The assembly substrate 1000 can be arranged such that the organic layer OL with a plurality of openings OLH formed thereon of the assembly substrate 1000 faces the chamber CB.

[0235] Next, the magnet MG can be positioned on the assembly substrate 1000. The light-emitting diodes LED that sink to the bottom of the chamber CB or float can be moved toward the assembly substrate 1000 by the magnetic force of the magnet MG.

[0236] At this time, the light-emitting diodes LED can include a magnetic material to be moved by a magnetic field. For example, any one of the n-type electrodes 124, 134, and 144 or the p-type electrodes 125, 135, and 145 of the light-emitting diodes LED includes a ferromagnetic material (such as iron (Fe), cobalt (Co), or nickel (Ni)) to align the direction in which the light-emitting diodes LED point to the magnet MG.

[0237] Next, referring to Figure 11B , the light-emitting diodes LED moved onto the assembly substrate 1000 by the magnet MG can be self-assembled on the assembly substrate 1000 by an electric field formed between the plurality of assembly electrodes AE.

[0238] Specifically, a voltage is applied to the plurality of assembly lines AL and the plurality of assembly electrodes AE to self-assemble the plurality of light-emitting diodes LED in the openings OLH of the organic layer OL. For example, different AC voltages are applied to the plurality of first assembly lines AL1, the plurality of first assembly electrodes AE1, the plurality of second assembly lines AL2, and the plurality of second assembly electrodes AE2 to form an electric field. The light-emitting diodes LED are polarized by the electric field mediator to have a polarity. The polarized light-emitting diodes LED can be moved to a specific direction or fixed to a specific direction by dielectrophoresis (DEP), i.e., an electric field. Therefore, the plurality of light-emitting diodes LED can be temporarily self-assembled in the openings OLH of the assembly substrate 1000 by dielectrophoresis.

[0239] At this time, the second light-emitting diode 130 and the third light-emitting diode 140 having an elliptical shape can be aligned such that a pair of n-type electrodes are guided to adjacent assembly electrodes AE. For example, the second light-emitting diode 130 is aligned such that one of the pair of second n-type electrodes 134 is guided to the first assembly electrode AE1 and the other is guided to the second assembly electrode AE2. Thus, the second light-emitting diode can be self-assembled in the second opening OLH2.

[0240] Meanwhile, the second light-emitting diode 130 and the third light-emitting diode 140 having an elliptical shape can be respectively aligned along the major axis directions of the second opening OLH2 and the third opening OLH3. At this time, the second light-emitting diode 130 and the third light-emitting diode 140 can be self-assembled on the assembly substrate 1000 in various directions along the major axis directions of the second opening OLH2 and the third opening OLH3 respectively. For example, when the major axis directions of each of the second opening OLH2 and the third opening OLH3 in one unit area UA are different from the major axis directions of each of the second opening OLH2 and the third opening OLH3 in an adjacent unit area UA, the major axis of each of the second light-emitting diode 130 and the third light-emitting diode 140 in one unit area UA can be self-assembled in a direction different from the major axis of each of the second light-emitting diode 130 and the third light-emitting diode 140 provided in the adjacent unit area UA.

[0241] After the self-assembly is completed, the fluid WT can evaporate from the assembly substrate 1000. At this time, before the fluid WT is completely evaporated, an electric field is formed between the assembly electrodes AE to fix the light-emitting diode LED to the opening OLH. When the drying of the assembly substrate 1000 is completed, the electric field can be removed. At this time, even after the electric field is removed, the light-emitting diode LED can be temporarily fixed to the assembly substrate 1000 by van der Waals forces.

[0242] Next, referring to Figures 11C to 11E , the multiple light-emitting diodes LED and the multiple alignment keys AK of the assembly substrate 1000 are transferred to the donor 2000.

[0243] First, referring to Figure 11C and Figure 11D, the assembly substrate 1000 and the donor 2000 are aligned such that a plurality of light-emitting diodes LED and the donor 2000 face each other. At this time, by overlapping the first alignment region 1000Ba of the assembly substrate 1000 and the second alignment region 2000bb of the donor 2000, the assembly substrate 1000 and the donor 2000 can be aligned. For example, the assembly substrate 1000 and the donor 2000 can be aligned such that the first alignment pattern AP1 of the assembly substrate 1000 and the second alignment pattern AP2 of the donor 2000 overlap each other. The assembly substrate 1000 and the donor 2000 can be aligned such that the circular second alignment pattern AP2 is disposed in the empty space of the donut-shaped first alignment pattern AP1. In the non-transfer region of the donor 2000, the transfer region includes a plurality of dummy bumps 2032 and a plurality of alignment bumps 2033. The plurality of dummy bumps 2032 can increase the bonding strength between the assembly substrate 1000 and the donor 2000 during the transfer process and can minimize the deformation of the plurality of chip bumps disposed in the transfer region due to the impact applied to the donor 2000. In addition, the plurality of dummy bumps 2032 are in contact with the organic layer OL of the assembly substrate 1000 to maintain the bonding state between the assembly substrate 1000 and the donor 2000.

[0244] In this case, the alignment key AK of the assembly substrate 1000 can be aligned to overlap with the alignment bump 2033 disposed in the non-transfer region of the donor 2000.

[0245] Refer to Figure 11E , when the first alignment pattern AP1 and the second alignment pattern AP2 are aligned, the plurality of chip bumps 2031 can be aligned to respectively correspond to the plurality of light-emitting diodes LED. Each of the plurality of chip bumps 2031 can be disposed above a pair of first light-emitting diodes 120, a pair of second light-emitting diodes 130, and a pair of third light-emitting diodes 140.

[0246] Therefore, after the assembly substrate 1000 and the donor 2000 are aligned, the assembly substrate 1000 and the donor 2000 can be bonded such that the upper part of the light-emitting diode LED can be in contact with the donor 2000. At this time, the donor 2000 is formed of an adhesive material such that the upper parts of the plurality of light-emitting diodes LED are bonded to the donor 2000 to move from the assembly substrate 1000 to the donor 2000. At this time, the plurality of light-emitting diodes LED aligned in a random direction on the assembly substrate 1000 can move to the donor 2000 while maintaining the alignment direction.

[0247] The plurality of alignment keys AK can also be transferred to the alignment bumps 2033 of the donor 2000 together with the plurality of light-emitting diodes LED transferred to the plurality of chip bumps 2031.

[0248] Next, referring to Figure 11F , a plurality of light-emitting diodes LEDs on the donor 2000 are transferred onto the adhesive layer AD of the display panel PN.

[0249] First, the display panel PN is aligned with the adhesive layer AD and the donor 2000. After the donor 2000 is set such that the plurality of light-emitting diodes LEDs of the donor 2000 and the adhesive layer AD of the display panel PN face each other, the display panel PN and the donor 2000 can be aligned. When the display panel PN and the donor 2000 are aligned, the alignment key AK temporarily attached to the alignment bump 2033 of the donor 2000 is aligned with the third alignment pattern AP3 of the display panel PN, so that the donor 2000 and the display panel PN are aligned. The third alignment pattern AP3 is a pattern provided in the non-active area NA of the display panel PN and can be formed of the same material as any one of the plurality of wirings or electrodes provided in the display panel PN. For example, the third alignment pattern AP3 can be formed in a rectangular shape in which an X-shaped pattern is provided. Thus, the donor 2000 and the display panel PN can be aligned so that the alignment key AK is set at the center of the X-shaped portion of the third alignment pattern AP3.

[0250] In addition, referring together to Figure 11F and Figure 11G , the donor 2000 and the display device 100 are joined to transfer the light-emitting diodes LEDs on the donor 2000 onto the adhesive layer AD. The plurality of light-emitting diodes LEDs provided on the donor 2000 are provided to correspond to the plurality of sub-pixels SP, so that all the light-emitting diodes LEDs on the donor 2000 can be transferred onto the display panel PN at once without selectively transferring the light-emitting diodes LEDs. The plurality of light-emitting diodes LEDs transferred onto the display panel PN adhere to the adhesive layer AD to be temporarily fixed.

[0251] At this time, the plurality of light-emitting diodes LEDs aligned in various directions on the donor 2000 can move to the display panel PN while maintaining the alignment direction.

[0252] The alignment key AK can be transferred together with the plurality of light-emitting diodes LEDs. The alignment key AK can be transferred onto the third alignment pattern AP3 of the non-active area NA. However, the alignment key AK transferred onto the display panel PN is not connected to a separate connection electrode CE, so that it does not emit light.

[0253] Next, referring to Figure 11H , after the light-emitting diodes LEDs are transferred onto the adhesive layer AD of the display panel PN, a first connection electrode CE1 and a second connection electrode CE2 are formed to electrically connect the light-emitting diodes LEDs to the driving transistor DT and the power supply line VDD.

[0254] First, a second planarization layer 117 covering a plurality of light-emitting diodes LED is formed. At this time, the thickness of the second planarization layer 117 is configured to be less than the thickness of the plurality of light-emitting diodes LED, such that the upper portions of the plurality of light-emitting diodes LED can be disposed outside the second planarization layer 117. For example, the light-emitting layers 122, 132, and 142 and the p-type semiconductor layers 123, 133, and 143 of the plurality of light-emitting diodes LED can be disposed above the top surface of the second planarization layer 117. At least a portion of the n-type semiconductor layers 121, 131, and 142 of the plurality of light-emitting diodes LED can be covered by the second planarization layer 117.

[0255] In the present disclosure, it is described that the second planarization layer 117 initially has a thickness smaller than the thickness of the n-type semiconductor layers 121, 131, and 141 of the plurality of light-emitting diodes LED. However, the thickness of the second planarization layer 117 can be adjusted by performing an ashing process.

[0256] Next, a first connection electrode CE1 can be formed on the second planarization layer 117. A conductive material layer is formed on the entire surface of the substrate 110 and patterned to form the first connection electrode CE1.

[0257] Meanwhile, as Figure 3 shown, the n-type semiconductor layers 121, 131, and 141 can be aligned in various directions. For example, as Figure 3 shown, the n-type semiconductor layers 121, 131, and 141 can be aligned in the row direction in one pixel PX, the n-type semiconductor layers 121, 131, and 141 can be aligned in the column direction in adjacent pixels PX, and the n-type semiconductor layers 121, 131, and 141 can be aligned in the diagonal direction in another adjacent pixel PX. In this case, it may be difficult to connect the plurality of randomly arranged light-emitting diodes LED and the first connection electrode CE1, and it may be vulnerable to short-circuit defects and the like. On the contrary, in the display device 100 according to an exemplary embodiment of the present disclosure, the first connection electrode CE1 is disposed to surround the side surfaces of the plurality of light-emitting diodes LED. Therefore, the first connection electrode CE1 and the light-emitting diodes LED can be easily electrically connected regardless of the alignment direction of the light-emitting diodes LED.

[0258] Next, referring to Figure 11H , a third planarization layer 118 is formed on the first connection electrode CE1 and the second planarization layer 117. The third planarization layer 118 can be formed to cover the second planarization layer 117, the light-emitting layers 122, 132, and 142 and the p-type semiconductor layers 123, 133, and 143 of the plurality of light-emitting diodes LED.

[0259] An ashing process is performed on the third planarization layer 118 to reduce the thickness of the third planarization layer 118 as a whole and expose the p-type electrodes 125, 135, and 145 of a plurality of light-emitting diodes LED from the third planarization layer 118.

[0260] Finally, a second connection electrode CE2 corresponding to the p-type semiconductor layers 123, 133, and 143 is formed on the third planarization layer 118. The second connection electrode CE2 can be electrically connected to the power supply line VDD through a fourth contact hole CH4 formed in the third planarization layer 118. The second connection electrode CE2 contacts the top surfaces of the p-type electrodes 125, 135, and 145 exposed from the third planarization layer 118 to be electrically connected to the p-type electrodes 125, 135, and 145 and the p-type semiconductor layers 123, 133, and 143. Accordingly, only the p-type electrodes 125, 135, and 145 on the p-type semiconductor layers 123, 133, and 143 of the plurality of light-emitting diodes LED can be exposed to the outside through the ashing process. The second connection electrode CE2 is formed by forming and patterning a metal layer on the entire surface of the substrate 110 on the second planarization layer 117 to easily electrically connect the second connection electrode CE2 to the p-type semiconductor layers 123, 133, and 143 and the p-type electrodes 125, 135, and 145.

[0261] Accordingly, in the display device 100 and the method of manufacturing the display device 100 according to an exemplary embodiment of the present disclosure, a plurality of light-emitting diodes LED are self-assembled on the assembly substrate 1000 in an arrangement corresponding to a plurality of sub-pixels SP. Thereafter, the plurality of light-emitting diodes LED on the assembly substrate 1000 can be transferred to the display panel PN using the donor 2000. When the light-emitting diodes LED are self-assembled using an electric field, the process of transferring the plurality of light-emitting diodes LED from the wafer to the donor 2000 by aligning the plurality of light-emitting diodes LED at intervals corresponding to the plurality of sub-pixels SP can be omitted. In addition, the light-emitting diodes LED can be easily self-assembled in the correct position using an electric field and a plurality of openings OLH to minimize alignment errors. Accordingly, the plurality of light-emitting diodes LED are self-assembled using the assembly substrate 1000 in an arrangement corresponding to the sub-pixels SP and transferred to the display panel PN as they are. Accordingly, the alignment errors of the plurality of light-emitting diodes LED can be minimized, and the transfer process can be simplified.

[0262] Meanwhile, in the display device 100 and the method of manufacturing the display device 100 according to an exemplary embodiment of the present disclosure, the plurality of light-emitting diodes LED are not self-assembled on the assembly substrate 1000 in the arrangement on the wafer, but are self-assembled at random positions. Accordingly, the wavelength deviation on the wafer can be minimized and displayed on the display panel PN as it is.

[0263] Meanwhile, the brightness characteristics of multiple light-emitting diodes may be affected by the shape of the light-emitting diodes. For example, brightness deviation may occur according to the shape of multiple electrodes provided in the multiple light-emitting diodes and the multiple semiconductor layers. Therefore, when multiple light-emitting diodes are formed to have an asymmetrical shape, brightness deviation may occur depending on the viewing angle. For example, when multiple light-emitting diodes are formed to have an elliptical shape, the brightness characteristics in the short-axis direction of the light-emitting diodes may be different from those in the long-axis direction.

[0264] Meanwhile, on the display panel, all of the multiple light-emitting diodes may be arranged to be aligned in the same direction. For example, when multiple light-emitting diodes are formed to have an elliptical shape, all of the long-axis directions of the multiple light-emitting diodes may be arranged along the same direction. Therefore, on the display panel, the brightness characteristics in the corresponding direction may be different from those in another direction. Therefore, when all of the multiple light-emitting diodes are aligned in the same direction, due to the brightness asymmetry characteristics of the multiple light-emitting diodes, the brightness asymmetry characteristics may be visible in the display device.

[0265] Therefore, in the display device 100 and the manufacturing method of the display device 100 according to an exemplary embodiment of the present disclosure, the long-axis directions of the multiple openings OLH are formed in various directions on the assembly substrate 1000. Therefore, the light-emitting diodes LED can self-assemble in various directions according to the shape of the multiple openings OLH, and the multiple light-emitting diodes LED aligned in various directions along the multiple openings OLH are transferred to the display panel PN. Therefore, the multiple light-emitting diodes LED can be aligned on the display panel PN in various directions. Therefore, even if the multiple light-emitting diodes LED are formed to have an asymmetrical shape, the multiple light-emitting diodes LED are aligned in various directions to reduce brightness deviation. Therefore, color difference and stain caused by a change in the viewing angle of the display panel PN can be minimized, and color uniformity can be improved.

[0266] Figure 12 is a plan view of an assembly substrate according to another exemplary embodiment of the present disclosure. Compared with Figures 9 to 11H the assembly substrate 1000 of Figure 12 only the multiple assembly electrodes AE of the assembly substrate 1100 of

[0267] are different, and other configurations are basically the same, so redundant descriptions are omitted. Figure 12 Referring to

[0268] In at least one unit area UA, the shapes of the multiple first assembly electrodes AE1 and the multiple second assembly electrodes AE2 may be different from the shapes of the multiple first assembly electrodes AE1 and the multiple second assembly electrodes AE2 in an adjacent unit area UA. For example, asFigure 12 As shown, the planar shape of each of the plurality of first assembly electrodes AE1 and the plurality of second assembly electrodes AE2 provided in a unit area UA may be triangular. Additionally, the planar shape of each of the plurality of first assembly electrodes AE1 and the plurality of second assembly electrodes AE2 in adjacent unit areas UA may be rectangular.

[0269] Furthermore, when the planar shapes of the plurality of first assembly electrodes AE1 and the plurality of second assembly electrodes AE2 are triangular, in at least one unit area UA, the plurality of first assembly electrodes AE1 and the plurality of second assembly electrodes AE2 may be arranged to be spaced apart from each other along the diagonal direction. Additionally, when the planar shapes of the plurality of first assembly electrodes AE1 and the plurality of second assembly electrodes AE2 are rectangular, in at least one unit area UA, the plurality of first assembly electrodes AE1 and the plurality of second assembly electrodes AE2 may be arranged to be spaced apart from each other along the column direction or the row direction.

[0270] Therefore, in each of the plurality of unit areas UA, the area of overlap of each of the plurality of openings OLH with the plurality of first assembly electrodes AE1 and the plurality of second assembly electrodes AE2 may be the same.

[0271] In another assembly substrate 1100 of the present disclosure, the major axis directions of the plurality of openings OLH may be formed in various directions. Thus, the light-emitting diodes LED can self-assemble according to the shape of the plurality of openings OLH, and the plurality of light-emitting diodes LED can be aligned in various directions on the display panel PN, so that the brightness deviation of the display panel PN can be reduced.

[0272] In another assembly substrate 1100 of the present disclosure, the major axis directions of the plurality of openings OLH of the plurality of assembly electrodes AE may be formed in various directions. For example, the shapes of the plurality of assembly electrodes AE may be different in each unit area UA. Among the plurality of first assembly electrodes AE1 and the plurality of second assembly electrodes AE2, the adjacent first assembly electrode AE1 and second assembly electrode AE2 may be spaced apart from each other in various directions in each unit area UA. Therefore, the area of overlap of each of the plurality of openings OLH with the plurality of first assembly electrodes AE1 and the plurality of second assembly electrodes AE2 may be the same in each of the plurality of unit areas UA. Thus, when a voltage is applied to the plurality of assembly electrodes AE, all the electric fields formed in the openings OLH may be the same, and the degree of polarization of the light-emitting diodes LED caused by the electric field may also be the same. Therefore, in another assembly substrate 1100 according to the present disclosure, the light-emitting diodes LED can be uniformly self-assembled in the plurality of openings OLH to improve the assembly efficiency.

[0273] Exemplary embodiments of the present disclosure may also be described as follows:

[0274] According to one aspect of the present disclosure, an assembled substrate includes: an assembly substrate; a plurality of first assembly lines disposed on the assembly substrate; a plurality of second assembly lines disposed on the assembly substrate and alternately arranged with the plurality of first assembly lines; and an organic layer disposed on the plurality of first assembly lines and the plurality of second assembly lines and including a plurality of openings, the plurality of openings including a plurality of first oval openings and a plurality of second oval openings having a different planar shape from the plurality of first oval openings. A plurality of unit regions composed of the plurality of first oval openings and the plurality of second oval openings are defined on the assembly substrate, and in the plurality of unit regions, the major axis directions of the plurality of openings in at least one unit region are different from the major axis directions of the plurality of openings in adjacent unit regions.

[0275] The major axes of the plurality of openings can be set in various directions.

[0276] In at least one unit region, the major axes of the plurality of openings can be randomly set.

[0277] Each of the plurality of first assembly lines can include a plurality of first assembly electrodes disposed to overlap the plurality of openings, and each of the plurality of second assembly lines can include a plurality of second assembly electrodes disposed to overlap the plurality of openings. The areas of the plurality of openings overlapping the plurality of first assembly electrodes and the plurality of second assembly electrodes in at least one unit region can be different from the areas of the plurality of openings overlapping the plurality of first assembly electrodes and the plurality of second assembly electrodes in adjacent unit regions.

[0278] Each of the plurality of first assembly lines can include a plurality of first assembly electrodes disposed to overlap the plurality of openings, and each of the plurality of second assembly lines can include a plurality of second assembly electrodes disposed to overlap the plurality of openings. The shapes of the plurality of first assembly electrodes and the plurality of second assembly electrodes in at least one unit region can be different from the shapes of the plurality of first assembly electrodes and the plurality of second assembly electrodes in adjacent unit regions.

[0279] In each of the plurality of unit regions, the areas of the plurality of openings overlapping the plurality of first assembly electrodes and the plurality of second assembly electrodes can be the same.

[0280] In at least one unit region, the planar shapes of the plurality of first assembly electrodes and the plurality of second assembly electrodes can be triangular, and in adjacent unit regions, the planar shapes of the plurality of first assembly electrodes and the plurality of second assembly electrodes can be rectangular.

[0281] In at least one unit area, a plurality of first assembly electrodes and a plurality of second assembly electrodes may be arranged to be spaced apart from each other in the column direction, and in adjacent unit areas, the plurality of first assembly electrodes and the plurality of second assembly electrodes may be arranged to be spaced apart from each other in the column direction, and in another adjacent unit area, the plurality of first assembly electrodes and the plurality of second assembly electrodes may be arranged to be spaced apart from each other in a diagonal direction.

[0282] The plurality of openings may further include a plurality of circular openings.

[0283] According to another aspect of the present disclosure, a method for manufacturing a display device includes: self-assembling a plurality of light-emitting diodes on an assembly substrate; transferring the plurality of light-emitting diodes self-assembled on the assembly substrate to a donor; and transferring the plurality of light-emitting diodes on the donor to an adhesive layer of a display panel. Self-assembling the plurality of light-emitting diodes is a step of applying a voltage to the plurality of assembly electrodes to form an electric field and using the electric field to self-assemble the plurality of light-emitting diodes on the plurality of assembly electrodes. The plurality of light-emitting diodes include a plurality of first elliptical light-emitting diodes and second elliptical light-emitting diodes having a different planar shape from the plurality of first elliptical light-emitting diodes. Self-assembling the plurality of light-emitting diodes on the assembly substrate includes assembling at least a part of the first elliptical light-emitting diodes in a direction different from that of adjacent first elliptical light-emitting diodes, and assembling at least a part of the second elliptical light-emitting diodes in a direction different from that of adjacent second elliptical light-emitting diodes.

[0284] The assembly substrate may include a plurality of first openings corresponding to the planar shape of the plurality of first elliptical light-emitting diodes and a plurality of second elliptical openings corresponding to the planar shape of the plurality of second elliptical light-emitting diodes. Self-assembling the plurality of light-emitting diodes on the assembly substrate may include the step of assembling the plurality of first elliptical light-emitting diodes and the plurality of second elliptical light-emitting diodes in each of the plurality of first elliptical openings and the plurality of second elliptical openings.

[0285] The major axis of each of the plurality of first elliptical openings and the major axis of each of the plurality of second elliptical openings may be arranged on the assembly substrate in various directions, and self-assembling the plurality of light-emitting diodes on the assembly substrate may include the step of assembling the plurality of first elliptical light-emitting diodes and the plurality of second elliptical light-emitting diodes along the respective major axis directions of each of the plurality of first elliptical openings and the plurality of second elliptical openings.

[0286] The plurality of light-emitting diodes may further include a plurality of circular light-emitting diodes. The assembly substrate may further include a plurality of circular openings corresponding to the planar shape of the plurality of circular light-emitting diodes, and self-assembling the plurality of light-emitting diodes on the assembly substrate may include the step of assembling the plurality of circular light-emitting diodes in the plurality of circular openings.

[0287] According to another aspect of the present disclosure, a display device includes: a substrate in which a plurality of pixels including a plurality of sub-pixels are defined; and a plurality of light-emitting diodes disposed in the plurality of pixels, the plurality of light-emitting diodes including a plurality of elliptical light-emitting diodes, and in at least one of the plurality of pixels, the major axes of the plurality of elliptical light-emitting diodes are disposed in directions different from the major axes of the plurality of elliptical light-emitting diodes disposed in adjacent pixels.

[0288] The plurality of light-emitting diodes may include a plurality of first light-emitting diodes, a plurality of second light-emitting diodes, and a plurality of third light-emitting diodes that emit light of different colors. The planar shape of the plurality of first light-emitting diodes may be circular, the planar shape of the plurality of second light-emitting diodes may be elliptical, and the planar shape of the plurality of third light-emitting diodes may be an elliptical shape different from the planar shape of the plurality of second light-emitting diodes. Each of the plurality of light-emitting diodes may include an n-type semiconductor layer, a light-emitting layer disposed on the n-type semiconductor layer, a p-type semiconductor layer disposed on the light-emitting layer, a p-type electrode disposed on the p-type semiconductor layer, and an n-type electrode disposed on the n-type semiconductor layer and spaced apart from the light-emitting layer and the p-type semiconductor layer. The side surfaces of the light-emitting layer and the p-type semiconductor layer facing the n-type electrode may be disposed along the periphery of the n-type electrode.

[0289] In each of the plurality of light-emitting diodes, the n-type electrode may be disposed on one side of the plurality of light-emitting diodes, and the p-type electrode may be disposed on the other side of the plurality of light-emitting diodes.

[0290] The n-type electrode may include a curved surface corresponding to the periphery of the n-type semiconductor layer and a side surface formed by a plane connecting the curved surfaces.

[0291] The n-type electrode may be formed by two side surfaces curved in one direction.

[0292] In each of the plurality of light-emitting diodes, the n-type electrode may be disposed at both ends of the plurality of light-emitting diodes.

[0293] The ratio of the major axis to the minor axis of the plurality of second light-emitting diodes may be different from the ratio of the major axis to the minor axis of the plurality of third light-emitting diodes.

[0294] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto, and the present disclosure may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

Claims

1. An assembly substrate for assembling a plurality of light emitting diodes, the assembly substrate comprising: Assembling substrates; A plurality of first assembly lines are arranged on the assembly substrate; A plurality of second assembly lines are arranged on the assembly substrate and are arranged alternately with the plurality of first assembly lines; as well as an organic layer disposed on the plurality of first assembly lines and the plurality of second assembly lines and comprising a plurality of groups of openings, and Wherein, a plurality of unit areas are defined on the assembly substrate, each of the plurality of unit areas includes a group of openings among the plurality of groups of openings, and among the plurality of unit areas, a long axis direction of a group of openings in at least one unit area is different from a long axis direction of a group of openings in an adjacent unit area.

2. The assembly substrate according to claim 1, wherein: Each group of openings in the multiple groups of openings includes a first elliptical opening and a second elliptical opening having a planar shape different from that of the first elliptical opening. Among the multiple unit areas, the long axis direction of the first elliptical opening and the second elliptical opening in at least one unit area is the same and different from the long axis direction of the first elliptical opening and the second elliptical opening in adjacent unit areas.

3. The assembly substrate according to claim 1, wherein: The long axes of the multiple groups of openings are arranged along different directions.

4. The assembly substrate according to claim 1, wherein: In the at least one unit region, the long axis of each group of openings in the plurality of groups of openings is randomly arranged.

5. The assembly substrate according to claim 1, wherein: The assembly substrate includes a plurality of first assembly electrodes arranged to overlap with each of the plurality of groups of openings and connected to each of the plurality of first assembly lines, The assembly substrate includes a plurality of second assembly electrodes arranged to overlap with each of the plurality of groups of openings and connected to each of the plurality of second assembly lines, and An area of ​​each of the plurality of groups of openings in the at least one unit region that overlaps with the plurality of first mounting electrodes and the plurality of second mounting electrodes is different from an area of ​​each of the plurality of groups of openings in an adjacent unit region that overlaps with the plurality of first mounting electrodes and the plurality of second mounting electrodes.

6. The assembly substrate according to claim 1, wherein: The assembly substrate includes a plurality of first assembly electrodes arranged to overlap the plurality of groups of openings and connected to each of the plurality of first assembly lines, The assembly substrate includes a plurality of second assembly electrodes arranged to overlap the plurality of groups of openings and connected to each of the plurality of second assembly lines, and The shapes of the plurality of first mount electrodes and the plurality of second mount electrodes in the at least one unit region are different from the shapes of the plurality of first mount electrodes and the plurality of second mount electrodes in an adjacent unit region.

7. The assembly substrate according to claim 6, wherein: In each of the plurality of unit regions, an area of ​​each of the plurality of groups of openings overlapping with the plurality of first mounting electrodes and the plurality of second mounting electrodes is the same.

8. The assembly substrate according to claim 7, wherein: In the at least one unit region, the planar shapes of the plurality of first mounting electrodes and the plurality of second mounting electrodes are triangles, and In the adjacent cell region, a planar shape of the plurality of first mount electrodes and the plurality of second mount electrodes is a rectangle.

9. The assembly substrate according to claim 7, wherein: In the at least one unit region, the plurality of first mounting electrodes and the plurality of second mounting electrodes are arranged to be spaced apart from each other in a column direction, In the adjacent cell region, the plurality of first mounting electrodes and the plurality of second mounting electrodes are arranged to be spaced apart from each other along the column direction, and In another adjacent cell region, the plurality of first mount electrodes and the plurality of second mount electrodes are disposed to be spaced apart from each other in an oblique direction.

10. The assembly substrate according to claim 1, wherein: The plurality of groups of openings also include circular openings.

11. A method for manufacturing a display device, comprising: self-assembling a plurality of light emitting diodes on an assembly substrate; transferring the plurality of light emitting diodes self-assembled on the assembly substrate to a donor; as well as transferring the plurality of light emitting diodes on the donor to a display panel, The self-assembly of the plurality of light emitting diodes is a step of applying a voltage to a plurality of assembly electrodes to form an electric field and utilizing the electric field to self-assemble the plurality of light emitting diodes on the plurality of assembly electrodes. The plurality of light emitting diodes include a plurality of groups of light emitting diodes, each of the plurality of groups of light emitting diodes includes a first elliptical light emitting diode and a second elliptical light emitting diode having a planar shape different from that of the first elliptical light emitting diode, The self-assembly of a plurality of light emitting diodes on an assembly substrate comprises: assembling the first elliptical LEDs in another adjacent group of LEDs in a different direction from the first elliptical LEDs in one group of LEDs, and The second elliptical light emitting diodes in another adjacent group of light emitting diodes are assembled in a direction different from the second elliptical light emitting diodes in one group of light emitting diodes.

12. The method for manufacturing a display device according to claim 11, wherein: The assembly substrate includes a first elliptical opening corresponding to a planar shape of the first elliptical light emitting diode and a second elliptical opening corresponding to a planar shape of the second elliptical light emitting diode, and The self-assembly of a plurality of light emitting diodes on an assembly substrate comprises: The step of assembling the first and second elliptical light emitting diodes in each of the first and second elliptical openings.

13. The method for manufacturing a display device according to claim 12, wherein: The major axis of the first elliptical opening and the major axis of the second elliptical opening are arranged on the assembly substrate along different directions, and The self-assembly of a plurality of light emitting diodes on an assembly substrate comprises: The step of assembling the first elliptical light emitting diode and the second elliptical light emitting diode along different major axis directions of the first elliptical opening and the second elliptical opening.

14. The method for manufacturing a display device according to claim 13, wherein: Each of the plurality of groups of light emitting diodes further comprises a circular light emitting diode, The assembly substrate further includes a circular opening corresponding to the planar shape of the circular light emitting diode, and The self-assembly of a plurality of light emitting diodes on an assembly substrate comprises: The step of assembling a circular light emitting diode in the circular opening.

15. A display device, comprising: a substrate having a plurality of pixels defined therein, each of the plurality of pixels comprising a plurality of sub-pixels; as well as A plurality of light emitting diodes are respectively arranged in the plurality of sub-pixels, The plurality of light emitting diodes include a plurality of groups of light emitting diodes, each of the plurality of groups of light emitting diodes includes a plurality of elliptical light emitting diodes, and Among the plurality of sub-pixels, major axes of the plurality of elliptical light emitting diodes in at least one sub-pixel are disposed in a direction different from major axes of the plurality of elliptical light emitting diodes disposed in an adjacent sub-pixel.

16. The display device according to claim 15, wherein: Each of the plurality of groups of light emitting diodes comprises a first light emitting diode, a second light emitting diode and a third light emitting diode that emit light of different colors, The planar shape of the first light emitting diode is a circle, the planar shape of the second light emitting diode is an ellipse, and the planar shape of the third light emitting diode is an ellipse different from the planar shapes of the plurality of second light emitting diodes, Each of the plurality of light emitting diodes comprises: n-type semiconductor layer; A light emitting layer disposed on the n-type semiconductor layer; A p-type semiconductor layer disposed on the light-emitting layer; A p-type electrode disposed on the p-type semiconductor layer; and an n-type electrode disposed on the n-type semiconductor layer and spaced apart from the light emitting layer and the p-type semiconductor layer, and The light emitting layer and the side surface of the p-type semiconductor layer facing the n-type electrode are disposed along a periphery of the n-type electrode.

17. The display device according to claim 16, wherein: In each of the plurality of light emitting diodes, the n-type electrode is disposed on one side of the plurality of light emitting diodes, and the p-type electrode is disposed on the other side of the plurality of light emitting diodes.

18. The display device according to claim 17, wherein: The n-type electrode includes a curved surface corresponding to a periphery of the n-type semiconductor layer and a side surface formed by a flat surface connecting the curved surface.

19. The display device according to claim 17, wherein: The n-type electrode is formed by two side surfaces bent in one direction.

20. The display device according to claim 17, wherein: In each of the plurality of light emitting diodes, the n-type electrode is provided at both ends of the plurality of light emitting diodes.

21. The display device according to claim 16, wherein: A ratio of a major axis to a minor axis of the second light emitting diode is different from a ratio of a major axis to a minor axis of the third light emitting diode.

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