Display device

Abstract

The invention relates to a display device. The display device includes pixel electrodes disposed in a first direction and a second direction crossing the first direction; a pixel defining layer disposed on the pixel electrodes, exposing a central portion of each of the pixel electrodes, covering a peripheral portion of each of the pixel electrodes, the first pixel defining layer extends in the first direction and is spaced apart from each other in the second direction, and the second pixel defining layer extends in the second direction and is spaced apart from each other in the first direction; and a spacer disposed between two of the second pixel defining layers disposed adjacent to each other in the first direction and between two of the pixel electrodes disposed adjacent to each other in the second direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device. Background Art

[0002] Flat panel display devices have replaced cathode ray tube display devices as commonly used display devices due to their light weight and thin characteristics. Representative examples of flat panel displays include liquid crystal displays (LCDs) and organic light emitting displays (OLEDs).

[0003] The flat panel display device includes a display area that displays an image. The display area includes an emission area that emits light and a non-emission area arranged around the emission area. The light emitting element is arranged in the emission area, and a structure such as a spacer is arranged in the non-emission area. Summary of the invention

[0004] Embodiments of the present invention provide a display device with improved display quality.

[0005] According to an embodiment, a display device includes: a plurality of thin film transistors; an insulating layer disposed on the thin film transistors and including an organic insulating material; a plurality of pixel electrodes disposed on the insulating layer, electrically connected to the thin film transistors, and disposed in a first direction and a second direction intersecting the first direction; and a pixel defining layer disposed on the insulating layer and the pixel electrodes, exposing a central portion of each of the pixel electrodes, and covering a peripheral portion of each of the pixel electrodes. The pixel defining layer includes: a plurality of first pixel defining layers extending in a first direction and spaced apart from each other in a second direction; and a plurality of second pixel defining layers extending in a second direction and spaced apart from each other in the first direction. The display device also includes: a spacer disposed on the insulating layer, and disposed between two second pixel defining layers disposed in the second pixel defining layer to be adjacent to each other in the first direction and between two pixel electrodes disposed in the pixel electrode to be adjacent to each other in the second direction.

[0006] In an embodiment, the spacer is spaced apart from each of the second pixel defining layers in a plan view.

[0007] In an embodiment, the spacer is located inside one of the first pixel defining layers in a plan view.

[0008] In an embodiment, an outer side surface of the spacer contacts an inner side surface of one first pixel defining layer.

[0009] In an embodiment, a lower surface of the spacer and a lower surface of each of the first pixel defining layers contact an upper surface of the insulating layer.

[0010] In an embodiment, a distance between an upper surface of the insulating layer and an upper surface of the spacer is greater than a distance between an upper surface of the insulating layer and an upper surface of each of the second pixel defining layers.

[0011] In an embodiment, the display device further includes: a plurality of emission layers disposed on the pixel electrode, extending in the second direction, and spaced apart from each other in the first direction; and a common electrode disposed on the pixel electrode, the pixel defining layer, and the emission layer. Each of the emission layers is disposed between two second pixel defining layers disposed adjacent to each other in the first direction.

[0012] In an embodiment, the emission layer includes a first emission layer, a second emission layer and a third emission layer. The first emission layer, the second emission layer and the third emission layer emit light of different colors and are sequentially arranged in a first direction.

[0013] In an embodiment, the spacer is located inside one of the emission layers in a plan view.

[0014] In an embodiment, an outer side surface of the spacer contacts an inner side surface of one of the emission layers.

[0015] In an embodiment, the display device further includes: an auxiliary electrode disposed under the insulating layer and overlapping one of the first pixel defining layers. The common electrode is electrically connected to the auxiliary electrode through a contact hole penetrating the insulating layer and one of the first pixel defining layers.

[0016] In an embodiment, the display device further includes a first dam disposed on one of the first pixel defining layers and surrounding the contact hole in a plan view.

[0017] In an embodiment, the first dam is located inside one of the emission layers in a plan view.In a plan view, one emission layer is disposed outside the first dam and is not disposed inside the first dam.

[0018] In an embodiment, an outer side surface of the first dam contacts an inner side surface of one of the emission layers.

[0019] In an embodiment, the first dam is spaced apart from the spacer, and at least one of the pixel electrodes or at least one of the second pixel defining layers is interposed between the first dam and the spacer in a plan view.

[0020] In an embodiment, a through hole is defined, the through hole passing through one of the first pixel defining layers and exposing an upper surface of the insulating layer. The display device further includes: a second dam disposed on the one of the first pixel defining layers and surrounding the through hole in a plan view.

[0021] In an embodiment, the second dam is spaced apart from the spacer, and at least one of the pixel electrodes or at least one of the second pixel defining layers is interposed between the second dam and the spacer in a plan view.

[0022] According to an embodiment, a display device includes: a plurality of thin film transistors; an insulating layer disposed on the thin film transistors and including an organic insulating material; a plurality of pixel electrodes disposed on the insulating layer, electrically connected to the thin film transistors, and disposed in a first direction and a second direction intersecting the first direction; and a pixel defining layer disposed on the insulating layer and the pixel electrodes, exposing a central portion of each of the pixel electrodes, and covering a peripheral portion of each of the pixel electrodes. The pixel defining layer includes: a plurality of first pixel defining layers extending in a first direction and spaced apart from each other in a second direction; and a plurality of second pixel defining layers extending in the second direction and spaced apart from each other in the first direction. The display device also includes: an auxiliary electrode disposed under the insulating layer and overlapping with one of the first pixel defining layers; a plurality of emission layers disposed on the pixel electrodes, extending in the second direction, and spaced apart from each other in the first direction; and a common electrode disposed on the pixel electrodes, the pixel defining layer, and the emission layer, and electrically connected to the auxiliary electrode through a contact hole passing through the insulating layer and one of the first pixel defining layers.

[0023] In an embodiment, the display device further includes a dam disposed on the one first pixel defining layer and surrounding the contact hole in a plan view.

[0024] According to an embodiment, a display device includes: a plurality of thin film transistors; an insulating layer disposed on the thin film transistors and including an organic insulating material; a plurality of pixel electrodes disposed on the insulating layer, electrically connected to the thin film transistors, and disposed in a first direction and a second direction intersecting the first direction; and a pixel defining layer disposed on the insulating layer and the pixel electrodes, exposing a central portion of each of the pixel electrodes, and covering a peripheral portion of each of the pixel electrodes. The pixel defining layer includes: a plurality of first pixel defining layers extending in a first direction and spaced apart from each other in a second direction; and a plurality of second pixel defining layers extending in the second direction and spaced apart from each other in the first direction. The display device also includes: a dam disposed on one of the first pixel defining layers and surrounding a through hole in a plan view, the through hole passing through one of the first pixel defining layers and exposing an upper surface of the insulating layer.

[0025] A display device according to an embodiment of the present invention may include a pixel defining layer defining an emission region and a non-emission region. The pixel defining layer may include a first pixel defining layer extending in one direction and a second pixel defining layer intersecting the first pixel defining layer. A structure such as a spacer disposed in the non-emission region may overlap with the first pixel defining layer and not overlap with the second pixel defining layer. Therefore, the width of the second pixel defining layer may be reduced, and a display device having high resolution and improved display quality may be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other features of the present invention will become more apparent by describing in detail the embodiments of the present invention with reference to the attached drawings.

[0027] Figure 1 is a plan view showing a display device according to an embodiment.

[0028] Figure 2 It is shown that the Figure 1 A plan view of a pixel in a display device.

[0029] Figure 3 It is along Figure 2 A cross-sectional view taken along line II'.

[0030] Figure 4 It is along Figure 2 A cross-sectional view taken along line II-II'.

[0031] Figure 5 It is along Figure 2 A cross-sectional view taken along line III-III'.

[0032] Figure 6 It is along Figure 2 A cross-sectional view taken along line IV-IV'.

[0033] Figure 7 It is along Figure 2 A cross-sectional view taken along line V-V'.

[0034] Figures 8 to 18 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0035] Embodiments of the present invention will be described more fully hereinafter with reference to the accompanying drawings.In all drawings, the same reference numerals may refer to the same elements.

[0036] It will be understood that when an element is referred to as being associated with another element (such as being "on" another element), it can be directly on the other element or intervening elements may be present between them. Conversely, when an element is referred to as being associated with another element (such as being "directly on" another element), there are no intervening elements.

[0037] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the teachings herein, the "first element", "first component", "first region", "first layer" or "first section" discussed below may be referred to as a second element, second component, second region, second layer or second section.

[0038] The terms used herein are only used for the purpose of describing specific embodiments, and are not intended to be limiting. As used herein, "one", "the", "at least one" do not represent a limit to quantity, and are intended to include both the singular and the plural, unless the context clearly indicates otherwise. For example, "an element" has the same meaning as "at least one element", unless the context clearly indicates otherwise. "At least one" should not be interpreted as limiting "one" or "one". "Or" means "and / or". As used herein, reference numerals can represent single elements or multiple elements. For example, the reference numerals marking the elements in the singular form in the drawings can be used to reference multiple singular elements in the text of the specification.

[0039] As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It will be further understood that when used in this specification, the terms "comprises" and / or "comprising" or "includes" and / or "including" specify the presence of stated features, regions, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or groups thereof.

[0040] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the figures. It will be understood that relative terms are intended to include different orientations of the device in addition to the orientations depicted in the drawings. For example, if the device in one of the figures is turned over, the element described as being on the "lower" side of the other elements will then be oriented on the "upper" side of the other elements. Therefore, depending on the specific orientation of the drawings, the term "lower" may include both "lower" and "upper" orientations. Similarly, if the device in one of the figures is turned over, the element described as being "below" or "below" the other elements will then be oriented "above" the other elements. Therefore, the term "below" or "below" may include both upper and lower orientations.

[0041] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, in view of the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0042] Figure 1 is a plan view showing a display device according to an embodiment.

[0043] refer to Figure 1 In an embodiment, the display device 10 may have a display surface defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. The display device 10 may display an image in a third direction DR3 through the display surface. For example, the second direction DR2 may be substantially perpendicular to the first direction DR1. The third direction DR3 may be substantially parallel to the normal direction of the display surface. The display surface may correspond to the front surface (or upper surface) of the display device 10.

[0044] The display device 10 may include a display area DA and a non-display area NDA. A plurality of pixels PX generating an image may be disposed in the display area DA.

[0045] Each of the pixels PX may include a pixel circuit and a light emitting element. The pixel circuit may include at least one thin film transistor and at least one capacitor. The thin film transistor may generate a driving current and provide the generated driving current to the light emitting element. The light emitting element may emit light based on the driving current. For example, the light emitting element may include an organic light emitting diode, an inorganic light emitting diode, a quantum dot light emitting diode, etc. An image may be generated by combining the light emitted from each of the pixels PX.

[0046] The non-display area NDA may be located around the display area DA. The non-display area NDA may be located outside the display area DA. For example, in a plan view, the non-display area NDA may surround the display area DA. In a plan view, the non-display area NDA may completely or partially surround the display area DA.

[0047] The driver may be disposed in the non-display area NDA. The driver may provide various driving signals (eg, driving voltage, gate signal, data signal, etc.) for driving the pixels PX to the display area DA. For example, the driver may include a data driver, a gate driver, etc.

[0048] Figure 2 It is shown that the Figure 1 A plan view of a pixel in a display device.

[0049] refer to Figure 2 , the display area DA may include emission areas EA (eg, first emission area EA1 , second emission area EA2 , and third emission area EA3 ) emitting light of different colors and a non-emission area NEA.

[0050] The first emission area EA1, the second emission area EA2, and the third emission area EA3 are disposed adjacent to each other and may form one pixel area. The display area DA may include a plurality of pixel areas.

[0051] Light of a first color may be emitted from the first emission area EA1, light of a second color may be emitted from the second emission area EA2, and light of a third color may be emitted from the third emission area EA3. A first sub-pixel SPX1 emitting light of the first color may be disposed in the first emission area EA1, a second sub-pixel SPX2 emitting light of the second color may be disposed in the second emission area EA2, and a third sub-pixel SPX3 emitting light of the third color may be disposed in the third emission area EA3. For example, the first color may be red, the second color may be green, and the third color may be blue, but this is an example, and embodiments are not limited thereto. The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 disposed in one pixel area may form one pixel PX.

[0052] In an embodiment, in a plan view, a plurality of pixel areas may be arranged in a matrix form in the first direction DR1 and the second direction DR2. That is, in a plan view, a plurality of pixels PX may be arranged in a matrix form in the first direction DR1 and the second direction DR2. For example, in each of the pixel areas, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be sequentially arranged to be spaced apart from each other in the first direction DR1. That is, in each of the pixel areas, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be sequentially arranged to be spaced apart from each other in the first direction DR1. In addition, a plurality of first emission areas EA1 may be arranged to be spaced apart from each other in the second direction DR2, a plurality of second emission areas EA2 may be arranged to be spaced apart from each other in the second direction DR2, and a plurality of third emission areas EA3 may be arranged to be spaced apart from each other in the second direction DR2.

[0053] The non-emission area NEA may be an area that does not emit light. The non-emission area NEA may be disposed adjacent to the first emission area EA1, the second emission area EA2, and the third emission area EA3. In an embodiment, in a plan view, the non-emission area NEA may surround each of the first emission area EA1, the second emission area EA2, and the third emission area EA3. For example, in a plan view, the non-emission area NEA may have a grid shape.

[0054] The first emission area EA1, the second emission area EA2, and the third emission area EA3 and the non-emission area NEA may be defined by the pixel defining layer 160. The pixel defining layer 160 may define a first pixel opening OP1 exposing a central portion of the first pixel electrode PE1 of the first sub-pixel SPX1, a second pixel opening OP2 exposing a central portion of the second pixel electrode PE2 of the second sub-pixel SPX2, and a third pixel opening OP3 exposing a central portion of the third pixel electrode PE3 of the third sub-pixel SPX3. The pixel defining layer 160 may cover a peripheral portion of each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. For example, in a plan view, the pixel defining layer 160 may have a grid shape.

[0055] In a plan view, the first emission area EA1 may be defined by the first pixel opening OP1, the second emission area EA2 may be defined by the second pixel opening OP2, and the third emission area EA3 may be defined by the third pixel opening OP3. In a plan view, the non-emission area NEA may be defined as an area where the pixel defining layer 160 is disposed. In other words, the non-emission area NEA may be defined as an area overlapping the pixel defining layer 160.

[0056] In an embodiment, the pixel defining layer 160 may include a first pixel defining layer 162 and a second pixel defining layer 164. Figure 2 As shown in , each of the first pixel defining layers 162 may extend in the first direction DR1, and the first pixel defining layers 162 may be spaced apart from each other in the second direction DR2. For example, each of the first pixel defining layers 162 may extend longitudinally in the first direction DR1, and the first pixel defining layers 162 may be spaced apart from each other in the second direction DR2. Each of the second pixel defining layers 164 may extend in the second direction DR2, and the second pixel defining layers 164 may be spaced apart from each other in the first direction DR1. For example, each of the second pixel defining layers 164 may extend longitudinally in the second direction DR2, and the second pixel defining layers 164 may be spaced apart from each other in the first direction DR1. The first pixel defining layer 162 and the second pixel defining layer 164 may cross each other.

[0057] In an embodiment, the non-emission area NEA may include a first non-emission area NEA1, a second non-emission area NEA2, and a third non-emission area NEA3. Each of the first non-emission areas NEA1 may be defined as an area where the first pixel defining layer 162 is disposed and the second pixel defining layer 164 is not disposed. In other words, each of the first non-emission areas NEA1 may be defined as an area overlapping the first pixel defining layer 162 and not overlapping the second pixel defining layer 164. For example, in a plan view, the first non-emission areas NEA1 may be disposed in a matrix form in the first direction DR1 and the second direction DR2.

[0058] Each of the second non-emission areas NEA2 may be defined as an area where the second pixel defining layer 164 is disposed and the first pixel defining layer 162 is not disposed. In other words, each of the second non-emission areas NEA2 may be defined as an area overlapping the second pixel defining layer 164 and not overlapping the first pixel defining layer 162. For example, in a plan view, the second non-emission areas NEA2 may be disposed in a matrix form in the first direction DR1 and the second direction DR2.

[0059] Each of the third non-emission areas NEA3 may be defined as an area where both the first pixel defining layer 162 and the second pixel defining layer 164 are disposed. In other words, each of the third non-emission areas NEA3 may be defined as an area overlapping both the first pixel defining layer 162 and the second pixel defining layer 164. That is, each of the third non-emission areas NEA3 may be an area where the first pixel defining layer 162 and the second pixel defining layer 164 cross each other. For example, in a plan view, the third non-emission areas NEA3 may be disposed in a matrix form in the first direction DR1 and the second direction DR2.

[0060] In an embodiment, a structure such as the spacer 170, the auxiliary electrode contact portion ACP, or the thickness measuring portion TMP may be disposed in a portion of the first non-emission area NEA1 of the display area DA. For example, one of the spacer 170, the auxiliary electrode contact portion ACP, and the thickness measuring portion TMP may be disposed in one of the first non-emission areas NEA1, and in the other of the first non-emission areas NEA1, all of the spacer 170, the auxiliary electrode contact portion ACP, and the thickness measuring portion TMP may not be disposed. In an embodiment, a structure such as the spacer 170, the auxiliary electrode contact portion ACP, or the thickness measuring portion TMP is not disposed in the second non-emission area NEA2 and the third non-emission area NEA3.

[0061] In the comparative example, the structure is disposed in the third non-emission area NEA3 where the first pixel defining layer 162 and the second pixel defining layer 164 cross each other. In this case, due to the size of the structure, there is a limitation in reducing the width in the first direction DR1 of each of the second pixel defining layers 164. That is, it may be difficult to reduce the width in the first direction DR1 of each of the second non-emission area NEA2 and the third non-emission area NEA3, and therefore, it may be difficult to achieve high resolution. However, according to an embodiment of the present invention, a structure such as a spacer 170, an auxiliary electrode contact portion ACP, or a thickness measurement portion TMP is not disposed in the second non-emission area NEA2 and the third non-emission area NEA3, and may be disposed only in the first non-emission area NEA1. Therefore, the width in the first direction DR1 of each of the second non-emission area NEA2 and the third non-emission area NEA3 may be reduced. That is, since the structure does not overlap with each of the second pixel defining layers 164, the width in the first direction DR1 of each of the second pixel defining layers 164 may be further reduced. Therefore, according to an embodiment of the present invention, a high-resolution display device 10 with improved display quality may be implemented.

[0062] Figure 2 It is shown that one spacer 170, three auxiliary electrode contact portions ACP, and one thickness measurement portion TMP are arranged to correspond to one pixel area. However, this is an example, and the embodiment is not limited thereto. For example, the setting or arrangement of the spacer 170, the auxiliary electrode contact portion ACP, and the thickness measurement portion TMP may be variously modified. For example, one spacer 170 may be arranged to correspond to a plurality of pixel areas. Similarly, one auxiliary electrode contact portion ACP may be arranged to correspond to a plurality of pixel areas, and one thickness measurement portion TMP may be arranged to correspond to a plurality of pixel areas. In addition, Figure 2The display device 10 is shown to include all of the spacer 170, the auxiliary electrode contact portion ACP, and the thickness measuring portion TMP, but according to an embodiment, some of the spacer 170, the auxiliary electrode contact portion ACP, and the thickness measuring portion TMP may be omitted. The spacer 170, the auxiliary electrode contact portion ACP, and the thickness measuring portion TMP will be described in more detail below.

[0063] Figure 3 It is along Figure 2 A cross-sectional view taken along line II'. Figure 4 It is along Figure 2 A cross-sectional view taken along line II-II'.

[0064] In the following, reference will be made to Figures 2 to 4 The plurality of pixels PX disposed in the plurality of pixel regions included in the display area DA are described in detail.

[0065] refer to Figures 2 to 4 In an embodiment, the display device 10 may include a substrate 110, a buffer layer 120, insulating layers 130, 140 and 150, a pixel defining layer 160, and a plurality of pixels PX. Each of the pixels PX may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3 that emit light of different colors. The first sub-pixel SPX1 may include a first pixel circuit and a first light-emitting element LED1 that emits light of a first color (e.g., red), and the first pixel circuit includes a first thin film transistor TR1. The second sub-pixel SPX2 may include a second pixel circuit and a second light-emitting element LED2 that emits light of a second color (e.g., green), and the second pixel circuit includes a second thin film transistor TR2. The third sub-pixel SPX3 may include a third pixel circuit and a third light-emitting element LED3 that emits light of a third color (e.g., blue), and the third pixel circuit includes a third thin film transistor TR3.

[0066] The substrate 110 may be an insulating substrate including or formed of a transparent material or an opaque material. In an implementation, the substrate 110 may be a rigid substrate including a material such as, for example, glass or quartz. In an implementation, the substrate 110 may be a flexible substrate including plastic.

[0067] The buffer layer 120 may be disposed on the substrate 110. The buffer layer 120 may prevent or reduce impurities such as, for example, oxygen or moisture from penetrating into the upper portion of the substrate 110 through the substrate 110. The buffer layer 120 may include an inorganic material. In an embodiment, for example, the buffer layer 120 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), aluminum oxide (AlO), aluminum nitride (AlN), tantalum oxide (TaO), hafnium oxide (HfO), zirconium oxide (ZrO), titanium oxide (TiO), etc., alone or in combination thereof. The buffer layer 120 may have a single-layer structure or a multilayer structure including a plurality of insulating layers. In an embodiment, the buffer layer 120 may be omitted.

[0068] The first thin film transistor TR1, the second thin film transistor TR2, and the third thin film transistor TR3 may be disposed on the buffer layer 120. The first thin film transistor TR1 may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. Each of the second thin film transistor TR2 and the third thin film transistor TR3 may be substantially the same as or similar to the first thin film transistor TR1.

[0069] The active layer ACT may be disposed on the buffer layer 120. The active layer ACT may include, for example, an oxide semiconductor, a silicon semiconductor, an organic semiconductor, etc. In an embodiment, the oxide semiconductor may include, for example, at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The silicon semiconductor may include, for example, amorphous silicon, polycrystalline silicon, etc. The active layer ACT may include a source region, a drain region, and a channel region located between the source region and the drain region.

[0070] The first insulating layer 130 may be disposed on the active layer ACT. The first insulating layer 130 may cover the active layer ACT on the buffer layer 120. The first insulating layer 130 may include an inorganic insulating material.

[0071] The gate electrode GE may be disposed on the first insulating layer 130. The gate electrode GE may overlap the channel region of the active layer ACT. The gate electrode GE may include a conductive material such as, for example, a metal, an alloy, a conductive metal nitride, a conductive metal oxide, a transparent conductive material, and the like. In an embodiment, the gate electrode GE may include, for example, gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), aluminum-containing alloy, silver-containing alloy, copper-containing alloy, molybdenum-containing alloy, aluminum nitride (AlN), tungsten nitride (WN), titanium nitride (TiN), chromium nitride (CrN), tantalum nitride (TaN), strontium ruthenium oxide (SrRuO), zinc oxide (ZnO), indium tin oxide (ITO), tin oxide (SnO), indium oxide (InO), gallium oxide (GaO), indium zinc oxide (IZO), etc., alone or in combination thereof. The gate electrode GE may have a single-layer structure or a multi-layer structure including a plurality of conductive layers.

[0072] The second insulating layer 140 may be disposed on the gate electrode GE. The second insulating layer 140 may cover the gate electrode GE on the first insulating layer 130. The second insulating layer 140 may include an inorganic insulating material.

[0073] The source electrode SE and the drain electrode DE may be disposed on the second insulating layer 140. The source electrode SE and the drain electrode DE may be connected to the source region and the drain region of the active layer ACT, respectively. Each of the source electrode SE and the drain electrode DE may include a conductive material.

[0074] The third insulating layer 150 may be disposed on the source electrode SE and the drain electrode DE. The third insulating layer 150 may include an organic insulating material. In an implementation, the third insulating layer 150 may include, for example, a photoresist, a polyacrylic-based resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, an acrylic-based resin, an epoxy-based resin, etc., used alone or in combination.

[0075] The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be disposed on the third insulating layer 150. The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be sequentially spaced apart from each other in the first direction DR1. In addition, a plurality of first pixel electrodes PE1 may be spaced apart from each other in the second direction DR2, a plurality of second pixel electrodes PE2 may be spaced apart from each other in the second direction DR2, and a plurality of third pixel electrodes PE3 may be spaced apart from each other in the second direction DR2. That is, in the display area DA, a plurality of pixel electrodes may be disposed in a matrix form along the first direction DR1 and the second direction DR2.

[0076] Each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may include a conductive material. Each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may have a single layer structure or a multi-layer structure including a plurality of conductive layers.

[0077] The first pixel electrode PE1 may overlap the first emission area EA1 . The first pixel electrode PE1 may be connected to the drain electrode DE of the first thin film transistor TR1 through a first contact hole formed in the third insulating layer 150 .

[0078] The second pixel electrode PE2 may overlap the second emission area EA2 . The second pixel electrode PE2 may be connected to the drain electrode of the second thin film transistor TR2 through a second contact hole formed in the third insulating layer 150 .

[0079] The third pixel electrode PE3 may overlap the third emission area EA3 . The third pixel electrode PE3 may be connected to the drain electrode of the third thin film transistor TR3 through a third contact hole formed in the third insulating layer 150 .

[0080] The pixel defining layer 160 may be disposed on the third insulating layer 150 and the first, second, and third pixel electrodes PE1, PE2, and PE3. The pixel defining layer 160 may define a first pixel opening OP1 exposing a central portion of the first pixel electrode PE1, a second pixel opening OP2 exposing a central portion of the second pixel electrode PE2, and a third pixel opening OP3 exposing a central portion of the third pixel electrode PE3. The pixel defining layer 160 may cover a peripheral portion of each of the first, second, and third pixel electrodes PE1, PE2, and PE3.

[0081] The pixel defining layer 160 may include a first pixel defining layer 162 and a second pixel defining layer 164. Each of the first pixel defining layer 162 and the second pixel defining layer 164 may include an organic insulating material. In an implementation, for example, each of the first pixel defining layer 162 and the second pixel defining layer 164 may include photoresist.

[0082] Each of the first pixel defining layers 162 may extend in the first direction DR1, and the first pixel defining layers 162 may be spaced apart from each other in the second direction DR2. Each of the second pixel defining layers 164 may extend in the second direction DR2, and the second pixel defining layers 164 may be spaced apart from each other in the first direction DR1. The first pixel defining layer 162 and the second pixel defining layer 164 may cross each other. The second pixel defining layer 164 may be disposed on the first pixel defining layer 162. The thickness of each of the second pixel defining layers 164 may be greater than the thickness of each of the first pixel defining layers 162. The upper surface of each of the second pixel defining layers 164 may have liquid repellency.

[0083] The first emission layer EL1 may be disposed on the first pixel electrode PE1, the second emission layer EL2 may be disposed on the second pixel electrode PE2, and the third emission layer EL3 may be disposed on the third pixel electrode PE3. In an embodiment, the first emission layer EL1, the second emission layer EL2, and the third emission layer EL3 may be formed by inkjet printing.

[0084] The first emission layer EL1 may be disposed at least in the first pixel opening OP1 of the pixel defining layer 160. Figure 4 As shown in , the first emission layer EL1 may extend in the second direction DR2. In the display area DA, a plurality of first emission layers EL1 each extending in the second direction DR2 may be spaced apart from each other in the first direction DR1. Each of the first emission layers EL1 may overlap with a plurality of first emission areas EA1 spaced apart from each other in the second direction DR2. That is, each of the first emission layers EL1 may overlap with a plurality of first pixel electrodes PE1 spaced apart from each other in the second direction DR2. In addition, each of the first emission layers EL1 may also overlap with a first non-emission area NEA1 disposed between two first emission areas EA1 adjacent to each other in the second direction DR2.

[0085] The second emission layer EL2 may be disposed at least in the second pixel opening OP2 of the pixel defining layer 160. In an embodiment, the second emission layer EL2 may extend in the second direction DR2. In the display area DA, a plurality of second emission layers EL2 each extending in the second direction DR2 may be spaced apart from each other in the first direction DR1. Each of the second emission layers EL2 may overlap with a plurality of second emission regions EA2 spaced apart from each other in the second direction DR2. That is, each of the second emission layers EL2 may overlap with a plurality of second pixel electrodes PE2 spaced apart from each other in the second direction DR2. In addition, each of the second emission layers EL2 may also overlap with a first non-emission region NEA1 between two second emission regions EA2 disposed adjacent to each other in the second direction DR2.

[0086] The third emission layer EL3 may be disposed at least in the third pixel opening OP3 of the pixel defining layer 160. In an embodiment, the third emission layer EL3 may extend in the second direction DR2. In the display area DA, a plurality of third emission layers EL3 each extending in the second direction DR2 may be spaced apart from each other in the first direction DR1. Each of the third emission layers EL3 may overlap with a plurality of third emission regions EA3 spaced apart from each other in the second direction DR2. That is, each of the third emission layers EL3 may overlap with a plurality of third pixel electrodes PE3 spaced apart from each other in the second direction DR2. In addition, each of the third emission layers EL3 may also overlap with a first non-emission region NEA1 between two third emission regions EA3 disposed adjacent to each other in the second direction DR2.

[0087] Each of the first emission layer EL1, the second emission layer EL2, and the third emission layer EL3 may extend in the second direction DR2, and the first emission layer EL1, the second emission layer EL2, and the third emission layer EL3 may be sequentially spaced apart from each other in the first direction DR1. Each of the first emission layer EL1, the second emission layer EL2, and the third emission layer EL3 may be disposed between two second pixel defining layers 164 disposed adjacent to each other in the first direction DR1 in the second pixel defining layers 164.

[0088] The first emission layer EL1 may include a first emission material that emits light of a first color (e.g., red), the second emission layer EL2 may include a second emission material that emits light of a second color (e.g., green), and the third emission layer EL3 may include a third emission material that emits light of a third color (e.g., blue). In some embodiments, each of the first to third emission materials may include at least one of an organic emission material and a quantum dot.

[0089] In an embodiment, the organic emission material may include a low molecular weight organic compound or a high molecular weight organic compound. Examples of low molecular weight organic compounds may include copper phthalocyanine, N,N'-diphenylbenzidine, tris-(8-hydroxyquinoline)aluminum, etc. Examples of high molecular weight organic compounds may include poly(3,4-ethylenedioxythiophene), polyaniline, polystyrene, polyfluorene, etc. These may be used alone or in combination.

[0090] In an embodiment, the quantum dot may include a core, the core including, for example, a II-VI compound, a III-V compound, a IV-VI compound, a IV element, and / or a IV compound. In an embodiment, the quantum dot may have a core-shell structure including a core and a shell surrounding the core. The shell may be used as a protective layer that can prevent the chemical denaturation of the core to maintain semiconductor properties, and may be used as a charging layer that can impart electrophoretic properties to the quantum dot.

[0091] The common electrode CE may be disposed on the first emission layer EL1, the second emission layer EL2, and the third emission layer EL3. The common electrode CE may also be disposed on the pixel defining layer 160. For example, the common electrode CE may completely overlap the display area DA. The common electrode CE may include a conductive material.

[0092] The first pixel electrode PE1, a portion of the first emission layer EL1, and a portion of the common electrode CE that overlap with each other in the first emission area EA1 may form a first light emitting element LED1. The second pixel electrode PE2, a portion of the second emission layer EL2, and a portion of the common electrode CE that overlap with each other in the second emission area EA2 may form a second light emitting element LED2. The third pixel electrode PE3, a portion of the third emission layer EL3, and a portion of the common electrode CE that overlap with each other in the third emission area EA3 may form a third light emitting element LED3.

[0093] According to an embodiment, the display device 10 may further include various functional layers disposed on the common electrode CE, such as, for example, an encapsulation layer, a color filter layer, a touch sensing layer, a polarization layer, and the like.

[0094] Figure 5 It is along Figure 2 A cross-sectional view taken along line III-III'. Figure 6 It is along Figure 2 A cross-sectional view taken along line IV-IV'. Figure 7 It is along Figure 2 A cross-sectional view taken along line V-V'.

[0095] In the following, reference will be made to Figure 2 , Figure 5 , Figure 6 and Figure 7The structure provided in the first non-emission area NEA1 included in the display area DA is described in detail.

[0096] First, refer to Figure 2 and Figure 5 In an implementation, a spacer 170 may be disposed on the third insulating layer 150. The spacer 170 may maintain a gap between the light emitting element layer and various structures (eg, a color conversion panel, a touch panel, etc.) that may be disposed on top of the light emitting element layer.

[0097] The spacer 170 may be disposed in the non-emission area NEA of the display area DA. The spacer 170 may be disposed in some of the first non-emission area NEA1, and may not be disposed in the second non-emission area NEA2 and the third non-emission area NEA3. The spacer 170 may include an organic insulating material. In an embodiment, for example, the spacer 170 may include a photoresist. Although in Figure 2 Only one spacer 170 is shown in FIG. 1 , but a plurality of spacers 170 may be provided. In this case, the plurality of spacers 170 may be respectively provided in different first non-emission areas NEA1 .

[0098] like Figure 2 As shown in , the spacer 170 may be disposed between two second pixel defining layers 164 disposed adjacent to each other in the first direction DR1 and between two pixel electrodes disposed adjacent to each other in the second direction DR2. In a plan view, the spacer 170 may be spaced apart from each of the adjacent second pixel defining layers 164. For example, as Figure 2 As shown in , the spacer 170 may be disposed between two first pixel electrodes PE1 disposed adjacent to each other in the second direction DR2. In a plan view, the spacer 170 may be spaced apart from each of the adjacent first pixel electrodes PE1. In an embodiment, the spacer 170 may be disposed between two second pixel electrodes PE2 disposed adjacent to each other in the second direction DR2, or between two third pixel electrodes PE3 disposed adjacent to each other in the second direction DR2.

[0099] As described above, the first non-emission area NEA1 provided with the spacer 170 may be an area provided with the first pixel defining layer 162. In an embodiment, in a plan view, the spacer 170 may be located inside one of the plurality of first pixel defining layers 162. In a plan view, one first pixel defining layer 162 may surround the spacer 170. For example, Figure 5 As shown in , a portion (eg, a lower portion) of the outer side surface of the spacer 170 may contact the inner side surface of one first pixel defining layer 162 .

[0100] In an implementation, both the spacer 170 and the first pixel defining layer 162 may be disposed directly on the third insulating layer 150. For example, Figure 5 As shown in FIG, the lower surface of the spacer 170 and the lower surface of the first pixel defining layer 162 may contact the upper surface of the third insulating layer 150. That is, the lower surface of the spacer 170 and the lower surface of the first pixel defining layer 162 may be on substantially the same plane.

[0101] The thickness of the spacer 170 may be greater than the sum of the thickness of the first pixel defining layer 162 and the thickness of the second pixel defining layer 164. For example, a distance d1 between an upper surface of the third insulating layer 150 and an upper surface of the spacer 170 in the first non-emission area NEA1 may be greater than a distance d2 between an upper surface of the third insulating layer 150 and an upper surface of the second pixel defining layer 164 in the third non-emission area NEA3. In other words, the level of the upper surface of the spacer 170 may be higher than that of the upper surface of the pixel defining layer 160.

[0102] In the first non-emission area NEA1 provided with the spacer 170, one of the first emission layer EL1, the second emission layer EL2, and the third emission layer EL3 may be provided around the spacer 170. In an embodiment, when the spacer 170 is provided between two first pixel electrodes PE1 provided to be adjacent to each other in the second direction DR2, the first emission layer EL1 may be provided around the spacer 170. In an embodiment, when the spacer 170 is provided between two second pixel electrodes PE2 provided to be adjacent to each other in the second direction DR2, the second emission layer EL2 may be provided around the spacer 170. In an embodiment, when the spacer 170 is provided between two third pixel electrodes PE3 provided to be adjacent to each other in the second direction DR2, the third emission layer EL3 may be provided around the spacer 170. Hereinafter, the configuration in which the spacer 170 is provided as shown in FIG. Figure 5 2. An embodiment in which the first emission layer EL1 is disposed around the spacer 170 as shown in FIG.

[0103] In a plan view, the spacer 170 may be located inside the first emission layer EL1. In a plan view, the first emission layer EL1 may surround the spacer 170. For example, a portion (eg, a middle portion) of an outer surface of the spacer 170 may contact an inner surface of the first emission layer EL1.

[0104] The common electrode CE may cover the pixel defining layer 160, the first, second, and third emission layers EL1, EL2, and EL3, and the spacer 170. For example, the common electrode CE may contact a portion (eg, an upper portion) of an outer side surface of the spacer 170 and an upper surface of the spacer 170.

[0105] refer to Figure 2 and Figure 6 In an embodiment, the auxiliary electrode AUE may be disposed under the third insulating layer 150. The auxiliary electrode AUE may include a conductive material. In an embodiment, the auxiliary electrode AUE may be disposed on the second insulating layer 140 and may be disposed on the same layer as the source electrode SE and the drain electrode DE. In an embodiment, the auxiliary electrode AUE may be disposed on the first insulating layer 130 and may be disposed on the same layer as the gate electrode GE.

[0106] In an embodiment, the auxiliary electrode AUE may be disposed in the non-emission area NEA of the display area DA. For example, the auxiliary electrode AUE may extend in the first direction DR1 and may overlap the first pixel defining layer 162. The auxiliary electrode AUE may be disposed between two pixel electrodes disposed adjacent to each other in the second direction DR2.

[0107] Despite Figure 2 Only one auxiliary electrode AUE is shown in FIG. 1 , but a plurality of auxiliary electrodes AUE may be provided. In this case, the plurality of auxiliary electrodes AUE may be provided to overlap with different first pixel defining layers 162 , respectively.

[0108] The auxiliary electrode contact portion ACP may be disposed in the non-emission area NEA of the display area DA. In an embodiment, the auxiliary electrode contact portion ACP may be disposed in some of the first non-emission area NEA1 and not disposed in the second non-emission area NEA2 and the third non-emission area NEA3. The common electrode CE may be electrically connected to the auxiliary electrode AUE through the auxiliary electrode contact portion ACP. Therefore, an IR drop of a voltage (e.g., a low power voltage ("ELVSS")) applied to the common electrode CE may be prevented or reduced.

[0109] In an implementation, a plurality of auxiliary electrode contact portions ACP may overlap each of the auxiliary electrodes AUE. Figure 2 It is shown that three auxiliary electrode contact portions ACP corresponding to the first emission area EA1, the second emission area EA2, and the third emission area EA3 are arranged to overlap with the auxiliary electrode AUE, but this is an example and the embodiment is not limited thereto. As described above, since the common electrode CE is completely arranged in the display area DA, in an embodiment, one auxiliary electrode contact portion ACP may be arranged per predetermined area (for example, every about 1 mm 2 It is sufficient to provide one auxiliary electrode contact portion (ACP).

[0110] like Figure 2As shown in , each of the auxiliary electrode contact portions ACP may be disposed between two second pixel defining layers 164 disposed adjacent to each other in the first direction DR1, and disposed between two pixel electrodes disposed adjacent to each other in the second direction DR2. In a plan view, the auxiliary electrode contact portion ACP may be spaced apart from each of the adjacent second pixel defining layers 164. In an embodiment, the auxiliary electrode contact portion ACP may be disposed between two first pixel electrodes PE1 disposed adjacent to each other in the second direction DR2. In a plan view, the auxiliary electrode contact portion ACP may be spaced apart from each of the adjacent first pixel electrodes PE1. In an embodiment, the auxiliary electrode contact portion ACP may be disposed between two second pixel electrodes PE2 disposed adjacent to each other in the second direction DR2, or between two third pixel electrodes PE3 disposed adjacent to each other in the second direction DR2.

[0111] The spacer 170 and the auxiliary electrode contact portion ACP may be respectively disposed in different first non-emission areas NEA1. The auxiliary electrode contact portion ACP may be spaced apart from the spacer 170 with at least one pixel electrode or at least one second pixel defining layer 164 interposed therebetween.

[0112] In the first non-emission area NEA1 provided with the auxiliary electrode contact portion ACP, one of the first emission layer EL1, the second emission layer EL2 and the third emission layer EL3 may be provided around the auxiliary electrode contact portion ACP. In an embodiment, when the auxiliary electrode contact portion ACP is provided between two first pixel electrodes PE1 provided to be adjacent to each other in the second direction DR2, the first emission layer EL1 may be provided around the auxiliary electrode contact portion ACP. In an embodiment, when the auxiliary electrode contact portion ACP is provided between two second pixel electrodes PE2 provided to be adjacent to each other in the second direction DR2, the second emission layer EL2 may be provided around the auxiliary electrode contact portion ACP. In an embodiment, when the auxiliary electrode contact portion ACP is provided between two third pixel electrodes PE3 provided to be adjacent to each other in the second direction DR2, the third emission layer EL3 may be provided around the auxiliary electrode contact portion ACP. Hereinafter, the auxiliary electrode contact portion ACP will be described. Figure 6 2. An embodiment in which the second emission layer EL2 is shown in FIG. 1 , where the second emission layer EL2 is disposed around the auxiliary electrode contact portion ACP.

[0113] In a plan view, the auxiliary electrode contact portion ACP may be located inside the second emission layer EL2. The auxiliary electrode contact portion ACP may include an auxiliary electrode contact hole CH and a first dam DM1. The auxiliary electrode contact hole CH may be defined in at least one insulating layer and the first pixel defining layer 162 on the auxiliary electrode AUE to expose a portion of the upper surface of the auxiliary electrode AUE. For example, the auxiliary electrode contact hole CH may pass through one of the first pixel defining layers 162 and the third insulating layer 150 in the third direction DR3.

[0114] The first dam DM1 may be disposed on the first pixel defining layer 162 defining the auxiliary electrode contact hole CH. In a plan view, the first dam DM1 may surround the auxiliary electrode contact hole CH. For example, in a plan view, the first dam DM1 may have a ring shape.

[0115] In an embodiment, the first dam DM1 may be disposed on the same layer as the second pixel defining layer 164 and may include the same material as the second pixel defining layer 164. For example, the thickness of the first dam DM1 may be substantially the same as that of the second pixel defining layer 164.

[0116] The first dam DM1 may be formed substantially simultaneously with the second pixel defining layer 164 .

[0117] In a plan view, the first dam DM1 may be located inside the second emission layer EL2. During the formation of the second emission layer EL2 around the auxiliary electrode contact hole CH, the first dam DM1 may prevent the second emission layer EL2 from flowing into the auxiliary electrode contact hole CH. That is, in a plan view, in an embodiment, the second emission layer EL2 may be disposed outside the first dam DM1 and not disposed inside the first dam DM1. In a plan view, the second emission layer EL2 may surround the first dam DM1. For example, Figure 6 As shown in FIG. 5 , a portion (eg, a lower portion) of an outer side surface of the first dam DM1 may contact an inner side surface of the second emission layer EL2 .

[0118] The common electrode CE may cover the pixel defining layer 160, the first, second, and third emission layers EL1, EL2, and EL3, and the first dam DM1. For example, the common electrode CE may contact a portion (eg, an upper portion) of an outer surface of the first dam DM1 and an upper surface of the first dam DM1.

[0119] refer to Figure 2 and Figure 7In an embodiment, the thickness measuring portion TMP may be disposed in the non-emission area NEA of the display area DA. In an embodiment, the thickness measuring portion TMP may be disposed in some of the first non-emission areas NEA1 and not disposed in the second and third non-emission areas NEA2 and NEA3.

[0120] The thickness measuring portion TMP may be disposed between two second pixel defining layers 164 disposed adjacent to each other in the first direction DR1, and between two pixel electrodes disposed adjacent to each other in the second direction DR2. In a plan view, the thickness measuring portion TMP may be spaced apart from each of the adjacent second pixel defining layers 164. In an embodiment, as shown in FIG. Figure 2 As shown in , the thickness measuring portion TMP may be disposed between two third pixel electrodes PE3 disposed adjacent to each other in the second direction DR2. In a plan view, the thickness measuring portion TMP may be spaced apart from each of the adjacent third pixel electrodes PE3. In an embodiment, the thickness measuring portion TMP may be disposed between two first pixel electrodes PE1 disposed adjacent to each other in the second direction DR2, or between two second pixel electrodes PE2 disposed adjacent to each other in the second direction DR2.

[0121] The spacer 170 and the thickness measuring portion TMP may be respectively disposed in different first non-emission areas NEA1. The thickness measuring portion TMP may be spaced apart from the spacer 170, with at least one pixel electrode or at least one second pixel defining layer 164 interposed therebetween. Likewise, the auxiliary electrode contact portion ACP and the thickness measuring portion TMP may be respectively disposed in different first non-emission areas NEA1. The thickness measuring portion TMP may be spaced apart from the auxiliary electrode contact portion ACP, with at least one pixel electrode or at least one second pixel defining layer 164 interposed therebetween.

[0122] In the first non-emission area NEA1 provided with the thickness measuring portion TMP, one of the first emission layer EL1, the second emission layer EL2, and the third emission layer EL3 may be provided around the thickness measuring portion TMP. In an embodiment, when the thickness measuring portion TMP is provided between two first pixel electrodes PE1 provided to be adjacent to each other in the second direction DR2, the first emission layer EL1 may be provided around the thickness measuring portion TMP. In an embodiment, when the thickness measuring portion TMP is provided between two second pixel electrodes PE2 provided to be adjacent to each other in the second direction DR2, the second emission layer EL2 may be provided around the thickness measuring portion TMP. In an embodiment, when the thickness measuring portion TMP is provided between two third pixel electrodes PE3 provided to be adjacent to each other in the second direction DR2, the third emission layer EL3 may be provided around the thickness measuring portion TMP. Hereinafter, the embodiment in which the thickness measuring portion TMP is provided between the two third pixel electrodes PE3 provided to be adjacent to each other in the second direction DR2 will be described. Figure 7 An embodiment in which the third emission layer EL3 is shown in FIG. 4 is disposed around the thickness measuring portion TMP.

[0123] In a plan view, the thickness measuring portion TMP may be located inside the third emission layer EL3. The thickness measuring portion TMP may include a through hole TH and a second dam DM2. The through hole TH may be defined in the first pixel defining layer 162 to expose a portion of the upper surface of the third insulating layer 150. For example, the through hole TH may pass through one of the first pixel defining layers 162 in the third direction DR3.

[0124] The second dam DM2 may be disposed on the first pixel defining layer 162 defining the through hole TH. In a plan view, the second dam DM2 may surround the through hole TH. For example, in a plan view, the second dam DM2 may have a ring shape.

[0125] In an embodiment, the second dam DM2 may be disposed on the same layer as the second pixel defining layer 164 and may include the same material as the second pixel defining layer 164. For example, the thickness of the second dam DM2 may be substantially the same as that of the second pixel defining layer 164.

[0126] The second dam DM2 may be formed substantially simultaneously with the second pixel defining layer 164 .

[0127] In a plan view, the second dam DM2 may be located inside the third emission layer EL3. During the formation of the third emission layer EL3 around the through hole TH, the second dam DM2 may prevent the third emission layer EL3 from flowing into the through hole TH. That is, in a plan view, in an embodiment, the third emission layer EL3 may be disposed outside the second dam DM2 and not disposed inside the second dam DM2. In a plan view, the third emission layer EL3 may surround the second dam DM2. For example, Figure 7As shown in FIG. 1 , a portion (eg, a lower portion) of the outer side surface of the second dam DM2 may contact the inner side surface of the third emission layer EL3. During the manufacturing process of the display device 10, the thickness of the third emission layer EL3 formed by inkjet printing may be measured using the inner space of the second dam DM2 and the through hole TH.

[0128] The common electrode CE may cover the pixel defining layer 160, the first, second and third emission layers EL1, EL2 and EL3 and the second dam DM2. For example, the common electrode CE may contact a portion (eg, an upper portion) of an outer surface of the second dam DM2 and an upper surface of the second dam DM2.

[0129] As described above, according to an embodiment, a structure such as the spacer 170, the auxiliary electrode contact portion ACP, or the thickness measurement portion TMP is not provided in the second non-emission area NEA2 and the third non-emission area NEA3, and may be provided only in the first non-emission area NEA1, so that the width in the first direction DR1 of each of the second non-emission area NEA2 and the third non-emission area NEA3 may be reduced. That is, since the structure does not overlap with each of the second pixel defining layers 164, the width in the first direction DR1 of each of the second pixel defining layers 164 may be further reduced. Therefore, according to an embodiment of the present invention, a high-resolution display device 10 with improved display quality may be implemented.

[0130] Figures 8 to 18 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment.

[0131] Figures 8 to 18 Shown is a reference Figures 1 to 7 The manufacturing method of the display device 10 is described. Figures 8 to 18 In each of the above, the A-A' cross-sectional view corresponds to Figure 3 The left part of the cross-sectional view, the BB' cross-sectional view corresponds to Figure 5 The cross-sectional view of C-C' corresponds to Figure 6 The cross-sectional view of , and the D-D' cross-sectional view corresponds to Figure 7 In the following, for the convenience of explanation, the previously referenced Figures 2 to 7 Further detailed description of the described elements and techniques.

[0132] refer to Figure 8, a buffer layer 120, a first insulating layer 130, a second insulating layer 140, a first thin film transistor TR1, and an auxiliary electrode AUE may be formed on the substrate 110. The auxiliary electrode AUE may be formed in the non-emission area NEA. A third insulating layer 150 may be formed on the second insulating layer 140 and may cover the first thin film transistor TR1 and the auxiliary electrode AUE. The third insulating layer 150 may be formed by providing an organic insulating material on the second insulating layer 140.

[0133] refer to Fig. 9 , a first contact hole and an auxiliary electrode contact hole CH may be formed in the third insulating layer 150. For example, a photoresist pattern may be formed on the third insulating layer 150, and the first contact hole and the auxiliary electrode contact hole CH may be formed by etching the third insulating layer 150 using the photoresist pattern as an etching mask. The first contact hole may expose a portion of the upper surface of the drain electrode of the first thin film transistor TR1. The auxiliary electrode contact hole CH may expose a portion of the upper surface of the auxiliary electrode AUE.

[0134] refer to Fig.10 , a first pixel electrode PE1 may be formed in the first emission area EA1 on the third insulating layer 150. For example, an initial conductive layer may be formed on the third insulating layer 150, and the initial conductive layer may be patterned to form the first pixel electrode PE1. The first pixel electrode PE1 may be electrically connected to the drain electrode of the first thin film transistor TR1 through a first contact hole.

[0135] refer to Fig.11 and Fig.12 , a spacer 170 may be formed in the non-emission area NEA on the third insulating layer 150. The spacer 170 may be formed in Figure 2 In some of the first non-emission areas NEA1.

[0136] First, if Fig.11 As shown in FIG. 1 , a first photoresist layer 170 p may be formed on the third insulating layer 150 and the first pixel electrode PE1. Fig.12 As shown in , the spacer 170 can be formed by patterning the first photoresist layer 170p through an exposure and development process using a first photomask. For example, the first photoresist layer 170p may include a positive photoresist. When the first photoresist layer 170p is developed, a portion of the first photoresist layer 170p corresponding to the light blocking portion of the first photomask may be retained to form the spacer 170, and other portions of the first photoresist layer 170p corresponding to the light transmitting portion of the first photomask may be removed.

[0137] refer to Fig.13 and Fig.14, a first pixel defining layer 162 may be formed on the third insulating layer 150 and the spacer 170. Figure 2 As shown in , each of the first pixel defining layers 162 may extend in the first direction DR1, and the first pixel defining layers 162 may be spaced apart from each other in the second direction DR2.

[0138] First, if Fig.13 As shown in FIG, a second photoresist layer 162p may be formed on the third insulating layer 150, the first pixel electrode PE1, and the spacer 170. The second photoresist layer 162p may cover the spacer 170. The thickness of the second photoresist layer 162p may be less than the thickness of the first photoresist layer 170p.

[0139] Then, if Fig.14 As shown in , the first pixel defining layer 162 may be formed by patterning the second photoresist layer 162p through an exposure and development process using a second photomask. For example, the second photoresist layer 162p may include a positive photoresist. When the second photoresist layer 162p is developed, a portion of the second photoresist layer 162p corresponding to the light blocking portion of the second photomask may be retained to form the first pixel defining layer 162, and other portions of the second photoresist layer 162p corresponding to the light transmitting portion of the second photomask may be removed.

[0140] Reference again Figure 2 , portions of the second photoresist layer 162p overlapping the first non-emission area NEA1 and the third non-emission area NEA3 may be retained to form the first pixel defining layer 162, and portions of the second photoresist layer 162p overlapping the first, second and third emission areas EA1, EA2 and EA3 and the second non-emission area NEA2 may be removed.

[0141] In some of the first non-emission areas NEA1 where the spacers 170 are formed, portions of the second photoresist layer 162p overlapping the spacers 170 may be removed (refer to Fig.14 That is, in a plan view, the first pixel defining layer 162 may surround the spacer 170.

[0142] In some of the first non-emission regions NEA1 where the auxiliary electrode AUE is formed, portions of the second photoresist layer 162p overlapping the auxiliary electrode contact hole CH formed in the third insulating layer 150 may be removed (refer to Fig.14 That is, the auxiliary electrode contact hole CH may pass through the first pixel defining layer 162 and the third insulating layer 150 in the third direction DR3. The auxiliary electrode contact hole CH may expose a portion of the upper surface of the auxiliary electrode AUE.

[0143] In some of the first non-emission areas NEA1 where the spacers 170 and the auxiliary electrode contact holes CH are not formed, a portion of the second photoresist layer 162p may be removed to form through holes TH (refer to Fig.14 A through hole TH may be defined in the first pixel defining layer 162 to expose a portion of an upper surface of the third insulating layer 150.

[0144] refer to Fig.15 and Fig.16 , a second pixel defining layer 164, a first dam DM1, and a second dam DM2 may be formed on the third insulating layer 150 and the first pixel defining layer 162. Figure 2 As shown in , each of the second pixel defining layers 164 may extend in the second direction DR2 , and the second pixel defining layers 164 may be spaced apart from each other in the first direction DR1 .

[0145] First, if Fig.15 As shown in FIG, a third photoresist layer 164p may be formed on the third insulating layer 150, the first pixel electrode PE1, the spacer 170, and the first pixel defining layer 162. The thickness of the third photoresist layer 164p may be less than the thickness of the first photoresist layer 170p. The sum of the thickness of the second photoresist layer 162p and the thickness of the third photoresist layer 164p may be less than the thickness of the first photoresist layer 170p.

[0146] Then, if Fig.16 As shown in , the second pixel defining layer 164, the first dam DM1, and the second dam DM2 can be formed by patterning the third photoresist layer 164p through an exposure and development process using a third photomask. For example, the third photoresist layer 164p may include a positive photoresist. When the third photoresist layer 164p is developed, a portion of the third photoresist layer 164p corresponding to the light blocking portion of the third photomask may be retained to form the second pixel defining layer 164, the first dam DM1, and the second dam DM2, and other portions of the third photoresist layer 164p corresponding to the light transmitting portion of the third photomask may be removed.

[0147] Further references Figure 2 , portions of the third photoresist layer 164p overlapping the second non-emission area NEA2 and the third non-emission area NEA3 may remain to form the second pixel defining layer 164, and portions of the third photoresist layer 164p overlapping the first, second and third emission areas EA1, EA2 and EA3 and the first non-emission area NEA1 may be removed.

[0148] In an embodiment, the third photoresist layer 164p may include a liquid repellent material. The liquid repellent material may include a fluorine-based material. During the formation of the third photoresist layer 164p, the liquid repellent material may be gathered in a portion of the third photoresist layer 164p adjacent to the upper surface of the third photoresist layer 164p. Therefore, the upper surface of each of the second pixel defining layers 164 may have liquid repellency.

[0149] If the spacers 170 are formed after forming the second pixel defining layer 164, the liquid repellency of the upper surface of each of the second pixel defining layers 164 may disappear due to the exposure and development process for forming the spacers 170. Therefore, the spacers 170 may be formed before forming the second pixel defining layer 164.

[0150] In some of the first non-emission areas NEA1 where the spacers 170 are formed, the third photoresist layer 164p may be completely removed (refer to Fig.16 B-B' in the figure.

[0151] In some of the first non-emission areas NEA1 where the auxiliary electrode contact holes CH are formed, portions of the third photoresist layer 164p surrounding the auxiliary electrode contact holes CH in a plan view may remain to form the first dam DM1, and other portions of the third photoresist layer 164p may be removed (refer to Fig.16 C-C' in the

[0152] In some of the first non-emission areas NEA1 where the through holes TH are formed, a portion of the third photoresist layer 164p surrounding the through holes TH in a plan view may remain to form the second dam DM2, and other portions of the third photoresist layer 164p may be removed (refer to Fig.16 D-D' in.

[0153] refer to Fig.17 , a first emission layer EL1, a second emission layer EL2 and a third emission layer EL3 may be formed. The first emission layer EL1, the second emission layer EL2 and the third emission layer EL3 may be formed by inkjet printing.

[0154] Reference again Figure 2, each of the first emission layer EL1, the second emission layer EL2, and the third emission layer EL3 may extend in the second direction DR2. That is, each of the first emission layers EL1 may overlap with a plurality of first pixel electrodes PE1 spaced apart from each other in the second direction DR2 and a plurality of first non-emission areas NEA1 spaced apart from each other in the second direction DR2. Each of the second emission layers EL2 may overlap with a plurality of second pixel electrodes PE2 spaced apart from each other in the second direction DR2 and a plurality of first non-emission areas NEA1 spaced apart from each other in the second direction DR2. Each of the third emission layers EL3 may overlap with a plurality of third pixel electrodes PE3 spaced apart from each other in the second direction DR2 and a plurality of first non-emission areas NEA1 spaced apart from each other in the second direction DR2.

[0155] In some of the first non-emission areas NEA1 where the spacer 170 is formed, one emission layer (eg, the first emission layer EL1) of the first emission layer EL1, the second emission layer EL2, and the third emission layer EL3 may be disposed outside the spacer 170 (refer to Fig.17 B-B' in the figure.

[0156] In some of the first non-emission areas NEA1 where the auxiliary electrode contact holes CH are formed, one of the first emission layers EL1, the second emission layer EL2, and the third emission layer EL3 (for example, the second emission layer EL2) may be disposed outside the first dam DM1 (refer to Fig.17 Due to the first dam DM1, the one emission layer may not flow into the auxiliary electrode contact hole CH passing through the third insulating layer 150 and the first pixel defining layer 162.

[0157] In some of the first non-emission areas NEA1 in which the through holes TH are formed, one of the first emission layer EL1, the second emission layer EL2, and the third emission layer EL3 (for example, the third emission layer EL3) may be disposed outside the second dam DM2 (refer to Fig.17 Due to the second dam DM2, the one emission layer may not flow into the through hole TH passing through the first pixel defining layer 162. In addition, the thickness of the one emission layer may be measured using the through hole TH.

[0158] refer to Fig.18 , a common electrode CE may be formed on the pixel defining layer 160, the first, second, and third emission layers EL1, EL2, and EL3, the spacer 170, the first and second dams DM1 and DM2. For example, the common electrode CE may be completely formed in the first, second, and third emission areas EA1, EA2, and EA3 and the non-emission area NEA.

[0159] In some of the first non-emission areas NEA1 where the auxiliary electrode contact holes CH are formed, the common electrode CE may be electrically connected to the auxiliary electrode AUE through the auxiliary electrode contact holes CH. Therefore, embodiments may prevent or reduce an IR drop of a voltage (eg, a low power voltage ("ELVSS")) applied to the common electrode CE.

[0160] As described above, according to an embodiment, a structure such as the spacer 170, the auxiliary electrode contact portion ACP, or the thickness measurement portion TMP is not provided in the second non-emission area NEA2 and the third non-emission area NEA3, but may be provided only in the first non-emission area NEA1 instead. Therefore, the width in the first direction DR1 of each of the second non-emission area NEA2 and the third non-emission area NEA3 may be reduced. That is, since the structure does not overlap with each of the second pixel defining layers 164, the width in the first direction DR1 of each of the second pixel defining layers 164 may be further reduced. Therefore, a high-resolution display device 10 with improved display quality may be implemented.

[0161] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. Display equipment, including: a plurality of thin film transistors; an insulating layer, disposed on the thin film transistor and comprising an organic insulating material; A plurality of pixel electrodes are disposed on the insulating layer, are electrically connected to the thin film transistors respectively, and are disposed in a first direction and a second direction intersecting the first direction; a pixel defining layer, disposed on the insulating layer and the pixel electrodes, exposing a central portion of each of the pixel electrodes, covering a peripheral portion of each of the pixel electrodes, and comprising: a plurality of first pixel defining layers extending in the first direction and spaced apart from each other in the second direction; and a plurality of second pixel defining layers extending in the second direction and spaced apart from each other in the first direction; and A spacer is disposed on the insulating layer and is disposed between two second pixel defining layers disposed adjacent to each other in the first direction in the second pixel defining layers and between two pixel electrodes disposed adjacent to each other in the second direction in the pixel electrodes.

2. The display device according to claim 1, wherein: The spacer is spaced apart from each of the second pixel defining layers in a plan view.

3. The display device according to claim 1, wherein: In a plan view, the spacer is located inside one of the first pixel defining layers.

4. The display device according to claim 3, wherein: An outer side surface of the spacer contacts an inner side surface of the one first pixel defining layer.

5. The display device according to claim 1, wherein: A lower surface of the spacer and a lower surface of each of the first pixel defining layers contact an upper surface of the insulating layer.

6. The display device according to claim 1, wherein: A distance between an upper surface of the insulating layer and an upper surface of the spacer is greater than a distance between the upper surface of the insulating layer and an upper surface of each of the second pixel defining layers.

7. The display device according to claim 1, further comprising: a plurality of emission layers, disposed on the pixel electrode, extending in the second direction, and spaced apart from each other in the first direction; as well as a common electrode, disposed on the pixel electrode, the pixel defining layer and the emission layer, Each of the emission layers is disposed between two second pixel defining layers that are adjacent to each other in the first direction.

8. The display device according to claim 7, wherein: The emission layer includes a first emission layer, a second emission layer and a third emission layer, and The first emission layer, the second emission layer, and the third emission layer emit light of different colors and are sequentially arranged in the first direction.

9. The display device according to claim 7, wherein: In a plan view, the spacer is located inside one of the emission layers.

10. The display device according to claim 9, wherein: An outer side surface of the spacer contacts an inner side surface of the one emission layer.

11. The display device according to claim 7, further comprising: an auxiliary electrode, disposed under the insulating layer and overlapping one of the first pixel defining layers, The common electrode is electrically connected to the auxiliary electrode through a contact hole that passes through the insulating layer and the first pixel defining layer.

12. The display device according to claim 11, further comprising: A dam is disposed on the one first pixel defining layer and surrounds the contact hole in a plan view.

13. The display device according to claim 12, wherein: In the plan view, The dam is located inside one of the emitting layers, and The one emission layer is disposed on the outer side of the dam and is not disposed on the inner side of the dam.

14. The display device according to claim 13, wherein: An outer side surface of the dam contacts an inner side surface of the one emission layer.

15. The display device according to claim 12, wherein: In the plan view, the dam is spaced apart from the spacer, and at least one of the pixel electrodes or at least one of the second pixel defining layers is interposed between the dam and the spacer.

16. The display device according to claim 7, wherein: A through hole is defined, the through hole passes through one of the first pixel defining layers and exposes the upper surface of the insulating layer, and the display device further includes: A dam is disposed on the one first pixel defining layer and surrounds the through hole in a plan view.

17. The display device according to claim 16, wherein: In the plan view, the dam is spaced apart from the spacer, and at least one of the pixel electrodes or at least one of the second pixel defining layers is interposed between the dam and the spacer.

18. Display equipment, including: a plurality of thin film transistors; an insulating layer, disposed on the thin film transistor and comprising an organic insulating material; A plurality of pixel electrodes are disposed on the insulating layer, are electrically connected to the thin film transistors respectively, and are disposed in a first direction and a second direction intersecting the first direction; a pixel defining layer, disposed on the insulating layer and the pixel electrodes, exposing a central portion of each of the pixel electrodes, covering a peripheral portion of each of the pixel electrodes, and comprising: a plurality of first pixel defining layers extending in the first direction and spaced apart from each other in the second direction; and a plurality of second pixel defining layers extending in the second direction and spaced apart from each other in the first direction; an auxiliary electrode, disposed under the insulating layer and overlapping one of the first pixel defining layers; a plurality of emission layers disposed on the pixel electrode, extending in the second direction, and spaced apart from each other in the first direction; and A common electrode is disposed on the pixel electrode, the pixel defining layer and the emission layer, and is electrically connected to the auxiliary electrode through a contact hole passing through the insulating layer and the one first pixel defining layer.

19. The display device according to claim 18, further comprising: A dam is disposed on the one first pixel defining layer and surrounds the contact hole in a plan view.

20. Display equipment, including: a plurality of thin film transistors; an insulating layer, disposed on the thin film transistor and comprising an organic insulating material; A plurality of pixel electrodes are disposed on the insulating layer, are electrically connected to the thin film transistors respectively, and are disposed in a first direction and a second direction intersecting the first direction; a pixel defining layer, disposed on the insulating layer and the pixel electrodes, exposing a central portion of each of the pixel electrodes, covering a peripheral portion of each of the pixel electrodes, and comprising: a plurality of first pixel defining layers extending in the first direction and spaced apart from each other in the second direction; and a plurality of second pixel defining layers extending in the second direction and spaced apart from each other in the first direction; and A dam is disposed on one of the first pixel defining layers and surrounds a through hole in a plan view, the through hole passing through the one first pixel defining layer and exposing an upper surface of the insulating layer.

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