Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises a substrate, a first conductive layer and an anode conductive layer which are arranged in sequence. The first conductive layer comprises a plurality of first signal transmission lines extending along a first direction, a plurality of first connecting lines extending along a second direction and a plurality of first connecting blocks, and the first direction and the second direction are crossed; the first connecting block is connected with the first signal transmission line through a first connecting line; the anode conducting layer comprises a plurality of first overlapped anodes and a plurality of first isolated anodes, the orthographic projection of the first signal transmission line and the orthographic projection of the first anodes on the substrate are overlapped, and the orthographic projection of the first connecting line and the orthographic projection of the first overlapped anodes on the substrate are overlapped; a first dummy line extending in the second direction is arranged on the side, close to the substrate, of the anode conducting layer, the orthographic projection of the first end of the first dummy line on the substrate falls on the orthographic projection of the first signal transmission line, and the orthographic projection of the first end of the first dummy line on the substrate and the orthographic projection of the first isolated anode are at least partially overlapped.

Description

Technical Field

[0001] This application relates to, but is not limited to, display technologies, and particularly to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technologies, flexible display devices that use OLED or QLED as light-emitting devices and are signal-controlled by Thin Film Transistors (TFTs) have become the mainstream products in the current display field.

[0003] Currently, existing display devices have problems such as color deviation. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this application. This overview is not intended to limit the scope of protection of the claims.

[0005] The present disclosure provides a display substrate and a display device, which can solve problems such as color deviation existing in existing display devices.

[0006] In a first aspect, an embodiment of the present disclosure provides a display substrate, including: a substrate, a first conductive layer, and an anode conductive layer sequentially disposed on the substrate; the first conductive layer includes a plurality of first signal transmission lines extending along a first direction, a plurality of first connection lines extending along a second direction, and a plurality of first connection blocks, where the first direction and the second direction intersect; the first connection blocks are connected to the first signal transmission lines through the first connection lines; the anode conductive layer includes a plurality of anode electrodes, and the plurality of anode electrodes include a plurality of first anodes, and the plurality of first anodes include a plurality of first overlapping anodes and a plurality of first isolated anodes, and at least a part of the orthographic projection of the first signal transmission line on the substrate overlaps with at least a part of the orthographic projection of the first anode on the substrate, and at least a part of the orthographic projection of the first connection line on the substrate overlaps with at least a part of the orthographic projection of the first overlapping anode on the substrate; the display substrate further includes a first dummy line located on a side of the anode conductive layer close to the substrate, and the first dummy line extends along the second direction; a first end of the first dummy line overlaps with the orthographic projection of the first signal transmission line on the substrate, and at least a part of the orthographic projection of the first end of the first dummy line on the substrate overlaps with at least a part of the orthographic projection of the first isolated anode on the substrate.

[0007] In an exemplary embodiment, the first conductive layer further includes a second connection block. The second connection block and the first connection block are located on one side of the first signal transmission line along the second direction, and the second connection block is not connected to the first signal transmission line. The orthographic projection of the first dummy line on the substrate is located between the orthographic projection of the first signal transmission line on the substrate and the orthographic projection of the second connection block on the substrate.

[0008] In an exemplary embodiment, the first dummy line is located in the first conductive layer. A first end of the first dummy line is connected to the first signal transmission line, and a second end of the first dummy line is not connected to the second connection block.

[0009] In an exemplary embodiment, the display substrate further includes a second conductive layer. The second conductive layer is located on a side of the first conductive layer close to the anode conductive layer. The first dummy line is located in the second conductive layer, and the orthographic projection of the second end of the first dummy line on the substrate does not overlap with the orthographic projection of the second connection block on the substrate.

[0010] In an exemplary embodiment, the display substrate further includes a second conductive layer. The second conductive layer is located on a side of the first conductive layer close to the anode conductive layer. The first dummy line is located in the second conductive layer. In the second direction, the length of the first dummy line is the same as the length of the first connection line.

[0011] In an exemplary embodiment, the display substrate further includes a second dummy line. The second dummy line is located on a side of the first dummy line close to the anode conductive layer. The orthographic projection of the first end of the second dummy line on the substrate falls on the orthographic projection of the first signal transmission line on the substrate. The length of the second dummy line is the same as the length of the first connection line, and the orthographic projection of the second dummy line on the substrate covers the orthographic projection of the first dummy line on the substrate.

[0012] In an exemplary embodiment, the anode conductive layer includes a plurality of second anodes. The orthographic projection of the second connection block on the substrate at least partially overlaps with the orthographic projection of the second anode on the substrate. The first dummy line is disposed on a side of the second anode close to the substrate, or the first dummy line and the second dummy line are disposed on a side of the second anode close to the substrate.

[0013] In an exemplary embodiment, the display substrate includes a plurality of first signal transfer lines extending in the second direction. The first signal transfer lines are located on a side of the first signal transmission lines close to the anode conductive layer, and the first signal transfer lines are connected to the first signal transmission lines through the first connection blocks.

[0014] In an exemplary embodiment, the plurality of anode electrodes include a plurality of electrode rows distributed in the first direction and a plurality of electrode columns distributed in the second direction. In the second direction, a single first signal transmission line and a single electrode row are alternately arranged; the anode electrode has a first symmetry axis extending in the first direction; two first signal transmission lines located on both sides of the anode electrode in the second direction are arranged to be axisymmetric about the first symmetry axis of the anode electrode.

[0015] In an exemplary embodiment, the anode electrode has a second symmetry axis extending in the second direction; the first signal transfer line coincides with the second symmetry axis of a single electrode column.

[0016] In an exemplary embodiment, in the first direction, a single electrode column is spaced between adjacent first signal transfer lines.

[0017] In an exemplary embodiment, in the second direction, two adjacent first signal transmission lines form a transmission line group, and the two first signal transmission lines within a single transmission line group are connected to each other through a first connection segment and a second connection segment arranged in the second direction; the first connection segment and the second connection segment are axisymmetric about the second symmetry axis of the electrode column.

[0018] In an exemplary embodiment, a single first signal transfer line includes a plurality of transfer segments, and the transfer segments are arranged to connect adjacent transmission line groups in the second direction.

[0019] In an exemplary embodiment, the anode electrode includes a first part and a second part that are symmetric to each other, and the first part and the second part are axisymmetric about the first symmetry axis of the anode electrode; the overlapping area of the metal structure on the substrate side of the first part with the first part is a first area, and the overlapping area of the metal structure on the substrate side of the second part with the second part is a second area; the display substrate further includes a compensation electrode block, and the compensation electrode block is located on a side of the anode electrode close to the substrate, and the compensation electrode block is arranged to make the first area greater than or equal to 0.8 times and less than or equal to 1.2 times the second area.

[0020] In a second aspect, embodiments of the present disclosure provide a display device, including the display substrate described above.

[0021] For the display substrate provided by the embodiments of the present disclosure, by providing a first dummy line on the side of the first isolated anode close to the substrate, the first isolated anode can be supported below one side of the first signal transmission line in the second direction, making the flatness of the first isolated anode and the first overlapping anode more uniform, improving the uniformity of the flatness of the first anode, thereby avoiding color shift or abnormal off-screen display in the display device and enhancing the display effect. This solves the problem of color shift and other issues existing in existing display devices.

[0022] Other aspects can be understood after reading and understanding the drawings and the detailed description. Description of the Drawings

[0023] The drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure.

[0024] Figure 1 It is a schematic structural diagram of a display device;

[0025] Figure 2 It is a schematic structural diagram of a display substrate;

[0026] Figure 3 It is a schematic plan view of a display area in a display substrate;

[0027] Figure 4 It is a schematic cross-sectional view of a display area in a display substrate;

[0028] Figure 5 It is a schematic equivalent circuit diagram of a pixel driving circuit;

[0029] Figure 6 It is a top view of a display substrate in some technologies;

[0030] Figure 7 It is a top view of a display substrate provided by an exemplary embodiment;

[0031] Figure 8 It is a top view of a display substrate provided by another exemplary embodiment;

[0032] Figure 9 It is a top view of a display substrate provided by another exemplary embodiment;

[0033] Figure 10 It is a top view of an anode electrode, a first signal transmission line, and a first signal transfer line in an exemplary embodiment;

[0034] Figure 11ATop view before setting the compensation electrode block under the first anode in an exemplary embodiment;

[0035] Figure 11B It is Figure 11A Top view after setting the compensation electrode block under the first anode in;

[0036] Figure 12A Top view before setting the compensation electrode block under the second anode in an exemplary embodiment;

[0037] Figure 12B It is Figure 12A Top view after setting the compensation electrode block under the second anode in;

[0038] Figure 13A Top view before setting the compensation electrode block under the third anode in an exemplary embodiment;

[0039] Figure 13B It is Figure 13A Top view after setting the compensation electrode block under the third anode in. Detailed implementation manners

[0040] The present disclosure describes multiple embodiments, but this description is exemplary rather than restrictive, and it will be obvious to those of ordinary skill in the art that there can be more embodiments and implementation solutions within the scope of the embodiments described in the present disclosure. Although many possible feature combinations are shown in the drawings and discussed in the detailed implementation manners, many other combination ways of the disclosed features are also possible. Unless specifically restricted, any feature or element of any embodiment can be combined with any other feature or element in any other embodiment, or can replace any other feature or element in any other embodiment.

[0041] The present disclosure includes and contemplates combinations with features and elements known to those of ordinary skill in the art. The embodiments, features, and elements already disclosed in the present disclosure can also be combined with any conventional features or elements to form unique inventive solutions defined by the claims. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present disclosure can be implemented alone or in any appropriate combination. Therefore, the embodiments are not subject to other restrictions except those made according to the appended claims and their equivalent replacements. In addition, various modifications and changes can be made within the scope of protection of the appended claims.

[0042] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not depend on the specific order of the steps described herein, the method or process should not be limited to the specific order of steps described. As those of ordinary skill in the art will understand, other step orders are possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims directed to the method and / or process should not be limited to performing their steps in the order written, as those skilled in the art can readily understand that these orders can vary and still remain within the spirit and scope of the embodiments of the present disclosure.

[0043] In the drawings, sometimes, for clarity, the sizes of one or more constituent elements, the thicknesses of layers, or regions are exaggerated. In addition, the drawings schematically show ideal examples, and one aspect of the present disclosure is not limited to the shapes, numerical values, etc. shown in the drawings.

[0044] The ordinal numbers such as "first", "second", "third", etc. in this specification are provided to avoid confusion of constituent elements and are not intended to limit in terms of quantity. "Plurality" in the present disclosure means two or more quantities.

[0045] In this specification, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of constituent elements with reference to the drawings, and are only for facilitating the description of this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation on the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of the described constituent elements. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the circumstances.

[0046] In this specification, unless otherwise clearly specified and limited, the terms "install", "connect", and "couple" shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, an indirect connection through an intermediate member, or the communication inside two elements. For those of ordinary skill in the art, the meanings of the above terms in the present disclosure can be understood according to the circumstances.

[0047] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current mainly flows.

[0048] In this specification, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" sometimes swap with each other. Therefore, in this specification, the "source electrode" and "drain electrode" can be swapped with each other, and the "source terminal" and "drain terminal" can be swapped with each other.

[0049] In this specification, "electrically connected" includes cases where components are connected together through an element having a certain electrical effect. There are no particular restrictions on the "element having a certain electrical effect" as long as it can transmit electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0050] In this specification, "parallel" means a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state where the angle is -5° or more and 5° or less. Additionally, "perpendicular" means a state where the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state where the angle is 85° or more and 95° or less.

[0051] In this specification, "film" and "layer" can be swapped with each other. For example, sometimes "conductive layer" can be changed to "conductive film". Similarly, sometimes "insulating film" can be changed to "insulating layer".

[0052] Triangles, rectangles, trapezoids, pentagons, hexagons, etc. in this specification are not strictly defined and can be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc. There can be some small deformations due to tolerances, and there can be chamfers, rounded edges, and deformations, etc.

[0053] "About" in this disclosure means not strictly defining the boundary and allowing values within the range of process and measurement errors.

[0054] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0055] Figure 1 It is a schematic structural diagram of a display device. AsFigure 1 As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may at least include a pixel driving circuit. The pixel driving circuit is respectively connected to the scan signal line, the light-emitting signal line, and the data signal line. The light-emitting unit may include a light-emitting device, and the light-emitting device is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide a gray value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light-emitting driver to the light-emitting driver. The data driver may use the gray value and the control signal received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3,..., and Dn. For example, the data driver may sample the gray value using a clock signal and apply the data voltage corresponding to the gray value to the data signal lines D1 to Dn in pixel row units, where n may be a natural number. The scan driver may generate scan signals to be provided to the scan signal lines S1, S2, S3,..., and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide scan signals having conductive level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register and may generate scan signals in such a way that the scan start signal provided in the form of a conductive level pulse is sequentially transmitted to the next-stage circuit under the control of the clock signal, where m may be a natural number. The light-emitting driver may generate emission signals to be provided to the light-emitting signal lines E1, E2, E3,..., and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light-emitting driver may sequentially provide emission signals having cut-off level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver may be configured in the form of a shift register and may generate emission signals in such a way that the emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to the next-stage circuit under the control of the clock signal, where o may be a natural number. In an exemplary embodiment, the pixel array may be disposed on a display substrate.

[0056] Figure 2 It is a schematic structural diagram of a display substrate. As Figure 2 ​As shown, the display substrate may include a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on the other sides of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of sub-pixels constituting a pixel array, and the plurality of sub-pixels are configured to display dynamic pictures or still images. The display area 100 may be referred to as an active area (AA). In an exemplary embodiment, the display substrate may adopt a flexible substrate, and thus the display substrate may be deformable, such as curling, bending, folding, or rolling up.

[0057] In an exemplary embodiment, the bonding area 200 may include a fan-out area, a bending area, a driving chip area, and a bonding pin area sequentially arranged along a direction away from the display area 100. The fan-out area is connected to the display area 100 and may at least include a plurality of parallel data lead-out lines. The bending area is connected to the fan-out area and may include a composite insulating layer provided with grooves and is configured to bend the bonding area to the back of the display area. The driving chip area may at least include an integrated circuit (IC) configured to be connected to a plurality of data fan-out lines. The bonding pin area may at least include a plurality of bonding pads configured to be bonded and connected to an external flexible printed circuit (FPC). In a display substrate, since the width of the bonding area 200 is smaller than the width of the display area 100, the signal lines of the integrated circuit and the bonding pads in the bonding area 200 need to be introduced into the wider display area 100 through the fan-out area in a fan-out routing manner. The greater the width gap between the display area 100 and the bonding area 200, the more oblique fan-out lines in the fan-out area, and the greater the distance between the driving chip area and the display area 100. Therefore, the fan-out area occupies a large space, resulting in greater difficulty in the narrow design of the lower border.

[0058] In an exemplary embodiment, the border region 300 may include a circuit region, a power line region, a crack dam region, and a cutting region that are sequentially arranged in a direction away from the display region 100. The circuit region is connected to the display region 100 and may at least include a gate driving circuit, and the gate driving circuit is connected to the scanning signal line and the light-emitting signal line of the pixel driving circuit in the display region 100. The power line region is connected to the circuit region and may at least include a border power lead, and the border power lead extends along a direction parallel to the edge of the display region and is connected to the cathode in the display region 100. The crack dam region is connected to the power line region and may at least include a plurality of cracks provided on the composite insulating layer. The cutting region is connected to the crack dam region and may at least include a cutting groove provided on the composite insulating layer, and the cutting groove is configured to be cut by a cutting device along the cutting groove respectively after all the film layers of the display substrate are prepared. In another display substrate, the border power lead is configured to continuously provide a transmitted low-level signal. In order to reduce the voltage drop of the low-level signal, the width of the border power lead is relatively large, resulting in a relatively large width of the left and right borders of the display device.

[0059] In an exemplary embodiment, at least one isolation dam may be provided in the fan-out region in the bonding region 200 and the power line region in the border region 300. The isolation dam may extend along a direction parallel to the edge of the display region to form an annular structure surrounding the display region 100, and the edge of the display region is the edge of the display region close to the bonding region or the border region.

[0060] In an exemplary embodiment, the display area 100 further includes a plurality of data signal lines 72 extending along the second direction Y, a plurality of first connection lines 81 extending along the first direction X, and a plurality of first dummy lines 82 extending along the second direction Y. The data signal lines 72 are respectively connected to a plurality of pixel driving circuits in a pixel column, and the data signal lines 72 are configured to provide data signals to the connected pixel driving circuits. The first ends of the plurality of first connection lines 81 are correspondingly connected to the plurality of data signal lines 72, the second ends of the plurality of first connection lines 81 are correspondingly connected to the first ends of the plurality of first dummy lines 82, the second ends of the plurality of first dummy lines 82 are correspondingly connected to the first ends of a plurality of data lead lines 210 in the bonding area 200, and after the second ends of the plurality of data lead lines 210 extend along the second direction Y and cross the bending area, they are connected to the driving chip in the driving chip area, so that the driving chip applies the data signal provided by the driving chip to the data signal lines 72 through the data lead lines 210, the first connection lines 81, and the first dummy lines 82. In the exemplary embodiment, the first connection lines 81 and the first dummy lines 82 can form data connection lines, forming a structure where the data connection lines are located in the display area (Fanout in AA, abbreviated as FIAA). Since the data connection lines are arranged in the display area, the lower border width can be reduced and the screen-to-body ratio can be increased. By the same principle, a plurality of power connection lines can be arranged in the display area, and the plurality of power connection lines can be connected to the border power lead lines arranged in the border area 300 and extend along the second direction Y and then be connected to the corresponding signal terminals in the bonding area 200, forming a structure where the power connection lines are located in the display area (VSSin AA, abbreviated as SIAA). This design can reduce the voltage drop of the power signal during transmission, which not only helps to reduce the power consumption of the display substrate but also helps to achieve a narrow border.

[0061] Figure 3 It is a schematic plan view of a display area in a display substrate. As Figure 3 shown, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 that emits light of a first color, a second sub-pixel P2 that emits light of a second color, a third sub-pixel P3 that emits light of a third color, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may at least include a pixel driving circuit. The pixel driving circuit is respectively connected to a scanning signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line and output a corresponding current to the light-emitting unit. The light-emitting units in each sub-pixel are respectively connected to the pixel driving circuit of the corresponding sub-pixel, and the light-emitting unit is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the corresponding sub-pixel.

[0062] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 may be green sub-pixels (G) that emit green light. In an exemplary embodiment, the shape of the sub-pixel may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the four sub-pixels may be arranged in a diamond pattern to form an RGBG pixel arrangement. In other exemplary embodiments, the four sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, square, or other patterns, and the present disclosure does not limit this here.

[0063] In an exemplary embodiment, the pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, or triangular pattern, etc., and the present disclosure does not limit this here.

[0064] Figure 4 FIG. is a schematic cross-sectional structure diagram of a display area in a display substrate, showing the structures of three sub-pixels in the display area. As Figure 4 shown, in a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and a packaging structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementation manners, the display substrate may include other film layers, such as a touch control structure layer, etc., and the present disclosure does not limit this here.

[0065] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, and each circuit unit may at least include a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, and each light-emitting unit may at least include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits corresponding color light under the drive of the anode and the cathode. The packaging structure layer 104 may include a stacked first packaging layer, a second packaging layer, and a third packaging layer. The first packaging layer and the third packaging layer may be made of inorganic materials, and the second packaging layer may be made of organic materials. The second packaging layer is disposed between the first packaging layer and the third packaging layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0066] Figure 5It is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. As Figure 5 shown, the pixel driving circuit may include eight transistors (a first transistor T1 to an eighth transistor T8) and one storage capacitor C, and the pixel driving circuit is respectively connected to ten signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, a light emitting signal line EM, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a data signal line DATA and a first power supply line VDD).

[0067] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3 and a fourth node N4. Among them, the first node N1 is respectively connected to a first pole of the second transistor T2, a gate electrode of the third transistor T3 and a first end of the storage capacitor C, the second node N2 is respectively connected to a first pole of the third transistor T3, a second pole of the fourth transistor T4, a second pole of the fifth transistor T5 and a second pole of the eighth transistor T8, the third node N3 is respectively connected to a second pole of the first transistor T1, a second pole of the second transistor T2, a second pole of the third transistor T3 and a first pole of the sixth transistor T6, the fourth node N4 is respectively connected to a second pole of the sixth transistor T6 and a second pole of the seventh transistor T7, and the fourth node N4 is further connected to an anode of the light emitting device EL.

[0068] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1, and a second end of the storage capacitor C is connected to the first power supply line VDD.

[0069] In an exemplary embodiment, the first transistor T1 may be referred to as a first initialization transistor. The gate electrode of the first transistor T1 is connected to the third scan signal line S3. The first pole of the first transistor T1 is connected to the first initial signal line INIT1. The second pole of the first transistor T1 is connected to the third node N3. The second transistor T2 may be referred to as a compensation transistor. The gate electrode of the second transistor T2 is connected to the fourth scan signal line S4. The first pole of the second transistor T2 is connected to the first node N1. The second pole of the second transistor T2 is connected to the third node N3. The third transistor T3 may be referred to as a driving transistor. The gate electrode of the third transistor T3 is connected to the first node N1, that is, the gate electrode of the third transistor T3 is connected to the first end of the storage capacitor C. The first pole of the third transistor T3 is connected to the second node N2. The second pole of the third transistor T3 is connected to the third node N3. The fourth transistor T4 may be referred to as a data writing transistor. The gate electrode of the fourth transistor T4 is connected to the first scan signal line S1. The first pole of the fourth transistor T4 is connected to the data signal line DATA. The second pole of the fourth transistor T4 is connected to the second node N2. The fifth transistor T5 may be referred to as a first light emission control transistor. The gate electrode of the fifth transistor T5 is connected to the light emission signal line EM. The first pole of the fifth transistor T5 is connected to the first power supply line VDD. The second pole of the fifth transistor T5 is connected to the second node N2. The sixth transistor T6 may be referred to as a second light emission control transistor. The gate electrode of the sixth transistor T6 is connected to the light emission signal line EM. The first pole of the sixth transistor T6 is connected to the third node N3. The second pole of the sixth transistor T6 is connected to the fourth node N4. The seventh transistor T7 may be referred to as a second initialization transistor. The gate electrode of the seventh transistor T7 is connected to the second scan signal line S2. The first pole of the seventh transistor T7 is connected to the second initial signal line INIT2. The second pole of the seventh transistor T7 is connected to the fourth node N4. The eighth transistor T8 may be referred to as a third initialization transistor. The gate electrode of the eighth transistor T8 is connected to the second scan signal line S2. The first pole of the eighth transistor T8 is connected to the third initial signal line INIT3. The second pole of the eighth transistor T8 is connected to the second node N2.

[0070] In an exemplary embodiment, the light emitting device EL may be an OLED, including a stacked anode (first pole), an organic light emitting layer, and a cathode (second pole), or may be a QLED, including a stacked anode (first pole), a quantum dot light emitting layer, and a cathode (second pole).

[0071] In an exemplary embodiment, the first pole of the light emitting device EL is connected to the fourth node N4. The second pole of the light emitting device EL is connected to the second power supply line VSS. The signal of the second power supply line VSS is a continuously provided low level signal. The signal of the first power supply line VDD is a continuously provided high level signal.

[0072] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be P-type transistors, or may be N-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementation manners, the first transistor T1 to the eighth transistor T8 may include P-type transistors and N-type transistors.

[0073] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may employ low-temperature polysilicon transistors, or may employ oxide transistors, or may employ low-temperature polysilicon transistors and metal-oxide transistors. The active layer of the low-temperature polysilicon transistor uses low-temperature poly-silicon (abbreviated as LTPS), and the active layer of the metal-oxide transistor uses metal-oxide semiconductor (Oxide). The low-temperature polysilicon transistor has advantages such as high mobility and fast charging, and the oxide transistor has advantages such as low leakage current. Integrating the low-temperature polysilicon transistor and the metal-oxide transistor on a display substrate to form a (Low Temperature Polycrystalline and Oxide display substrate, abbreviated as LTPO display substrate) can utilize the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve the display quality.

[0074] In an exemplary embodiment, the second transistor T2 may employ a metal-oxide transistor, and the first transistor T1, the third transistor T3 to the eighth transistor T8 may employ low-temperature polysilicon transistors.

[0075] In some technologies, in a display substrate adopting a structure such as FIAA or SIAA, in a direction perpendicular to the display substrate, different signal transmission lines (such as data signal lines 72, first connection lines 81, first dummy lines 82, etc.) may be disposed in different film layers, and the signal transmission lines between different film layers may be connected through vias, and connection blocks may be disposed at the vias to connect different signal transmission lines. Figure 6 Is a top view of a display substrate in some technologies, schematically showing the positional relationship of an anode electrode, a single first signal transmission line, a single first connection line, a single first connection block, and a single second connection block, and other structures of the display substrate are omitted for illustration. As Figure 6As shown, the display substrate may include a substrate, a first conductive layer disposed on the substrate, and an anode conductive layer disposed on a side of the first conductive layer away from the substrate. The first conductive layer may include a first signal transmission line 11, a first connection block 12, a first connection line 13, and a second connection block 14. The first signal transmission line 11 may extend along a first direction X. The first signal transmission line 11 and the first connection block 12 are connected by the first connection line 13. The first connection line 13 may extend along a second direction Y. The first direction X and the second direction Y intersect each other. The second connection block 14 is not connected to the first signal transmission line 11. For example, the second connection block 14 may be a virtual connection block located at the same position as the first connection block 13 but not connected to the first connection line 13, so that the metal line density between different sub-pixels tends to be consistent, and the phenomenon of display device off-screen mura can be improved. The anode conductive layer includes anodes of a plurality of light-emitting devices. The light-emitting devices may include, for example, a first light-emitting device, a second light-emitting device, a third light-emitting device, and a fourth light-emitting device. The first light-emitting device may emit red light, the second light-emitting device may emit blue light, the third light-emitting device and the fourth light-emitting device may emit green light. The anode conductive layer may include a first anode 100A of the first light-emitting device, a second anode 100B of the second light-emitting device, a third anode 100C of the third light-emitting device, and a fourth anode 100D of the fourth light-emitting device. As Figure 6 shown, the orthographic projection of the first signal transmission line 11 on the substrate and the orthographic projection of the first anode 100A on the substrate at least partially overlap. The orthographic projections of the first connection block 12 and the second connection block 13 on the substrate and the orthographic projection of the first anode 100A on the substrate may not overlap. The orthographic projection of the first connection line 13 on the substrate and the orthographic projections of some of the plurality of first anodes 100A on the substrate at least partially overlap. The plurality of first anodes 100A that overlap with the orthographic projection of the first connection line 13 on the substrate may be referred to as first overlapping anodes, and the remaining plurality of first anodes 100A may be referred to as first isolated anodes. Figure 6 The first anode 100A on the left side in [[]] Figure 6 Figure 6 is a first isolated anode, and the first anode 100A on the right side is a first overlapping anode. It can be seen that there is a first connection line 13 providing support below the side of the first overlapping anode on the right side close to the first connection block 12, while there is no corresponding support below the side of the first isolated anode on the left side in the second direction Y of the first signal transmission line 11 ( Figure 6 the side close to the second connection block 14 in [[]] Figure 6 ), which results in different surface flatnesses of different first anodes 100A. The multiple first signal transmission lines, multiple first connection lines, multiple first connection blocks, and multiple second connection blocks disposed on the display substrate are distributed below the anode electrode, which causes uneven flatness of the anode electrode. Through research by the inventors of the present application, it is found that this uneven flatness of the anode surface will cause color deviation or off-screen display defects in the subsequent formed display device.

[0076] An embodiment of the present disclosure provides a display substrate, including: a substrate, a first conductive layer, and an anode conductive layer sequentially disposed on the substrate; the first conductive layer includes a plurality of first signal transmission lines extending in a first direction, a plurality of first connection lines extending in a second direction, and a plurality of first connection blocks, the first direction and the second direction intersect; the first connection blocks are connected to the first signal transmission lines through the first connection lines; the anode conductive layer includes a plurality of anode electrodes, the plurality of anode electrodes include a plurality of first anodes, the plurality of first anodes include a plurality of first overlapping anodes and a plurality of first isolated anodes, a positive projection of the first signal transmission line on the substrate and a positive projection of the first anode on the substrate at least partially overlap, a positive projection of the first connection line on the substrate and a positive projection of the first overlapping anode on the substrate at least partially overlap; the display substrate further includes a first dummy line located on a side of the anode conductive layer close to the substrate, the first dummy line extends in the second direction; a positive projection of a first end of the first dummy line on the substrate falls on a positive projection of the first signal transmission line on the substrate, and a positive projection of the first end of the first dummy line on the substrate and a positive projection of the first isolated anode on the substrate at least partially overlap.

[0077] For the display substrate proposed in the embodiment of the present disclosure, by providing a first dummy line on a side of the first isolated anode close to the substrate, a support can be formed under the first isolated anode on a side of the first signal transmission line in the second direction, so that the flatness of the first isolated anode and the first overlapping anode is more uniform, the uniformity of the flatness of the first anode can be improved, thereby avoiding color deviation or abnormal off-screen display of the display device and improving the display effect.

[0078] In an exemplary embodiment, the first conductive layer further includes a second connection block, the second connection block and the first connection block are located on the same side of the first signal transmission line in the second direction, and the second connection block is not connected to the first signal transmission line; a positive projection of the first dummy line on the substrate is located between a positive projection of the first signal transmission line on the substrate and a positive projection of the second connection block on the substrate.

[0079] In an exemplary embodiment, a positive projection of a second end of the first dummy line on the substrate may be located outside a positive projection of the first isolated anode on the substrate in the second direction.

[0080] In this embodiment, the first isolated anode can be supported by the first dummy line below one side of the first signal transmission line in the second direction. Along the second direction, the overlapping length between the first dummy line and the first isolated anode is approximately the same as the overlapping length between the first connection line and the first overlapping anode, so that the supporting effect of the first dummy line on the first isolated anode is equivalent to the supporting effect of the first connection line on the first overlapping anode, which can improve the uniformity of the flatness of the first anode.

[0081] In an exemplary embodiment, the display substrate includes a plurality of first signal transfer lines extending along the second direction. The first signal transfer lines are located on the side of the first signal transmission line close to the anode conductive layer, and the first signal transfer lines are connected to the first signal transmission line through the first connection blocks.

[0082] Figure 7 It is a top view of the display substrate provided for an exemplary embodiment, showing the positional relationship of the anode electrode, the first signal transmission line, the first connection line, the first dummy line, the first connection block and the second connection block, and other structures of the display substrate are omitted for illustration. Figure 7 and Figure 6 The difference is that the first dummy line 15 is added, and the other structures can refer to the description of Figure 6 above and will not be elaborated here. As Figure 7 shown, the first dummy line 15 can extend along the second direction Y. The orthogonal projection of the first end of the first dummy line 15 on the substrate can fall on the orthogonal projection of the first signal transmission line 11 on the substrate. The orthogonal projection of the first end of the first dummy line 15 on the substrate and the orthogonal projection of the first isolated anode on the substrate overlap at least partially. For example, the orthogonal projection of the second end of the first dummy line 15 on the substrate can be located on one side of the orthogonal projection of the first isolated anode on the substrate in the second direction Y. The first dummy line 15 can provide support below the side of the first anode 100A close to the second connection block 14. By providing the first dummy line 15, the uniformity of the surface flatness of different first anodes 100A can be increased, which helps to reduce problems such as color deviation and off-screen display defects of the display device.

[0083] In an exemplary embodiment, the second connection block 14 can be located on one side of the first anode 100A in the second direction Y. The first dummy line 15 can be located between the first signal transmission line 11 and the second connection block 14. The orthogonal projection of the second end of the first dummy line 15 on the substrate can be located on the side of the orthogonal projection of the first isolated anode on the substrate close to the second connection block 14.

[0084] In an exemplary embodiment, the positive projection of the first overlapping anode on the substrate and the positive projection of the first connection line 13 on the substrate have a first overlapping area, and the positive projection of the first isolated anode on the substrate and the positive projection of the first dummy line 15 on the substrate have a second overlapping area. The first overlapping area can be 0.8 times to 1.2 times the second overlapping area. For example, the first overlapping area and the second overlapping area can be set to be equal, and the present disclosure does not limit this.

[0085] In an exemplary embodiment, in the plane of the display substrate, the first connection line 13 has a first dimension d1 along the first direction X, and the first dummy line 15 has a second dimension d2 along the first direction X. The first dimension d1 can be 0.8 times to 1.2 times the second dimension d2. For example, the first dimension d1 and the second dimension d2 can be set to be equal, and the present disclosure does not limit this.

[0086] In an exemplary embodiment, the first dummy line 15 can be disposed in the first conductive layer. For example, the first end of the first dummy line 15 can be connected to the first signal transmission line 11, and the second end of the first dummy line 15 does not contact the second connection block 14.

[0087] Figure 8 A top view of the display substrate provided for another exemplary embodiment schematically shows the positional relationship of the anode electrode, the signal transmission line, the first connection line, the second dummy line, the first connection block, and the second connection block, and other structures of the display substrate are schematically omitted. Figure 8 and Figure 7 The difference lies in the different lengths of the first dummy line 15, and the other structures can refer to the description of Figure 7 above and will not be elaborated here. As Figure 8 shown, the display substrate can include a second conductive layer. The second conductive layer can be disposed on a side of the first conductive layer close to the anode conductive layer, and the first dummy line 15 can be disposed in the second conductive layer. When the first dummy line 15 is disposed in the second conductive layer, the positive projection of the first end of the first dummy line 15 on the substrate can fall on the positive projection of the first signal transmission line 11 on the substrate, and the positive projection of the second end of the first dummy line 15 on the substrate can fall on the positive projection of the second connection block 14 on the substrate. The present disclosure does not limit this.

[0088] This setting in this embodiment can make the length of the first dummy line 15 along the second direction Y the same as the length of the first connection line 13, which helps to keep the light reflection conditions of the metal below different first anodes 100A consistent, thereby improving the display effect.

[0089] Figure 9A top view of a display substrate provided for another exemplary embodiment schematically shows the positional relationship of an anode electrode, a first signal transmission line, a first signal adapter line, a first connection line, a first dummy line, a second dummy line, a first connection block, and a second connection block, and other structures of the display substrate are schematically omitted. Figure 9 and Figure 7 The difference lies in that a second dummy line 16 and a first signal adapter line 17 are added, and a first dummy line 15 and a second dummy line 16 are provided on the lower side of the second anode 100B. The remaining structures can be referred to the description of Figure 7 above and will not be elaborated here.

[0090] As Figure 9 shown, the second dummy line 16 can be located in the film layer on the side of the first dummy line 15 close to the anode conductive layer. The second connection block 14 can be located on one side of the first anode 100A in the second direction Y. The second dummy line 16 can extend along the second direction Y. The orthographic projection of the first end of the second dummy line 16 on the substrate can fall on the orthographic projection of the first signal transmission line 11 on the substrate, and the orthographic projection of the second end of the second dummy line 16 on the substrate can fall on the orthographic projection of the second connection block 14 on the substrate. The second dummy line 16 can provide support to the side below the first isolated anode close to the second connection block 14. By providing the second dummy line 16, the uniformity of the surface flatness of different first anodes 100A can be increased, thereby helping to reduce problems such as color shift and off-screen display defects of the display device. Moreover, by providing the orthographic projections of the two ends of the second dummy line 16 in the second direction Y on the substrate to fall on the orthographic projections of the first signal transmission line 11 and the second connection block 14 respectively, and the length of the second dummy line 16 along the second direction Y is the same as the length of the first connection line 13 along the second direction Y, the metal reflection conditions below different first anodes 100A are similar, reducing the reflection difference of the metal below different first anodes 100A and improving the display effect.

[0091] In the exemplary embodiment, the orthographic projection of the second dummy line 16 on the substrate can cover the orthographic projection of the first dummy line 15 on the substrate. The display substrate can include a first conductive layer, a second conductive layer, a third conductive layer, and an anode conductive layer sequentially provided on the substrate. The first dummy line 15 can be provided in the first conductive layer, and the second dummy line 16 can be provided in the second conductive layer, or the first dummy line 15 can be provided in the second conductive layer, and the second dummy line 16 can be provided in the third conductive layer. The present disclosure does not limit this.

[0092] In an exemplary embodiment, the first overlapping area of the positive projection of the first overlapping anode on the substrate and the positive projection of the first connection line 13 on the substrate may be set to 0.8 times to 1.2 times the third overlapping area of the positive projection of the first isolated anode on the substrate and the positive projection of the second dummy line 16 on the substrate. For example, the first overlapping area and the third overlapping area may be set to be equal, and the present disclosure does not limit this.

[0093] In an exemplary embodiment, the first dimension d1 of the first connection line 13 along the first direction X may be set to 0.8 times to 1.2 times the third dimension d3 of the second dummy line 16 along the first direction X. For example, the first dimension d1 and the third dimension d3 may be set to be equal, and the present disclosure does not limit this.

[0094] As Figure 9 shown, the display substrate may include a first signal transfer line 17 extending along the second direction Y. In a direction perpendicular to the display substrate, the first signal transfer line 17 may be located on a side of the first signal transmission line 11 close to the anode conductive layer. The first signal transfer line 17 may be connected to the first signal transmission line 11 through a first connection block 12, so that the first signal transfer line 17 and the first signal transmission line 11 may form a mesh structure for signal transmission. The positive projection of the first signal transmission line 11 on the substrate and the positive projection of the second anode 100B on the substrate at least partially overlap. The positive projection of the second anode 100B on the substrate and the positive projection of the second connection block 14 on the substrate may at least partially overlap. In an exemplary embodiment, the positive projection of the first connection line 13 on the substrate and the positive projections of some of the plurality of second anodes 100B on the substrate may at least partially overlap. The second dummy line 16 may be located on a side of the first dummy line 15 close to the anode conductive layer. The first dummy line 15 and the second dummy line 16 may extend along the second direction Y, and the positive projection of the second dummy line 16 on the substrate may cover the positive projection of the first dummy line 15 on the substrate. By providing the first dummy line 15 and the second dummy line 16 below both the first anode 100A and the second anode 100B, the uniformity of the surface flatness of different first anodes 100A and different second anodes 100B can be improved, and it helps to reduce the reflection difference of the metal layers below different first anodes 100A and different second anodes 100B, thereby helping to improve the display effect. In an exemplary embodiment, the positive projection of the second anode 100B on the substrate and the positive projection of the second connection block 14 on the substrate may not overlap. In other embodiments, Figure 9 the shown display substrate may also be provided with only the first dummy line 15 or the second dummy line 16, and the present disclosure does not limit this.

[0095] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include a substrate, a first conductive layer, a second conductive layer, and an anode conductive layer sequentially disposed on the substrate. The first dummy line 15 may be located in the first conductive layer, and the second dummy line 16 and the first signal transfer line 17 may be located in the second conductive layer. Alternatively, in a direction perpendicular to the display substrate, the display substrate may include a substrate, a first conductive layer, a second conductive layer, a third conductive layer, and an anode conductive layer sequentially disposed on the substrate. The first dummy line 15 may be located in the second conductive layer, the second dummy line 16 may be located in the third conductive layer, and the first signal transfer line 17 may be located in the second conductive layer or the third conductive layer. The film layer distribution of different structures may be set as needed, and the present disclosure does not limit this.

[0096] In an exemplary embodiment, the first signal transmission line 11 and the first signal transfer line 17 may be configured to transmit any one of signals such as a low-level signal, a data signal, an initial signal (the signal transmitted by the initial signal line), etc., and the present disclosure does not limit this.

[0097] In other embodiments, when the positive projection of the third anode 100C (or the fourth anode 100D) on the substrate at least partially overlaps with the positive projection of the first signal transmission line 11 on the substrate, and the positive projection of some of the third anodes 100C among the plurality of third anodes 100C (or some of the fourth anodes 100D among the plurality of fourth anodes 100D) on the substrate at least partially overlaps with the positive projection of the first connection line 13 on the substrate, at least one of the first dummy line 15 and the second dummy line 16 may be disposed on the side of the third anode 100C (or the fourth anode 100D) close to the substrate. For the specific setting situation, reference may be made to the description above for Figures 7 to 9 which will not be elaborated here.

[0098] In an exemplary embodiment, Figures 7 to 9 the solutions in

[0099] In some technologies, the display substrate may adopt a Colorfilter On Encapsulation (COE) structure on the package, that is, a color filter is directly formed on the side of the display substrate encapsulation layer away from the substrate. This structure can replace the original polarizer, making the display device thinner and lighter, and can improve the color gamut, reduce power consumption, and improve the use experience of the display device. However, in this structure of the display device, a display defect of green-purple separation may occur under a line light source. The inventors of the present application have found through research that this defect is caused by insufficient flatness of the anode of the light-emitting device. Even if the thickness of the flat layer under the anode conductive layer is increased, this defect cannot be eliminated.

[0100] Figure 10The top view of the anode electrode, the first signal transmission line, and the first signal adapter line in an exemplary embodiment. Figure 10 The circles in it represent the anode electrodes, and other structures are schematically omitted. As Figure 10 shown, multiple anode electrodes can be arranged in an array, including multiple electrode rows arranged in a first direction and multiple electrode columns arranged in a second direction. The orthographic projection of the anode electrode on the substrate can be an axisymmetric figure. A single anode electrode has a first symmetry axis O1 along the first direction X and a second symmetry axis O2 along the second direction Y. The display substrate can include multiple first signal transmission lines 11 whose main body portions extend along the first direction X. A single first signal transmission line 11 is respectively arranged on both sides of the single anode electrode in the second direction Y. The two first signal transmission lines 11 located on both sides of the single anode electrode in the second direction Y are symmetrically arranged along the first symmetry axis O1 of the anode electrode. Taking Figure 10Taking two first signal transmission lines 11 on both sides of the third anode 100C as an example, these two first signal transmission lines 11 can be axisymmetric about the first symmetry axis O1 of the third anode 100C, and these two first signal transmission lines 11 can be connected to each other through the first connection section 111 and the second connection section 112. The two first signal transmission lines 11 connected to each other through the first connection section 111 and the second connection section 112 can be referred to as a transmission line group. The first connection section 111 and the second connection section 112 can extend along the second direction Y. A single first signal transmission line 11 can be axisymmetrically arranged about the second symmetry axis O2 of the third anode 100C. Multiple first connection sections 111 and multiple second connection sections 112 can be axisymmetrically arranged about the second symmetry axis O2 of the third anode 100C. The display substrate can include multiple first signal transfer lines 17 whose main body parts extend along the second direction Y. A single first signal transfer line 17 can include multiple transfer sections. Each transfer section can be arranged to connect the transmission line groups adjacent along the second direction Y. The first signal transfer line 17 can coincide with the first symmetry axis O1 of the first anode 100A and the first symmetry axis O1 of the second anode 100B. A single first signal transmission line 11 can be axisymmetrically arranged along the first signal transfer line 17. Multiple first connection sections 111 and multiple second connection sections 112 can be axisymmetrically arranged along the first signal transfer line 17. The display substrate can include multiple conductive blocks 18. Multiple conductive blocks 18 can be axisymmetrically arranged about the first symmetry axis O1 of the third anode 100C. Multiple conductive blocks 18 can be axisymmetrically arranged about the first symmetry axis O1 of the fourth anode 100D. Multiple conductive blocks 18 can be axisymmetrically arranged about the second symmetry axis O2 of the first anode 100A. Multiple conductive blocks 18 can be axisymmetrically arranged about the second symmetry axis O2 of the second anode 100B. The conductive block 18 can be a structure such as a virtual electrode, etc., and the present disclosure does not limit this. In this embodiment, by arranging structures such as the first signal transmission line 11 and the first signal transfer line 17 located below the anode conductive layer to be axisymmetric about the symmetry axis of the anode, the wiring distribution below the anode conductive layer is uniform, which helps to improve the uniformity of the flatness of the anode conductive layer, thereby eliminating the display defects of the COE structure display device and improving the display effect.

[0101] In an exemplary embodiment, the display substrate may include a plurality of compensation electrode blocks. The orthographic projection of the compensation electrode blocks on the substrate may at least partially overlap with the orthographic projection of the anode electrode on the substrate. The plurality of compensation electrode blocks may be disposed in the conductive layer adjacent to the anode conductive layer and close to the substrate side. A single anode electrode may be divided into a first symmetric part and a second symmetric part along a first symmetry axis O1. The metal structures (including metal wires and conductive blocks, etc.) disposed under the first part are not the same as those disposed under the second part, which may cause differences in flatness between the first part and the second part of the anode. The overlapping area of the orthographic projection of the metal structure under the first part on the substrate and the orthographic projection of the first part on the substrate is a first area, and the overlapping area of the orthographic projection of the metal structure under the second part on the substrate and the orthographic projection of the second part on the substrate is a second area. By disposing compensation electrode blocks under the anode, the first area and the second area can be made approximately equal, thereby improving the flatness of the anode. A single anode electrode may be divided into a third symmetric part and a fourth symmetric part along a second symmetry axis O2. The overlapping area of the orthographic projection of the metal structure under the third part on the substrate and the orthographic projection of the third part on the substrate is a third area, and the overlapping area of the orthographic projection of the metal structure under the fourth part on the substrate and the orthographic projection of the fourth part on the substrate is a fourth area. By disposing compensation electrode blocks under the anode, the third area and the fourth area can be made approximately equal, thereby improving the flatness of the anode.

[0102] Figure 11A FIG. is a top view before disposing a compensation electrode block under a first anode in an exemplary embodiment. Figure 11B is Figure 11A FIG. is a top view after disposing a compensation electrode block under the first anode in, with other structures omitted for illustration. As Figure 11A shown, a first metal structure 21, a second metal structure 22, a third metal structure 23, a fourth metal structure 24, and a fifth metal structure 25 are disposed under a first anode 100A. The first metal structure 21, the second metal structure 22, and the third metal structure 23 may be connected to each other. The pattern formed by the first metal structure 21, the second metal structure 22, and the third metal structure 23 may be axisymmetric along a second symmetry axis O2 of the first anode 100A. The third metal structure 23 and the fourth metal structure 24 may be axisymmetric along a second symmetry axis O3 of the first anode 100A. In Figure 11A FIG., the third area and the fourth area of the first anode 100A are approximately equal, while the first area and the second area of the first anode 100A are not equal, which will result in low uniformity of the flatness of the first anode 100A. As Figure 11BAs shown, a first compensation electrode block 251 may be disposed on a side of the fifth metal structure 25 close to the anode conductive layer, so that the first area and the second area of the first anode 100A are approximately equal. The first compensation electrode block 251 may be axially symmetric along the second symmetry axis O2 of the first anode 100A. In the first direction X, the distance between the edge of the first compensation electrode block 251 and the second symmetry axis O2 of the first anode 100A is a first length L1. By adjusting the size of the first compensation electrode block 251, the ratio of the first area to the second area can be adjusted. For example, the first area may be set to be greater than or equal to 0.8 times and less than or equal to 1.2 times the second area. The present disclosure does not limit this.

[0103] In an exemplary embodiment, the display substrate may include a substrate and a first conductive layer, a second conductive layer, a third conductive layer, and an anode conductive layer sequentially disposed on the substrate. The first metal structure 21 to the fifth metal structure 25 may be disposed in the second conductive layer, and the first compensation electrode block 251 may be disposed in the third conductive layer. Alternatively, the first compensation electrode block 251 may be disposed on a side of the fifth metal structure 25 close to the anode conductive layer, and the remaining structures may be disposed in any conductive layer as needed. The present disclosure does not limit this.

[0104] Figure 12A It is a top view before the compensation electrode block is disposed under the second anode in an exemplary embodiment. Figure 12B For Figure 12A It is a top view after the compensation electrode block is disposed under the second anode in , and other structures are omitted for illustration. Figure 12A And Figure 12B The structure of Figure 11A And Figure 11B is similar to the structure in Figure 11A And Figure 11B , except that the first compensation electrode block 251 is replaced by the second compensation electrode block 252. The remaining structures may refer to the descriptions of

[0105] As Figure 12B shown, the second compensation electrode block 252 may be axially symmetric along the second symmetry axis O2 of the second anode 100B. In the first direction X, the distance between the edge of the second compensation electrode block 252 and the second symmetry axis O2 of the second anode 100B is a second length L2, and the second length L2 may be greater than or equal to the first length L1. Figure 12B In , by setting the second compensation electrode block 252, the ratio of the first area to the second area can be controlled to reach 99.98%, greatly improving the uniformity of the flatness of the second anode 100B. The ratio range of the first area to the second area, the film layer arrangement of the display substrate, etc. may refer to the descriptions of Figure 11A And Figure 11B , and will not be elaborated here.

[0106] Figure 11B and Figure 12B illustrates the cases of compensating the first anode 100A and the second anode 100B respectively, which can specifically improve the uniformity of the flatness of different first anodes 100A and the uniformity of the flatness of the second anode 100B. In an exemplary embodiment, the shapes and sizes of the first compensation electrode block 251 and the second compensation electrode block 252 can be set to be the same, so as to uniformly compensate the first anode 100A and the second anode 100B, which helps to improve the flatness of the anode on the whole display substrate and simplifies the manufacturing process. The present disclosure does not limit this.

[0107] Figure 13A is a top view before arranging the compensation electrode block under the third anode in an exemplary embodiment. Figure 13B is Figure 13A a top view after arranging the compensation electrode block under the third anode in Figure 13A which omits other structures for illustration. As Figure 13A shown, a sixth metal structure 31, a seventh metal structure 32, an eighth metal structure 33 and a ninth metal structure 34 are arranged under the third anode 100C. The sixth metal structure 31 and the seventh metal structure 32 can be axisymmetric about the second symmetry axis O2 of the third anode 100C, and the eighth metal structure 33 and the ninth metal structure 34 can be axisymmetric about the second symmetry axis O2 of the third anode 100C. In Figure 13B the third area and the fourth area of the third anode 100C are approximately equal, while the first area and the second area of the third anode 100C are not equal, which will lead to low uniformity of the flatness of the third anode 100C. As shown, a third compensation electrode block 311 can be arranged on the side of the sixth metal structure 31 close to the anode conductive layer, and a fourth compensation electrode block 321 can be arranged on the side of the seventh metal structure 32 close to the anode conductive layer, so that the first area and the second area of the third anode 100C are approximately equal. The third compensation electrode block 311 and the fourth compensation electrode block 321 can be axisymmetric about the second symmetry axis O2 of the third anode 100C. By adjusting the sizes of the third compensation electrode block 311 and the fourth compensation electrode block 321, the ratio of the first area and the second area of the third anode 100C can be adjusted. For example, the first area can be set to be greater than or equal to 0.8 times and less than or equal to 1.2 times the second area. The present disclosure does not limit this.

[0108] In an exemplary embodiment, the display substrate may include a substrate, and a first conductive layer, a second conductive layer, a third conductive layer, and an anode conductive layer sequentially disposed on the substrate. The sixth metal structure 31 to the ninth metal structure 34 may be disposed on the second conductive layer, and the third compensation electrode block 311 and the fourth compensation electrode block 321 may be disposed on the third conductive layer. Alternatively, the third compensation electrode block 311 may be disposed on a side of the sixth metal structure 31 close to the anode conductive layer, and the fourth compensation electrode block 321 may be disposed on a side of the seventh metal structure 32 close to the anode conductive layer. The remaining structures may be disposed on any conductive layer as needed, and the present disclosure does not limit this.

[0109] In an exemplary embodiment, the structure of the fourth anode 100D and the situation of disposing the compensation electrode block may be the same as that of the third anode 100C, and will not be described herein again.

[0110] Figures 7 to 13B The solutions in [description] can be arbitrarily combined with each other, and the present disclosure does not limit this.

[0111] The embodiments of the present disclosure further provide a display device, including the display substrate described in any of the above embodiments. The display device may be: an OLED display, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any product or component with a display function. The embodiments of the present disclosure are not limited thereto.

[0112] Although the disclosed embodiments of the present invention are as above, the described content is only an embodiment adopted for facilitating the understanding of the present invention and is not used to limit the present invention. Any person skilled in the art within the scope of the present invention, without departing from the spirit and scope disclosed by the present invention, may make any modifications and changes in the form and details of the implementation. However, the scope of patent protection of the present invention shall still be subject to the scope defined by the appended claims.

Claims

1. A display substrate, characterized in that, it includes: a substrate, a first conductive layer, and an anode conductive layer that are sequentially disposed on the substrate; the first conductive layer includes a plurality of first signal transmission lines extending in a first direction, a plurality of first connection lines extending in a second direction, and a plurality of first connection blocks, where the first direction and the second direction intersect; the first connection blocks are connected to the first signal transmission lines through the first connection lines; the anode conductive layer includes a plurality of anode electrodes, the plurality of anode electrodes include a plurality of first anodes, the plurality of first anodes include a plurality of first overlapping anodes and a plurality of first isolated anodes, at least a part of the orthographic projection of the first signal transmission line on the substrate overlaps with at least a part of the orthographic projection of the first anode on the substrate, and at least a part of the orthographic projection of the first connection line on the substrate overlaps with at least a part of the orthographic projection of the first overlapping anode on the substrate; the display substrate further includes a first dummy line on a side of the anode conductive layer close to the substrate, and the first dummy line extends in the second direction; the orthographic projection of the first end of the first dummy line on the substrate falls on the orthographic projection of the first signal transmission line on the substrate, and at least a part of the orthographic projection of the first end of the first dummy line on the substrate overlaps with at least a part of the orthographic projection of the first isolated anode on the substrate.

2. The display substrate according to claim 1, characterized in that, the first conductive layer further includes a second connection block, the second connection block and the first connection block are located on the same side of the first signal transmission line along the second direction, and the second connection block is not connected to the first signal transmission line; the orthographic projection of the first dummy line on the substrate is located between the orthographic projection of the first signal transmission line on the substrate and the orthographic projection of the second connection block on the substrate.

3. The display substrate according to claim 2, characterized in that, the first dummy line is located in the first conductive layer, the first end of the first dummy line is connected to the first signal transmission line, and the second end of the first dummy line is not connected to the second connection block.

4. The display substrate according to claim 2, characterized in that, the display substrate further includes a second conductive layer, the second conductive layer is located on a side of the first conductive layer close to the anode conductive layer, the first dummy line is located in the second conductive layer, and the orthographic projection of the second end of the first dummy line on the substrate does not overlap with the orthographic projection of the second connection block on the substrate.

5. The display substrate according to claim 2, characterized in that, the display substrate further includes a second conductive layer, the second conductive layer is located on a side of the first conductive layer close to the anode conductive layer, the first dummy line is located in the second conductive layer, and in the second direction, the length of the first dummy line is the same as the length of the first connection line.

6. The display substrate according to claim 3 or 4, characterized in that, The display substrate further includes a second dummy line, and the second dummy line is located on a side of the first dummy line close to the anode conductive layer; a positive projection of a first end of the second dummy line on the substrate falls on a positive projection of the first signal transmission line on the substrate, and in a second direction, a length of the second dummy line is the same as a length of the first connection line, and a positive projection of the second dummy line on the substrate covers a positive projection of the first dummy line on the substrate.

7. The display substrate according to claim 6, wherein, the anode conductive layer includes a plurality of second anodes, and a positive projection of the second connection block on the substrate and a positive projection of the second anode on the substrate at least partially overlap; the first dummy line is disposed on a side of the second anode close to the substrate, or the first dummy line and the second dummy line are disposed on a side of the second anode close to the substrate.

8. The display substrate according to claim 1, wherein, the display substrate includes a plurality of first signal transfer lines extending in the second direction, the first signal transfer lines are located on a side of the first signal transmission line close to the anode conductive layer, and the first signal transfer lines are connected to the first signal transmission line through the first connection blocks.

9. The display substrate according to claim 8, wherein, the plurality of anode electrodes include a plurality of electrode rows distributed in a first direction and a plurality of electrode columns distributed in the second direction, and in the second direction, a single first signal transmission line and a single electrode row are alternately arranged; the anode electrode has a first axis of symmetry extending in the first direction; two first signal transmission lines located on both sides of the anode electrode in the second direction are arranged to be axisymmetric about the first axis of symmetry of the anode electrode.

10. The display substrate according to claim 9, wherein, the anode electrode has a second axis of symmetry extending in the second direction; the first signal transfer line coincides with the second axis of symmetry of a single electrode column.

11. The display substrate according to claim 10, wherein, in the first direction, a single electrode column is spaced between adjacent first signal transfer lines.

12. The display substrate according to claim 11, wherein, in the second direction, two adjacent first signal transmission lines form a transmission line group, and two first signal transmission lines within a single transmission line group are connected to each other through a first connection segment and a second connection segment arranged in the second direction; the first connection segment and the second connection segment are axisymmetric about the second axis of symmetry of the electrode column.

13. The display substrate according to claim 12, wherein, a single first signal transfer line includes a plurality of transfer segments, and the transfer segments are arranged to connect adjacent transmission line groups in the second direction.

14. The display substrate according to claim 9, wherein, The anode electrode includes a first part and a second part that are symmetric to each other, and the first part and the second part are axially symmetric about the first axis of symmetry of the anode electrode; the overlapping area between the positive projection of the metal structure on the substrate on the side of the first part close to the substrate and the first part is a first area, and the overlapping area between the positive projection of the metal structure on the substrate on the side of the second part close to the substrate and the second part is a second area; The display substrate further includes a compensation electrode block, the compensation electrode block is located on the side of the anode electrode close to the substrate, and the compensation electrode block is configured to make the first area greater than or equal to 0.8 times the second area and less than or equal to 1.2 times the second area.

15. A display device, characterized in that, it includes the display substrate according to any one of claims 1 to 14.

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