Display device, method of manufacturing the same, and head mounted display including the same

Abstract

A display device, a method of manufacturing the display device, and a head mounted display including the display device are provided. The display device includes: a first light emitting unit configured to emit first light; a second light emitting unit configured to emit second light; a third light emitting unit configured to emit third light; a first lens overlapping the first light emitting unit and including a first sub-lens overlapping a first portion of the first light emitting unit and a second sub-lens overlapping a second portion of the first light emitting unit; a second lens overlapping the second light emitting unit; and a third lens overlapping the third light emitting unit, in which a length of the first light emitting unit in the second direction is greater than a length of the second light emitting unit in the second direction and greater than a length of the third light emitting unit in the second direction.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0166218 filed in the Korean Intellectual Property Office on November 27, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] One or more embodiments of the present disclosure relate to a display device, a method of manufacturing a display device, and a head-mounted display including the display device. Background Art

[0003] A head-mounted display (HMD) is an image display device that is worn on the user's head in the form of glasses or a helmet to form a focus at a close distance in front of the user's eyes. The head-mounted display can realize virtual reality (VR) or augmented reality (AR).

[0004] The head-mounted display magnifies an image displayed on a small display device by using a plurality of lenses, and displays the magnified image. Therefore, the display device applied to the head-mounted display can appropriately provide a high-resolution image (for example, an image with a resolution of 3000 PPI (pixels per inch) or more. For this purpose, an organic light emitting diode on silicon (OLEDoS), which is a high-resolution small organic light emitting display device, is used as a display device applied to the head-mounted display. OLEDoS is an image display device in which an organic light emitting diode (OLED) is located on a semiconductor wafer substrate including a complementary metal oxide semiconductor (CMOS). Summary of the invention

[0005] Aspects of embodiments of the present disclosure provide a display device capable of providing a high-resolution image.

[0006] Aspects of embodiments of the present disclosure also provide a method of manufacturing a display device capable of providing a high-resolution image.

[0007] Aspects of embodiments of the present disclosure also provide a head-mounted display capable of providing high-resolution images.

[0008] However, aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] According to one or more embodiments of the present disclosure, a display device is provided, comprising: a first light emitting unit configured to emit a first light; a second light emitting unit configured to emit a second light; a third light emitting unit configured to emit a third light; a first lens overlapping the first light emitting unit and comprising a first sub-lens overlapping a first portion of the first light emitting unit and a second sub-lens overlapping a second portion of the first light emitting unit; a second lens overlapping the second light emitting unit; and a third lens overlapping the third light emitting unit, wherein a length of the first light emitting unit in the second direction is greater than a length of the second light emitting unit in the second direction, and greater than a length of the third light emitting unit in the second direction.

[0010] The length of the first sub-lens in the second direction may be smaller than the length of the second sub-lens in the second direction.

[0011] The length of the first light emitting unit in the first direction crossing the second direction may be smaller than the length of the second light emitting unit in the first direction, and may be smaller than the length of the third light emitting unit in the first direction.

[0012] The length of the first sub-lens in the first direction may be substantially equal to the length of the second sub-lens in the first direction.

[0013] The length of the first sub-lens in the first direction may be smaller than the length of the second lens in the first direction, and may be smaller than the length of the third lens in the first direction.

[0014] The length of the second sub-lens in the first direction may be smaller than the length of the second lens in the first direction, and may be smaller than the length of the third lens in the first direction.

[0015] The length of the second light emitting unit in the second direction may be smaller than the length of the third light emitting unit in the second direction.

[0016] A length of the second lens in the second direction may be smaller than a length of the third lens in the second direction.

[0017] The length of the second light emitting unit in the first direction may be substantially equal to the length of the third light emitting unit in the first direction.

[0018] A length of the second lens in the first direction may be substantially equal to a length of the third lens in the first direction.

[0019] A first gap between the first sub-lens and the second sub-lens in the second direction may be smaller than a second gap between the second lens and the third lens in the second direction.

[0020] A first line passing through a center of the first sub-lens and a center of the second lens and a second line passing through a center of the second sub-lens and a center of the third lens may be substantially parallel.

[0021] A third line passing through a center of a first gap between the first sub-lens and the second sub-lens in the second direction and a center of a second gap between the second lens and the third lens in the second direction may be substantially parallel to the first line and the second line.

[0022] According to one or more embodiments of the present disclosure, a method for manufacturing a display device is provided, the method comprising the following steps: forming a light-emitting element, the light-emitting element comprising a first electrode on a substrate, a light-emitting stack above the first electrode, and a second electrode above the light-emitting stack; forming an encapsulation layer above the second electrode; forming a color filter above the encapsulation layer; and forming a first lens, a second lens, and a third lens above the color filter.

[0023] The steps of forming the first lens, the second lens, and the third lens may include: forming a first lens layer over the color filter; forming a second lens pattern layer including a convex pattern over the first lens layer; and etching the first lens layer and the second lens pattern layer to form the first lens, the second lens, and the third lens.

[0024] The thickness of the first lens layer may be greater than the thickness of the second lens pattern layer.

[0025] A thickness of the first lens layer etched by the etching step may be greater than a thickness of the second lens pattern layer.

[0026] The step of forming the first lens, the second lens, and the third lens may further include dry etching to remove portions of the first lens layer and the encapsulation layer above the pad metal layer of the pad portion.

[0027] The dry etching step may include using carbon tetrafluoride (CF 4 ), carbon tetrafluoride (CF 4 ) and oxygen (O 2 ) or carbon tetrafluoride (CF 4 ) and argon (Ar).

[0028] According to one or more embodiments of the present disclosure, a head-mounted display is provided, which includes: a display device, including: a first light-emitting unit, configured to emit a first light; a second light-emitting unit, configured to emit a second light, and having a length in a second direction that is smaller than a length of the first light-emitting unit in the second direction; a third light-emitting unit, configured to emit a third light, and having a length in the second direction that is smaller than a length of the first light-emitting unit in the second direction; a first lens, overlapping with the first light-emitting unit, and including a first sub-lens overlapping with a first portion of the first light-emitting unit and a second sub-lens overlapping with a second portion of the first light-emitting unit; a second lens, overlapping with the second light-emitting unit; and a third lens, overlapping with the third light-emitting unit; a shell member, configured to accommodate the display device; and an optical member, configured to magnify a display image of the display device.

[0029] According to the foregoing and other embodiments of the present disclosure, and according to a head mounted display including a display device according to the embodiment, a light emitting unit formed to be elongated in one direction is overlapped with a plurality of lenses, so that the color difference of light of the display device can be uniform regardless of the azimuth angle. Therefore, the reduction in the color uniformity of light emitted from the display device according to the azimuth angle can be reduced, prevented or minimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other embodiments of the present disclosure will become more apparent by describing the embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 is an exploded perspective view showing a display device according to one or more embodiments; Figure 2 is a block diagram showing a display device according to one or more embodiments; Figure 3 is an equivalent circuit diagram of a first sub-pixel according to one or more embodiments; Figure 4 is a layout diagram showing an example of a display panel according to one or more embodiments; Figure 5 It is shown Figure 4 An example layout diagram of a display area; Figure 6 It is shown along Figure 5 A cross-sectional view of an example of a display panel taken along line AA'; Figure 7 It is shown in detail Figure 6 an enlarged cross-sectional view of region A; Figure 8 It is shown Figure 4 An example layout diagram of a first pad of a first pad portion; Fig. 9 It is shown along Figure 8 A cross-sectional view of an example of a display panel taken along line BB'; Fig.10 is an example diagram showing color difference values ​​according to azimuth angles; Fig.11 is a flowchart illustrating a method of manufacturing a display device according to one or more embodiments; Figures 12 to 23 is a cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments; Fig.24 is a perspective view showing a head mounted display according to one or more embodiments; Fig.25 It is shown Fig.24 an exploded perspective view of an example of a head mounted display; and Fig.26 is a perspective view illustrating a head mounted display according to one or more embodiments. DETAILED DESCRIPTION

[0031] By referring to the detailed description and the accompanying drawings of the embodiments, the aspects and features of the embodiments of the present disclosure and the methods for realizing the same can be more easily understood. Hereinafter, the embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments can be implemented in various different forms and should not be interpreted as being limited to the embodiments shown here. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and the aspects and features of the present disclosure will be fully conveyed to those skilled in the art. Therefore, the processes, elements and techniques that are not necessary for those of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described.

[0032] Unless otherwise specified, the same reference numerals, symbols or combinations thereof denote the same elements throughout the drawings and written description, and therefore, description thereof will not be repeated. In addition, parts not related to the description of one or more embodiments may not be shown to make the description clear.

[0033] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity. In addition, the use of cross-hatching and / or shading is often provided in the drawings to clarify the boundaries between adjacent elements. As such, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the illustrated elements, and / or any other characteristic, attribute, property, etc. of an element.

[0034] Various embodiments are described herein with reference to schematically illustrated cross-sectional views of embodiments and / or intermediate structures. As such, variations in the shapes of the drawings caused by, for example, manufacturing techniques and / or tolerances are anticipated. In addition, for the purpose of describing embodiments according to the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the specific illustrated shapes of the regions, but rather include deviations in shapes caused by, for example, manufacturing.

[0035] For example, an implanted region illustrated as a rectangle may have rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions illustrated in the accompanying drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to be limiting. Additionally, as will be appreciated by those skilled in the art, the described embodiments may be modified in a variety of different ways, all without departing from the spirit or scope of the present disclosure.

[0036] In the detailed description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of the various embodiments. However, it is apparent that the various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0037] For ease of explanation, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used here to describe the relationship of one element or feature to another element or feature as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatially relative terms are intended to cover different orientations of the device in use or in operation. For example, if the device in the drawings is turned over, the element described as "below" or "below" or "below" other elements or features will then be oriented to be "above" the other elements or features. Therefore, the example terms "below" and "below" can cover both above and below. The device can be oriented otherwise (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used here should be interpreted accordingly. Similarly, when a first component is described as being arranged "on" a second component, this means that the first component is arranged at the upper or lower side of the second component, and is not limited to the upper side of the second component based on the direction of gravity.

[0038] Furthermore, in this specification, the phrase "on a plane" or "in a plan view" means viewing a target portion from the top, and the phrase "in section" means viewing a section formed by vertically cutting the target portion from the side.

[0039] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "bonded to" another element, layer, region, or component, the element, layer, region, or component may be directly formed on, directly on, directly connected to, or directly bonded to the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly bonded to the other element, layer, region, or component such that one or more intervening elements, layers, regions, or components may be present. For example, when a layer, region, or component is referred to as being "electrically connected to" or "electrically bonded to" another layer, region, or component, the layer, region, or component may be directly electrically connected to or directly bonded to the other layer, region, and / or component, or there may be intervening layers, regions, or components. However, "directly connected / directly coupled" means that one component is directly connected or coupled to another component without intervening components. At the same time, other expressions describing the relationship between components (such as, "between," "immediately between," "adjacent to," and "directly adjacent to") may be similarly interpreted. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0040] For the purpose of the present disclosure, expressions such as "at least one of ...," "one of ...," and "selected from ...", when following (before) a list of elements, modify the entire list of elements without modifying the individual elements in the list. For example, "at least one of X, Y, and Z," and "at least one of the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as XYZ, XYY, XZ, YZ, and ZZ as examples), or any variation thereof. Similarly, expressions such as "at least one of A and / or B" may include A, B, or A and B. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, expressions such as "A and / or B" may include A, B, or A and B. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0041] It will be understood that, although the terms "first", "second", "third", etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer, or part described below may be referred to as a second element, component, region, layer, or part.

[0042] In the example, the X-axis, Y-axis and / or Z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0043] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "one" and "a (kind / person)" are also intended to include plural forms. It will also be understood that when used in this specification, the terms "include" and its variations, "have" and its variations, "include" and its variations illustrate the presence of stated features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups.

[0044] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as approximate terms rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. "About" or "approximately" as used herein include the stated values ​​and mean: within the acceptable range of deviations of the specific value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0045] When one or more embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in a reverse order to the described order.

[0046] In addition, any numerical range disclosed and / or described herein is intended to include all sub-ranges of the same numerical precision contained in the range. For example, the range of "1.0 to 10.0" is intended to include all sub-ranges between the minimum value 1.0 and the maximum value 10.0 (and including the minimum value 1.0 and the maximum value 10.0), for example, with a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit described here is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to modify this specification (including claims) to explicitly describe any sub-range contained in the scope of explicit description here. All such ranges are intended to be inherently described in this specification so that the modification of any such sub-ranges explicitly described will meet the requirements.

[0047] The electronic device (or electrical device) and / or any other related device or component according to one or more embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., an application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or on separate IC chips. In addition, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate.

[0048] In addition, the various components of these devices can be processes or threads running on one or more processors in one or more computing devices, which execute computer program instructions and interact with other system components for performing the various functions described herein. Computer program instructions are stored in a memory that can be implemented in a computing device using a standard memory device (such as a random access memory (RAM) as an example). Computer program instructions can also be stored in other non-temporary computer-readable media (such as a CD-ROM, a flash drive, etc. as an example). In addition, it should be recognized by those skilled in the art that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices without departing from the spirit and scope of the present disclosure.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having, for example, a meaning consistent with their meaning in the context of the relevant art and / or in this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0050] Figure 1 is an exploded perspective view illustrating a display device according to one or more embodiments. Figure 2 is a block diagram illustrating a display device according to one or more embodiments.

[0051] Reference Figure 1 and Figure 2 The display device 10 according to one or more embodiments is a device that displays a moving image or a still image. The display device 10 according to one or more embodiments can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notepads, electronic books, portable multimedia players (PMPs), navigation systems, ultra-mobile PCs (UMPCs), etc. For example, the display device 10 according to one or more embodiments can be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device terminal. Optionally, the display device 10 according to one or more embodiments can be applied to smart watches, watch phones, head-mounted displays (HMDs) for realizing virtual reality and augmented reality, etc.

[0052] The display device 10 according to one or more embodiments includes a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , a timing control circuit 400 , and a power supply circuit 500 .

[0053] The display panel 100 may have a planar shape similar to a quadrilateral shape. For example, the display panel 100 may have a planar shape similar to a quadrilateral having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. In the display panel 100, a corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be a right angle or rounded with a curvature (e.g., a predetermined curvature). The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may conform to the planar shape of the display panel 100, but the present disclosure is not limited thereto.

[0054] like Figure 2As shown in FIG. 1 , the display panel 100 includes a display area DAA for displaying an image and a non-display area NDA where no image is displayed.

[0055] The display area DAA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0056] A plurality of pixels PX may be arranged in a matrix in the first direction DR1 and the second direction DR2. A plurality of scan lines SL and a plurality of emission control lines EL may extend in the first direction DR1 while being arranged in the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 while being arranged in the first direction DR1.

[0057] The plurality of scan lines SL include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines EBL. The plurality of emission control lines EL include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0058] The plurality of pixels PX include a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 may include Figure 3 The plurality of pixel transistors shown in the figure may be formed by a semiconductor process and located on a semiconductor substrate SSUB (see Figure 6 For example, a plurality of pixel transistors of the data driver 700 may be formed of a complementary metal oxide semiconductor (CMOS).

[0059] Each of the plurality of sub-pixels SP1, SP2, and SP3 may be connected to one write scan line GWL among a plurality of write scan lines GWL, one control scan line GCL among a plurality of control scan lines GCL, one bias scan line EBL among a plurality of bias scan lines EBL, one first emission control line EL1 among a plurality of first emission control lines EL1, one second emission control line EL2 among a plurality of second emission control lines EL2, and one data line DL among a plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 may receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL, and may emit light from the light emitting element LE (see FIG. 1 ) according to the data voltage. Figure 3 ) emits light.

[0060] The non-display area NDA includes a scan driver 610 , an emission driver 620 , and a data driver 700 .

[0061] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors may be formed on a semiconductor substrate SSUB (see FIG. Figure 6 ). For example, a plurality of scanning transistors and a plurality of light emitting transistors may be formed by CMOS. Figure 2 , the scan driver 610 is shown to be located on the left side of the display area DAA and the emission driver 620 is located on the right side of the display area DAA, but the present disclosure is not limited thereto. For example, the scan driver 610 and the emission driver 620 may be located on either side of the left and right sides of the display area DAA.

[0062] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 400, and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal in response to the scan timing control signal SCS, and may sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS, and may sequentially output the bias scan signal to the bias scan line EBL.

[0063] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 may receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 may generate a first emission control signal according to the emission timing control signal ECS, and may sequentially output the first emission control signal to the first emission control line EL1. The second emission control driver 622 may generate a second emission control signal according to the emission timing control signal ECS, and may sequentially output the second emission control signal to the second emission control line EL2.

[0064] The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed on a semiconductor substrate SSUB (see FIG. Figure 6 For example, the plurality of data transistors may be formed of CMOS.

[0065] The data driver 700 may receive the digital video data DATA and the data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and outputs the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 610, and the data voltage may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0066] The heat dissipation layer 200 may overlap the display panel 100 in the third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be located on one surface of the display panel 100 (for example, located on the rear surface of the display panel 100). The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a layer containing, for example, graphite, silver (Ag), copper (Cu), or aluminum (Al) having high thermal conductivity.

[0067] The circuit board 300 may be electrically connected to a first pad (also referred to as a “pad” or “pad”) portion PDA1 (see FIG. 1 ) of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film. Figure 4 ) of multiple first pads PD1 (see Figure 4 ). The circuit board 300 may be a flexible printed circuit board having a flexible material or a flexible film. Figure 1 100, but the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be located on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. One end of the circuit board 300 may be the first pad portion PDA1 of the circuit board 300 and the display panel 100 by using a conductive adhesive member (see Figure 4 ) of multiple first pads PD1 (see Figure 4 ) on the opposite end of the other end of the connection.

[0068] The timing control circuit 400 may receive digital video data DATA and a timing signal input from the outside. The timing control circuit 400 may generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 in response to the timing signal. The timing control circuit 400 may output the scan timing control signal SCS to the scan driver 610, and output the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 may output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0069] The power supply circuit 500 can generate a plurality of panel driving voltages according to a power supply voltage from the outside. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT and supply the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT to the display panel 100. Figure 3 A first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT are described.

[0070] Each of the timing control circuit 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) and may be attached to one surface of the circuit board 300. In this case, a scan timing control signal SCS, an emission timing control signal ECS, digital video data DATA, and a data timing control signal DCS of the timing control circuit 400 may be supplied to the display panel 100 through the circuit board 300. In addition, a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 through the circuit board 300.

[0071] Optionally, similar to the scan driver 610, the emission driver 620, and the data driver 700, each of the timing control circuit 400 and the power supply circuit 500 may be located in the non-display area NDA of the display panel 100. In this case, the timing control circuit 400 may include a plurality of timing transistors, and the power supply circuit 500 may include a plurality of power supply transistors. The plurality of timing transistors and the plurality of power supply transistors may be formed on the semiconductor substrate SSUB (see FIG. 1 ) by a semiconductor process. Figure 6 ). For example, the plurality of timing transistors and the plurality of power supply transistors may be formed of CMOS. Each of the timing control circuit 400 and the power supply circuit 500 may be located between the data driver 700 and the first pad portion PDA1 (see Figure 4 )between.

[0072] Figure 3 is an equivalent circuit diagram of a first sub-pixel according to one or more embodiments.

[0073] Reference Figure 3, the first sub-pixel SP1 may be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. In addition, the first sub-pixel SP1 may be connected to a first drive voltage line VSL to which a first drive voltage VSS corresponding to a low potential voltage is applied, a second drive voltage line VDL to which a second drive voltage VDD corresponding to a high potential voltage is applied, and a third drive voltage line VIL to which a third drive voltage VINT corresponding to an initialization voltage is applied. That is, the first drive voltage line VSL may be a low potential voltage line, the second drive voltage line VDL may be a high potential voltage line, and the third drive voltage line VIL may be an initialization voltage line. In this case, the first drive voltage VSS may be lower than the third drive voltage VINT. The second drive voltage VDD may be higher than the third drive voltage VINT.

[0074] The first subpixel SP1 includes a plurality of transistors T1 , T2 , T3 , T4 , T5 , and T6 , a light emitting element LE, a first capacitor CP1 , and a second capacitor CP2 .

[0075] The light emitting element LE emits light in response to a driving current flowing through the channel of the first transistor T1. The emission amount of the light emitting element LE may be proportional to the driving current. The light emitting element LE may be located between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light emitting element LE may be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light emitting element LE may be connected to the first driving voltage line VSL. The first electrode of the light emitting element LE may be an anode electrode, and the second electrode of the light emitting element LE may be a cathode electrode. The light emitting element LE may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer located between the first electrode and the second electrode, but the present disclosure is not limited thereto. For example, the light emitting element LE may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor located between the first electrode and the second electrode, in which case the light emitting element LE may be a micro light emitting diode.

[0076] The first transistor T1 may be a driving transistor that controls a source-drain current (hereinafter, referred to as a "driving current") flowing between its source electrode and drain electrode according to a voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0077] The second transistor T2 may be located between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL may be applied to one electrode of the first capacitor CP1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor CP1.

[0078] The third transistor T3 may be located between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. To this end, since the gate electrode and the drain electrode of the first transistor T1 may be connected, the first transistor T1 may operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0079] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Therefore, the driving current of the first transistor T1 may be supplied to the light emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0080] The fifth transistor T5 may be located between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line EBL to connect the third node N3 to the third driving voltage line VIL. Therefore, the third driving voltage VINT of the third driving voltage line VIL may be applied to the first electrode of the light emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0081] The sixth transistor T6 may be located between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, the second drive voltage VDD of the second drive voltage line VDL may be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0082] The first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0083] The second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and the other electrode connected to the second driving voltage line VDL.

[0084] The first node N1 is a junction point between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is a junction point between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a junction point between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE.

[0085] Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be a P-type MOSFET, but the present disclosure is not limited thereto. Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be an N-type MOSFET. Alternatively, some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be a P-type MOSFET, and each of the remaining transistors may be an N-type MOSFET.

[0086] Despite Figure 3 FIG. 4 shows that the first sub-pixel SP1 includes six transistors T1, T2, T3, T4, T5 and T6 and two capacitors CP1 and CP2, but it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to Figure 3 For example, the number of transistors and the number of capacitors of the first sub-pixel SP1 are not limited to Figure 3 The quantity shown in .

[0087] In addition, the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 can be combined with Figure 3The equivalent circuit diagram of the first sub-pixel SP1 described above is substantially the same. Therefore, the description of the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 will not be repeated in this specification.

[0088] Figure 4 is a layout diagram illustrating an example of a display panel according to one or more embodiments.

[0089] Reference Figure 4 The display area DAA of the display panel 100 according to one or more embodiments includes a plurality of pixels PX arranged in a matrix form. The non-display area NDA of the display panel 100 according to one or more embodiments includes a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad part PDA1, and a second pad part PDA2.

[0090] The scan driver 610 may be located at a first side of the display area DAA, and the emission driver 620 may be located at a second side of the display area DAA. For example, the scan driver 610 may be located at one side of the display area DAA in the first direction DR1, and the emission driver 620 may be located at the other side of the display area DAA in the first direction DR1. The scan driver 610 may be located on the left side of the display area DAA, and the emission driver 620 may be located on the right side of the display area DAA. However, the present disclosure is not limited thereto, and the scan driver 610 and the emission driver 620 may be located on either side of the first side and the second side of the display area DAA.

[0091] The first pad portion PDA1 may include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 through a conductive adhesive member. The first pad portion PDA1 may be located at a third side of the display area DAA. For example, the first pad portion PDA1 may be located at one side of the display area DAA in the second direction DR2.

[0092] The first pad portion PDA1 may be located outside the data driver 700 in the second direction DR2. That is, the first pad portion PDA1 may be closer to the edge of the display panel 100 than the data driver 700.

[0093] The second pad portion PDA2 may include a plurality of second pads PD2 corresponding to inspection pads for testing whether the display panel 100 operates normally. The plurality of second pads PD2 may be connected to a jig or a probe in an inspection process, or may be connected to a circuit board for inspection. The circuit board for inspection may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0094] The first distribution circuit 710 distributes the data voltage applied through the first pad part PDA1 to the plurality of data lines DL. For example, the first distribution circuit 710 may distribute the data voltage applied through one first pad PD1 of the first pad part PDA1 to P (P is a positive integer of 2 or more) data lines DL, and as a result, the number of the plurality of first pads PD1 may be reduced. The first distribution circuit 710 may be located at a third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 may be located at one side of the display area DAA in the second direction DR2. The first distribution circuit 710 may be located at a lower side of the display area DAA.

[0095] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the emission driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 may be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 may be located at a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 may be located at the other side of the display area DAA in the second direction DR2. The second distribution circuit 720 may be located at an upper side of the display area DAA.

[0096] Figure 5 It is shown Figure 4 An example layout diagram of the display area, Fig.10 is an example diagram showing color difference values ​​according to azimuth angles. To simplify the description, Figure 5 A first light emitting unit EA1 of a first sub-pixel SP1, a second light emitting unit EA2 of a second sub-pixel SP2, a third light emitting unit EA3 of a third sub-pixel SP3, a first lens LNS1, a second lens LNS2, and a third lens LNS3 are shown.

[0097] Reference Figure 5 Each of the first light emitting unit EA1, the second light emitting unit EA2 and the third light emitting unit EA3 may be formed by a pixel defining layer PDL (see Figure 7 ) limited area.

[0098] The length of the first light emitting cell EA1 in the first direction DR1 may be smaller than the length of the second light emitting cell EA2 in the first direction DR1 and smaller than the length of the third light emitting cell EA3 in the first direction DR1. The length of the second light emitting cell EA2 in the first direction DR1 and the length of the third light emitting cell EA3 in the first direction DR1 may be substantially the same.

[0099] The length of the first light emitting cell EA1 in the second direction DR2 may be greater than that of the second light emitting cell EA2 and greater than that of the third light emitting cell EA3 in the second direction DR2. The length of the second light emitting cell EA2 in the second direction DR2 may be less than that of the third light emitting cell EA3 in the second direction DR2.

[0100] In each of the plurality of pixels PX, the first light emitting cell EA1 and the second light emitting cell EA2 may be adjacent to each other in the first direction DR1. Further, the first light emitting cell EA1 and the third light emitting cell EA3 may be adjacent to each other in the first direction DR1. Further, the second light emitting cell EA2 and the third light emitting cell EA3 may be adjacent to each other in the second direction DR2. The area of ​​the first light emitting cell EA1, the area of ​​the second light emitting cell EA2, and the area of ​​the third light emitting cell EA3 may be different.

[0101] The first light emitting unit EA1 may have a rectangular shape in a plan view having short sides in the first direction DR1 and long sides in the second direction DR2. The second light emitting unit EA2 may have a rectangular shape in a plan view having long sides in the first direction DR1 and short sides in the second direction DR2. The third light emitting unit EA3 may have a rectangular shape in a plan view having long sides in the first direction DR1 and short sides in the second direction DR2.

[0102] The first light emitting unit EA1 may emit a first light, the second light emitting unit EA2 may emit a second light, and the third light emitting unit EA3 may emit a third light. Here, the first light may be light in a blue band, the second light may be light in a green band, and the third light may be light in a red band. For example, the blue band may be a band of light having a main peak wavelength in the range of about 370 nm to about 460 nm, the green band may be a band of light having a main peak wavelength in the range of about 480 nm to about 560 nm, and the red band may be a band of light having a main peak wavelength in the range of about 600 nm to about 750 nm.

[0103] The first lens LNS1 may overlap the first light emitting unit EA1 in the third direction DR3. The second lens LNS2 may overlap the second light emitting unit EA2 in the third direction DR3. The third lens LNS3 may overlap the third light emitting unit EA3 in the third direction DR3.

[0104] The first lens LNS1 includes a first sub-lens LNS11 and a second sub-lens LNS12. The first sub-lens LNS11 may overlap with a first portion of the first light emitting unit EA1 in the third direction DR3. The second sub-lens LNS12 may overlap with a second portion of the first light emitting unit EA1 in the third direction DR3. The area of ​​the first portion of the first light emitting unit EA1 may be different from the area of ​​the second portion of the first light emitting unit EA1. For example, the area of ​​the first portion of the first light emitting unit EA1 may be smaller than the area of ​​the second portion of the first light emitting unit EA1.

[0105] The length of the second sub-lens LNS12 in the first direction DR1 may be less than the length of the second sub-lens LNS12 in the second direction DR2. The length of the first sub-lens LNS11 in the first direction DR1 may be substantially the same as the length of the first sub-lens LNS11 in the second direction DR2, but the present disclosure is not limited thereto. For example, in one or more embodiments, the length of the first sub-lens LNS11 in the first direction DR1 may be less than the length of the first sub-lens LNS11 in the second direction DR2. In addition, the length of the first sub-lens LNS11 in the second direction DR2 may be less than the length of the second sub-lens LNS12 in the second direction DR2. The length of the first sub-lens LNS11 in the first direction DR1 may be substantially equal to the length of the second sub-lens LNS12 in the first direction DR1.

[0106] Among the first lights emitted from the first light emitting unit EA1, the first lights emitted in the lateral direction of the display device 10 may be refracted toward the front surface of the display device 10 by the first sub-lens LNS11 and the second sub-lens LNS12 of the first lens LNS1. Therefore, the ratio of the first lights emitted to the front surface of the display device 10 may be increased.

[0107] The length of the second lens LNS2 in the first direction DR1 may be greater than its length in the second direction DR2. The length of the second lens LNS2 in the first direction DR1 may be greater than each of the length of the first sub-lens LNS11 in the first direction DR1 and the length of the second sub-lens LNS12 in the first direction DR1. The length of the second lens LNS2 in the second direction DR2 may be substantially the same as the length of the first sub-lens LNS11 in the second direction DR2. The length of the second lens LNS2 in the second direction DR2 may be less than the length of the second sub-lens LNS12 in the second direction DR2.

[0108] Among the second lights emitted from the second light emitting unit EA2, the second lights emitted in the lateral direction of the display device 10 may be refracted by the second lens LNS2 toward the front surface of the display device 10. Therefore, the ratio of the second lights emitted to the front surface of the display device 10 may be increased.

[0109] The length of the third lens LNS3 in the first direction DR1 may be greater than its length in the second direction DR2. The length of the third lens LNS3 in the first direction DR1 may be greater than each of the length of the first sub-lens LNS11 in the first direction DR1 and the length of the second sub-lens LNS12 in the first direction DR1. The length of the third lens LNS3 in the first direction DR1 may be substantially the same as the length of the second lens LNS2 in the first direction DR1. The length of the third lens LNS3 in the second direction DR2 may be greater than the length of the first sub-lens LNS11 in the second direction DR2. The length of the third lens LNS3 in the second direction DR2 may be substantially the same as the length of the second sub-lens LNS12 in the second direction DR2. The length of the third lens LNS3 in the second direction DR2 may be greater than the length of the second lens LNS2 in the second direction DR2.

[0110] Among the third lights emitted from the third light emitting unit EA3, the third lights emitted in the lateral direction of the display device 10 may be refracted toward the front surface of the display device 10 by the third lens LNS3. Therefore, the ratio of the third lights emitted to the front surface of the display device 10 may be increased.

[0111] At the same time, the length of the first light emitting unit EA1 in the second direction DR2 may be greater than the sum of the length of the second light emitting unit EA2 in the second direction DR2 and the length of the third light emitting unit EA3 in the second direction DR2. In this case, if there is only one lens overlapping the first light emitting unit EA1, the length of the lens in the second direction DR2 may be relatively very large compared to the length of the lens in the first direction DR1. As a result, the ratio of the first light emitted in the second direction DR2 without being refracted by the lens to the first light emitted from the first light emitting unit EA1 may increase compared to the ratio of the first light emitted in the first direction DR1 without being refracted by the lens to the first light emitted from the first light emitting unit EA1. Therefore, a difference may occur between the color difference in the first direction DR1 and the color difference in the second direction DR2. Therefore, the color uniformity of the light emitted from the display device 10 may be reduced according to the azimuth.

[0112] like Figure 5As shown in , because the first light emitting unit EA1 overlaps with the first sub-lens LNS11 and the second sub-lens LNS12, each of the length of the first sub-lens LNS11 in the second direction DR2 and the length of the second sub-lens LNS12 in the second direction DR2 can be smaller than the length of the first light emitting unit EA1 in the second direction DR2. That is, compared with the case where the first light emitting unit EA1 overlaps with one lens, in the case where the first light emitting unit EA1 overlaps with the first sub-lens LNS11 and the second sub-lens LNS12, the length of the first sub-lens LNS11 in the second direction DR2 can be smaller than its length in the first direction DR1, and the length of the second sub-lens LNS12 in the second direction DR2 can be smaller than its length in the first direction DR1. Therefore, the difference between the ratio of the first light emitted in the second direction DR2 without being refracted by the lens to the first light emitted from the first light emitting unit EA1 and the ratio of the first light emitted in the first direction DR1 without being refracted by the lens to the first light emitted from the first light emitting unit EA1 can be reduced.

[0113] For example, Fig.10 2 shows the color difference of the display device 10 measured at azimuth angles of 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, and 315 degrees. Fig.10 As shown in , the difference between the light color differences of the display device 10 can be measured to be about 0.003 or less regardless of the azimuth angle. That is, the light color difference of the display device 10 can be measured uniformly. Therefore, the reduction in the color uniformity of the light emitted from the display device 10 according to the azimuth angle can be reduced, prevented or minimized.

[0114] In addition, as used herein, the gap between the first sub-lens LNS11 and the second sub-lens LNS12 may be the minimum distance between the first sub-lens LNS11 and the second sub-lens LNS12 in the second direction DR2. The gap between the second lens LNS2 and the third lens LNS3 may be the minimum distance between the second lens LNS2 and the third lens LNS3 in the second direction DR2. The gap between the first sub-lens LNS11 and the second sub-lens LNS12 may be smaller than the gap between the second lens LNS2 and the third lens LNS3. That is, by reducing or minimizing the gap between the first sub-lens LNS11 and the second sub-lens LNS12, the area of ​​the first light emitting unit EA1 may be mostly overlapped with the first sub-lens LNS11 and the second sub-lens LNS12. Therefore, the emission of the first light emitted from the first light emitting unit EA1 without passing through the first sub-lens LNS11 and the second sub-lens LNS12 may be reduced or minimized.

[0115] A virtual line passing through a center C11 of the first sub-lens LNS11 and a center C2 of the second lens LNS2 in a plan view is defined as a first virtual line VL1. In addition, a virtual line passing through a center C12 of the second sub-lens LNS12 and a center C3 of the third lens LNS3 in a plan view is defined as a second virtual line VL2. In addition, a virtual line passing through a center CG1 of a gap between the first sub-lens LNS11 and the second sub-lens LNS12 and a center CG2 of a gap between the second lens LNS2 and the third lens LNS3 in a plan view is defined as a third virtual line VL3.

[0116] The first virtual line VL1, the second virtual line VL2, and the third virtual line VL3 may be parallel to each other. For example, the first virtual line VL1, the second virtual line VL2, and the third virtual line VL3 may extend in the first direction DR1. Therefore, the first sub-lens LNS11 and the second lens LNS2 may be aligned in the first direction DR1, and the second sub-lens LNS12 and the third lens LNS3 may be aligned in the first direction DR1.

[0117] A virtual line passing through the center C11 of the first sub-lens LNS11 and the center C12 of the second sub-lens LNS12 in the plan view is defined as a fourth virtual line VL4. In addition, a virtual line passing through the center C2 of the second lens LNS2 and the center C3 of the third lens LNS3 in the plan view is defined as a fifth virtual line VL5. In addition, a virtual line passing through the center CG3 of the gap between the first sub-lens LNS11 and the second lens LNS2 and the center CG4 of the gap between the second sub-lens LNS12 and the third lens LNS3 in the plan view is defined as a sixth virtual line VL6. The gap between the first sub-lens LNS11 and the second lens LNS2 refers to the minimum distance between the first sub-lens LNS11 and the second lens LNS2 in the first direction DR1. The gap between the second sub-lens LNS12 and the third lens LNS3 refers to the minimum distance between the second sub-lens LNS12 and the third lens LNS3 in the first direction DR1.

[0118] The fourth virtual line VL4, the fifth virtual line VL5, and the sixth virtual line VL6 may be parallel to each other. For example, the fourth virtual line VL4, the fifth virtual line VL5, and the sixth virtual line VL6 may extend in the second direction DR2. Therefore, the first sub-lens LNS11 and the second sub-lens LNS12 may be aligned in the second direction DR2, and the second lens LNS2 and the third lens LNS3 may be aligned in the second direction DR2.

[0119] although Figure 5 It is illustrated that the first sub-lens LNS11 , the second sub-lens LNS12 , the second lens LNS2 , and the third lens LNS3 have an elliptical shape in a plan view, but the present disclosure is not limited thereto.

[0120] Figure 6 It is shown along Figure 5 A cross-sectional view of an example of a display panel taken along line AA′. Figure 7 It is shown in detail Figure 6 An enlarged cross-sectional view of area A.

[0121] Reference Figure 6 and Figure 7 , the display panel 100 includes a semiconductor backplane SBP, a light emitting element backplane EBP, a display element layer EML, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL and a polarizing plate POL.

[0122] The semiconductor backplane SBP includes a semiconductor substrate SSUB, a plurality of pixel transistors PTR, a plurality of semiconductor insulating layers covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively. The plurality of pixel transistors PTR may be reference Figure 3 The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are described.

[0123] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate or a silicon germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of well regions WA may be located on the top surface of the semiconductor substrate SSUB. A plurality of well regions WA may be regions doped with a second type of impurity. The second type of impurity may be different from the aforementioned first type of impurity. For example, when the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. Alternatively, when the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0124] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode thereof, and a channel region CH between the source region SA and the drain region DA.

[0125] The lower insulating layer BINS may be located between the gate electrode GE and the well area WA. The side insulating layer SINS may be located on a side surface of the gate electrode GE. The side insulating layer SINS may be located on the lower insulating layer BINS.

[0126] Each of the source region SA and the drain region DA may be a region doped with first type impurities. The gate electrode GE of the pixel transistor PTR may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be located on one side of the gate electrode GE, and the drain region DA may be located on the other side of the gate electrode GE.

[0127] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 between the channel region CH and the source region SA and a second low-concentration impurity region LDD2 between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having a lower impurity concentration than the source region SA due to the lower insulating layer BINS. The second low-concentration impurity region LDD2 may be a region having a lower impurity concentration than the drain region DA due to the lower insulating layer BINS. The distance between the source region SA and the drain region DA may be increased due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH of each of the pixel transistors PTR may be increased, so that punch-through and hot carrier phenomena that may be caused by a short channel may be reduced or prevented.

[0128] The first semiconductor-insulating layer SINS1 may be located on the semiconductor substrate SSUB. The first semiconductor-insulating layer SINS1 may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-type inorganic layer is formed, but the present disclosure is not limited thereto.

[0129] The second semiconductor-insulating layer SINS2 may be located on the first semiconductor-insulating layer SINS1. The second semiconductor-insulating layer SINS2 may be made of silicon oxide (SiO x )-type inorganic layer is formed, but the present disclosure is not limited thereto.

[0130] A plurality of contact terminals CTE may be located on the second semiconductor-insulating layer SINS2. Each of the plurality of contact terminals CTE may be connected to any one of the gate electrode GE, the source area SA, and the drain area DA of each of the pixel transistors PTR through a hole penetrating the first semiconductor-insulating layer SINS1 and the second semiconductor-insulating layer SINS2. The plurality of contact terminals CTE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one or more of them.

[0131] The third semiconductor-insulating layer SINS3 may be located on a side surface of each of the plurality of contact terminals CTE. The top surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor-insulating layer SINS3. The third semiconductor-insulating layer SINS3 may be made of silicon oxide (SiO x )-type inorganic layer is formed, but the present disclosure is not limited thereto.

[0132] The semiconductor substrate SSUB may be replaced with a glass substrate or a polymer resin substrate (such as polyimide). In this case, the thin film transistor may be located on the glass substrate or the polymer resin substrate. The glass substrate may be a rigid substrate that does not bend, and the polymer resin substrate may be a flexible substrate that can be bent or folded.

[0133] The light emitting element backplane EBP includes a first conductive layer ML1, a second conductive layer ML2, a third conductive layer ML3, a fourth conductive layer ML4, a fifth conductive layer ML5, a sixth conductive layer ML6, a seventh conductive layer ML7 and an eighth conductive layer ML8 and a plurality of vias VA1, VA2, VA3, VA4, VA5, VA6, VA7, VA8 and VA9. In addition, the light emitting element backplane EBP includes a plurality of interlayer insulating layers INS1, INS2, INS3, INS4, INS5, INS6, INS7, INS8 and INS9 located between corresponding conductive layers among the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8.

[0134] The first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8 are used to connect the plurality of contact terminals CTE exposed from the semiconductor backplane SBP, thereby realizing Figure 3 The circuit of the first sub-pixel SP1 shown in FIG. That is, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are formed only on the semiconductor backplane SBP, and the connection between the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 and the first capacitor CP1 and the second capacitor CP2 is realized through the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5 and the first electrode of the light emitting element LE is also completed through the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8.

[0135] The first interlayer insulating layer INS1 may be located on the semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first interlayer insulating layer INS1 to be connected to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first conductive layers ML1 may be located on the first interlayer insulating layer INS1 and may be connected to the first vias VA1.

[0136] The second interlayer insulating layer INS2 may be located on the first interlayer insulating layer INS1 and the first conductive layer ML1. Each of the second via holes VA2 may penetrate the second interlayer insulating layer INS2 and may be connected to the exposed first conductive layer ML1. Each of the second conductive layers ML2 may be located on the second interlayer insulating layer INS2 and may be connected to the second via holes VA2.

[0137] The third interlayer insulating layer INS3 may be located on the second interlayer insulating layer INS2 and the second conductive layer ML2. Each of the third via holes VA3 may penetrate the third interlayer insulating layer INS3 and may be connected to the exposed second conductive layer ML2. Each of the third conductive layers ML3 may be located on the third interlayer insulating layer INS3 and may be connected to the third via holes VA3.

[0138] The fourth interlayer insulating layer INS4 may be located on the third interlayer insulating layer INS3 and the third conductive layer ML3. Each of the fourth via holes VA4 may penetrate the fourth interlayer insulating layer INS4 and may be connected to the exposed third conductive layer ML3. Each of the fourth conductive layers ML4 may be located on the fourth interlayer insulating layer INS4 and may be connected to the fourth via holes VA4.

[0139] The fifth interlayer insulating layer INS5 may be located on the fourth interlayer insulating layer INS4 and the fourth conductive layer ML4. Each of the fifth via holes VA5 may penetrate the fifth interlayer insulating layer INS5 and may be connected to the exposed fourth conductive layer ML4. Each of the fifth conductive layers ML5 may be located on the fifth interlayer insulating layer INS5 and may be connected to the fifth via holes VA5.

[0140] The sixth interlayer insulating layer INS6 may be located on the fifth interlayer insulating layer INS5 and the fifth conductive layer ML5. Each of the sixth vias VA6 may penetrate the sixth interlayer insulating layer INS6 and may be connected to the exposed fifth conductive layer ML5. Each of the sixth conductive layers ML6 may be located on the sixth interlayer insulating layer INS6 and may be connected to the sixth vias VA6.

[0141] The seventh interlayer insulating layer INS7 may be located on the sixth interlayer insulating layer INS6 and the sixth conductive layer ML6. Each of the seventh via holes VA7 may penetrate the seventh interlayer insulating layer INS7 and may be connected to the exposed sixth conductive layer ML6. Each of the seventh conductive layers ML7 may be located on the seventh interlayer insulating layer INS7 and may be connected to the seventh via hole VA7.

[0142] The eighth interlayer insulating layer INS8 may be located on the seventh interlayer insulating layer INS7 and the seventh conductive layer ML7. Each of the eighth vias VA8 may penetrate the eighth interlayer insulating layer INS8 and may be connected to the exposed seventh conductive layer ML7. Each of the eighth conductive layers ML8 may be located on the eighth interlayer insulating layer INS8 and may be connected to the eighth vias VA8.

[0143] The first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7 and the eighth via VA8 can be formed of substantially the same material. The first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7 and the eighth via VA8 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy including any one or more thereof. The first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7 and the eighth via VA8 may be made of substantially the same material. The first interlayer insulating layer INS1, the second interlayer insulating layer INS2, the third interlayer insulating layer INS3, the fourth interlayer insulating layer INS4, the fifth interlayer insulating layer INS5, the sixth interlayer insulating layer INS6, the seventh interlayer insulating layer INS7, and the eighth interlayer insulating layer INS8 may be made of silicon oxide (SiO x )-type inorganic layer is formed, but the present disclosure is not limited thereto.

[0144] The thickness of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5 and the sixth conductive layer ML6 may be respectively greater than the thickness of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5 and the sixth via VA6. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5 and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5 and the thickness of the sixth conductive layer ML6 may be substantially the same. For example, the thickness of the first conductive layer ML1 may be approximately 1360Å. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5 and the sixth conductive layer ML6 may be approximately 1440Å. The thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 may be approximately 1150Å.

[0145] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 may be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be approximately 9000Å. The thickness of each of the seventh via VA7 and the eighth via VA8 may be approximately 6000Å.

[0146] The ninth interlayer insulating layer INS9 may be located on the eighth interlayer insulating layer INS8 and the eighth conductive layer ML8. The ninth interlayer insulating layer INS9 may include silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ) or a silicon (Si)-based inorganic layer of silicon carbonitride (SiCN), but the present disclosure is not limited thereto.

[0147] Each of the ninth via holes VA9 may penetrate the ninth interlayer insulating layer INS9 and may be connected to the exposed eighth conductive layer ML8. The ninth via hole VA9 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one or more of them. The thickness of the ninth via hole VA9 may be approximately 16500Å.

[0148] The display element layer EML may be located on the light emitting element backplane EBP. The display element layer EML may include a reflective electrode layer RL, a tenth interlayer insulating layer INS10, light emitting elements LE, a pixel defining layer PDL, and a plurality of trenches TRC. Each of the light emitting elements LE includes a first electrode AND, a light emitting stack IL, and a second electrode CAT.

[0149] The reflective electrode layer RL may be located on the ninth interlayer insulating layer INS9. The reflective electrode layer RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. Figure 6 As shown in , the reflective electrode layer RL may include first, second, third, and fourth reflective electrodes RL1, RL2, RL3, and RL4, and a step layer STPL.

[0150] Each of the first reflective electrodes RL1 may be located on the ninth interlayer insulating layer INS9 and may be connected to the ninth via hole VA9. The first reflective electrode RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one or more of them. The first reflective electrode RL1 may include titanium nitride (TiN).

[0151] Each of the second reflective electrodes RL2 may be located on the first reflective electrode RL1. The second reflective electrode RL2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one or more of them. For example, the second reflective electrode RL2 may include aluminum.

[0152] In the first sub-pixel SP1, the step layer STPL may be located on the second reflective electrode RL2. The step layer STPL may be omitted from each of the second sub-pixel SP2 and the third sub-pixel SP3. In order to advantageously reflect the light of the first color emitted from the first stacked layer IL1 of the first sub-pixel SP1, the thickness of the step layer STPL may be set in consideration of the wavelength of the light of the first color and the distance from the second electrode CAT to the fourth reflective electrode RL4. The step layer STPL may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-type inorganic layer is formed, but the present disclosure is not limited thereto. The thickness of the step layer STPL may be about 400 Å.

[0153] In the first sub-pixel SP1, the third reflective electrode RL3 may be located on the second reflective electrode RL2 and the step layer STPL. In the second sub-pixel SP2 and the third sub-pixel SP3, the third reflective electrode RL3 may be located on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one or more of them. For example, the third reflective electrode RL3 may include titanium nitride (TiN).

[0154] At least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 may be omitted.

[0155] The fourth reflective electrode RL4 may be located on the third reflective electrode RL3, respectively. The fourth reflective electrode RL4 may reflect light from the first stack layer IL1, the second stack layer IL2, and the third stack layer IL3. The fourth reflective electrode RL4 may include a metal having a relatively high reflectivity to reflect light. The fourth reflective electrode RL4 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one or more of them. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0156] The tenth interlayer insulating layer INS10 may be located on the ninth interlayer insulating layer INS9 and the fourth reflective electrode RL4. The tenth interlayer insulating layer INS10 may include silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ) or a silicon (Si)-based inorganic layer of silicon carbonitride (SiCN), but the present disclosure is not limited thereto.

[0157] Each of the tenth via holes VA10 may be connected to the reflective electrode layer RL exposed through the tenth interlayer insulating layer INS10. The tenth via hole VA10 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one or more thereof. Due to the presence of the step layer STPL, the thickness of the tenth via hole VA10 in the first sub-pixel SP1 may be less than the thickness of the tenth via hole VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the thickness of the tenth via hole VA10 in the first sub-pixel SP1 may be about 800Å, and the thickness of the tenth via hole VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3 may be about 1200Å.

[0158] In at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, in order to adjust the resonance distance of the light emitted from the light emitting element LE, the step layer STPL may be omitted from at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Optionally, the thickness of the step layer STPL may be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Due to the presence or thickness difference of the step layer STPL, the distance between the second electrode CAT and the reflective electrode layer RL may be different between at least two of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. That is, in order to adjust the distance from the reflective electrode layer RL to the second electrode CAT according to the main wavelength of the light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence or absence of the step layer STPL may be determined, or the thickness of the step layer STPL may be set. Figure 6 It is shown that the distance between the first electrode AND and the reflective electrode layer RL in the third sub-pixel SP3 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1. In addition, the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1, but the present disclosure is not limited thereto.

[0159] Each of the tenth via holes VA10 may penetrate the tenth interlayer insulating layer INS10 in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, and may be connected to the exposed reflective electrode layer RL. The tenth via hole VA10 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one or more of them. The thickness of the tenth via hole VA10 in the first sub-pixel SP1 may be less than the thickness of the tenth via hole VA10 in the third sub-pixel SP3.

[0160] The first electrode AND of each of the light emitting elements LE may be located on the tenth interlayer insulating layer INS10 and may be connected to the tenth via VA10. The first electrode AND of each of the light emitting elements LE may be connected to the drain area DA or the source area SA of the pixel transistor PTR through the tenth via VA10, the first reflective electrode RL1, the second reflective electrode RL2, the third reflective electrode RL3, and the fourth reflective electrode RL4, the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7, the eighth via VA8, and the ninth via VA9, the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7, and the eighth conductive layer ML8, and the contact terminal CTE. The first electrode AND of each of the light emitting elements LE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one or more of them. For example, the first electrode AND of each of the light emitting elements LE may be titanium nitride (TiN).

[0161] The pixel defining layer PDL may be located on a portion of the first electrode AND of each of the light emitting elements LE. The pixel defining layer PDL may cover an edge of the first electrode AND of each of the light emitting elements LE. The pixel defining layer PDL may be used to divide the first light emitting cell EA1, the second light emitting cell EA2, and the third light emitting cell EA3.

[0162] The first light emitting cell EA1 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second light emitting cell EA2 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third light emitting cell EA3 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0163] The pixel defining layer PDL may include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3. The first pixel defining layer PDL1 may be located at the edge of the first electrode AND of each of the light emitting elements LE. The second pixel defining layer PDL2 may be located on the first pixel defining layer PDL1. The third pixel defining layer PDL3 may be located on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be made of silicon oxide (SiO x ) type inorganic layer is formed, but the present disclosure is not limited thereto. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may each have a thickness of about 500Å.

[0164] When the first pixel defining layer PDL1, the second pixel defining layer PDL2 and the third pixel defining layer PDL3 are formed into one pixel defining layer, the height of one pixel defining layer increases so that the first encapsulation inorganic layer TFE1 may be cut off due to step coverage. Step coverage refers to the ratio of the degree of coating of the film on the inclined portion to the degree of coating of the film on the flat portion. The lower the step coverage, the more likely the film will be cut off at the inclined portion.

[0165] Therefore, in order to reduce or prevent the possibility of the first encapsulation inorganic layer TFE1 being cut off due to the step coverage, the first pixel defining layer PDL1, the second pixel defining layer PDL2 and the third pixel defining layer PDL3 may have a cross-sectional structure with a step portion. For example, the width of the first pixel defining layer PDL1 may be greater than the width of the second pixel defining layer PDL2 and the width of the third pixel defining layer PDL3. The width of the second pixel defining layer PDL2 may be greater than the width of the third pixel defining layer PDL3. The width of the first pixel defining layer PDL1 refers to the horizontal length of the first pixel defining layer PDL1 defined in the first direction DR1 and the second direction DR2.

[0166] Each of the plurality of trenches TRC may penetrate the first pixel defining layer PDL1 , the second pixel defining layer PDL2 , and the third pixel defining layer PDL3 . The tenth interlayer insulating layer INS10 may be partially recessed at each of the plurality of trenches TRC.

[0167] At least one trench TRC may be located between adjacent sub-pixels SP1, SP2, and SP3. Figure 7 It is shown that two trenches TRC are located between adjacent sub-pixels SP1 , SP2 , and SP3 , but the present disclosure is not limited thereto.

[0168] The light emitting stack IL may include a plurality of intermediate layers. Figure 7 The light emitting stack IL is shown to have a three-series structure including a first stack layer IL1, a second stack layer IL2, and a third stack layer IL3, but the present disclosure is not limited thereto. For example, the light emitting stack IL may have a two-series structure including two intermediate layers.

[0169] In the three-series structure, the light emitting stack IL may have a series structure including a plurality of stack layers IL1, IL2, and IL3 that emit different corresponding lights. For example, the light emitting stack IL may include a first stack layer IL1 that emits light of a first color, a second stack layer IL2 that emits light of a third color, and a third stack layer IL3 that emits light of a second color. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 may be sequentially stacked.

[0170] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0171] A first charge generation layer for supplying charges to the second stack layer IL2 and for supplying electrons to the first stack layer IL1 may be located between the first stack layer IL1 and the second stack layer IL2. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first stack layer IL1 and a P-type charge generation layer for supplying holes to the second stack layer IL2. The N-type charge generation layer may include a dopant of a metal material.

[0172] The second charge generation layer for supplying charges to the third stack layer IL3 and for supplying electrons to the second stack layer IL2 may be located between the second stack layer IL2 and the third stack layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second stack layer IL2 and a P-type charge generation layer for supplying holes to the third stack layer IL3.

[0173] The first stacked layer IL1 may be located on the first electrode AND and the pixel defining layer PDL, and may be located on the bottom surface of each groove TRC. Due to the groove TRC, the first stacked layer IL1 may be cut off between adjacent sub-pixels SP1, SP2, and SP3. The second stacked layer IL2 may be located on the first stacked layer IL1. Due to the groove TRC, the second stacked layer IL2 may be cut off between adjacent sub-pixels SP1, SP2, and SP3. The cavity ESS or empty space may be located between the first stacked layer IL1 and the second stacked layer IL2 in the groove TRC. The third stacked layer IL3 may be located on the second stacked layer IL2. The third stacked layer IL3 is not cut off by the groove TRC, and may be positioned in each of the grooves TRC to cover the second stacked layer IL2. That is, in the three-series structure, each of the plurality of grooves TRC may be a structure for cutting off the first stacked layer IL1 to the second stacked layer IL2, the first charge generation layer, and the second charge generation layer of the display element layer EML between the sub-pixels SP1, SP2, and SP3 adjacent to each other. In addition, in the two-tandem structure, each of the trenches TRC may be a structure for cutting off the charge generation layer located between the lower intermediate layer and the upper intermediate layer and the lower intermediate layer.

[0174] In order to stably cut off the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2 and SP3, the height of each of the plurality of grooves TRC may be greater than the height of the pixel defining layer PDL. The height of each of the plurality of grooves TRC refers to the length of each of the plurality of grooves TRC in the third direction DR3. The height of the pixel defining layer PDL refers to the length of the pixel defining layer PDL in the third direction DR3. In order to cut off the first stacked layer IL1, the second stacked layer IL2 and the third stacked layer IL3 of the display element layer EML between adjacent sub-pixels SP1, SP2 and SP3, another structure may exist instead of the groove TRC. For example, an inverted tapered partition wall may be located on the pixel defining layer PDL instead of the groove TRC.

[0175] The number of stacked layers IL1, IL2, and IL3 emitting different corresponding lights is not limited to Figure 7. For example, the light emitting stack IL may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first stacked layer IL1, and the other may include a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one intermediate layer and for supplying charges to the other intermediate layer may be located between the two intermediate layers.

[0176] in addition, Figure 7 It is shown that the first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 are all located in the first light emitting cell EA1, the second light emitting cell EA2, and the third light emitting cell EA3, but the present disclosure is not limited thereto. For example, the first stacked layer IL1 may be located in the first light emitting cell EA1, and may be omitted from the second light emitting cell EA2 and the third light emitting cell EA3. In addition, the second stacked layer IL2 may be located in the second light emitting cell EA2, and may be omitted from the first light emitting cell EA1 and the third light emitting cell EA3. In addition, the third stacked layer IL3 may be located in the third light emitting cell EA3, and may be omitted from the first light emitting cell EA1 and the second light emitting cell EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0177] The second electrode CAT may be located on the third stacked layer IL3. The second electrode CAT may be located on the third stacked layer IL3 on each of the plurality of trenches TRC. The second electrode CAT may be formed of a transparent conductive material (TCO) such as ITO or IZO that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode CAT is formed of the semi-transmissive conductive material, light emission efficiency may be improved in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 due to a microcavity effect.

[0178] The encapsulation layer TFE may be located on the display element layer EML. The encapsulation layer TFE may include at least one inorganic layer TFE1 and TFE2 to reduce or prevent oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1 and a second encapsulation inorganic layer TFE2.

[0179] The first encapsulation inorganic layer TFE1 may be located on the second electrode CAT, and the second encapsulation inorganic layer TFE2 may be located on the first encapsulation inorganic layer TFE1. The first encapsulation inorganic layer TFE1 may be formed in which titanium oxide (TiO x ) layer and aluminum oxide (AlO x) layers are alternately stacked. The first encapsulating inorganic layer TFE1 may be formed by a chemical vapor deposition (CVD) process. The second encapsulating inorganic layer TFE2 may be made of aluminum oxide (AlO x ), but the present disclosure is not limited thereto. The second encapsulation inorganic layer TFE2 may be formed by an atomic layer deposition (ALD) process.

[0180] The organic layer APL may be a layer for increasing the interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. The organic layer APL may be an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0181] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS1 (eg, LNS11 and LNS12), LNS2, and LNS3, and a filling layer FIL. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be located on the organic layer APL.

[0182] The first color filter CF1 may overlap the first light emitting unit EA1 of the first sub-pixel SP1. The first color filter CF1 may transmit light of a first color (e.g., light of a blue wavelength band). The blue wavelength band may be about 370 nm to about 460 nm. Therefore, the first color filter CF1 may transmit light of a first color among the light emitted from the first light emitting unit EA1.

[0183] The second color filter CF2 may overlap the second light emitting unit EA2 of the second sub-pixel SP2. The second color filter CF2 may transmit light of a second color (e.g., light of a green wavelength band). The green wavelength band may be about 480 nm to about 560 nm. Therefore, the second color filter CF2 may transmit light of a second color among the light emitted from the second light emitting unit EA2.

[0184] The third color filter CF3 may overlap the third light emitting unit EA3 of the third sub-pixel SP3. The third color filter CF3 may transmit light of a third color (e.g., light of a red wavelength band). The red wavelength band may be about 600 nm to about 750 nm. Therefore, the third color filter CF3 may transmit light of a third color among the light emitted from the third light emitting unit EA3.

[0185] The plurality of lenses LNS1, LNS2, and LNS3 may be located on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. For example, the first sub-lens LNS11 and the second sub-lens LNS12 of the first lens LNS1 may be located on the first color filter CF1, the second lens LNS2 may be located on the second color filter CF2, and the third lens LNS3 may be located on the third color filter CF3. Each of the plurality of lenses LNS1, LNS2, and LNS3 may have a cross-sectional shape that is convex in an upward direction.

[0186] Among the plurality of lenses LNS1, LNS2, and LNS3, adjacent lenses may be connected to each other. For example, each pair of the first sub-lens LNS11 and the second sub-lens LNS12, the first sub-lens LNS11 and the second lens LNS2, and the second sub-lens LNS12 and the third lens LNS3 may be connected to each other via a connecting portion LNC. In one or more embodiments, each pair of the second lens LNS2 and the third lens LNS3, the first sub-lens LNS11 and the third lens LNS3, and the second sub-lens LNS12 and the second lens LNS2 may also be connected to each other via a connecting portion LNC.

[0187] Each of the connection portions LNC may be located on any one of the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the connection portions LNC may be in contact with any one of the first color filter CF1, the second color filter CF2, and the third color filter CF3. The thickness of the connection portion LNC may be less than each of the thickness of the first sub-lens LNS11, the thickness of the second sub-lens LNS12, the thickness of the second lens LNS2, and the thickness of the third lens LNS3.

[0188] Alternatively, the connection portion LNC may be omitted. In this case, the first sub-lens LNS11, the second sub-lens LNS12, the second lens LNS2, and the third lens LNS3 may be positioned to be spaced apart from each other.

[0189] The filling layer FIL may be located on the plurality of lenses LNS. The filling layer FIL may have a refractive index (e.g., a predetermined refractive index) such that light travels in a third direction DR3 at an interface between the filling layer FIL and the plurality of lenses LNS. Further, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0190] The cover layer CVL may be located on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it is used as a packaging substrate, and the filling layer FIL may be used to bond the cover layer CVL. When the cover layer CVL is a polymer resin, it may be directly coated onto the filling layer FIL.

[0191] The polarizing plate POL may be located on one surface of the cover layer CVL. The polarizing plate POL may be a structure for reducing or preventing visibility degradation caused by reflection of external light. The polarizing plate POL may include a linear polarizing plate and a phase delay film. For example, the phase delay film may be a λ / 4 plate (quarter wave plate), but the present disclosure is not limited thereto. However, when visibility degradation caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3, the polarizing plate POL may be omitted.

[0192] like Figure 6 and Figure 7 As shown in , by forming a light emitting element backplane EBP and a display element layer EML on a semiconductor substrate SSUB on which a plurality of transistors are formed, the size of a plurality of pixels PX can be greatly reduced, so that a display device 10 displaying a high-resolution image can be provided.

[0193] Figure 8 It is shown Figure 4 A layout diagram of an example of a first pad of a first pad portion. Fig. 9 It is shown along Figure 8 A cross-sectional view of an example of a display panel taken along line BB'.

[0194] Reference Figure 8 and Fig. 9 , the light emitting element backplane EBP also includes a pad conductive layer PML.

[0195] Each of the first pads PD1 includes a first subpad BPD and a second subpad IPD in which the pad conductive layer PML is divided by a tenth interlayer insulating layer INS10. Both the first subpad BPD and the second subpad IPD may be electrically connected to a pad or a bump of the circuit board 300 through a conductive adhesive member. In addition, the second subpad IPD may be connected to a jig or a probe in an inspection process, or may be connected to a circuit board for inspection via a conductive film.

[0196] The area of ​​the first subpad BPD may be greater than that of the second subpad IPD. The length of the first subpad BPD in the first direction DR1 may be substantially the same as that of the second subpad IPD in the first direction DR1. The length of the first subpad BPD in the second direction DR2 may be greater than that of the second subpad IPD in the second direction DR2.

[0197] The pad conductive layer PML may include a first subpad conductive layer SPML1 and a second subpad conductive layer SPML2. The first subpad conductive layer SPML1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one or more of them. The second subpad conductive layer SPML2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one or more of them. For example, the first subpad conductive layer SPML1 may be made of aluminum (Al) and may have a thickness of approximately 12000Å. In addition, the second subpad conductive layer SPML2 may be made of titanium nitride (TiN) and may have a thickness of approximately 600Å. The thickness of the pad conductive layer PML may be greater than the thickness of the reflective electrode layer RL.

[0198] A portion of the top surface of the second subpad conductive layer SPML2 corresponding to the first subpad BPD may be exposed without being covered by the tenth interlayer insulating layer INS10. A top surface of the second subpad conductive layer SPML2 corresponding to the second subpad IPD may be exposed without being covered by the tenth interlayer insulating layer INS10. The first subpad conductive layer SPML1 may be connected to the ninth via VA9 penetrating the ninth interlayer insulating layer INS9 to be connected to the eighth conductive layer ML8.

[0199] Fig.11 is a flowchart illustrating a method of manufacturing a display device according to one or more embodiments. Figures 12 to 23 is a cross-sectional view showing a method of manufacturing a display device according to one or more embodiments. Figures 11 to 23 A method of manufacturing a display device is described in detail.

[0200] like Fig.12 and Fig.13 As shown in FIG. 1 , a light emitting element backplane EBP is formed on a semiconductor substrate SSUB, and a display element layer EML (including a light emitting element LE) is formed on the light emitting element backplane EBP. Fig.11 Operation S110).

[0201] A first conductive layer ML1, a second conductive layer ML2, a third conductive layer ML3, a fourth conductive layer ML4, a fifth conductive layer ML5, a sixth conductive layer ML6, a seventh conductive layer ML7 and an eighth conductive layer ML8, a first via VA1, a second via VA2, a third via VA3, a fourth via VA4, a fifth via VA5, a sixth via VA6, a seventh via VA7, an eighth via VA8 and a ninth via VA9, as well as a first interlayer insulating layer INS1, a second interlayer insulating layer INS2, a third interlayer insulating layer INS3, a fourth interlayer insulating layer INS4, a fifth interlayer insulating layer INS5, a sixth interlayer insulating layer INS6, a seventh interlayer insulating layer INS7, an eighth interlayer insulating layer INS8 and a ninth interlayer insulating layer INS9 and a pad conductive layer PML of a light emitting element backplane EBP are formed on a semiconductor substrate SSUB.

[0202] For example, a first interlayer insulating layer INS1 is formed on a semiconductor substrate SSUB, and first vias VA1 penetrating the first interlayer insulating layer INS1 to be respectively connected to the contact terminals CTE of the semiconductor substrate SSUB are formed by a photolithography process. A first conductive layer ML1 connected to the first vias VA1 is formed on the first interlayer insulating layer INS1 by a photolithography process. Then, a second interlayer insulating layer INS2 is formed on the first conductive layer ML1, and second vias VA2 penetrating the second interlayer insulating layer INS2 to be respectively connected to the first conductive layer ML1 are formed by a photolithography process. A second conductive layer ML2 connected to the second vias VA2 is formed on the second interlayer insulating layer INS2 by a photolithography process. Subsequently, a third interlayer insulating layer INS3 is formed on the second conductive layer ML2, and third vias VA3 penetrating the third interlayer insulating layer INS3 to be respectively connected to the second conductive layer ML2 are formed by a photolithography process. A third conductive layer ML3 connected to the third vias VA3 is formed on the third interlayer insulating layer INS3 by a photolithography process. Thereafter, a fourth interlayer insulating layer INS4 is formed on the third conductive layer ML3, and fourth via holes VA4 penetrating the fourth interlayer insulating layer INS4 to be respectively connected to the third conductive layer ML3 are formed by a photolithography process. Fourth conductive layers ML4 respectively connected to the fourth via holes VA4 are formed on the fourth interlayer insulating layer INS4 by a photolithography process.

[0203] Then, a fifth interlayer insulating layer INS5 is formed on the fourth conductive layer ML4, and fifth vias VA5 penetrating the fifth interlayer insulating layer INS5 to be respectively connected to the fourth conductive layer ML4 are formed by a photolithography process. A fifth conductive layer ML5 connected to the fifth vias VA5 is formed on the fifth interlayer insulating layer INS5 by a photolithography process. Subsequently, a sixth interlayer insulating layer INS6 is formed on the fifth conductive layer ML5, and sixth vias VA6 penetrating the sixth interlayer insulating layer INS6 to be respectively connected to the fifth conductive layer ML5 are formed by a photolithography process. A sixth conductive layer ML6 connected to the sixth vias VA6 is formed on the sixth interlayer insulating layer INS6 by a photolithography process. Thereafter, a seventh interlayer insulating layer INS7 is formed on the sixth conductive layer ML6, and seventh vias VA7 penetrating the seventh interlayer insulating layer INS7 to be respectively connected to the sixth conductive layer ML6 are formed by a photolithography process. A seventh conductive layer ML7 connected to the seventh vias VA7 is formed on the seventh interlayer insulating layer INS7 by a photolithography process. Then, an eighth interlayer insulating layer INS8 is formed on the seventh conductive layer ML7, and eighth vias VA8 penetrating the eighth interlayer insulating layer INS8 to be respectively connected to the seventh conductive layer ML7 are formed by a photolithography process. An eighth conductive layer ML8 connected to the eighth vias VA8 are formed on the eighth interlayer insulating layer INS8 by a photolithography process. Subsequently, a ninth interlayer insulating layer INS9 is formed on the eighth conductive layer ML8, and ninth vias VA9 penetrating the ninth interlayer insulating layer INS9 to be respectively connected to the eighth conductive layer ML8 are formed on the ninth interlayer insulating layer INS9 by a photolithography process.

[0204] Then, on the first pad part PDA1 and the second pad part PDA2 (see Figure 4 ) in which a first sub-pad conductive layer SPML1 of the pad conductive layer PML connected to the ninth via hole VA9 is formed on the ninth interlayer insulating layer INS9, and a second sub-pad conductive layer SPML2 is formed on the first sub-pad conductive layer SPML1.

[0205] In addition, the reflective electrode layer RL of the display element layer EML, the tenth interlayer insulating layer INS10, the tenth via hole VA10, the light emitting element LE and the pixel defining layer PDL, and a plurality of trenches TRC are formed on the light emitting element backplane EBP.

[0206] For example, first reflective electrodes RL1 of the reflective electrode layer RL respectively connected to the ninth via holes VA9 are formed on the ninth interlayer insulating layer INS9, and second reflective electrodes RL2 of the reflective electrode layer RL are respectively formed on the first reflective electrodes RL1. Then, step layers STPL for setting the resonance distance are formed on some of the second reflective electrodes RL2 of the reflective electrode layer RL. Thereafter, third reflective electrodes RL3 of the reflective electrode layer RL are respectively formed on the step layers STPL located on some of the second reflective electrodes RL2 and the remaining second reflective electrodes RL2, and fourth reflective electrodes RL4 of the reflective electrode layer RL are respectively formed on the third reflective electrodes RL3.

[0207] Then, a tenth interlayer insulating layer INS10 covering the reflective electrode layer RL is formed, and tenth via holes VA10 penetrating the tenth interlayer insulating layer INS10 to be respectively connected to the fourth reflective electrodes RL4 are formed. In addition, the tenth interlayer insulating layer INS10 may be formed to cover the edge of the pad conductive layer PML. In addition, the tenth interlayer insulating layer INS10 may be formed on the top surface of the second subpad conductive layer SPML2 to separate the first subpad BPD and the second subpad IPD.

[0208] Then, the first electrodes AND of the light emitting element LE, which are respectively connected to the tenth via holes VA10, are formed on the tenth interlayer insulating layer INS10. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 of the pixel defining layer PDL covering the edge of each of the first electrodes AND are sequentially formed. Thereafter, a trench TRC is formed to penetrate the first pixel defining layer PDL1, the second pixel defining layer PDL2, the third pixel defining layer PDL3, and the tenth interlayer insulating layer INS10 (or a portion thereof). Then, the first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 of the light emitting stack IL are formed on the first electrode AND, the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3. In this case, the first stack layer IL1 and the second stack layer IL2 may be cut off in each of the trenches TRC. Subsequently, the second electrode CAT of the light emitting element LE is formed on the third stack layer IL3.

[0209] like Fig.14 and Fig.15 As shown in FIG. 1 , an encapsulation layer TFE ( Fig.11 Operation S120).

[0210] A first encapsulation inorganic layer TFE1 and a second encapsulation inorganic layer TFE2 of the encapsulation layer TFE are sequentially formed on the second electrode CAT. The first encapsulation inorganic layer TFE1 may be formed by chemical vapor deposition (CVD), and the second encapsulation inorganic layer TFE2 may be formed by atomic layer deposition (ALD). In this case, the second encapsulation inorganic layer TFE2 may be formed between the first pad portion PDA1 and the second pad portion PDA2 (see Figure 4 ) is formed on the second sub-pad conductive layer SPML2 and the tenth interlayer insulating layer INS10.

[0211] like Fig.16 As shown in FIG. , color filters CF1, CF2 and CF3 are formed on the encapsulation layer TFE ( Fig.11 Operation S130).

[0212] An organic layer APL is formed on the encapsulation layer TFE. On the organic layer APL, a first color filter CF1 is formed overlapping the first light emitting cell EA1, a second color filter CF2 is formed overlapping the second light emitting cell EA2, and a third color filter CF3 is formed overlapping the third light emitting cell EA3.

[0213] In the following, reference is made to Fig.11 Referring to operations S140 , S150 , and S160 , a method of forming the first lens LNS1 , the second lens LNS2 , and the third lens LNS3 on the plurality of color filters CF1 , CF2 , and CF3 will be described in detail.

[0214] like Fig.17 and Fig.18 As shown in FIG. 1 , a first lens layer LNL1 is formed on the color filters CF1 , CF2 , and CF3 , and a second lens pattern layer LNL2 ( Fig.11 Operation S140).

[0215] The first lens layer LNL1 may be formed not only on the color filters CF1, CF2, and CF3, but also on the first pad part PDA1 and the second pad part PDA2 (see FIG. Figure 4 ) is formed on the second encapsulation inorganic layer TFE2.

[0216] The second lens pattern layer LNL2 may be formed by a photolithography process. The second lens pattern layer LNL2 may have a pattern shape that is convex upward on the first lens layer LNL1 located on the color filters CF1, CF2, and CF3. The second lens pattern layer LNL2 may not be located above the edges of the color filters CF1, CF2, and CF3. That is, the second lens pattern layers LNL2 may be located to be spaced apart from each other.

[0217] In addition, the second lens pattern layer LNL2 may be formed on the first pad part PDA1 and the second pad part PDA2 (see Figure 4 ) is formed on the first lens layer LNL1 located above the second sub-pad conductive layer SPML2 and the tenth interlayer insulating layer INS10. The second lens pattern layer LNL2 may be formed to be flat, and the first pad portion PDA1 and the second pad portion PDA2 (see Figure 4 ) does not have a raised pattern shape.

[0218] The first lens layer LNL1 and the second lens pattern layer LNL2 are etched by dry etching to form Fig.19 and Fig. 20 The multiple lenses LNS1, LNS2 and LNS3 shown in Fig.11 Operation S150).

[0219] Since the second lens pattern layer LNL2 positioned above the color filters CF1 , CF2 , and CF3 has an upwardly convex shape, the plurality of lenses LNS1 , LNS2 , and LNS3 may have an upwardly convex shape similar to the second lens pattern layer LNL2 .

[0220] The thickness of the first lens layer LNL1 may be greater than the thickness of the second lens pattern layer LNL2. For example, the first lens layer LNL1 may have a thickness of approximately 2.5 μm, and the second lens pattern layer LNL2 may have a thickness of approximately 1.5 μm. In this case, if the thickness of the first lens layer LNL1 etched by dry etching is controlled to be greater than the thickness of the second lens pattern layer LNL2 and less than the thickness of the first lens layer LNL1, even when the first lens layer LNL1 and the second lens pattern layer LNL2 are etched together, the first lens layer LNL1 located in the region where the second lens pattern layer LNL2 is not formed may remain as a connection portion LNC, thereby protecting the plurality of color filters CF1, CF2, and CF3. However, the present disclosure is not limited thereto, and the first lens layer LNL1 located in the region where the second lens pattern layer LNL2 is not formed may be entirely etched, and in this case, the connection portion LNC may be omitted.

[0221] The first lens layer LNL1 and the second lens pattern layer LNL2 may be formed of the same material. Alternatively, when the first lens layer LNL1 and the second lens pattern layer LNL2 are formed of different materials, the etching rate of the etching gas used for dry etching on the first lens layer LNL1 and the etching rate of the second lens pattern layer LNL2 may be substantially the same.

[0222] like Fig. 20 and Fig.21 As shown in FIG. , etching is performed on the first pad portion PDA1 and the second pad portion PDA2 (see Figure 4) in which the first lens layer LNL1 and the second encapsulation inorganic layer TFE2 ( Fig.11 Operation S160).

[0223] Since the second lens pattern layer LNL2 is located in the entire area of ​​the first subpad BPD and the second subpad IPD, the first lens layer LNL1 may remain in the first pad portion PDA1 and the second pad portion PDA2 (see Figure 4 ) instead of being removed in operation S150. Because the first subpad BPD and the second subpad IPD may be appropriately exposed to be connected to the conductive adhesive member, the first lens layer LNL1 may be removed by etching the first lens layer LNL1 through a dry etching process. In addition, the second encapsulation inorganic layer TFE2 may also be removed through a dry etching process.

[0224] Alternatively, the first lens layer LNL1 and the second encapsulation inorganic layer TFE2 may be removed through a single dry etching process.

[0225] The gas used in the dry etching process may be carbon tetrafluoride (CF 4 ), carbon tetrafluoride (CF 4 ) and oxygen (O 2 ) or carbon tetrafluoride (CF 4 ) and argon (Ar).

[0226] In this case, if Fig.21 As shown in FIG. 1 , in addition to the first pad portion PDA1 and the second pad portion PDA2 (see Figure 4 ) is formed in the remaining area other than the dry etching process so that it can be protected from the etching gas. For example, the mask pattern MP can be a photoresist pattern. The mask pattern MP can be removed by a stripping process after the dry etching process.

[0227] like Fig.23 As shown in FIG. 1 , a filling layer FIL is formed on the plurality of lenses LNS1 , LNS2 , and LNS3 , and a cover layer CVL ( Fig.11 Operation S170).

[0228] The cover layer CVL may be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it is used as a packaging substrate, and the filling layer FIL may be used to bond the cover layer CVL. When the cover layer CVL is a polymer resin, it may be directly coated onto the filling layer FIL.

[0229] Then, the polarizing plate POL is attached to the cover layer CVL.

[0230] Fig.24is a perspective view illustrating a head mounted display according to one or more embodiments. Fig.25 It is shown Fig.24 An exploded perspective view of an example of a head-mounted display.

[0231] Reference Fig.24 and Fig.25 According to one or more embodiments, a head-mounted display 1000 includes a first display device 10_1, a second display device 10_2, a shell member 1100, a shell cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted strap 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520 and a control circuit board 1600.

[0232] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Figure 1 and Figure 2 The display devices 10 described are substantially the same, so descriptions of the first display device 10_1 and the second display device 10_2 will be omitted.

[0233] The first optical member 1510 may be located between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be located between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0234] The middle frame 1400 may be located between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0235] The control circuit board 1600 may be located between the middle frame 1400 and the housing member 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA, and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the connector.

[0236] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0237] The housing member 1100 is used to accommodate the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 is positioned to cover one opening surface of the housing member 1100. The housing cover 1200 may include a first eyepiece 1210 for placing a user's left eye and a second eyepiece 1220 for placing a user's right eye. Fig.24 and Fig.25 It is shown that the first eyepiece 1210 and the second eyepiece 1220 are separately positioned, but the present disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0238] The first eyepiece 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Therefore, the user may view the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and may view the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0239] The headband 1300 is used to fix the housing member 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 remain located on the left eye and the right eye of the user, respectively. Fig.26 As shown in , when the housing member 1200_1 is implemented to be lightweight and compact, the head mounted display 1000_1 may be provided with a glasses frame instead of the head mounted band 1300 .

[0240] In addition, the head mounted display 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0241] Fig.26is a perspective view illustrating a head mounted display according to one or more embodiments.

[0242] Reference Fig.26 The head mounted display 1000_1 according to one or more embodiments may be a glasses type display device in which the housing member 1200_1 is implemented in a lightweight and compact manner. The head mounted display 1000_1 according to one or more embodiments may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path changing member 1070, and a housing member 1200_1.

[0243] The housing member 1200_1 may include a display device 10_3, an optical member 1060, and an optical path changing member 1070. An image displayed on the display device 10_3 may be enlarged by the optical member 1060, and may be provided to the right eye of the user through the right-eye lens 1020 after its optical path is changed by the optical path changing member 1070. As a result, the user may view, through the right eye, an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image viewed through the right-eye lens 1020 are combined.

[0244] Fig.26 The housing member 1200_1 is shown to be located at the right end of the support frame 1030, but the present disclosure is not limited thereto. For example, the housing member 1200_1 may be located at the left end of the support frame 1030, and in this case, the image of the display device 10_3 may be provided to the left eye of the user. Alternatively, the housing member 1200_1 may be located at both the left and right ends of the support frame 1030, and in this case, the user may view the image displayed on the display device 10_3 through both the left and right eyes.

[0245] However, it should be understood that the aspects and features of the embodiments of the present disclosure are not limited to the aspects and features set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art by referring to the claims and their equivalents included therein.

Claims

1. A display device, comprising: A first light emitting unit configured to emit a first light; a second light emitting unit configured to emit a second light; a third light emitting unit configured to emit a third light; a first lens overlapping the first light emitting unit and comprising a first sub-lens overlapping a first portion of the first light emitting unit and a second sub-lens overlapping a second portion of the first light emitting unit; a second lens, overlapping the second light emitting unit; as well as a third lens, overlapping the third light emitting unit, The length of the first light emitting unit in the second direction is greater than the length of the second light emitting unit in the second direction, and greater than the length of the third light emitting unit in the second direction.

2. The display device according to claim 1, wherein: A length of the first sub-lens in the second direction is smaller than a length of the second sub-lens in the second direction.

3. The display device according to claim 1, wherein: A length of the first light emitting unit in a first direction crossing the second direction is smaller than a length of the second light emitting unit in the first direction, and smaller than a length of the third light emitting unit in the first direction.

4. The display device according to claim 3, wherein: The length of the first sub-lens in the first direction is equal to the length of the second sub-lens in the first direction.

5. The display device according to claim 3, wherein: The length of the first sub-lens in the first direction is smaller than the length of the second lens in the first direction, and smaller than the length of the third lens in the first direction.

6. The display device according to claim 3, wherein: The length of the second sub-lens in the first direction is smaller than the length of the second lens in the first direction, and smaller than the length of the third lens in the first direction.

7. The display device according to claim 1, wherein: The length of the third light emitting unit in the second direction is greater than the length of the second light emitting unit in the second direction.

8. The display device according to claim 1, wherein: A length of the second lens in the second direction is smaller than a length of the third lens in the second direction.

9. The display device according to claim 3, wherein: The length of the second light emitting unit in the first direction is equal to the length of the third light emitting unit in the first direction.

10. The display device according to claim 3, wherein: A length of the second lens in the first direction is equal to a length of the third lens in the first direction.

11. The display device according to claim 1, wherein: A first gap between the first sub-lens and the second sub-lens in the second direction is smaller than a second gap between the second lens and the third lens in the second direction.

12. The display device according to claim 1, wherein: A first line passing through a center of the first sub-lens and a center of the second lens is parallel to a second line passing through a center of the second sub-lens and a center of the third lens.

13. The display device according to claim 12, wherein: A third line passing through a center of a first gap between the first sub-lens and the second sub-lens in the second direction and a center of a second gap between the second lens and the third lens in the second direction is parallel to the first line and the second line.

14. A method for manufacturing a display device, the method comprising the following steps: forming a light emitting element including a first electrode on a substrate, a light emitting stack over the first electrode, and a second electrode over the light emitting stack; forming an encapsulation layer above the second electrode; forming a color filter over the encapsulation layer; as well as A first lens, a second lens, and a third lens are formed over the color filter.

15. The method of claim 14, wherein: The steps of forming the first lens, the second lens and the third lens include: forming a first lens layer above the color filter; forming a second lens pattern layer including a convex pattern over the first lens layer; and The first lens layer and the second lens pattern layer are etched to form the first lens, the second lens, and the third lens.

16. The method of claim 15, wherein: The thickness of the first lens layer is greater than the thickness of the second lens pattern layer.

17. The method of claim 15, wherein: The first lens layer is etched to a thickness greater than a thickness of the second lens pattern layer through the etching step.

18. The method of claim 15, wherein: The step of forming the first lens, the second lens, and the third lens further includes dry etching to remove portions of the first lens layer and the encapsulation layer above the pad metal layer of the pad portion.

19. The method of claim 18, wherein: The dry etching step includes using carbon tetrafluoride, carbon tetrafluoride and oxygen, or carbon tetrafluoride and argon.

20. A head mounted display, the head mounted display comprising: A display device, comprising: a first light emitting unit configured to emit a first light; a second light emitting unit configured to emit a second light and having a length in a second direction smaller than a length of the first light emitting unit in the second direction; a third light emitting unit configured to emit a third light and having a length in the second direction smaller than the length of the first light emitting unit in the second direction; a first lens overlapping the first light emitting unit and comprising a first sub-lens overlapping a first portion of the first light emitting unit and a second sub-lens overlapping a second portion of the first light emitting unit; a second lens overlapping the second light emitting unit; and a third lens overlapping the third light emitting unit; a housing member configured to accommodate the display device; and The optical member is configured to magnify a display image of the display device.

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