Display device and electronic device including the same

Abstract

A display device and an electronic apparatus including the same are disclosed. The display device includes: a base layer including a display area (DA) and a non-DA; a circuit element layer on the base layer and including a power supply electrode (PSE) overlapping the non-DA, circuit elements, and a shield electrode connected to the PSE and overlapping some of the circuit elements; a display element layer on the circuit element layer and including a light emitting element including a first electrode, a light emitting unit, and a second electrode, and a connection electrode connecting the second electrode to the PSE and including a first through hole; a thin film encapsulation layer (TFEL) on the display element layer and including an organic layer overlapping the DA; and an input sensing layer on the TFEL and including a sensing electrode and a sensing signal line connected to the sensing electrode. The sensing signal line is overlapped with the connecting electrode. Some of the first vias overlap the shield electrode.

Description

[0001] This application is a divisional application of the invention patent application with the application date of September 9, 2019, application number "201910863488.3" and invention name "display device". Technical Field

[0002] Example embodiments relate generally to a display device, and more particularly, to a display device including an input sensing unit. Background Art

[0003] The display device displays images and can be used in multimedia devices such as televisions, portable phones, tablet computers, navigators, game consoles, etc. Multimedia devices may include a keyboard or a mouse as an input device. Some display devices may include a sensing panel as an input device.

[0004] The above information disclosed in this section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0005] Some exemplary embodiments provide an input sensing unit integrated display device capable of reducing noise to the input sensing unit.

[0006] Additional aspects will be set forth in the detailed description which follows, and in part will be obvious from the disclosure, or may be learned by practice of the inventive concepts.

[0007] According to some exemplary embodiments, a display device includes a substrate layer, a circuit element layer, a display element layer, a thin film encapsulation layer, and an input sensing layer. The substrate layer includes a display area and a non-display area. The circuit element layer is disposed on the substrate layer. The circuit element layer includes: a power electrode overlapping the non-display area; a circuit element located on the substrate layer; and a shielding electrode connected to the power electrode and overlapping at least some of the circuit elements. The display element layer is disposed on the circuit element layer. The display element layer includes: a light emitting element including a first electrode, a light emitting unit, and a second electrode; and a connecting electrode connecting the second electrode to the power electrode. The connecting electrode includes a first through hole. The thin film encapsulation layer is disposed on the display element layer. The thin film encapsulation layer includes an organic layer overlapping the display area. The input sensing layer is disposed on the thin film encapsulation layer. The input sensing layer includes a sensing electrode and a sensing signal line connected to the sensing electrode. The sensing signal line overlaps the connecting electrode. At least some of the first through holes of the connecting electrode overlap the shielding electrode.

[0008] According to some exemplary embodiments, a display device includes a pixel, a power line, a driving circuit, a connecting electrode and a shielding electrode. The pixel is arranged in a display area of ​​the display device, and each of the pixels includes a light-emitting element. The power line is arranged in a non-display area of ​​the display device, and the non-display area surrounds the display area. The driving circuit is arranged between the power line and the display area. The driving circuit is configured to provide a signal to the pixel. The connecting electrode electrically connects the power line to each light-emitting element of the pixel. The shielding electrode is connected to the power line. The shielding electrode is arranged between the driving circuit and the connecting electrode.

[0009] The foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings illustrate exemplary embodiments of the inventive concept and, together with the description, are used to explain the principles of the inventive concept, wherein the accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated into and constitute a part of this specification. In the drawings: Figure 1 is a perspective view of a display device according to some exemplary embodiments; Figure 2 According to some exemplary embodiments, Figure 1 A cross-sectional view of the display device taken along the section line AA'; Figure 3 According to some exemplary embodiments, Figure 2 A cross-sectional view of a display module in a display device; Figure 4 According to some exemplary embodiments, Figure 3 A plan view of a display unit in a display module; Figure 5 According to some exemplary embodiments, Figure 4 A circuit diagram of a pixel in a display unit; Figure 6 According to some exemplary embodiments, Figure 5 A cross-sectional view of a pixel taken along the section line BB'; Figure 7 According to some exemplary embodiments, Figure 2 A cross-sectional view of an input sensing unit in a display device; Figure 8 According to some exemplary embodiments Figure 7 A plan view of an input sensing unit; Fig. 9 According to some exemplary embodiments, Figure 7 A plan view of a first conductive layer in an input sensing unit; Fig.10 According to some exemplary embodiments, Figure 7 A plan view of a second conductive layer in an input sensing unit; Fig.11 According to some exemplary embodiments Fig.10 An enlarged view of area BB; Fig.12 is a diagram showing a method according to some exemplary embodiments Figure 3 A cross-sectional view of an example of a display module in which area AA is enlarged; Fig.13 is a cross-sectional view showing a comparative example of a display module; Fig.14 is a diagram showing a plurality of components included in a stacked manner according to some exemplary embodiments. Fig.12 A plan view of a shielding electrode, a connecting electrode, and a second electrode in a display module; Fig.15 is a diagram showing a method according to some exemplary embodiments Figure 3 A cross-sectional view of another example of a display module in which area AA is enlarged; Fig.16 is a diagram showing a method according to some exemplary embodiments Figure 3 A cross-sectional view of another example of a display module in which area AA is enlarged; Fig.17 is a diagram showing a plurality of components included in a stacked manner according to some exemplary embodiments. Fig.16 A plan view of a shielding electrode, a connecting electrode, and a second electrode in a display module; Fig.18 is a diagram showing a method according to some exemplary embodiments Fig.12 A plan view of yet another example of a display module; Fig.19 is a diagram showing a method of implementing ... Fig.18 A cross-sectional view of an example of a display module taken along the section line CC'; Fig. 20 is a diagram showing a method according to some exemplary embodiments Fig.12 A plan view of yet another example of a display module; and Fig.21 is a diagram showing a method according to some exemplary embodiments Figure 3 FIG. 4 is a cross-sectional view of yet another example of a display module in which area AA is enlarged. DETAILED DESCRIPTION

[0011] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various exemplary embodiments. However, it is apparent that various exemplary embodiments may be implemented without these specific details or using one or more equivalent arrangements. In other cases, in order to avoid unnecessarily obscuring various exemplary embodiments, known structures and devices are shown in block diagram form. In addition, various exemplary embodiments may be different, but need not be mutually exclusive. For example, without departing from the inventive concept, the specific shape, configuration and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment.

[0012] Unless otherwise specified, the illustrated exemplary embodiments will be understood to provide exemplary features that vary the details of some exemplary embodiments. Therefore, unless otherwise specified, the various illustrated features, components, modules, layers, films, panels, regions, aspects, etc. (hereinafter, individually or collectively referred to as "elements") may be further combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0013] The use of cross hatching and / or shadows in the drawings is generally used to make the boundaries between adjacent elements clear. Thus, unless specified, the presence or absence of cross hatching or shadows does not express or indicate any preference or requirement for special materials, material properties, sizes, ratios, commonalities between the elements shown and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the sizes and relative sizes of the elements may be exaggerated for the purpose of clarity and / or description. Thus, the sizes and relative sizes of the elements are not necessarily limited to the sizes and relative sizes shown in the drawings. When the exemplary embodiments may be implemented differently, a specific process sequence may be performed in a sequence different from that described. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to that described. In addition, the same reference numerals represent the same elements.

[0014] When an element is referred to as being "on" another element, "connected to" or "coupled to" another element, the element may be directly on the other element, directly connected to or directly coupled to the other element, or there may be intermediate elements. However, when an element is referred to as being "directly on" another element, "directly connected to" or "directly coupled to" another element, there are no intermediate elements. Other terms and / or phrases used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", "on" versus "directly on", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection. In addition, the DR1 axis, the DR2 axis, and the DR3 axis are not limited to the three axes of a rectangular coordinate system, but may be interpreted in a broader sense. For example, the DR1 axis, the DR2 axis, and the DR3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0015] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, the first element discussed below may be named as the second element without departing from the disclosed teachings.

[0016] For descriptive purposes, spatially relative terms such as "under," "below," "under," "down," "above," "up," "above," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein to describe the relationship of one element to another (other) element as shown in the accompanying drawings. Spatially relative terms are intended to include different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as "under" or "beneath" other elements or features will subsequently be positioned as "above" the other elements or features. Thus, the exemplary term "under" can include both above and below orientations. In addition, the device can be positioned otherwise (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein are interpreted accordingly.

[0017] The terms used herein are for the purpose of describing specific embodiments, and are not intended to be limited. As used herein, unless the context clearly indicates otherwise, the singular forms "one (kind / person)" and "said (the)" are also intended to include plural forms. In addition, when the terms "comprise" and / or "include" and their variations are used in this specification, it is explained that there are stated features, integral bodies, steps, operations, elements, components and / or their groups, but one or more other features, integral bodies, steps, operations, elements, components and / or their groups are not excluded from existence or addition. It should also be noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms rather than as terms of degree, so they are used to explain the inherent deviations in measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0018] Various exemplary embodiments are described herein with reference to cross-sectional views, isometric views, perspective views, plan views, and / or exploded views that are schematic diagrams of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shapes of the drawings caused by, for example, manufacturing techniques and / or tolerances will be expected. Therefore, the exemplary embodiments disclosed herein should not be construed as being limited to the shapes of the specifically illustrated regions, but will include deviations in shape caused by, for example, manufacturing. To this end, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and are not intended to be limiting as such.

[0019] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure is a part. Unless expressly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an ideal or overly formal sense.

[0020] As is customary in the art, some exemplary embodiments are shown and described in the accompanying drawings according to functional blocks, units and / or modules. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, storage elements, wiring connections, etc.), and these blocks, units and / or modules can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and they can be optionally driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs certain functions and processors that perform other functions (e.g., one or more programmed microprocessors and related circuits). In addition, without departing from the inventive concept, each block, unit and / or module of some exemplary embodiments can be physically separated into two or more interactive and discrete blocks, units and / or modules. Furthermore, without departing from the inventive concept, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules.

[0021] Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0022] Figure 1 is a perspective view of a display device according to some exemplary embodiments.

[0023] Reference Figure 1 , the display device 1 may display an image through a display surface (or front surface). The display surface may be parallel to a plane defined by a first direction axis (i.e., an axis extending along the first direction DR1) and a second direction axis (i.e., an axis extending along the second direction DR2). The normal direction of the display surface (i.e., the thickness direction of the display device 1) may be defined as a third direction DR3. The front surface (or upper surface) and the rear surface (or lower surface) of each member or unit described below may be divided along the third direction DR3. However, Figure 1 The first direction DR1, the second direction DR2, and the third direction DR3 shown in FIG. 1 are merely examples but may be converted into different directions.

[0024] The display device 1 may have a flat display surface, but the exemplary embodiment is not limited thereto. For example, the display device 1 may have a curved display surface, a stereoscopic display surface, etc. The stereoscopic display surface may include a plurality of display areas indicating different directions, and may include, for example, a polygonal columnar display surface.

[0025] The display device 1 may be a rigid display device. However, exemplary embodiments are not limited thereto. For example, the display device 1 may be a flexible display device. Figure 1 The display device applicable to a mobile phone terminal is exemplarily shown. Figure 1 Although not shown in the figure, the electronic module, camera module, power module, etc. mounted on the main board are arranged in a bracket or a housing together with the display device 1, thereby constituting a mobile phone terminal. The display device 1 can be applied not only to large electronic devices such as televisions and monitors, but also to small and medium-sized electronic devices such as tablet computers, car navigation systems, game consoles, smart watches, etc.

[0026] The display surface includes a display area DA displaying an image and a non-display area NDA adjacent to the display area DA. The non-display area NDA is an area where no image is displayed. The display area DA may have a rectangular shape including rounded corners. The non-display area NDA may surround the display area DA. However, exemplary embodiments are not limited thereto, but the shape of the display area DA and the shape of the non-display area NDA may be relatively designed.

[0027] Figure 2 According to some exemplary embodiments, Figure 1 A cross-sectional view of the display device taken along the section line AA'.

[0028] Reference Figure 2 , the display device 1 includes a protection film PM, a display module DM, an optical member LM, a window WM, a first adhesive member AM1, a second adhesive member AM2, and a third adhesive member AM3.

[0029] The window WM may be disposed above the display module DM, and the optical member LM may be disposed between the display module DM and the window WM. The protective film PM may be disposed under the display module DM. The first adhesive member AM1 attaches the display module DM to the protective film PM, the second adhesive member AM2 attaches the display module DM to the optical member LM, and the third adhesive member AM3 attaches the optical member LM to the window WM.

[0030] The protective film PM protects the display module DM. The protective film PM provides a first outer surface OS-L exposed to the outside and provides an adhesive surface to be bonded to the first adhesive member AM1. The adhesive surface faces away from the first outer surface OS-L. The protective film PM prevents external moisture from penetrating the display module DM and absorbs external impact.

[0031] The protective film PM may include a plastic film as a base layer. The protective film PM may include a plastic film as a base substrate. The plastic film may include any one selected from polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), poly (arylethersulfone) and any combination of at least two of the above materials. The material constituting the protective film PM is not limited to plastic resin, but may include an organic / inorganic composite material.

[0032] The protective film PM may include a porous organic layer and an inorganic material filling the pores of the porous organic layer. The protective film PM may also include a functional layer formed on a plastic film. The functional layer may include a resin layer. The functional layer may be formed by coating. The protective film PM may be omitted.

[0033] The window WM can protect the display module DM from external impacts and can provide an input surface OS-U to the user. The window WM may include a plastic film as a base member. The window WM may have a multilayer structure. The base member of the window WM may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. The window WM may also include a frame pattern. The multilayer structure may be formed by a continuous process or a bonding process using an adhesive layer. The window WM may also include a functional layer disposed on the base member. The functional layer may include a hard coating, a fingerprint prevention layer, an anti-reflection layer and / or a self-repairing layer, etc.

[0034] The optical member LM reduces external light reflectivity. The optical member LM may include a polarizing film. The optical member LM may further include a retardation film. The optical member LM may be omitted.

[0035] The display module DM may include a display unit DP and an input sensing unit TS. The display unit DP may be an organic light-emitting display panel, but is not particularly limited. For example, the display unit DP may be a quantum dot light-emitting display panel, which is another type of self-luminous display panel. The quantum dot light-emitting display panel may include a light-emitting layer including quantum dots and quantum rods. Hereinafter, the display unit DP will be described assuming that it is an organic light-emitting display panel.

[0036] The display unit DP generates an image corresponding to input image data. The display unit DP provides a first display panel surface BS1-L and a second display panel surface BS1-U facing each other in the thickness direction DR3.

[0037] The input sensing unit TS is directly disposed on the display unit DP. As used herein, the phrase "directly disposed on" refers to being formed through a continuous process without using a separate adhesive layer for attachment.

[0038] The input sensing unit TS acquires coordinate information of the external input. Here, the external input may be a sensing event generated by a user or a sensing pen, etc. The input sensing unit TS may sense the external input, for example, in a capacitive manner. The operation method of the input sensing unit TS is not specifically limited. For example, the input sensing unit TS may sense the external input by electromagnetic induction and / or pressure sensing, etc.

[0039] Although in Figure 2 Although not shown in the figure, the display module DM may also include an anti-reflection layer. The anti-reflection layer may include a color filter or a stacked structure of a conductive layer / insulating layer / conductive layer. The anti-reflection layer may reduce the external light reflectivity by absorbing, destructively interfering or polarizing light incident from the outside. The anti-reflection layer may replace the function of the optical member LM.

[0040] Each of the first bonding member AM1, the second bonding member AM2, and the third bonding member AM3 may be an organic bonding layer such as an optically clear adhesive film (OCA), an optically clear resin (OCR), or a pressure-sensitive adhesive film (PSA). The organic bonding layer may include bonding materials such as polyurethane, polyacrylate, polyester, polyepoxy, or polyvinyl acetate.

[0041] In the following, reference will be made to Figures 3 to 13 The display module DM (ie, the display unit DP and the input sensing unit TS) is described in detail.

[0042] Figure 3 According to some exemplary embodiments, Figure 2 A cross-sectional view of a display module in a display device. Figure 4 According to some exemplary embodiments, Figure 3 A plan view of a display unit in a display module.

[0043] First, refer to Figure 3 The display unit DP includes a base layer SUB, a circuit layer (also called a circuit element layer) DP-CL located on the base layer SUB, a display element layer DP-OLED located on the circuit layer DP-CL, and a thin film encapsulation layer TFE located on the display element layer DP-OLED.

[0044] The base layer SUB may include at least one plastic film.The base layer SUB may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate as a flexible substrate.

[0045] The circuit layer DP-CL may include a semiconductor layer, an insulating layer (or an intermediate insulating layer), and a conductive layer. The conductive layer of the circuit layer DP-CL may constitute a signal line or a driving circuit of a pixel to be described later.

[0046] The display element layer DP-OLED includes a light emitting element (eg, an organic light emitting diode).

[0047] The thin film encapsulation layer TFE seals (e.g., hermetically seals) the display element layer DP-OLED. The thin film encapsulation layer TFE includes an inorganic layer and an organic layer. The thin film encapsulation layer TFE may include at least two inorganic layers and an organic layer disposed between the at least two inorganic layers. The inorganic layer protects the display element layer DP-OLED from water / oxygen, and the organic layer protects the display element layer DP-OLED from foreign substances such as dust particles. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer may include, but is not limited to, an acrylic organic layer.

[0048] The input sensing unit TS is directly disposed on the thin film encapsulation layer TFE. The input sensing unit TS includes a sensing electrode and a sensing signal line. The sensing electrode and the sensing signal line may have a single-layer structure or a multi-layer structure.

[0049] The sensing electrode and the sensing signal line may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), poly (3,4-ethylenedioxythiophene) (PEDOT), metal nanowires or graphene. The sensing electrode and the sensing signal line may include a metal layer such as molybdenum, silver, titanium, copper, aluminum or an alloy including at least one of the above materials. The sensing electrode and the sensing signal line may have the same layer structure or different layer structures. Figures 7 to 11 The details of the input sensing unit TS are described later. Fig.12 describe Figure 3 Area AA is shown in FIG.

[0050] Reference Figure 4 , the display unit DP includes a display area DA and a non-display area NDA on a plane.

[0051] As reference Figure 1 As described, the non-display area NDA may be defined along the edge of the display area DA. The display area DA and the non-display area NDA of the display unit DP correspond to the display area DA and the non-display area NDA of the display device 1, respectively. The display area DA and the non-display area NDA of the display unit DP are not necessarily the same as the display area DA and the non-display area NDA of the display device 1, but may be changed according to the structure / design of the display unit DP.

[0052] The display unit DP includes a driving circuit, a plurality of signal lines SL-Vint, SL-VDD, ELC, GL, DL, and SL-D, a power electrode E-VSS, and a plurality of pixels PX. An area where the pixels PX are arranged may be defined as a display area DA.

[0053] The drive circuit may include a scan drive circuit GDC. The scan drive circuit GDC generates a plurality of scan signals and outputs (e.g., sequentially) the plurality of scan signals to a plurality of scan lines GL to be described later. In addition, the scan drive circuit GDC generates a plurality of light emission control signals and outputs the plurality of light emission control signals to a plurality of light emission control lines ELC.

[0054] Although Figure 4 2 shows that the scan signal and the light emission control signal are output from one scan drive circuit GDC, but the exemplary embodiment is not limited thereto. For example, a plurality of scan drive circuits may divide and output the scan signal, and may divide and output the light emission control signal. In addition, the drive circuit for generating and outputting the scan signal and the drive circuit for generating and outputting the light emission control signal may be separately classified. For example, the drive circuits facing in the second direction DR2 may also be arranged. Figure 4 Another scan driving circuit which is different from the scan driving circuit GDC and is shown in FIG.

[0055] The scan driving circuit GDC may be included in the circuit layer DP-CL. The scan driving circuit GDC may include a plurality of thin film transistors formed by the same process as the driving circuit in the pixel PX.

[0056] Although Figure 4 Although not shown in the figure, the display unit DP may further include a data driving circuit connected to a pad (also referred to as a "pad") PD in the form of a chip on film (COF). The data driving circuit may be integrated in the circuit layer DP-CL.

[0057] The signal lines GL, DL, ELC, SL-VDD, SL-Vint, and SL-D may include a scan line GL, a light emitting control line ELC, a data line DL, a power line SL-VDD, an initialization voltage line SL-Vint, and a dummy signal line SL-D. The signal lines GL, DL, ELC, SL-VDD, SL-Vint, and SL-D are included in the circuit layer DP-CL, and some signal lines may be omitted. The pad PD may be connected to the ends of the signal lines GL, DL, ELC, SL-VDD, SL-Vint, and SL-D.

[0058] The scan lines GL are connected to corresponding pixels PX among the pixels PX, respectively, and the data lines DL are connected to corresponding pixels PX among the pixels PX, respectively. The light emission control lines ELC may be arranged in parallel with corresponding scan lines GL among the scan lines GL, respectively.

[0059] The power line SL-VDD is connected to the pixel PX and may provide a first power voltage to the pixel PX. The power line SL-VDD may include a plurality of lines extending in the first direction DR1 and a plurality of lines extending in the second direction DR2.

[0060] The initialization voltage line SL-Vint may provide an initialization voltage to the pixel PX. The initialization voltage line SL-Vint may include a plurality of lines extending in the first direction DR1 and a plurality of lines extending in the second direction DR2.

[0061] The dummy signal line SL-D may provide a control signal to the scan driving circuit GDC. The dummy signal line SL-D may provide a second power supply voltage to the power supply electrode E-VSS. The level of the second power supply voltage is different from the level of the first power supply voltage. The level of the second power supply voltage may be lower than the level of the first power supply voltage.

[0062] The power electrode E-VSS is disposed in the non-display area NDA and has a shape extending along one (or more) edges of the base layer SUB. Figure 4 As shown in , the power electrode E-VSS may have a shape facing three edges. The power electrode E-VSS may also be included in the circuit layer DP-CL.

[0063] like Figure 4 As shown in , the power electrode E-VSS is disposed outside the scan driving circuit GDC. The power electrode E-VSS may extend along an edge of the substrate layer SUB. The non-display area NDA may include a first non-display area NDA1 and a second non-display area NDA2 facing each other in a first direction DR1 with the display area DA therebetween. The non-display area NDA may include a third non-display area NDA3 and a fourth non-display area NDA4 facing each other in a second direction DR2 with the display area DA therebetween. The power electrode E-VSS may be disposed in at least one non-display area of ​​the first non-display area NDA1, the third non-display area NDA3, and the fourth non-display area NDA4. As shown in Figure 4 As shown in FIG. 1 , the power supply electrode E-VSS may be disposed in the first non-display area NDA1 , the third non-display area NDA3 , and the fourth non-display area NDA4 .

[0064] In some exemplary embodiments, the display unit DP may further include a shielding electrode (shielding layer or blocking layer) SHL.

[0065] like Figure 4 As shown in FIG. 1 , the shielding electrode SHL may be disposed in the non-display area NDA, and the shielding electrode SHL may overlap the power electrode E-VSS and the scan driving circuit GDC. Fig.13As described above, the shielding electrode SHL may be directly connected to the power electrode E-VSS and may cover at least a portion of the scan driving circuit GDC. The shielding electrode SHL may be electrically insulated from the scan driving circuit GDC. The shielding electrode SHL may cover the scan driving circuit GDC, thereby blocking noise generated by the scan driving circuit GDC and propagating to the input sensing unit TS to be described later. Therefore, the noise of the scan driving circuit GDC to the input sensing unit TS may be reduced or prevented. Fig.12 and Fig.13 The detailed structure and function of the shielding electrode SHL are described.

[0066] Figure 5 According to some exemplary embodiments, Figure 4 Circuit diagram of a pixel in a display unit.

[0067] Reference Figure 5 , the pixel PX may include a light emitting element EL, first to seventh transistors T1 to T7, and a capacitor (or storage capacitor) Cst.

[0068] A data signal DATA, a first scan signal GW, a second scan signal GI, a third scan signal GB, and a light emitting control signal EM may be provided to the pixel PX. Here, the second scan signal GI may be the same as the first scan signal GW of the previous point or the previous row. For example, the second scan signal GI[n] provided to the pixel PX of the nth row may be the same as the first scan signal GW[n-1] provided to the pixel PX of the n-1th row. Similarly, the third scan signal GB may be the same as the second scan signal GI of the next point or the next row. For example, the third scan signal GB[n] provided to the pixel PX of the nth row may be the same as the second scan signal GI[n+1] provided to the pixel PX of the n+1th row.

[0069] Each of the first to seventh transistors T1 to T7 may include a first electrode, a second electrode, and a gate electrode. One of the first and second electrodes may be a source electrode, and the other of the first and second electrodes may be a drain electrode.

[0070] Each of the first to seventh transistors T1 to T7 may be a thin film transistor. Each of the first to seventh transistors T1 to T7 may be a p-channel metal oxide semiconductor field effect transistor (PMOS transistor) or an n-channel metal oxide semiconductor field effect transistor (NMOS transistor). Hereinafter, the first to seventh transistors T1 to T7 will be described assuming that they are PMOS transistors.

[0071] The light emitting element EL may include an anode electrode and a cathode electrode. The anode electrode of the light emitting element EL may be connected to the fourth node N4, and the cathode electrode thereof may be connected to the second power supply line (ie, wiring for transmitting the second power supply voltage ELVSS).

[0072] The first transistor (or driving transistor) T1 may include: a first electrode connected (or electrically connected) to the first node N1; a second electrode connected to the second node N2; and a gate electrode connected to the third node N3. The first transistor T1 may provide a driving current Id to the light emitting element EL based on a voltage of the third node N3 (or a data voltage stored in the capacitor Cst to be described later).

[0073] The second transistor (or switching transistor) T2 may include: a first electrode connected to the data line (or receiving the data signal DATA); a second electrode connected to the first node N1; and a gate electrode connected to the first scan line or receiving the first scan signal GW. The second transistor T2 may be turned on in response to the first scan signal GW and may transmit the data signal DATA to the first node N1.

[0074] The third transistor T3 may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode connected to the first scan line or receiving the first scan signal GW. The third transistor T3 may be turned on in response to the first scan signal GW and may transmit the data signal DATA to the third node N3.

[0075] The capacitor Cst may be connected between the third node N3 and the first power voltage ELVDD. The capacitor Cst may store or maintain the supplied data signal DATA.

[0076] The fourth transistor T4 may include a first electrode connected to the third node N3 , a second electrode connected to the initialization voltage line SL-Vint or receiving the initialization voltage VINT, and a gate electrode connected to the second scan line (or receiving the second scan signal GI).

[0077] The fourth transistor T4 may be turned on in response to the second scan signal GI before the data signal DATA is stored in the capacitor Cst (or after the light emitting element EL emits light), and may initialize the third node N3 (or the capacitor Cst) with the initialization voltage VINT.

[0078] In some exemplary embodiments, the third transistor T3 and the fourth transistor T4 may be implemented as a double transistor (ie, a transistor in the form of a combination of two transistors). In this case, leakage current of the third transistor T3 and the fourth transistor T4 and degradation of display quality caused by the leakage current may be prevented or reduced.

[0079] The fifth transistor (or first light emission control transistor) T5 and the sixth transistor (or second light emission control transistor) T6 may be connected between the first power line and the light emitting element EL and may form a current path through which the driving current Id generated by the first transistor T1 moves.

[0080] The fifth transistor T5 may include a first electrode connected to the first power line to receive the first power voltage ELVDD, a second electrode connected to the first node N1, and a gate electrode connected to the light emitting control line ELC or receiving the light emitting control signal EM.

[0081] The sixth transistor T6 may include a first electrode connected to the second node N2 , a second electrode connected to the fourth node N4 (or the anode electrode of the light emitting element EL), and a gate electrode connected to the light emitting control line ELC or receiving the light emitting control signal EM.

[0082] The fifth transistor T5 and the sixth transistor T6 are turned on in response to the light emission control signal EM. In this case, the driving current Id is supplied to the light emitting element EL, and the light emitting element EL may emit light having brightness corresponding to the driving current Id.

[0083] The seventh transistor T7 may include a first electrode connected to the fourth node N4 , a second electrode connected to the initialization voltage line SL-Vint (or receiving the initialization voltage VINT), and a gate electrode connected to the third scan line (or receiving the third scan signal GB).

[0084] The seventh transistor T7 may be turned on in response to the third scan signal GB before the light emitting element EL emits light (or after the light emitting element EL emits light), and may initialize the anode electrode of the light emitting element EL using the initialization voltage VINT. The light emitting element EL may include a parasitic capacitor, and the parasitic capacitor may be charged or discharged by the driving current Id while the light emitting element EL emits light, so that the anode electrode of the light emitting element EL may have a non-constant voltage. Therefore, the parasitic capacitor and the auxiliary capacitor of the light emitting element EL may be initialized by the seventh transistor T7.

[0085] Although in Figure 5 FIG. 4 shows that the seventh transistor T7 receives the third scan signal GB, but the exemplary embodiment is not limited thereto. For example, the seventh transistor T7 may receive the second scan signal GI.

[0086] Figure 6 According to some exemplary embodiments, Figure 5 A cross-sectional view of a pixel taken along the section line BB'. Figure 6 Shown and included in Figure 5The cross section corresponding to the second transistor T2, the first transistor T1, the sixth transistor T6 and the light emitting element EL in the pixel PX.

[0087] Reference Figure 6 , the pixel PX may include a substrate layer SUB, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE. Figure 4 The described base layer SUB is basically the same, so a redundant description will not be repeated.

[0088] First, the circuit element layer DP-CL will be described.

[0089] The circuit element layer DP-CL may include a buffer layer BFL, a semiconductor layer 100 , a first insulating layer 10 , a first conductive layer 200 , a second insulating layer 20 , a second conductive layer 300 , a third insulating layer 30 , a third conductive layer 400 , and a fourth insulating layer 40 .

[0090] The buffer layer BFL may be disposed on the base layer SUB. The buffer layer BFL improves the bonding force between the base layer SUB and the conductive pattern or between the base layer SUB and the semiconductor pattern. The buffer layer BFL may include an inorganic layer. Figure 6 Although not shown in the figure, a barrier layer for preventing the inflow of foreign substances may be further provided on the base layer SUB. The buffer layer BFL and the barrier layer may be selectively provided or omitted.

[0091] The semiconductor layer 100 may be disposed on the buffer layer BFL. The semiconductor layer 100 may include a semiconductor pattern of the second transistor T2 (hereinafter, referred to as a second semiconductor pattern) OSP2, a semiconductor pattern of the first transistor T1 (hereinafter, referred to as a first semiconductor pattern) OSP1, and a semiconductor pattern of the sixth transistor T6 (hereinafter, referred to as a sixth semiconductor pattern) OSP6. The first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6 may be selected from the group consisting of an amorphous silicon pattern, a polycrystalline silicon pattern, and a metal oxide semiconductor pattern; however, exemplary embodiments are not limited thereto.

[0092] The first insulating layer 10 may be disposed on the semiconductor layer 100. Figure 6 2 and 3 , the first insulating layer 10 is shown to be provided in the form of a layer covering the first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6, but this is only illustrative and the exemplary embodiment is not limited thereto. For example, the first insulating layer 10 may be provided in a pattern provided corresponding to the first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6.

[0093] The first insulating layer 10 may include a plurality of inorganic layers. The inorganic layer may include at least one of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer.

[0094] The first conductive layer 200 is disposed on the first insulating layer 10. The first conductive layer 200 may include a gate electrode GE1 of the first transistor T1 (hereinafter, referred to as the first gate electrode), a gate electrode GE2 of the second transistor T2 (hereinafter, referred to as the second gate electrode), and a gate electrode GE6 of the sixth transistor T6 (hereinafter, referred to as the sixth gate electrode). The first gate electrode GE1, the second gate electrode GE2, and the sixth gate electrode GE6 may be connected to the scanning line GL (refer to Figure 4 )The second insulating layer 20 may be provided on the first conductive layer 200. The second insulating layer 20 may cover the first gate electrode GE1, the second gate electrode GE2 and the sixth gate electrode GE6.

[0095] The second conductive layer 300 is disposed on the second insulating layer 20. The second conductive layer 300 may include an input electrode (hereinafter, referred to as a first input electrode) SE1 and an output electrode (hereinafter, referred to as a first output electrode) DE1 of the first transistor T1, an input electrode (hereinafter, referred to as a second input electrode) SE2 and an output electrode (hereinafter, referred to as a second output electrode) DE2 of the second transistor T2, and an input electrode (hereinafter, referred to as a sixth input electrode) SE6 and an output electrode (hereinafter, referred to as a sixth output electrode) DE6 of the sixth transistor T6.

[0096] The first output electrode DE1 is connected to the first semiconductor pattern OSP1 through the first contact hole CNT1 penetrating the first insulating layer 10 and the second insulating layer 20. Similarly, the first input electrode SE1 is connected to the first semiconductor pattern OSP1 through the second contact hole CNT2 penetrating the first insulating layer 10 and the second insulating layer 20. The second input electrode SE2 and the second output electrode DE2 are electrically connected to the second semiconductor pattern OSP2 through the fourth contact hole CNT4 and the third contact hole CNT3 penetrating the first insulating layer 10 and the second insulating layer 20, respectively. The second input electrode SE2 may be electrically connected to the first output electrode DE1 or may be integrated with the first output electrode DE1. The sixth input electrode SE6 and the sixth output electrode DE6 are electrically connected to the sixth semiconductor pattern OSP6 through the fifth contact hole CNT5 and the sixth contact hole CNT6 penetrating the first insulating layer 10 and the second insulating layer 20, respectively. The sixth input electrode SE6 may be electrically connected to the first input electrode SE1 or may be integrated with the first input electrode SE1. Although the first transistor T1, the second transistor T2, and the sixth transistor T6 are shown in the drawings as having a top gate structure, exemplary embodiments are not limited thereto. For example, at least one of the first transistor T1 , the second transistor T2 , and the sixth transistor T6 may be modified into a bottom gate structure or a double gate structure.

[0097] The third insulating layer 30 is disposed on the second conductive layer 300 (and the second insulating layer 20). The third insulating layer 30 may cover the first input electrode SE1, the second input electrode SE2, the sixth input electrode SE6, the first output electrode DE1, the second output electrode DE2, and the sixth output electrode DE6. The third insulating layer 30 includes an organic layer and / or an inorganic layer. The third insulating layer 30 may include an organic material to provide a flat surface.

[0098] The third conductive layer 400 may be disposed on the third insulating layer 30. The third conductive layer 400 may include a data line DL and a data pattern 410. The data line DL is connected to the second output electrode DE2 of the second transistor T2 through a seventh contact hole CNT7 penetrating the third insulating layer 30. The data pattern 410 is connected to the sixth output electrode DE6 of the sixth transistor T6 through an eighth contact hole CNT8 penetrating the third insulating layer 30.

[0099] Although Figure 6 Although not shown in the figure, the third conductive layer 400 may further include a shielding electrode SHL. The shielding electrode SHL is disposed in the non-display area NDA. Fig.12 A detailed structure of the shielding electrode SHL and a stacked structure of the non-display area NDA are described.

[0100] The fourth insulating layer 40 may be disposed on the third conductive layer 400 (and the third insulating layer 30). The fourth insulating layer 40 may cover the data line DL and the data pattern 410. The fourth insulating layer 40 includes an organic layer and / or an inorganic layer. The fourth insulating layer 40 may include an organic material to provide a flat surface.

[0101] The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 may be defined as an intermediate insulating layer. Depending on the circuit structure of the pixel PX, at least one of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 may be omitted, or at least one other insulating layer may be added.

[0102] Hereinafter, the display element layer DP-OLED will be described.

[0103] The pixel defining layer PDL and the organic light emitting diode OLED are disposed on the fourth insulating layer 40. The first electrode AE ​​is disposed on the fourth insulating layer 40. The first electrode AE ​​is connected to the data pattern 410 through a ninth contact hole CNT9 penetrating the fourth insulating layer 40. Since the data pattern 410 is connected to the sixth output electrode DE6, the first electrode AE ​​may be electrically connected to the sixth output electrode DE6 (i.e., the sixth transistor T6) through the data pattern 410.

[0104] An opening OP is defined in the pixel defining layer PDL. The opening OP of the pixel defining layer PDL exposes at least a portion of the first electrode AE.

[0105] The pixel PX may be arranged in a pixel region on a plane. The pixel region may include a light emitting region PXA and a non-light emitting region NPXA adjacent to the light emitting region PXA. The non-light emitting region NPXA may surround the light emitting region PXA. The light emitting region PXA is defined to correspond to a portion of the first electrode AE ​​exposed by the opening OP.

[0106] The hole control layer HCL may be commonly disposed in the light emitting region PXA and the non-light emitting region NPXA. Figure 6 , but a common layer such as a hole control layer HCL may be provided for a plurality of pixels PX (see Figure 4 ) formed on public land.

[0107] The light emitting layer EML is disposed on the hole control layer HCL. The light emitting layer EML may be disposed in a region corresponding to the opening OP. That is, the light emitting layer EML may be formed separately in each pixel PX. The light emitting layer EML may include an organic material and / or an inorganic material. Figure 6A patterned light emitting layer EML is shown, but the light emitting layer EML may be commonly provided for the pixels PX. At this time, the light emitting layer EML may generate white light; however, the exemplary embodiment is not limited thereto. The light emitting layer EML may have a multi-layer structure.

[0108] The electronic control layer ECL is disposed on the light emitting layer EML. The electronic control layer ECL may be directed to the pixel PX (refer to Figure 5 ) formed on public land.

[0109] The second electrode CE is disposed on the electron control layer ECL. The second electrode CE is disposed in common with respect to the pixels PX.

[0110] The thin film encapsulation layer TFE is disposed on the second electrode CE. The thin film encapsulation layer TFE is disposed commonly for the pixels PX. The thin film encapsulation layer TFE may directly cover the second electrode CE. A cover layer covering the second electrode CE may also be disposed between the thin film encapsulation layer TFE and the second electrode CE. In this case, the thin film encapsulation layer TFE may directly cover the cover layer.

[0111] Figure 7 According to some exemplary embodiments, Figure 2 A cross-sectional view of an input sensing unit in a display device. Figure 8 According to some exemplary embodiments Figure 7 A plan view of an input sensing unit.

[0112] Reference Figure 7 , the input sensing unit TS includes a first conductive layer TS-CL1, a first insulating layer (hereinafter, referred to as a first sensing insulating layer) TS-IL1, a second conductive layer TS-CL2, and a second insulating layer (hereinafter, referred to as a second sensing insulating layer) TS-IL2. The first conductive layer TS-CL1 is directly disposed on the thin film encapsulation layer TFE. However, the exemplary embodiment is not limited thereto, but another inorganic layer or an organic layer may be disposed between the first conductive layer TS-CL1 and the thin film encapsulation layer TFE. Each of the first conductive layer TS-CL1 and the second conductive layer TS-CL2 may have a single-layer structure, or may have a multi-layer structure stacked along a third direction DR3. The conductive layer having a multi-layer structure may include at least two or more layers of a transparent conductive layer and a metal layer. The conductive layer having a multi-layer structure may include a metal layer containing different metals. The transparent conductive layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, or graphene. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy of at least one of the above materials. For example, each of the first conductive layer TS-CL1 and the second conductive layer TS-CL2 may have a triple-layer structure of titanium / aluminum / titanium.

[0113] Each of the first conductive layer TS-CL1 and the second conductive layer TS-CL2 includes a plurality of patterns. Hereinafter, it is assumed that the first conductive layer TS-CL1 includes a first conductive pattern and the second conductive layer TS-CL2 includes a second conductive pattern. Each of the first conductive pattern and the second conductive pattern may include a sensing electrode and a sensing signal line.

[0114] Each of the first sensing insulating layer TS-IL1 and the second sensing insulating layer TS-IL2 may include an inorganic material or an organic material. The inorganic material may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The organic material may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0115] Each of the first sensing insulating layer TS-IL1 and the second sensing insulating layer TS-IL2 may have a single layer structure or a multi-layer structure. Each of the first sensing insulating layer TS-IL1 and the second sensing insulating layer TS-IL2 may have at least one layer of an inorganic layer and an organic layer. The inorganic layer and the organic layer may be formed by chemical vapor deposition.

[0116] The first sensing insulating layer TS-IL1 insulates the first conductive layer TS-CL1 and the second conductive layer TS-CL2, and its shape is not limited. The shape of the first sensing insulating layer TS-IL1 can be changed according to the shape of the first conductive pattern and the shape of the second conductive pattern. The first sensing insulating layer TS-IL1 may cover the entire thin film encapsulation layer TFE, or may include a plurality of insulating patterns. It is sufficient that the plurality of insulating patterns overlap with the first connection unit CP1 or the second connection unit CP2 to be described later.

[0117] Although Figure 7 A double-layer input sensing unit TS is shown in FIG. 1 , but this is only an exemplary example, and the exemplary embodiments are not limited thereto. For example, a single-layer input sensing unit includes a conductive layer and an insulating layer covering the conductive layer. The conductive layer includes sensing electrodes and sensing signal lines connected to the sensing electrodes. The single-layer input sensing unit can acquire coordinate information in a self-capacitance manner.

[0118] Reference Figure 8, the input sensing unit TS may include: first sensing electrodes (or first to fourth driving electrodes) TE1-1 to TE1-4 (i.e., TE1-1, TE1-2, TE1-3, and TE1-4); first sensing signal lines (or first to fourth driving signal lines) SL1-1 to SL1-4 (i.e., SL1-1, SL1-2, SL1-3, and SL1-4), connected to the first sensing electrodes TE1-1 to TE1-4; second sensing electrodes (or first to fifth second sensing electrodes) TE2-1 to TE2-5 (i.e., TE2-1, TE2-2, TE2-3, TE2-4 and TE2-5); second sensing signal lines (or first to fifth second sensing signal lines) SL2-1 to SL2-5 (i.e., SL2-1, SL2-2, SL2-3, SL2-4 and SL2-5), connected to the second sensing electrodes TE2-1 to TE2-5; and a pad unit PADa, connected to the first sensing signal lines SL1-1 to SL1-4 and the second sensing signal lines SL2-1 to SL2-5 (hereinafter, may be referred to as “second sensing signal lines SL2 (refer to Fig.14 )").Although Figure 8 4 shows that the input sensing unit TS includes four first sensing electrodes TE1 - 1 to TE1 - 4 and five second sensing electrodes TE2 - 1 to TE2 - 5 , but this is merely an illustrative example, and exemplary embodiments are not limited thereto.

[0119] Each of the first sensing electrodes TE1-1 to TE1-4 may have a grid shape in which a plurality of sensing openings are defined. Each of the first sensing electrodes TE1-1 to TE1-4 includes a plurality of first sensing sensor units SP1 and a plurality of first connection units CP1. The first sensing sensor units SP1 are arranged along a first direction DR1. Each first connection unit CP1 connects two adjacent first sensing sensor units SP1 among the first sensing sensor units SP1. The first sensing signal lines SL1-1 to SL1-4 may also have a grid shape.

[0120] The second sensing electrodes TE2-1 to TE2-5 are insulated from the first sensing electrodes TE1-1 to TE1-4 and cross the first sensing electrodes TE1-1 to TE1-4. Each of the second sensing electrodes TE2-1 to TE2-5 may have a grid shape in which a plurality of sensing openings are defined. Each of the second sensing electrodes TE2-1 to TE2-5 includes a plurality of second sensing sensor units SP2 and a plurality of second connection units CP2. The second sensing sensor units SP2 are arranged along the second direction DR2. Each second connection unit CP2 connects two adjacent second sensing sensor units SP2 among the second sensing sensor units SP2. The second sensing signal lines SL2-1 to SL2-5 may also have a grid shape.

[0121] The first sensing electrodes TE1-1 to TE1-4 are electrostatically connected to the second sensing electrodes TE2-1 to TE2-5. When a sensing signal is applied to the first sensing electrodes TE1-1 to TE1-4, a capacitor is formed between the first sensing sensor unit SP1 and the second sensing sensor unit SP2.

[0122] Some of the first sensing sensor unit SP1, the first connection unit CP1, the first sensing signal lines SL1-1 to SL1-4, the second sensing sensor unit SP2, the second connection unit CP2, and the second sensing signal lines SL2-1 to SL2-5 may be Figure 7 The first conductive layer TS-CL1 shown in FIG. 1 is patterned, and the others can be formed by using Figure 7 The second conductive layer TS-CL2 shown in FIG. 1 is formed by patterning.

[0123] Heretofore, the input sensing unit TS in which the first connection unit CP1 and the second connection unit CP2 cross each other has been exemplarily shown and described, but exemplary embodiments are not limited thereto. For example, each first connection unit CP1 may be deformed into a V-shape so as not to overlap with the second connection unit CP2.

[0124] In addition, heretofore, the first sensing sensor unit SP1 and the second sensing sensor unit SP2 each having a rhombus shape have been exemplarily shown and described, but exemplary embodiments are not limited thereto.

[0125] Reference Figures 9 to 11 A more detailed configuration of the input sensing unit TS will be described.

[0126] Fig. 9 According to some exemplary embodiments, Figure 7 A plan view of the first conductive layer in an input sensing unit. Fig.10 According to some exemplary embodiments, Figure 7 A plan view of the second conductive layer in an input sensing unit. Fig.11 According to some exemplary embodiments Fig.10 An enlarged view of area BB.

[0127] Reference Figure 7 and Fig. 9 , the first conductive pattern is disposed on the thin film encapsulation layer TFE. The first conductive pattern may include a first connection unit (or bridge pattern) CP1. The first connection unit CP1 may be directly disposed on the thin film encapsulation layer TFE. The first connection unit CP1 corresponds to Figure 8 The first connection unit CP1 is shown in FIG.

[0128] Although Fig.10 Although not shown, the first sensing insulating layer TS-IL1 covering the first connection unit CP1 is disposed on the thin film encapsulation layer TFE. A contact hole for partially exposing the first connection unit CP1 is defined in the first sensing insulating layer TS-IL1. The contact hole may be formed by a photolithography process.

[0129] Reference Figure 7 and Fig.10 , the second conductive pattern is disposed on the first sensing insulating layer TS-IL1. The second conductive pattern may include a first sensing sensor unit SP1, a second connection unit CP2, first sensing signal lines SL1-1 to SL1-4, a second sensing sensor unit SP2, and second sensing signal lines SL2-1 to SL2-5. Fig.10 Although not shown in the figure, the second sensing insulating layer TS-IL2 covering the second conductive pattern is disposed on the first sensing insulating layer TS-IL1.

[0130] In some exemplary embodiments, the first conductive pattern may include first sensing electrodes TE1-1 to TE1-4 and first sensing signal lines SL1-1 to SL1-4. The second conductive pattern may include second sensing electrodes TE2-1 to TE2-5 and second sensing signal lines SL2-1 to SL2-5. In this case, no contact hole is defined in the first sensing insulating layer TS-IL1.

[0131] In some exemplary embodiments, the first conductive pattern and the second conductive pattern may be interchanged. That is, the second conductive pattern may include the first connection unit CP1.

[0132] In some exemplary embodiments, the first conductive pattern may further include dummy signal lines corresponding to the first sensing signal lines SL1-1 to SL1-4 and the second sensing signal lines SL2-1 to SL2-5. The dummy signal lines and the sensing signal lines corresponding to each other may be connected to each other through contact holes penetrating the first sensing insulating layer TS-IL1. The dummy signal lines may reduce the resistance of the sensing signal lines.

[0133] Reference Fig.11 , the first sensing sensor unit SP1 and the second sensing sensor unit SP2 overlap with the non-light emitting area NPXA. A plurality of grid holes TS-OPR, TS-OPG, and TS-OPB are defined in the first sensing sensor unit SP1 and the second sensing sensor unit SP2. The grid holes TS-OPR, TS-OPG, and TS-OPB may correspond one-to-one to the light emitting areas PXA-R, PXA-G, and PXA-B.

[0134] The light-emitting areas PXA-R, PXA-G and PXA-B can be Figure 6The light emitting areas PXA of the embodiment of the present invention are substantially the same. An organic light emitting diode OLED is provided for each of the light emitting areas PXA-R, PXA-G, and PXA-B. The organic light emitting diode OLED may include a first organic light emitting diode for generating light of a first color, a second organic light emitting diode for generating light of a second color, and a third organic light emitting diode for generating light of a third color.

[0135] The light emitting areas PXA-R, PXA-G and PXA-B can be based on the organic light emitting diode OLED (refer to Figure 6 ) of the light-emitting layer EML (reference Figure 6 ) have different areas according to the color of the light emitted. The areas of the light emitting regions PXA-R, PXA-G, and PXA-B may be determined according to the type of the organic light emitting diode OLED. The light emitting regions PXA-R, PXA-G, and PXA-B may be divided into at least two groups.

[0136] Although Fig.11 The light emitting regions PXA-R, PXA-G, and PXA-B divided into three groups are shown, but this is only an illustrative example, and the exemplary embodiment is not limited thereto. For example, the grid holes TS-OPR, TS-OPG, and TS-OPB may be divided into two groups or four or more groups having different areas.

[0137] Fig.11 A first grid hole TS-OPR having a first area, a second grid hole TS-OPG having a second area different from the first area, and a third grid hole TS-OPB having a third area different from the first area and the second area are shown. The areas of the grid holes TS-OPR, TS-OPG, and TS-OPB can be determined according to the type of the organic light emitting diode OLED overlapped with the grid holes TS-OPR, TS-OPG, and TS-OPB.

[0138] Each of the first sensing sensor unit SP1 and the second sensing sensor unit SP2 may include grid lines defining grid holes TS-OPR, TS-OPG, and TS-OPB. The grid lines may include: first grid lines extending in a fourth direction DR4 crossing the first direction DR1 and the second direction DR2; and second grid lines extending in a fifth direction DR5 crossing the fourth direction DR4. The line widths of the first grid lines and the second grid lines may be several micrometers.

[0139] Fig.11Four grid line units M1, M2, M3 and M4 defining one grid hole TS-OPR are shown. The grid line units M1, M2, M3 and M4 constitute a portion of the first grid line and the second grid line. The first grid line unit M1 and the second grid line unit M2 face each other in the fourth direction DR4, and the third grid line unit M3 and the fourth grid line unit M4 face each other in the fifth direction DR5. Although Fig.11 1 and 2 show that the grid holes TS-OPR, TS-OPG and TS-OPB correspond to the light-emitting regions PXA-R, PXA-G and PXA-B one by one, but the exemplary embodiment is not limited thereto. For example, one grid hole TS-OPR, TS-OPG or TS-OPB may correspond to two or more light-emitting regions PXA-R, PXA-G and PXA-B.

[0140] Although Fig.11 , the areas of the light emitting regions PXA-R, PXA-G, and PXA-B are different, but the exemplary embodiment is not limited thereto. For example, the sizes of the light emitting regions PXA-R, PXA-G, and PXA-B may be equal to each other, and the sizes of the grid holes TS-OPR, TS-OPG, and TS-OPB may also be equal to each other.

[0141] Fig.12 is a diagram showing a method according to some exemplary embodiments Figure 3 FIG. 1 is a cross-sectional view of an example of a display module in which area AA is enlarged. Fig.13 is a cross-sectional view showing a comparative example of a display module. Fig.13 Shown with Fig.12 The corresponding area. Fig.14 is a diagram showing a plurality of components included in a stacked manner according to some exemplary embodiments. Fig.12 A plan view of a shielding electrode, a connecting electrode and a second electrode in a display module. Fig.14 According to some exemplary embodiments, Fig.12 The plane area corresponding to the cross section.

[0142] First, refer to Fig.12 Since the stacked structure of the circuit layer DP-CL, the display element layer DP-OLED and the thin film encapsulation layer TFE arranged in the display area DA is different from that of the reference Figure 6 The described stacked structures are basically the same, so redundant descriptions will not be repeated. For ease of explanation, the hole control layer HCL and the electron control layer ECL will be omitted, but it should be understood that the display element layer DP-OLED includes the hole control layer HCL and the electron control layer ECL.

[0143] Similarly, since the stacked structure of the input sensing unit TS disposed in the display area DA is the same as that already referred to Figures 7 to 11The described stacked structures are substantially the same, so redundant descriptions will not be repeated. For ease of explanation, the first conductive layer TS-CL1 and the second sensing insulating layer TS-IL2 will be omitted, but it should be understood that the input sensing unit TS includes the first conductive layer TS-CL1 and the second sensing insulating layer TS-IL2.

[0144] Fig.12 2 shows that the thin film encapsulation layer TFE includes a first inorganic layer IOL1, an organic layer OL and a second inorganic layer IOL2.

[0145] Hereinafter, the non-display area NDA will be mainly described.

[0146] The scan drive circuit GDC constituting the circuit layer DP-CL is arranged in the non-display area NDA. The scan drive circuit GDC includes at least one transistor GDC-T formed by the same process as the sixth transistor T6. The scan drive circuit GDC includes a signal line GDC-SL arranged on the same layer as the input electrode SE6 of the sixth transistor T6. The initialization voltage line SL-Vint and the power electrode E-VSS are also arranged on the same layer as the input electrode SE6 of the sixth transistor T6. Since the initialization voltage line SL-Vint, the power electrode E-VSS and the input electrode SE6 of the sixth transistor T6 are formed by the same process, they can have the same layer structure and can include the same material.

[0147] If already referred to Figure 4 As described above, the power electrode E-VSS is provided outside the scan driving circuit GDC.

[0148] The shielding electrode (or shielding layer) SHL is disposed on the third insulating layer 30. The shielding electrode SHL may be directly connected to the power electrode E-VSS and may overlap at least a portion of the scan driving circuit GDC. In addition, the shielding electrode SHL may overlap at least a portion of the second electrode CE to be described later, or may partially overlap the second electrode CE. The shielding electrode SHL may be formed by the same process as the data line DL and may overlap with the data pattern 410 (or the data line DL (refer to Figure 6 )) include the same layer structure and the same material. In addition, the shielding electrode SHL may have the same thickness as that of the data pattern 410 (or the data line DL).

[0149] The shielding electrode SHL is set in the reference Figure 4 At least one of the first non-display area NDA1, the third non-display area NDA3 and the fourth non-display area NDA4 described above. Figure 4As shown in FIG. 1 , the shielding electrode SHL may be disposed in the first non-display area NDA1 , the third non-display area NDA3 , and the fourth non-display area NDA4 .

[0150] The connection electrode E-CNT is disposed on the fourth insulating layer 40. The connection electrode E-CNT connects the power electrode E-VSS (or the shielding electrode SHL) to the second electrode CE. The connection electrode E-CNT may overlap with the power electrode E-VSS, may overlap with the shielding electrode SHL, and may overlap with the second electrode CE. The connection electrode E-CNT transmits the second power supply voltage from the power electrode E-VSS to the second electrode CE. Since the connection electrode E-CNT and the first electrode AE ​​are formed by the same process, the connection electrode E-CNT may include the same layer structure and the same material as the first electrode AE. The connection electrode E-CNT and the first electrode AE ​​may have the same thickness.

[0151] Similar to the shielding electrode SHL, the connection electrode E-CNT is disposed in at least one of the first non-display area NDA1, the third non-display area NDA3, and the fourth non-display area NDA4. For example, the connection electrode E-CNT may be disposed in the first non-display area NDA1, the third non-display area NDA3, and the fourth non-display area NDA4.

[0152] A plurality of first through holes H_VIA1 are defined in the connection electrode E-CNT. The first through holes H_VIA1 exhaust gas generated in a process of forming the fourth insulating layer 40.

[0153] In some exemplary embodiments, each first through hole H_VIA1 of the connection electrode E-CNT may overlap with the shielding electrode SHL, or may be covered by the shielding electrode SHL. For reference, when the connection electrode E-CNT includes the first through hole H_VIA1, noise propagates from the scan driving circuit GDC to the input sensing unit TS through the first through hole H_VIA1 of the connection electrode E-CNT, and the noise affects the second sensing signal line SL2, thereby degrading the sensitivity of the input sensing unit TS. Therefore, the shielding electrode SHL (i.e., the shielding electrode SHL connected to the power supply electrode E-VSS) may cover the first through hole H_VIA1 of the connection electrode E-CNT based on the scan driving circuit GDC, thereby blocking the noise propagating from the scan driving circuit GDC to the input sensing unit TS through the first through hole H_VIA1 of the connection electrode E-CNT. Therefore, the degradation of the sensitivity of the input sensing unit TS due to noise can be prevented.

[0154] The second electrode CE may overlap at least a portion of the shielding electrode SHL, or may partially overlap the shielding electrode SHL. In the region where the connecting electrode E-CNT does not overlap the shielding electrode SHL, noise may be transmitted from the scanning driving circuit GDC through some of the first through holes H_VIA1 of the connecting electrode E-CNT (refer to the later described Fig.15 ) is transmitted to the input sensing unit TS. In this way, the second electrode CE can cover the area where the shielding electrode SHL and the connecting electrode E-CNT do not overlap, thereby blocking the noise transmitted from the scan driving circuit GDC to the input sensing unit TS.

[0155] For reference, in consideration of tolerance (or process error, for example, an error that may occur during the formation of a sub-structure), the second electrode CE is spaced apart from the edge of the display module DM by a predetermined distance D_REF or more. Since the display module DM includes the shielding electrode SHL, the second electrode CE may be spaced apart from the edge of the display module DM by a distance greater than the predetermined distance D_REF by a margin D_MG, and the second sensing signal line SL2 of the input sensing unit TS may be arranged under more relaxed conditions. That is, since the display module DM includes the shielding electrode SHL, the second electrode CE and the second sensing signal line SL2 may be arranged under more relaxed conditions (i.e., more relaxed positions and restrictions). For example, the second sensing signal line SL2 may not overlap with the second electrode CE. Fig.13 It is mentioned about the arrangement conditions of the second electrodes CE and the second sensing signal lines SL2.

[0156] Reference Fig.13, the display module DM_C according to the comparative example does not include the shielding electrode SHL. The second electrode CE_C may be separated from the edge of the display module DM_C by a predetermined distance D_REF, and may cover some of the first through holes H_VIA1 of the connection electrode E-CNT. In this case, the other first through holes H_VIA1 of the connection electrode E-CNT (i.e., the through holes arranged in the area within the predetermined distance D_REF from the edge of the display module DM_C) are not covered by the second electrode CE_C. Therefore, noise may propagate from the scan drive circuit GDC through the other first through holes H_VIA1 to the dummy sensing signal line SL2_V, and the sensitivity of the input sensing unit TS may be degraded by the noise. In order to eliminate the influence of noise, the dummy sensing signal line SL2_V may not be formed, but the second sensing signal line SL2 may be set only in the overlapping area BTWA (i.e., the area where the first through holes H_VIA1 of the connection electrode E-CNT are covered by the second electrode CE_C). As the overlapping area BTWA in which the second sensing signal line SL2 can be arranged relatively decreases, a short circuit between the second sensing signal lines SL2 may occur, or the resistance of the second sensing signal line SL2 may decrease as the width of the second sensing signal line SL2 decreases, and the sensitivity of the input sensing unit TS may deteriorate.

[0157] Therefore, the display module DM according to various exemplary embodiments may cover the first through hole H_VIA1 of the connection electrode E-CNT with the shielding electrode SHL, thereby not only preventing or reducing degradation of the sensitivity of the input sensing unit TS but also reducing restrictions on the arrangement positions of the second electrode CE and the second sensing signal line SL2.

[0158] Refer again Fig.12 , the dam portions DM1 and DM2 may be disposed in the non-display area NDA. The dam portions DM1 and DM2 may include a first dam portion DM1 and a second dam portion DM2. The first dam portion DM1 and the second dam portion DM2 may be spaced apart from each other in the second direction DR2. Fig.12 Although not shown, the first dam DM1 and the second dam DM2 may be disposed on a plane to surround the display area DA. The first dam DM1 and the second dam DM2 may be disposed in at least one of the first non-display area NDA1, the third non-display area NDA3, and the fourth non-display area NDA4.

[0159] The first dam DM1 may be disposed on the power electrode E-VSS. The first dam DM1 may be a single layer and may be formed simultaneously with the pixel defining layer PDL. Since the first dam DM1 and the pixel defining layer PDL are formed by the same process, the thickness of the first dam DM1 may be the same as the thickness of the pixel defining layer PDL, and the first dam DM1 and the pixel defining layer PDL may include the same material. In some exemplary embodiments, the thickness of the first dam DM1 may be less than the thickness of the pixel defining layer PDL.

[0160] The second dam DM2 may be disposed outside the first dam DM1. For example, a distance between the second dam DM2 and the display area DA may be greater than a distance between the first dam DM1 and the display area DA.

[0161] The second dam DM2 may cover a portion of the power electrode E-VSS. The second dam DM2 may have a multilayer structure. The lower portion of the second dam DM2 may be formed simultaneously with the third insulating layer 30, the central portion of the second dam DM2 may be formed simultaneously with the fourth insulating layer 40, and the upper portion of the second dam DM2 may be formed simultaneously with the pixel defining layer PDL.

[0162] The first inorganic layer IOL1 may cover the first dam DM1 and the second dam DM2. The edge of the first inorganic layer IOL1 may be in contact with the second insulating layer 20. The organic layer OL may overlap with the circuit element (e.g., the transistor GDC-T of the scan driving circuit GDC), and the edge of the organic layer OL may not overlap with the first dam DM1 and the second dam DM2. In some exemplary embodiments, the edge of the organic layer OL is not disposed outside the second dam DM2. The second inorganic layer IOL2 may overlap with the first dam DM1 and the second dam DM2. The edge of the second inorganic layer IOL2 may be in contact with the first inorganic layer IOL1.

[0163] The first sensing insulating layer TS-IL1 may overlap the first dam DM1 and the second dam DM2. An edge of the first sensing insulating layer TS-IL1 may contact the second inorganic layer IOL2.

[0164] At least some of the second sensing signal lines SL2 disposed on the first sensing insulating layer TS-IL1 overlap the shielding electrode SHL. It is not necessary for all of the sensing signal lines SL2 to overlap the shielding electrode SHL, but it is sufficient that some of the second sensing signal lines SL2 overlap the shielding electrode SHL.

[0165] Reference Fig.14, the first through holes H_VIA1 connecting the electrodes E-CNT define a plurality of rows H-L1 to H-L4, and the plurality of rows H-L1 to H-L4 are arranged in the first direction DR1. The plurality of rows H-L1 to H-L4 may include holes (i.e., first through holes H_VIA1) arranged in the second direction DR2, and the plurality of rows H-L1 to H-L4 may include the same number of holes. However, exemplary embodiments are not limited thereto. For example, the plurality of rows H-L1 to H-L4 may include different numbers of holes. The planar shape of each of the plurality of first through holes H_VIA1 is a rectangle, but is not limited thereto.

[0166] The holes in the first row H-L1 of the plurality of rows H-L1 to H-L4 may be defined as first holes, and the holes in the second row H-L2 of the plurality of rows H-L1 to H-L4 may be defined as second holes. The holes in the third row H-L3 of the plurality of rows H-L1 to H-L4 may be defined as third holes. The first row H-L1 and the third row H-L3 may include the same number of holes. The first hole, the second hole, and the third hole may be aligned. However, exemplary embodiments are not limited thereto. For example, the first hole and the third hole may be aligned, and the second hole may be disposed between the first holes.

[0167] Fig.15 is a diagram showing a method according to some exemplary embodiments Figure 3 FIG. 4 is a cross-sectional view of another example of a display module in which area AA is enlarged.

[0168] Reference Fig.12 and Fig.15 , display module DM_1 and Fig.12 The display module DM of FIG. 1 is different in that the display module DM_1 includes a shielding electrode SHL_1 and a second electrode CE_1 .

[0169] The shielding electrode SHL_1 may be located in the same region as that described above except for the region in which the shielding electrode SHL_1 is disposed. Fig.12 The shielding electrode SHL described is substantially the same, and therefore, a redundant description will not be repeated.

[0170] The shielding electrode SHL_1 may partially overlap the scan driving circuit GDC. That is, the shielding electrode SHL_1 may only cover a portion of the scan driving circuit GDC (eg, a portion adjacent to an edge of the display module DM). Figure 4 ) may be provided in the third conductive layer 400 (refer to Figure 6 ), that is, disposed on the third insulating layer 30. To prevent disconnection from the data line DL, the shielding electrode SHL_1 may be spaced apart from the display area DA by a predetermined distance. In this case, the shielding electrode SHL_1 may be disposed to overlap only a portion of the scan driving circuit GDC.

[0171] In addition to the position where the second electrode CE_1 is disposed, the second electrode CE_1 may be located at the position where the second electrode CE_1 is disposed. Figure 6 and Fig.12 The second electrode CE described is substantially the same, and therefore, a redundant description will not be repeated.

[0172] like Fig.15 As shown in , the second electrode CE_1 may extend to a predetermined distance D_REF from the edge of the display module DM_1. Some of the second sensing signal lines SL2 may overlap with the shielding electrode SHL_1, and other of the second sensing signal lines SL2 may overlap with the second electrode CE_1, and the some of the second sensing signal lines SL2 are different from the other of the second sensing signal lines SL2. Since the second electrode CE_1 partially overlaps with the shielding electrode SHL_1, the second electrode CE_1 together with the shielding electrode SHL_1 may block noise propagating from the scan driving circuit GDC (or the circuit element layer DP-CL) to the input sensing unit TS.

[0173] Fig.16 is a diagram showing a method according to some exemplary embodiments Figure 3 FIG. 4 is a cross-sectional view of yet another example of a display module in which area AA is enlarged. Fig.17 is a diagram showing a plurality of components included in a stacked manner according to some exemplary embodiments. Fig.16 A plan view of a shielding electrode, a connecting electrode and a second electrode in a display module. Fig.17 Shown with Fig.16 The area corresponding to the cross section.

[0174] Reference Fig.12 , Fig.14 , Fig.16 and Fig.17 , Fig.16 and Fig.17 The display module DM_2 and Fig.12 and Fig.14 The display module DM of FIG. 1 is different from that of FIG. 2 in that the display module DM_2 includes a shielding electrode SHL_2. In addition to including a second through hole H_VIA2 in the shielding electrode SHL_2, the shielding electrode SHL_2 may be the same as that already described with reference to FIG. Fig.12 The shielding electrode SHL described is substantially the same, and therefore, a redundant description will not be repeated.

[0175] A plurality of second through holes H_VIA2 are defined in the shielding electrode SHL_2. The second through holes H_VIA2 exhaust gas generated in the process of forming the third insulating layer 30. That is, when the third insulating layer 30 includes an organic material, gas is generated in the process of forming the third insulating layer 30, and the gas is exhausted to the outside through the second through holes H_VIA2.

[0176] The second through hole H_VIA2 of the shielding electrode SHL_2 may be covered by the connection electrode E-CNT. The first through hole H_VIA1 of the connection electrode E-CNT may not overlap with the second through hole H_VIA2 of the shielding electrode SHL_2.

[0177] Similar to the first through hole H_VIA1 of the connecting electrode E-CNT, noise can propagate from the scan driving circuit GDC to the input sensing unit TS through the second through hole H_VIA2 of the shielding electrode SHL_2, but the connecting electrode E-CNT covers the second through hole H_VIA2 of the shielding electrode SHL_2, or the first through hole H_VIA1 of the connecting electrode E-CNT is arranged not to overlap with the second through hole H_VIA2 of the shielding electrode SHL_2, thereby preventing the propagation of noise.

[0178] Reference Fig.17 , showing that the connection electrode E-CNT and the shielding electrode SHL_2 overlap each other. Fig.12 The first through hole H_VIA1 of the connection electrode E-CNT described is the same, and thus a redundant description will not be repeated.

[0179] The second through holes H_VIA2 of the shielding electrode SHL_2 may be arranged to be interleaved with the first through holes H_VIA1 of the connection electrode E-CNT.

[0180] Similar to the first through hole H_VIA1 of the connection electrode E-CNT, the second through hole H_VIA2 of the shielding electrode SHL_2 defines a plurality of rows H-L11 to H-L13, and the plurality of rows H-L11 to H-L13 are arranged in the first direction DR1. The plurality of rows H-L11 to H-L13 may include holes arranged in the second direction DR2, and the plurality of rows H-L11 to H-L13 may include different numbers of holes. The planar shape of each of the plurality of second through holes H_VIA2 is the same as or similar to the planar shape of each of the plurality of first through holes H_VIA1, but exemplary embodiments are not limited thereto.

[0181] The rows H-L11 to H-L13 of the shielding electrode SHL_2 may be disposed between the rows H-L1 to H-L4 of the connecting electrodes E-CNT. That is, the rows H-L11 to H-L13 of the shielding electrode SHL_2 and the rows H-L1 to H-L4 of the connecting electrodes E-CNT are arranged alternately (or optionally). For example, the rows H-L11 to H-L13 of the shielding electrode SHL_2 and the rows H-L1 to H-L4 of the connecting electrodes E-CNT may be staggered with each other. In addition, when the second through hole H_VIA2 of the shielding electrode SHL_2 defines a plurality of columns V-L2, or when the first through hole H_VIA1 of the connecting electrode E-CNT defines a plurality of columns V-L1, the columns V-L2 of the shielding electrode SHL_2 and the columns V-L1 of the connecting electrodes E-CNT may be arranged alternately in the second direction DR2. That is, on the plane, the second through-holes H_VIA2 of the shielding electrode SHL_2 and the first through-holes H_VIA1 of the connection electrode E-CNT may have a checkerboard structure or a grid structure, and may be arranged not to overlap each other.

[0182] The connection electrode E-CNT may be connected to the power electrode E-VSS and the second electrode CE to reduce the total resistance and reduce the voltage drop of the second power voltage ELVSS. As the area of ​​the second through hole H_VIA2 of the connection electrode E-CNT decreases, the total resistance of the connection electrode E-CNT (and the voltage drop of the second power voltage ELVSS) may decrease. In this way, the connection electrode E-CNT may have a mesh structure.

[0183] In addition, since the shielding electrode SHL_2 is connected to the power supply electrode E-VSS but is not directly connected to the second electrode CE, the shape of the shielding electrode SHL_2 (or the shape of each of the second through holes H_VIA2 of the shielding electrode SHL_2) can be free (e.g., subject to fewer design constraints) compared to the shape of each of the first through holes H_VIA1 connecting the electrode E-CNT.

[0184] Fig.18 is a diagram showing a method according to some exemplary embodiments Fig.12 A plan view of yet another example of a display module. Fig.19 is a diagram showing a method of implementing ... Fig.18 A cross-sectional view of an example of a display module taken along the section line CC' in FIG. Fig. 20 is a diagram showing a method according to some exemplary embodiments Fig.12 A plan view of another example of a display module. Fig.18 and Fig. 20 (Its depiction corresponds to Fig.14) shows that the shielding electrode SHL_3, the connection electrode E-CNT or E-CNT_1, and the second electrode CE included in the display module DM_3 or DM_3_1 overlap each other.

[0185] First, refer to Figures 18 to 20 , Fig.18 Display module DM_3 or Fig. 20 The display module DM_3_1 and Fig.14 The display module DM of the embodiment of the present invention is different in that the display module DM_3 or DM_3_1 includes a shielding electrode SHL_3. In addition to including a third through hole H_VIA3 ​​in the shielding electrode SHL_3 compared to the second through hole H_VIA2 in the shielding electrode SHL_2, the shielding electrode SHL_3 may be the same as that already mentioned in reference. Fig.16 The shielding electrode SHL_2 described is substantially the same. Therefore, a redundant description will not be repeated.

[0186] A plurality of third through holes H_VIA3 ​​are defined in the shielding electrode SHL_3. The third through holes H_VIA3 ​​of the shielding electrode SHL_3 may be covered by the connection electrode E-CNT or E-CNT_1. The third through holes H_VIA3 ​​of the shielding electrode SHL_3 may be arranged to be interlaced with the first through holes H_VIA1 in the connection electrode E-CNT or the fourth through holes H_VIA4 in the connection electrode E-CNT_1. For example, the third through holes H_VIA3 ​​may be provided between the rows H-L1 to H-L4 of the connection electrode E-CNT or E-CNT_1.

[0187] Each third through hole H_VIA3 ​​may have a rectangular shape in which the length in the second direction DR2 is greater than the width in the first direction DR1. For example, each third through hole H_VIA3 ​​is a slit, and only one third through hole H_VIA3 ​​may be provided in a row. Each third through hole H_VIA3 ​​may correspond to all first through holes H_VIA1 included in a row (e.g., the first row H-L1) of the connection electrodes E-CNT or each fourth through hole H_VIA4 included in a row (e.g., the first row H-L1) of the connection electrodes E-CNT_1.

[0188] With respect to at least the display module DM_3, the second width W2 of each third through hole H_VIA3 ​​in the first direction DR1 may be smaller than the first width W1 of each first through hole H_VIA1 in the first direction DR1. However, since each third through hole H_VIA3 ​​has a shape elongated in the second direction DR2, the area of ​​each third through hole H_VIA3 ​​is greater than or equal to the total area of ​​the first through holes H_VIA1 included in one row (e.g., the first row H-L1) of the connection electrodes E-CNT. Since each third through hole H_VIA3 ​​has a relatively large area, the gas generated in the process of forming the third insulating layer 30 may be more easily discharged through the third through hole H_VIA3, and the noise propagating from the scan driving circuit GDC toward the input sensing unit TS may be more effectively blocked.

[0189] like Fig.19 As shown in , noise can propagate from the scan driving circuit GDC along the oblique direction DRD. When the noise propagates along the oblique direction DRD, as the propagation path of the noise becomes relatively longer, the noise is weakened, but the weakened noise affects the input sensing unit TS (or the second sensing signal line SL2).

[0190] As the second width W2 of each third through hole H_VIA3 ​​decreases, the range angle (i.e., the propagation range angle) at which noise can propagate from the scan driving circuit GDC through the third through hole H_VIA3 ​​can be narrowed, and within a corresponding range (i.e., a range corresponding to the range angle), the noise passing through the third through hole H_VIA3 ​​can be blocked by the connection electrode E-CNT. The range angle at which noise propagates through the third through hole H_VIA3 ​​can be determined by the thickness of the shielding electrode SHL_3, the second width W2 of each third through hole H_VIA3, the thickness of the fourth insulating layer 40 (i.e., the thickness DR3 in the third direction), etc. As the thickness of the shielding electrode SHL_3 increases, as the second width W2 of each third through hole H_VIA3 ​​decreases, and as the thickness of the fourth insulating layer 40 (i.e., the thickness in the third direction DR3) decreases, the range angle of noise can be reduced. However, the thickness of the shielding electrode SHL_3 and the thickness of the fourth insulating layer 40 (i.e., the thickness in the third direction DR3) may be predetermined by other circuit elements (e.g., transistors and pixels PX formed in the display area DA), etc. Therefore, the range angle of noise may be reduced by reducing the second width W2 of each third through hole H_VIA3 ​​(i.e., the second width W2 that may be independently determined).

[0191] However, as the second width W2 of each third through hole H_VIA3 ​​decreases, the area of ​​each third through hole H_VIA3 ​​decreases, and therefore, the gas may not be easily discharged. Therefore, considering the ease of gas discharge, the second width W2 of each third through hole H_VIA3 ​​may be 0.3 to 0.7 times, for example, 0.4 to 0.6 times, such as 0.5 times, of the first width W1 of each first through hole H_VIA1.

[0192] Although Fig.18 , the shielding electrode SHL_3 includes a slit-type third through hole H_VIA3, but the exemplary embodiment is not limited thereto. For example, the connecting electrode E-CNT may include a slit-type first through hole H_VIA1. As another example, Fig. 20 As shown in FIG. 1 , the shielding electrode SHL_3 may include a slit-type third through hole H_VIA3 ​​, and the connection electrode E-CNT_1 may include a slit-type fourth through hole H_VIA4 .

[0193] Fig.21 is a diagram showing a method according to some exemplary embodiments Figure 3 FIG. 4 is a cross-sectional view of yet another example of a display module in which area AA is enlarged.

[0194] Reference Figures 12 to 21 , Fig.21 The display module DM_4 and Fig.12 The difference between the display module DM and the display module DM_4 is that the display module DM_4 includes a shielding electrode SHL_4. In addition to the position where the shielding electrode SHL_4 is provided and the connection relationship of the shielding electrode SHL_4, the shielding electrode SHL_4 can be the same as that already mentioned in reference Fig.12 The shielding electrodes SHL described are substantially the same or similar, and therefore, a redundant description will not be repeated.

[0195] The shielding electrode SHL_4 may not overlap with the power electrode E-VSS and may be connected to the connection electrode E-CNT through the tenth contact hole CNT10 penetrating the fourth insulating layer 40 to expose the shielding electrode SHL_4. That is, the shielding electrode SHL_4 is electrically connected to the power electrode E-VSS and may be electrically connected to the power electrode E-VSS through the connection electrode E-CNT.

[0196] In some exemplary embodiments, the tenth contact hole CNT10 may include (or be connected to) the second electrode CE, that is, may be formed adjacent to the display area DA, and may be connected to the second electrode CE. Figure 6 The ninth contact hole CNT9 described is formed by the same process. In this case, similar to Fig.12The shielding electrode SHL_4 covers the first through hole H-VIA1 of the connection electrode E-CNT, thereby preventing noise from propagating from the scan driving circuit GDC to the input sensing unit TS through the first through hole H-VIA1. In an exemplary embodiment, the tenth contact hole CNT10 may overlap the second electrode CE.

[0197] Although Fig.21 FIG. 4 shows that the shielding electrode SHL_4 is connected to the connection electrode E-CNT through a tenth contact hole CNT10, but the exemplary embodiment is not limited thereto. For example, the shielding electrode SHL_4 may be connected to the connection electrode E-CNT through a plurality of contact holes (not shown), and the plurality of contact holes may be formed along the second direction DR2. Fig.21 It is shown in FIG. 1 that the shielding electrode SHL_4 does not include the second through hole H_VIA2 (refer to Fig.16 ), but the shielding electrode SHL_4 may include a second through hole H_VIA2.

[0198] According to various exemplary embodiments, the display device may include a shielding electrode disposed between the driving circuit and the connecting electrode and overlapping the sensing signal line of the input sensing unit, thereby reducing noise that would otherwise propagate to the input sensing unit and interfere with the input sensing unit. However, it should be noted that the effects of the inventive concept are not limited to or by the above, and various other effects are contemplated herein.

[0199] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as will be apparent to those of ordinary skill in the art.

Claims

1. A display device, the display device include: A substrate layer including a display area and a non-display area; a semiconductor layer disposed on the base layer, wherein the semiconductor layer includes a semiconductor pattern disposed in the display area, A first insulating layer, disposed on the semiconductor layer; a first conductive layer disposed on the first insulating layer, the first conductive layer comprising a gate electrode overlapping the semiconductor pattern; a second insulating layer, disposed on the first conductive layer; a second conductive layer disposed on the second insulating layer, the second conductive layer comprising a first electrode connected to the semiconductor pattern and a second electrode connected to the semiconductor pattern; a third insulating layer, disposed on the second conductive layer; a third conductive layer, disposed on the third insulating layer, the third conductive layer comprising a conductive pattern disposed in the display area and connected to the second electrode; a fourth insulating layer, disposed on the third conductive layer; a fourth conductive layer disposed on the fourth insulating layer, the fourth conductive layer comprising a third electrode connected to the conductive pattern and disposed in the display area; A light-emitting layer is disposed on the third electrode, and the light-emitting layer overlaps the third electrode; as well as a fifth conductive layer, disposed on the light-emitting layer, wherein the fifth conductive layer includes a fourth electrode stacked with the light-emitting layer, Wherein, the fourth conductive layer overlaps with the third conductive layer in the non-display area, wherein the third conductive layer comprises a plurality of first holes in the non-display area, the plurality of first holes exposing the third insulating layer, and The fourth conductive layer includes a plurality of second holes in the non-display area, and the plurality of second holes expose the fourth insulating layer.

2. The display device according to claim 1, in: The plurality of first holes includes a portion that does not overlap any of the plurality of second holes in a plan view.

3. The display device according to claim 1, in: A portion of the fourth conductive layer in the non-display area directly contacts a portion of the third conductive layer in the non-display area.

4. The display device according to claim 1, in: A portion of the third conductive layer in the non-display area and a portion of the fourth conductive layer in the non-display area are configured to receive the same electrical signal.

5. The display device according to claim 1, further comprising: include: A driving circuit is arranged between the base layer and the third insulating layer, and the driving circuit is arranged in the non-display area. Wherein, the third conductive layer and the fourth conductive layer overlap with the driving circuit.

6. The display device according to claim 5, in, At least one second hole among the plurality of second holes overlaps the driving circuit.

7. The display device according to claim 5, wherein the display device further comprises: include: an initialization voltage line, arranged in the non-display area, Wherein, the initialization voltage line is arranged between the driving circuit and the display area.

8. The display device according to claim 7, in, The second conductive layer includes the initialization voltage line.

9. The display device according to claim 1, further comprising: include: A power supply electrode is arranged in the non-display area, Wherein, the third conductive layer and the fourth conductive layer overlap with the power electrode.

10. The display device according to claim 9, in, The third conductive layer directly contacts the power electrode in the non-display area, and Wherein, the fourth conductive layer directly contacts the third conductive layer in the non-display area.

11. The display device according to claim 10, in, The fifth conductive layer directly contacts the fourth conductive layer in the non-display area.

12. The display device according to claim 9, in, The second conductive layer includes the power electrode.

13. The display device according to claim 1, further comprising: include: an inorganic layer, disposed on the fifth conductive layer; as well as an input sensing layer, disposed on the inorganic layer, the input sensing layer comprising sensing electrodes and sensing signal lines connected to the sensing electrodes, The sensing signal line overlaps the fourth conductive layer and the third conductive layer in the non-display area.

14. The display device according to claim 13, in, The sensing signal line overlaps at least one first hole among the plurality of first holes.

15. The display device according to claim 13, in, The sensing signal line overlaps at least one second hole among the plurality of second holes.

16. The display device according to claim 13, in, The inorganic layer covers the third conductive layer and the fourth conductive layer in the non-display area.

17. A display device, the display device include: A substrate layer including a display area and a non-display area; a pixel circuit disposed on the surface of the substrate layer, the pixel circuit comprising a plurality of transistors in the display area; A driving circuit is arranged on the surface of the substrate layer, and the driving circuit is arranged in the non-display area; a light emitting element disposed on the pixel circuit, the light emitting element comprising a first electrode electrically connected to the pixel circuit and disposed in the display area, a light emitting layer disposed on and overlapping the first electrode, and a second electrode disposed on the light emitting layer; An input sensing layer, disposed on the light emitting element, the input sensing layer comprising a sensing electrode in the display area and a sensing signal line in the non-display area; a first conductive layer, disposed in the non-display region between the driving circuit and the sensing signal line in a first direction perpendicular to the surface of the base layer; as well as a second conductive layer disposed between the first conductive layer and the sensing signal line in the non-display region in the first direction; Wherein, the first conductive layer and the second conductive layer are arranged in the non-display area, and Each of the first conductive layer and the second conductive layer is provided in a layer different from the second electrode of the light emitting element.

18. The display device according to claim 17, in: Each of the first conductive layer, the second conductive layer, and the second electrode of the light emitting element receives a voltage of the same level.

19. The display device according to claim 17, in: The first conductive layer includes a plurality of first holes in the non-display area, and The second conductive layer includes a plurality of second holes in the non-display area.

20. The display device according to claim 19, in: The plurality of first holes include a portion that does not overlap with any of the plurality of second holes in the first direction.

21. The display device according to claim 19, in: At least two first holes of the plurality of first holes and at least two second holes of the plurality of second holes overlap the driving circuit in the first direction.

22. The display device according to claim 17, wherein the display device further comprises: include: A first insulating layer, disposed on the pixel circuit and the driving circuit; as well as a second insulating layer, disposed on the first insulating layer, Wherein, the first conductive layer is disposed between the first insulating layer and the second insulating layer, and Wherein, the second insulating layer is arranged between the second conductive layer and the first conductive layer.

23. The display device according to claim 22, wherein the display device further comprises: include: a conductive pattern, arranged between the first insulating layer and the second insulating layer in the display area, The conductive pattern is directly connected to one of the plurality of transistors.

24. The display device according to claim 23, in, The first conductive layer and the conductive pattern are directly disposed on the first insulating layer.

25. The display device according to claim 24, in, The first electrode of the light emitting element directly contacts the conductive pattern, and The first electrode of the light emitting element and the second conductive layer are directly disposed on the second insulating layer.

26. The display device according to claim 22, in, A portion of the second conductive layer is provided between the second insulating layer and the second electrode of the light emitting element in the first direction.

27. The display device according to claim 26, in, The second conductive layer directly contacts the second electrode of the light emitting element in the non-display area.

28. The display device according to claim 17, in: A portion of the first conductive layer directly contacts a portion of the second conductive layer in the non-display area.

29. The display device according to claim 17, wherein the display device further comprises: include: an initialization voltage line, arranged in the non-display area, Wherein, the initialization voltage line is arranged between the driving circuit and the display area.

30. The display device according to claim 29, in, The initialization voltage line is disposed closer to the surface of the base layer than the first conductive layer.

31. The display device according to claim 17, wherein the display device further comprises: include: A power supply electrode is arranged in the non-display area, The first conductive layer and the second conductive layer overlap with the power electrode in the first direction.

32. The display device according to claim 31, in, The first conductive layer directly contacts the power electrode in the non-display area, and Wherein, the second conductive layer directly contacts the first conductive layer in the non-display area.

33. The display device according to claim 32, in, The second conductive layer directly contacts the second electrode of the light emitting element in the non-display area.

34. The display device according to claim 32, in, The power electrode is disposed between the base layer and the first conductive layer.

35. The display device according to claim 17, further comprising: include: an inorganic layer, disposed between the input sensing layer and the light emitting element, Wherein, the second conductive layer directly contacts the inorganic layer in the non-display area.

36. An electronic device, comprising a display device, in, The display device comprises: A substrate layer including a display area and a non-display area; a semiconductor layer disposed on the base layer, wherein the semiconductor layer includes a semiconductor pattern disposed in the display area, A first insulating layer, disposed on the semiconductor layer; a first conductive layer disposed on the first insulating layer, the first conductive layer comprising a gate electrode overlapping the semiconductor pattern; a second insulating layer, disposed on the first conductive layer; a second conductive layer disposed on the second insulating layer, the second conductive layer comprising a first electrode connected to the semiconductor pattern and a second electrode connected to the semiconductor pattern; a third insulating layer, disposed on the second conductive layer; a third conductive layer, disposed on the third insulating layer, the third conductive layer comprising a conductive pattern disposed in the display area and connected to the second electrode; a fourth insulating layer, disposed on the third conductive layer; a fourth conductive layer disposed on the fourth insulating layer, the fourth conductive layer comprising a third electrode connected to the conductive pattern and disposed in the display area; a light-emitting layer, disposed on the third electrode, wherein the light-emitting layer overlaps the third electrode; and a fifth conductive layer, disposed on the light-emitting layer, wherein the fifth conductive layer includes a fourth electrode stacked with the light-emitting layer, Wherein, the fourth conductive layer overlaps with the third conductive layer in the non-display area, wherein the third conductive layer comprises a plurality of first holes in the non-display area, the plurality of first holes exposing the third insulating layer, and The fourth conductive layer includes a plurality of second holes in the non-display area, and the plurality of second holes expose the fourth insulating layer.

37. The electronic device according to claim 36, in, The electronic device is one of a mobile phone terminal, a television, a monitor, a tablet computer, a car navigation system, a game console, and a smart watch.

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