Bit length control for affine merge candidate derivation based on linear regression

Abstract

An example apparatus for coding video data includes a memory configured to store video data and one or more processors communicatively coupled to the memory. The one or more processors are configured to reduce a bit length of one or more input variables of a linear regression operation to generate one or more reduced bit length input variables including at least one of a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing a number of sub-blocks. The one or more processors are configured to perform a linear regression operation and derive an affine motion model based on performing a linear regression on the one or more reduced bit length input variables. The one or more processors are configured to code a current block of video data based on an affine motion model.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to U.S. Patent Application 18 / 481,590, filed on October 5, 2023, and U.S. Provisional Patent Application 63 / 379,555, filed on October 14, 2022, the entire contents of which are incorporated herein by reference. U.S. Patent Application 18 / 481,590, filed on October 5, 2023, claims the benefit of U.S. Provisional Patent Application 63 / 379,555, filed on October 14, 2022. Technical field

[0003] This disclosure relates to video encoding and video decoding. Background art

[0004] Digital video capabilities can be incorporated into a variety of devices, including digital televisions, digital live systems, wireless broadcast systems, personal digital assistants (PDAs), laptop or desktop computers, tablet computers, e - book readers, digital cameras, digital recording devices, digital media players, video game devices, electronic game consoles, cellular or satellite wireless telephones, so - called "smart phones", video teleconferencing devices, video streaming devices, etc. Digital video devices implement video encoding techniques, such as those described in standards defined by MPEG - 2, MPEG - 4, ITU - T H.263, ITU - T H.264 / MPEG - 4, Part 10, Advanced Video Coding (AVC), ITU - T H.265 / High Efficiency Video Coding (HEVC), ITU - T H.266 / Versatile Video Coding (VVC), and extensions of these standards, as well as proprietary video codecs / formats, such as AOMedia Video 1 (AV1) developed by the Alliance for Open Media. By implementing such video encoding techniques, video devices can more efficiently transmit, receive, encode, decode, and / or store digital video information.

[0005] Video encoding techniques include spatial (intra - picture) prediction and / or temporal (inter - picture) prediction to reduce or eliminate redundancy inherent in a video sequence. For block - based video coding, a video strip (e.g., a video picture or a portion of a video picture) can be segmented into video blocks, which may also be referred to as coding tree units (CTUs), coding units (CUs), and / or coding nodes. Video blocks in an intra - coded (I) strip of a picture are encoded using spatial prediction relative to reference samples in adjacent blocks within the same picture. Video blocks in an inter - coded (P or B) strip of a picture can be encoded using spatial prediction relative to reference samples in adjacent blocks within the same picture or temporal prediction relative to reference samples in other reference pictures. A picture can be referred to as a frame, and a reference picture can be referred to as a reference frame. SUMMARY OF THE INVENTION

[0006] In general, the present disclosure describes techniques for bit length control of affine merge candidate derivation based on linear regression. For example, the techniques described herein can apply bit length control to input variables and intermediate results in order to meet commonly defined bit length thresholds, e.g., for hardware implementation of a video coder (e.g., a video encoder and / or a video decoder). A video coder may use many different determinations and computations to encode and / or decode video data. When implementing such a video encoder in hardware, it may be impractical or impossible to successfully implement the video coder without (a) constraint(s) on the bit length of the input value(s) and / or intermediate value(s). For example, without limiting the bit length, some determinations and / or computations may result in data overflow. Thus, it may be desirable to keep the bit length of values in a hardware-implemented video coder at 64 bits or less such that the video coder can be successfully implemented in hardware. The present disclosure describes techniques for controlling the bit length of input and intermediate values for affine merge candidate derivation based on linear regression.

[0007] In one example, a method includes: controlling the bit length of input variables of a linear regression operation, the input variables including at least one of a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing the number of sub-blocks; performing a linear regression operation on the input variables with the controlled bit length; deriving an affine motion model based on performing the linear regression operation; and decoding a current block of video data based on the affine motion model.

[0008] In another example, a device includes a memory configured to store video data, and one or more processors communicatively coupled to the memory, the one or more processors being configured to: control the bit length of input variables for a linear regression operation, the input variables including at least one of a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing the number of sub-blocks; perform a linear regression operation on the input variables with the controlled bit length; derive an affine motion model based on performing the linear regression operation; and encode a current block of video data based on the affine motion model.

[0009] In another example, an apparatus includes: an apparatus for controlling a bit length of input variables of a linear regression operation to generate one or more input variables with reduced bit lengths, where the one or more input variables include at least one of a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing a number of sub-blocks; an apparatus for performing a linear regression operation on the input variables with controlled bit lengths; an apparatus for deriving an affine motion model based on performing the linear regression operation; and an apparatus for encoding a current block of video data based on the affine motion model.

[0010] In another example, a computer-readable storage medium is encoded with instructions that, when executed, cause one or more programmable processors to: control a bit length of input variables of a linear regression operation to generate one or more input variables with reduced bit lengths, where the input variables include at least one of a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing a number of sub-blocks; perform a linear regression operation on the input variables with controlled bit lengths; derive an affine motion model based on performing the linear regression operation; and decode a current block of video data based on the affine motion model.

[0011] Details of one or more examples are set forth in the accompanying drawings and the following description. Other features, objects, and advantages will be apparent from the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram illustrating an example video encoding and decoding system that can execute the techniques of the present invention.

[0013] Figures 2A - 2B is a conceptual diagram illustrating an example of sub-block based temporal motion vector prediction.

[0014] Figure 3 is a conceptual diagram showing example positions of spatial inheritance affine merge candidates.

[0015] Figure 4 is a conceptual diagram showing example positions of candidate positions of a constructed affine merge pattern.

[0016] Figure 5 is a conceptual diagram showing an example template in a reference picture and example reference sample points of the template.

[0017] Figure 6 is a conceptual diagram illustrating an example template and example template reference points of a block with sub-block motion using motion information of sub-blocks of a current block.

[0018] Figure 7 is a conceptual diagram illustrating example non-neighboring spatially adjacent blocks for deriving non-neighboring affine candidates.

[0019] Figure 8 is a conceptual diagram showing other example non - adjacent spatially - adjacent blocks for deriving non - adjacent affine candidates.

[0020] Figure 9 is a conceptual diagram showing example adjacent - block positions for obtaining motion information to construct affine - history - merge candidates.

[0021] Figure 10 is a conceptual diagram showing an example of searching for non - adjacent affine CUs and using motion information to derive non - refined candidates.

[0022] Figure 11 is a conceptual diagram showing an example of sub - block information for deriving refined candidates.

[0023] Figure 12 is a flowchart showing an example bit - length control technique for affine - merge - candidate derivation based on linear regression according to one or more aspects of the present disclosure.

[0024] Figure 13 is a block diagram illustrating an example video encoder that can execute the techniques of the present invention.

[0025] Figure 14 is a block diagram illustrating an example video decoder that can execute the techniques of the present invention.

[0026] Figure 15 is a flowchart showing an example method for encoding a current block according to the techniques of the present disclosure.

[0027] Figure 16 is a flowchart showing an example method for decoding a current block according to the techniques of the present disclosure. Detailed Description

[0028] Some video coding techniques are defined to use bit lengths that may be impractical or impossible to implement in hardware, such as when performing affine merge candidate derivation based on linear regression. Thus, the techniques described herein can apply bit length control to input variables and / or intermediate results to meet a generally defined bit length threshold, e.g., for hardware implementation of a video codec (e.g., a video encoder and / or a video decoder). The generally defined bit length threshold can be a threshold that is actually implemented in a hardware-based video codec. Since not restricting the bit lengths of input variables and / or intermediate results can lead to data overflow, it may be desirable to define a common bit length threshold. Different implementations can address data overflow in different ways, which may cause one decoder to decode the same encoded video data differently from another decoder. Thus, it may be desirable to restrict the bit lengths of input variables and / or intermediate results to meet the generally defined bit length threshold.

[0029] Thus, this disclosure describes techniques for keeping the bit lengths of values used in affine merge candidate derivation based on linear regression from exceeding a generally defined bit length threshold, thereby facilitating hardware implementation of such video codecs. For example, in a mobile device, hardware implementation may be more desirable than software implementation because hardware implementation may be more processing power efficient than software implementation.

[0030] Figure 1 is a block diagram illustrating an example video encoding and decoding system 100 that can execute the techniques of the present invention. The techniques of the present invention are generally directed to coding (encoding and / or decoding) video data. Generally, video data includes any data for processing video. Thus, video data can include raw, unencoded video, encoded video, decoded (e.g., reconstructed) video, and video metadata, such as signaling data.

[0031] As Figure 1 shown, in this example, system 100 includes a source device 102 that provides encoded video data to be decoded and displayed by a destination device 116. Specifically, source device 102 provides video data to destination device 116 via a computer-readable medium 110. Source device 102 and destination device 116 can be or include any of a variety of devices, such as a desktop computer, a notebook (i.e., laptop) computer, a mobile device, a tablet computer, a set-top box, a cellular phone such as a smart phone, a television, a camera, a display device, a digital media player, a video game console, a video streaming device, a broadcast receiver device, etc. In some cases, source device 102 and destination device 116 can be equipped for wireless communication and thus can be referred to as wireless communication devices.

[0032] In Figure 1In the example, source device 102 includes video source 104, memory 106, video encoder 200, and output interface 108. Destination device 116 includes input interface 122, video decoder 300, memory 120, and display device 118. According to the present invention, video encoder 200 of source device 102 and video decoder 300 of destination device 116 can be configured to apply the technology of bit length control solution to affine merge candidate derivation based on linear regression. Thus, source device 102 represents an example of a video encoding device, while destination device 116 represents an example of a video decoding device. In other examples, the source device and the destination device may include other components or arrangements. For example, source device 102 may receive video data from an external video source (e.g., an external camera). Similarly, destination device 116 may interface with an external display device instead of including an integrated display device.

[0033] As Figure 1 shown, system 100 is merely an example. In general, any digital video encoding and / or decoding device can perform the technology of bit length control solution for affine merge candidate derivation based on linear regression. Source device 102 and destination device 116 are merely examples of such decoding devices, where source device 102 generates decoded video data for transmission to destination device 116. The present disclosure refers to a "decoding" device as a device that performs decoding (encoding and / or decoding) of data. Thus, video encoder 200 and video decoder 300 respectively represent examples of decoding devices, specifically, a video encoder and a video decoder. In some examples, source device 102 and destination device 116 may operate in a substantially symmetric manner such that each of source device 102 and destination device 116 includes video encoding and decoding components. Thus, system 100 can support one-way or two-way video transmission between source device 102 and destination device 116, e.g., for video streaming, video playback, video broadcast, or video telephony.

[0034] In general, video source 104 represents a video data source (i.e., raw, unencoded video data) and provides a continuous series of pictures (also referred to as "frames") of video data to video encoder 200, which encodes the data of the pictures. The video source 104 of source device 102 may include a video capture device, such as a camera, a video archive containing previously captured raw video, and / or a video feed interface that receives video from a video content provider. As a further alternative, the video source 104 may generate computer graphics-based data as the source video, or a combination of live video, archived video, and computer-generated video. In each case, the video encoder 200 encodes the captured, pre-captured, or computer-generated video data. The video encoder 200 may reorder the pictures from the received order (sometimes referred to as "display order") into a decoding order for decoding. The video encoder 200 may generate a bitstream including the encoded video data. The source device 102 may then output the encoded video data via output interface 108 onto a computer-readable medium 110 for reception and / or retrieval by, for example, input interface 122 of destination device 116.

[0035] The memory 106 of source device 102 and the memory 120 of destination device 116 represent general-purpose memories. In some examples, the memories 106, 120 may store raw video data, such as raw video from video source 104 and raw decoded video data from video decoder 300. Additionally or optionally, the memories 106, 120 may store software instructions executable by, for example, video encoder 200 and video decoder 300. Although in this example, the memory 106 and the memory 120 are shown as separate from the video encoder 200 and the video decoder 300, it should be understood that the video encoder 200 and the video decoder 300 may also include internal memories for functionally similar or equivalent purposes. Further, the memories 106, 120 may store encoded video data, e.g., data output from video encoder 200 and input to video decoder 300. In some examples, portions of the memories 106, 120 may be allocated as one or more video buffers, e.g., for storing raw, decoded, and / or encoded video data.

[0036] Computer-readable medium 110 may represent any type of medium or device capable of transferring encoded video data from source device 102 to destination device 116. In one example, computer-readable medium 110 represents a communication medium that enables source device 102 to transfer encoded video data directly to destination device 116 in real time, such as via a radio frequency network or a computer-based network. According to a communication standard such as a wireless communication protocol, output interface 108 may modulate a transmission signal including the encoded video data, and input interface 122 may demodulate the received transmission signal. The communication medium may include any wireless or wired communication medium, such as the radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network, such as a local area network, a wide area network, or a global network such as the Internet. The communication medium may include routers, switches, base stations, or any other devices that may be used to facilitate communication from source device 102 to destination device 116.

[0037] In some examples, source device 102 may output encoded data from output interface 108 to storage device 112. Similarly, destination device 116 may access the encoded data from storage device 112 via input interface 122. Storage device 112 may include any of a variety of distributed or locally accessible data storage media, such as a hard disk drive, a Blu-ray disc, a DVD, a CD-ROM, flash memory, volatile or non-volatile memory, or any other suitable digital storage media for storing encoded video data.

[0038] In some examples, source device 102 may output encoded video data to file server 114 or another intermediate storage device that may store the encoded video data generated by source device 102. Destination device 116 may access the stored video data from file server 114 by streaming or downloading.

[0039] File server 114 may be any type of server device capable of storing encoded video data and transferring the encoded video data to destination device 116. File server 114 may represent a web server (e.g., for a website), a server configured to provide a file transfer protocol service (e.g., File Transfer Protocol (FTP) or File Delivery over Unidirectional Transport (FLUTE) protocol), a content delivery network (CDN) device, a Hypertext Transfer Protocol (HTTP) server, a Multimedia Broadcast Multicast Service (MBMS) or Enhanced MBMS (eMBMS) server, and / or a Network Attached Storage (NAS) device. File server 114 may additionally or optionally implement one or more HTTP streaming protocols, such as HTTP-based Dynamic Adaptive Streaming over HTTP (DASH), HTTP Live Streaming (HLS), Real Time Streaming Protocol (RTSP), HTTP Dynamic Streaming, etc.

[0040] The target device 116 can access the encoded video data from the file server 114 via any standard data connection, including an Internet connection. This can include a wireless channel (e.g., Wi-Fi connection), a wired connection (e.g., Digital Subscriber Line (DSL), cable modem, etc.), or a combination of both suitable for accessing the encoded video data stored on the file server 114. The input interface 122 can be configured to operate according to any one or more of the various protocols discussed above for retrieving or receiving media data from the file server 114, or other such protocols for retrieving media data.

[0041] The output interface 108 and the input interface 122 can represent a wireless transmitter / receiver, a modem, a wired network component (e.g., an Ethernet card), a wireless communication component operating according to any one of the various IEEE 802.11 standards, or other physical components. In an example where the output interface 108 and the input interface 122 include wireless components, the output interface 108 and the input interface 122 can be configured to transmit data (e.g., encoded video data) according to a cellular communication standard (e.g., 4G, 4G-LTE (Long Term Evolution), LTE-Advanced, 5G, etc.). In some examples where the output interface 108 includes a wireless transmitter, the output interface 108 and the input interface 122 can be configured to transmit data, such as encoded video data, according to other wireless standards, such as the IEEE 802.11 specification, the IEEE 802.15 specification (e.g., ZigBee TM ), Bluetooth TM standard, etc. In some examples, the source device 102 and / or the target device 116 can include respective System-on-Chip (SoC) devices. For example, the source device 102 can include an SoC device to perform the functions attributed to the video encoder 200 and / or the output interface 108, and the target device 116 can include an SoC device to perform the functions attributed to the video decoder 300 and / or the input interface 122.

[0042] The techniques of the present invention can be applied to support video decoding for any one of a variety of multimedia applications, such as over-the-air television broadcasting, cable television transmission, satellite television transmission, Internet streaming video transmission (e.g., Dynamic Adaptive Streaming over HTTP (DASH)), digital video encoded onto a data storage medium, decoding of digital video stored on a data storage medium, or other applications.

[0043] The input interface 122 of the target device 116 receives an encoded video bitstream from a computer-readable medium 110 (e.g., a communication medium, a storage device 112, a file server 114, etc.). The encoded video bitstream may contain signaling information defined by the video encoder 200, which is also used by the video decoder 300, such as syntax elements having values that describe the characteristics and / or processing of video blocks or other decoding units (e.g., slices, pictures, groups of pictures, sequences, etc.). The display device 118 displays decoded pictures of the decoded video data to the user. The display device 118 may represent any of a variety of display devices, such as a liquid crystal display (LCD), a plasma display, an organic light-emitting diode (OLED) display, or other types of display devices.

[0044] Although Figure 1 not shown in, in some examples, the video encoder 200 and the video decoder 300 may each be integrated with an audio encoder and / or an audio decoder and may include appropriate MUX-DEMUX units or other hardware and / or software to process a multiplexed stream that includes audio and video in a common data stream.

[0045] Both the video encoder 200 and the video decoder 300 may be implemented as any of a variety of suitable encoder and / or decoder circuits, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware, or any combination thereof. When these techniques are implemented partially in software, the device may store the instructions of the software in a suitable non-transitory computer-readable medium and execute these instructions in hardware using one or more processors to perform the techniques of the present disclosure. Each of the video encoder 200 and the video decoder 300 may be included in one or more encoders or decoders, any of which may be integrated as part of a combined encoder / decoder (codec) in a corresponding device. A device including the video encoder 200 and / or the video decoder 300 may implement the video encoder 200 and / or the video decoder 300 in a processing circuit such as an integrated circuit and / or a microprocessor. Such a device may be a wireless communication device, such as a cellular phone, or any other type of device described herein.

[0046] The video encoder 200 and the video decoder 300 may operate according to a video coding standard, such as ITU-T H.265, also known as High Efficiency Video Coding (HEVC) or an extension thereof, such as multi-view and / or scalable video coding extensions. Optionally, the video encoder 200 and the video decoder 300 may operate according to other proprietary or industry standards, such as ITU-T H.266, also known as Versatile Video Coding (VVC). In other examples, the video encoder 200 and the video decoder 300 may operate according to a proprietary video codec / format, such as AOMedia Video 1 (AV1), an extension of AV1, and / or a subsequent version of AV1 (e.g., AV2). In other examples, the video encoder 200 and the video decoder 300 may operate according to other proprietary formats or industry standards. However, the techniques of the present disclosure are not limited to any particular coding standard or format. Generally, the video encoder 200 and the video decoder 300 may be configured to perform the techniques of the present invention in conjunction with any video coding technique that uses affine merge candidate derivation based on linear regression. For example, the bit length control techniques disclosed herein may be used to meet a generally defined bit length threshold.

[0047] Generally, the video encoder 200 and the video decoder 300 may perform block-based coding of pictures. The term "block" generally refers to a structure that includes data to be processed (e.g., data to be encoded, decoded, or used during encoding and / or decoding). For example, a block may include a two-dimensional matrix of luminance and / or chrominance data samples. Generally, the video encoder 200 and the video decoder 300 may code video data represented in the YUV (e.g., Y, Cb, Cr) format. That is, the video encoder 200 and the video decoder 300 may code the luminance and chrominance components, rather than the red, green, and blue (RGB) data of the picture samples, where the chrominance components may include red hue and blue hue chrominance components. In some examples, the video encoder 200 converts the received RGB format data into a YUV representation before encoding, and the video decoder 300 converts the YUV representation into the RGB format. Optionally, preprocessing and postprocessing units (not shown) may perform these conversions.

[0048] The present disclosure may generally relate to the coding (e.g., encoding and decoding) of pictures, including the process of encoding or decoding the data of a picture. Similarly, the present invention may relate to the coding of blocks of a picture, including the process of encoding or decoding the data of a block, such as prediction and / or residual coding. The encoded video bitstream generally includes a series of values representing coding decisions (e.g., coding modes) and syntax elements that partition the picture into blocks. Therefore, a reference to a coded picture or block should generally be understood as a reference to the coded values of the syntax elements that form the picture or block.

[0049] HEVC defines various blocks, including coding units (CUs), prediction units (PUs), and transform units (TUs). According to HEVC, a video coder (e.g., video encoder 200) divides a coding tree unit (CTU) into CUs according to a quadtree structure. That is, the video coder divides the CTU and CUs into four equal, non-overlapping squares, and each node of the quadtree has zero or four children. A node without children may be referred to as a "leaf node", and the CU of such a leaf node may include one or more PUs and / or one or more TUs. The video coder may further divide the PUs and TUs. For example, in HEVC, the residual quadtree (RQT) represents the division of TUs. In HEVC, the PU represents inter-prediction data, while the TU represents residual data. The CU predicted intra-frame contains intra-frame prediction information, such as an intra-mode indicator.

[0050] As another example, video encoder 200 and video decoder 300 may be configured to operate according to VVC. According to VVC, a video coder (e.g., video encoder 200) divides a picture into a plurality of CTUs. Video encoder 200 may divide the CTUs according to a tree structure such as a quadtree-binary tree (QTBT) structure or a multi-type tree (MTT) structure. The QTBT structure eliminates the concept of multiple division types, such as the separation between the CU, PU, and TU in HEVC. The QTBT structure includes two layers: a first layer divided according to quadtree division, and a second layer divided according to binary tree division. The root node of the QTBT structure corresponds to the CTU. The leaf nodes of the binary tree correspond to the CUs.

[0051] In the MTT division structure, quadtree (QT) division, binary tree (BT) division, and one or more ternary tree (TT) (also referred to as ternary tree (TT)) divisions may be used to divide the blocks. Ternary or ternary tree division is a division that divides a block into three sub-blocks. In some examples, the ternary or ternary tree division divides the block into three sub-blocks without dividing the original block through the center. The division types in the MTT (e.g., QT, BT, and TT) may be symmetric or asymmetric.

[0052] When operating according to the AV1 codec, the video encoder 200 and the video decoder 300 may be configured to decode video data in blocks. In AV1, the largest decoding block that can be processed is called a superblock. In AV1, a superblock can be 128x128 luma samples or 64x64 luma samples. However, in subsequent video coding formats (e.g., AV2), the superblock may be defined by a different (e.g., larger) luma sample size. In some examples, the superblock is the top level of a block quadtree. The video encoder 200 may further divide the superblock into smaller decoding blocks. The video encoder 200 may divide the superblock and other decoding blocks into smaller blocks using square or non-square partitioning. Non-square blocks may include N / 2xN, NxN / 2, N / 4xN, and NxN / 4 blocks. The video encoder 200 and the video decoder 300 may perform separate prediction and transform processes on each decoding block.

[0053] AV1 also defines slices of video data. A slice is a rectangular array of superblocks that can be decoded independently of other slices. That is, the video encoder 200 and the video decoder 300 may encode and decode the decoding blocks within a slice respectively without using video data from other slices. However, the video encoder 200 and the video decoder 300 may perform filtering across slice boundaries. Slices may be uniform or non-uniform in size. Slice-based coding may enable parallel processing and / or multithreading in encoder and decoder implementations.

[0054] In some examples, the video encoder 200 and the video decoder 300 may use a single QTBT or MTT structure to represent each of the luma and chroma components, while in other examples, the video encoder 200 and the video decoder 300 may use two or more QTBT or MTT structures, such as one QTBT / MTT structure for the luma component and another QTBT / MTT structure for the two chroma components (or two QTBT / MTT structures for the respective chroma components).

[0055] The video encoder 200 and the video decoder 300 may be configured to use quadtree partitioning, QTBT partitioning, MTT partitioning, superblock partitioning, or other partitioning structures.

[0056] In some examples, a CTU includes a coding tree block (CTB) of luma samples, two corresponding CTBs of chroma samples of a picture having three sample arrays, or a CTB of samples of a monochrome picture or a picture decoded using three separate color planes and a syntax structure for decoding samples. For a certain value of N, a CTB can be an N×N sample block, such that partitioning a component into CTBs is a segmentation. A component is an array or a single sample that is one of the three arrays (luma and two chromas) that make up a picture in 4:2:0, 4:2:2, or 4:4:4 color format, or an array or a single sample of an array that makes up a monochrome format picture. In some examples, for some values of M and N, a decoding block is an M×N sample block, such that partitioning a CTB into decoding blocks is a segmentation.

[0057] Blocks (e.g., CTUs or CUs) can be grouped in various ways in a picture. As an example, a brick can refer to a rectangular region of CTU rows within a particular slice in a picture. A tile can be a rectangular CTU region within a particular tile column and a particular tile row in a picture. A slice column refers to a rectangular region of CTUs that has a height equal to the height of the picture and a width specified by a syntax element (e.g., a syntax element such as in a picture parameter set). A slice row refers to a rectangular region of CTUs that has a height specified by a syntax element (e.g., such as in a picture parameter set) and a width equal to the width of the picture.

[0058] In some examples, a tile can be divided into multiple bricks, and each brick can include one or more CTU rows within the tile. A brick that is not divided into multiple bricks can also be referred to as a brick. However, a brick that is a true subset of a tile may not be referred to as a tile. Bricks in a picture can also be arranged in a slice. A slice can be an integer number of bricks of a picture, which can be exclusively contained within a single network abstraction layer (NAL) unit. In some examples, a slice includes multiple complete tiles or a contiguous sequence of complete bricks of only one tile.

[0059] The present invention interchangeably uses "NxN" and "N by N" to refer to the sample dimensions of a block (e.g., a CU or other video block) in the vertical and horizontal dimensions, e.g., 16×16 samples or 16 by 16 samples. Generally, a 16x16 CU has 16 samples in the vertical direction (y = 16) and 16 samples in the horizontal direction (x = 16). Similarly, an NxN CU typically has N samples in the vertical direction and N samples in the horizontal direction, where N represents a non-negative integer value. Samples in a CU can be arranged in rows and columns. Additionally, a CU does not need to have the same number of samples in the horizontal direction as in the vertical direction. For example, a CU can include NxM samples, where M does not necessarily equal N.

[0060] Video encoder 200 encodes video data of a CU representing prediction and / or residual information and other information. The prediction information indicates how the CU is to be predicted to form a prediction block of the CU. The residual information generally represents the sample-by-sample difference between the CU samples before encoding and the prediction block.

[0061] To predict a CU, video encoder 200 generally forms a prediction block of the CU through inter-frame prediction or intra-frame prediction. Inter-frame prediction generally refers to predicting a CU from data of a previously decoded image, while intra-frame prediction generally refers to predicting a CU from previously decoded data of the same image. To perform inter-frame prediction, video encoder 200 may use one or more motion vectors to generate a prediction block. Video encoder 200 generally performs a motion search to identify a reference block that closely matches the CU, for example, in terms of the difference between the CU and the reference block. Video encoder 200 may calculate a difference metric using the sum of absolute differences (SAD), sum of squared differences (SSD), mean absolute difference (MAD), mean squared difference (MSD), or other such difference calculations to determine whether the reference block closely matches the current CU. In some examples, video encoder 200 may use uni-directional prediction or bi-directional prediction to predict the current CU.

[0062] Some examples of VVC also provide an affine motion compensation mode, which can be regarded as an inter-frame prediction mode. In the affine motion compensation mode, video encoder 200 may determine two or more motion vectors representing non-translational motion, such as zooming in or out, rotation, perspective motion, or other irregular motion types.

[0063] To perform intra-frame prediction, video encoder 200 may select an intra-frame prediction mode to generate a prediction block. Some examples of VVC provide 67 intra-frame prediction modes, including various directional modes, as well as a planar mode and a DC mode. Generally, video encoder 200 selects an intra-frame prediction mode that describes the neighboring samples of the current block (e.g., the block of the CU), and predicts the samples of the current block according to this mode. Assuming that video encoder 200 decodes CTUs and CUs in raster scan order (from left to right, top to bottom), such samples are generally above, above and to the left, or to the left of the current block in the same picture as the current block.

[0064] Video encoder 200 encodes data representing the prediction mode of the current block. For example, for an inter-frame prediction mode, video encoder 200 may encode data indicating which one of the various available inter-frame prediction modes is used, as well as the motion information of the corresponding mode. For example, for uni-directional or bi-directional inter-frame prediction, video encoder 200 may use advanced motion vector prediction (AMVP) or the merge mode to encode the motion vector. Video encoder 200 may use a similar mode to encode the motion vector of the affine motion compensation mode.

[0065] AV1 includes two general techniques for encoding and decoding the decoding blocks of video data. These two general techniques are intra prediction (e.g., intra-frame prediction or spatial prediction) and inter prediction (e.g., inter-frame prediction or temporal prediction). In the context of AV1, when predicting a block of the current frame of video data using an intra prediction mode, the video encoder 200 and the video decoder 300 do not use video data from other video data frames. For most intra prediction modes, the video encoder 200 encodes a block of the current frame based on the difference between the sample values in the current block and the predicted values generated from the reference samples in the same frame. The video encoder 200 determines the predicted values generated from the reference samples based on the intra prediction mode.

[0066] After prediction, such as intra prediction or inter prediction of a block, the video encoder 200 may calculate the residual data of the block. The residual data (e.g., residual block) represents the sample-by-sample difference between the block and the predicted block of the block, which is formed using the corresponding prediction mode. The video encoder 200 may apply one or more transforms to the residual block to generate transformed data in the transform domain rather than the sample domain. For example, the video encoder 200 may apply a discrete cosine transform (DCT), an integer transform, a wavelet transform, or a conceptually similar transform to the residual video data. Additionally, the video encoder 200 may apply a second transform after the first transform, such as a mode-dependent non-separable second transform (MDNSST), a signal-dependent transform, a Karhunen-Loeve transform (KLT), etc. The video encoder 200 generates transform coefficients after applying one or more transforms.

[0067] As described above, after any transform that generates transform coefficients, the video encoder 200 may perform quantization of the transform coefficients. Quantization generally refers to a process in which the transform coefficients are quantized to minimize as much as possible the amount of data used to represent the transform coefficients, thereby providing further compression. By performing the quantization process, the video encoder 200 may reduce the bit depth associated with some or all of the transform coefficients. For example, the video encoder 200 may round an n-bit value down to an m-bit value during quantization, where n is greater than m. In some examples, to perform quantization, the video encoder 200 may perform a bitwise right shift of the value to be quantized.

[0068] After quantization, the video encoder 200 may scan the transform coefficients to generate a one-dimensional vector from the two-dimensional matrix containing the quantized transform coefficients. The scan can be designed to place the higher energy (and thus lower frequency) transform coefficients at the front of the vector and the lower energy (and thus higher frequency) transform coefficients at the back of the vector. In some examples, the video encoder 200 may utilize a predefined scan order to scan the quantized transform coefficients to generate a serialized vector, and then entropy encode the quantized transform coefficients of the vector. In other examples, the video encoder 200 may perform an adaptive scan. After scanning the quantized transform coefficients to form a one-dimensional vector, the video encoder 200 may entropy encode the one-dimensional vector, e.g., according to context-adaptive binary arithmetic coding (CABAC). The video encoder 200 may also entropy encode the values of syntax elements that describe metadata associated with the encoded video data for use by the video decoder 300 when decoding the video data.

[0069] To perform CABAC, the video encoder 200 may assign a context within a context model to the symbol to be sent. The context may relate to, for example, whether the neighboring values of the symbol are zero values. Probability determination may be based on the context assigned to the symbol.

[0070] The video encoder 200 may further generate syntax data (e.g., block-based syntax data, picture-based syntax data, and sequence-based syntax data) to the video decoder 300, e.g., in a picture header, block header, slice header, or other syntax data (e.g., sequence parameter set (SPS), picture parameter set (PPS), or video parameter set (VPS)). The video decoder 300 may similarly decode such syntax data to determine how to decode the corresponding video data.

[0071] In this way, the video encoder 200 may generate a bitstream containing the encoded video data, e.g., syntax elements that describe the partitioning of a picture into blocks (e.g., CUs) and prediction and / or residual information for the blocks. Finally, the video decoder 300 may receive the bitstream and decode the encoded video data.

[0072] Generally, the video decoder 300 performs a process opposite to that performed by the video encoder 200 to decode the encoded video data of the bitstream. For example, the video decoder 300 may use CABAC to decode the values of the syntax elements of the bitstream in a manner generally similar (although inverse) to the CABAC encoding process of the video encoder 200. The syntax elements may define the partitioning information for partitioning a picture into CTUs and the partitioning of each CTU according to a corresponding partitioning structure (e.g., QTBT structure) to define the CUs of the CTU. The syntax elements may further define the prediction and residual information for the blocks (e.g., CUs) of the video data.

[0073] Residual information can be represented by, for example, quantized transform coefficients. The video decoder 300 may inverse quantize and inverse transform the quantized transform coefficients of a block to reproduce the residual block of the block. The video decoder 300 uses a signaling notified prediction mode (intra or inter prediction) and associated prediction information (e.g., motion information for inter prediction) to form a prediction block of the block. The video decoder 300 may then combine the prediction block and the residual block (on a sample-by-sample basis) to reproduce the original block. The video decoder 300 may perform additional processing, such as performing a deblocking process to reduce visual artifacts along block boundaries.

[0074] The present disclosure may generally refer to "signaling" certain information, such as syntax elements. The term "signaling" may generally refer to the communication of values for syntax elements and / or other data used to decode encoded video data. That is, the video encoder 200 may signal the values of syntax elements in a bitstream. Generally speaking, signaling refers to generating values in a bitstream. As described above, the source device 102 may transmit the bitstream to the destination device 116 either substantially in real time or non-real time, such as may occur when storing syntax elements to a storage device 112 for later retrieval by the destination device 116.

[0075] According to the techniques of the present invention, a video coder (e.g., the video encoder 200 or the video decoder 300) may control (e.g., reduce or limit) the bit length of input variables of a linear regression operation; perform a linear regression operation on the controlled bit length input variables; derive an affine motion model based on performing the linear regression operation; and decode a current block of video data based on the affine motion model.

[0076] Versatile Video Coding (VVC) (see, e.g., J. Chen, Y. Ye, and S.-H. Kim, "Algorithm Description of Versatile Video Coding and Test Model 9 (VTM 9)", Joint Video Team (JVT) of ITU-T SG 16 WP 3 and ISO / IEC JTC 1 / SC 29 / WG 11, 18th meeting: by teleconference, April 15 - 24, 2020, JVET-R2002), a recent video coding standard, was developed by the Joint Video Team (JVT) of ITU-T and ISO / . The VVC specification was completed in July 2020 and jointly released by ITU-T and ISO / IEC. The VVC specification defines the standard bitstream and picture formats, High-Level Syntax (HLS) and coding unit-level syntax, as well as the parsing and decoding processes. VVC also defines profile / tier / level (PTL) constraints, byte stream format, hypothetical reference decoder, and Supplemental Enhancement Information (SEI) in annexes.

[0077] Since April 2021, JVET has been developing Enhanced Compression Model (ECM) software (see, for example, M. Coban, F. L. Léannec, and J. "Algorithm Description of Enhanced Compression Model 2 (ECM 2)", Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO / IEC JTC 1 / SC 29 / WG 11, 23rd meeting: By teleconference, July 7 - 16, 2021, JVET-W2025), to enhance the compression capabilities. The coding toolset in the ECM software includes all the functional blocks in the hybrid video decoding framework (e.g., the video decoding framework using prediction), including intra prediction, inter prediction, transform and coefficient decoding, in-loop filtering, and entropy decoding. The technology of the present invention can be applied to ECM, video codecs at the prior art level, such as VVC, AV1, etc., and / or future video codecs.

[0078] Figures 2A - 2B It is a conceptual diagram illustrating an example of sub-block based temporal motion vector prediction (SbTMVP). SbTMVP predicts the motion vector of a sub-CU (e.g., a sub-block) within the current CU, as Figures 2A - 2B shown. First, the video encoder 200 or the video decoder 300 can check Figure 2A the spatial neighbor A1 of the current block 150 in . If A1 has a motion vector using the collocated image as its reference image, then that motion vector is selected as the motion offset to be applied. If no such motion is identified, then the motion offset is set to (0, 0). For example, the video encoder 200 or the video decoder 300 can determine whether A1 has a motion vector using the collocated picture as its reference picture and select the motion shift based on that determination.

[0079] Second, the motion offset identified above is added to the coordinates of the current block of the current image 154 to obtain sub-CU level motion information (motion vector and reference index) from the collocated image 152 as Figure 2B shown. For example, the video encoder 200 or the video decoder 300 can add the motion shift to the coordinates of the current block. Figure 2B The example in assumes that the motion offset is set to the motion of block A1. After identifying the motion information of the collocated sub-CU, the video encoder 200 or the video decoder 300 can convert the motion information into the motion vector and reference index of the current sub-CU in a manner similar to the TMVP (temporal motion vector prediction) process of VVC, where temporal motion scaling is applied to align the reference picture of the temporal motion vector with the reference picture of the current CU.

[0080] The SbTMVP prediction value is added as the first entry to the sub-block based merge candidate list, followed by affine merge candidates. SbTMVP differs from TMVP in two aspects: TMVP predicts motion at the CU level, while SbTMVP predicts motion at the sub-CU level. Although TMVP obtains the temporal motion vector from the collocated block in the collocated picture (the collocated block is the bottom-right or center block relative to the current CU), SbTMVP applies a motion offset before obtaining the temporal motion information from the collocated picture, where the motion offset is obtained from the motion vector of one of the spatial neighboring blocks of the current CU. For example, video encoder 200 or video decoder 300 may determine the SbTMVP prediction value and add this prediction value as the first entry to the sub-block based merge candidate list.

[0081] Now discuss the sub-block merge candidate list. The following four types of sub-block merge candidates are used to form the sub-block merge candidate list, where the first entry is SbTMVP and the other entries are affine merge candidates. The determination of SbTMVP is as described above.

[0082] The inherited affine merge candidate (I-AffineMVP) extrapolated from the CPMV (control point motion vector) of the neighboring CU can also be used in the sub-block merge candidate list. There are at most two inherited affine candidates in the sub-block merge candidate list, which are derived from the affine motion models of the neighboring blocks. For example, one from the left neighboring CU and one from the upper neighboring CU. For example, video encoder 200 or video decoder 300 may determine the inherited affine candidates and add up to two such candidates to the sub-block merge candidate list.

[0083] Figure 3 is a conceptual diagram showing the example positions of the spatial inherited affine merge candidates. Figure 3 The candidate block positions of the current block 156 are shown. For the left predictor, the scan order is A0->A1, and for the above predictor, the scan order is B0->B1->B2. Only the first inherited candidate in each group is selected. No pruning check is performed between the two inherited candidates. When the neighboring affine CU containing the scan position is identified, the control point motion vector (CPMV) from the identified affine CU is used to derive the CPMV of the affine merge candidate of the current CU (e.g., the current block 156).

[0084] Video encoder 200 or video decoder 300 may also add the constructed affine merge candidate (C-AffineMVP) derived using the translational MV of the neighboring CU to the sub-block merge candidate list. The constructed affine candidate means constructing the candidate by combining the neighboring translational motion information of each control point.

[0085] Figure 4It is a conceptual diagram showing example positions of candidate positions of the constructed affine merge mode. The motion information of the control points is derived from the specified spatial neighbors and temporal neighbors of the current block 400 shown in Figure 4 For the CPMVk (k = 1, 2, 3, 4), it represents the k-th control point. For CPMV1, check the B2->B3->A2 blocks and use the MV of the first available block. For CPMV2, check the B1->B0 module, and for CPMV3, check the A1->A0 module. If the TMVP is available, the TMVP is used as CPMV4. The following combinations of control point MVs are used to construct affine merge candidates with up to 6 different candidates in a given order: {CPMV1, CPMV2, CPMV3}, {CPMV1, CPMV2, CPMV4}, {CPMV1, CPMV3, CPMV4}, {CPMV2, CPMV3, CPMV4}, {CPMV1, CPMV2}, {CPMV1, CPMV3}. The combination of 3 CPMVs constructs 6-parameter affine merge candidates, and the combination of 2 CPMVs constructs 4-parameter affine merge candidates. To avoid the motion scaling process, if the reference indices of the control points are different, the relevant combinations of control point MVs can be discarded.

[0086] After checking the inherited affine merge candidates and the constructed affine merge candidates, if the list is not full, the video encoder 200 or the video decoder 300 can also add zero MVs to the sub-block merge candidate list. Zero MVs are inserted until the list is full.

[0087] Now discuss the adaptive reordering of merge candidates (ARMC). In ECM, the merge candidates are adaptively reordered by using template matching (TM). The reordering technique is applied to the regular merge candidate list, the TM merge candidate list, and the affine merge candidate list (e.g., the sub-block merge candidate list, excluding the SbTMVP candidates). For the TM merge mode, the merge candidates are reordered before the TM refinement process.

[0088] After the merge candidate list is constructed, the merge candidates are divided into several subgroups. For example, the video encoder 200 or the video decoder 300 can divide the merge candidates into subgroups. For the regular merge mode and the TM merge mode, the subgroup size is set to 5. For the affine merge mode, the subgroup size is set to 3. The merge candidates in each subgroup are reordered in ascending order according to the TM-based cost value. For simplicity, the merge candidates in the last subgroup rather than the first subgroup are not reordered.

[0089] As an example, the TM cost of a merge candidate can be measured by the sum of absolute differences (SAD) between the samples of the template of the current block and their corresponding reference samples. The template includes a set of reconstructed samples adjacent to the current block. The reference samples of the template are located by the motion information of the merge candidate.

[0090] Figure 5 is a conceptual diagram showing an example template in a reference picture and example reference samples of the template. When the merge candidate of the current block of the current picture 500 uses bidirectional prediction (e.g., having a reference picture in reference list 0 502 and a reference picture in reference list 1 504), the reference samples of the template of the merge candidate are also generated by bidirectional prediction, as Figure 5 shown. For a sub-block based merge candidate with a sub-block size equal to Wsub×Hsub, the above template includes several sub-templates of size Wsub×1, and the left template includes several sub-templates of size 1×Hsub. As Figure 6 shown, the motion information of the sub-blocks in the first row and the first column of the current block is used to derive the reference samples of each sub-template. For example, the video encoder 200 or the video decoder 300 can use bidirectional prediction and derive the reference samples of each sub-template.

[0091] Figure 6 is a conceptual diagram illustrating an example template and example template reference samples for a current block with sub-block motion using the motion information of the sub-blocks of the current block. The current image 602 includes a current block 600. The collocated picture 604 includes a collocated block 606. For a sub-block based merge candidate with a sub-block size equal to Wsub×Hsub, the above template includes several sub-templates 608 of size Wsub×1, and the left template includes several sub-templates 610 of size 1×Hsub. As Figure 6 shown, the motion information of the sub-blocks in the first row and the first column of the current block 600 is used to derive the reference samples of each sub-template.

[0092] Figure 7 is a conceptual diagram illustrating example non-neighboring spatially adjacent blocks for deriving non-neighboring affine candidates. Now, non-neighboring affine merge candidates are discussed. Currently, in the conventional merge list construction process of ECM, non-neighboring merge candidates are added as a new category of conventional merge candidates. For example, a non-neighboring merge candidate is a merge candidate that is not adjacent to the current block 700. As Figure 7As shown, the non - adjacent merge candidate scan pattern is used to search for non - adjacent merge candidates. Non - adjacent merge candidates may help improve the performance of the regular merge mode. Thus, video encoder 200 or video decoder 300 may search for non - adjacent affine CUs and add non - adjacent affine merge candidates to the sub - block merge candidate list to further improve the performance of the sub - block merge mode. In some examples, video encoder 200 or video decoder 300 may reuse the same non - adjacent merge scan pattern instead of searching for non - adjacent affine CUs. The scan order may follow the Figure 7 index shown therein. After finding a non - adjacent affine CU, video encoder 200 or video decoder 300 may directly derive the CPMV of the non - adjacent affine CU from the non - adjacent position to the current CU position, or derive the affine model of the current CU using the motion vector field of the non - adjacent affine CU through a linear regression process.

[0093] Figure 8 is a conceptual diagram showing other example non - adjacent spatially - adjacent blocks for deriving non - adjacent affine candidates. The extension of non - adjacent merge candidates to non - adjacent affine merge candidates has been proposed in the JVET - X meeting, and there can be various designs for the scan pattern. In "AHG12: Non - adjacent Spatial Neighbors for Affine Merge Mode" by W.Chen, X.Xiu, Y.-W.Chen, H.-J.Jhu, C.-W.Kuo, N.Yan, and X.Wang in October 2021, JVET - X0151, a scan pattern different from Figure 7 is described, as shown in Figure 8 .

[0094] The scan order may follow the Figure 8 order shown. For example, non - adjacent affine CUs may follow the Figure 8 scan order. Based on the distance from the non - adjacent spatially - adjacent blocks of the current block 800 to the current block 800, i.e., from near to far, the non - adjacent spatially - adjacent blocks of the current block 800 are examined. At a specific distance, video encoder 200 or video decoder 300 may scan horizontally from right to left and vertically from bottom to top.

[0095] By using any of the above scan patterns, (multiple) non - adjacent affine CUs can be identified, and their corresponding (multiple) motion vector fields can potentially be used as inputs to a linear regression process to derive the affine model of the current CU.

[0096] Now discuss the history-based affine merge candidates. The history merge candidates were introduced during the VVC standardization process, which buffers the motion vectors of previously decoded CUs and uses them for the motion vector prediction of the current CU. Similar to extending the non-neighboring merge candidates to non-neighboring affine merge candidates, the concept of history-based merge candidates can also be extended to history-based affine merge candidates.

[0097] Figure 9 is a conceptual diagram showing example neighboring block positions for obtaining motion information to construct affine history merge candidates. Practical examples of history-based affine merge candidate construction can be found in K. Zhang, L. Zhang, Z. Deng, N. Zhang, and Y. Wang, "Related to 3.12: Extension of Affine Model Inheritance Based on Historical Parameters", JVET-Y0161, January 2022. In this proposal, two different categories of affine history tables are proposed. In one type of affine history table, only the affine parameters from previously decoded CUs are buffered. Multiple tables are created, each corresponding to a given reference index and reference list. With this design, for a specific affine history table, all affine history entries share the same reference picture. When using the history table to construct an affine merge candidate for the current block (such as current block 900), as Figure 9 shown, the spatial neighbor block positions are first determined.

[0098] The reference list and reference index from the spatial neighbor block of the current block 900 are used to determine the affine history table. The motion vector is used as the base motion vector, and together with an entry in the affine history table, the affine merge candidate or motion vector field of the current CU can be derived. For example, the video encoder 200 or the video decoder 300 can derive the affine merge candidate or motion vector field of the current CU.

[0099] In another type of affine history table, not only the affine parameters, but also the top-left CPMV and top-left coordinates of the previously decoded CUs are buffered. The reference index and reference list are also used and will be inherited by the current CU. The affine merge candidate construction can be performed with any entry in the affine history table without additional information. The video encoder 200 or the video decoder 300 can use the buffered top-left CPMV, affine parameters, top-left coordinates, and the coordinates of the current CU to derive the affine model for the current CU. At the same time, since the top-left coordinates of the previously decoded CUs are buffered, the video encoder 200 or the video decoder 300 can also directly access the motion vector field of the decoded CUs.

[0100] Now, we discuss multiple linear regression. Multiple linear regression, also known as multiple regression, is a statistical technique that can be used to analyze the relationship between one dependent variable and several independent variables. The purpose of multiple regression analysis is to predict the value of an unknown single dependent variable using known values of independent variables. Each predicted value is weighted, where the weights represent their relative contribution to the overall prediction, and they are summed to form the prediction. Equation 1 gives the general model of multiple linear regression:

[0101] Y = a + b 1 X 1 + b 2 X 2 + … + b n X n (1)

[0102] Here, Y is the dependent variable, and X1, …, Xn are n independent variables. When calculating the weights a, b 1 , …, b n , the least squares method can be applied, where the mean square error between the statistical observation samples and the estimated values is minimized.

[0103] In VVC, block-based affine transform motion compensation prediction is applied to better represent zooming, rotation, perspective motion, and other irregular motions, where the motion vector of each sub-block is derived based on a linear model. The motion vector at the sample position (x, y) of the sub-block center is derived as:

[0104]

[0105] Here, taking mv x as an example, mv 0x , mv 1x and mv 2x are the horizontal motion vector components of the top-left, top-right, and bottom-left control point motion vectors (CPMVs), respectively, which are known for a given affine model. And W and H are the width and height of the current CU, which are also known. In this case, the equation to derive mv x can be written in the formula of linear regression. The same applies to mv y . Based on this observation, the affine motion model can be equivalently represented by two linear equations in matrix form as:

[0106]

[0107] where, respectively, and b x2 = mv 0x ; and b y2 = mv 0y .

[0108] Using the above equations, the derivation of the affine motion model can be equivalent to the derivation of certain coefficients in a linear equation. The estimation of such linear coefficients can be solved by multiple linear regression. For example, the video encoder 200 or the video decoder 300 can use multiple linear regression for affine model derivation.

[0109] To apply multiple linear regression to affine model derivation, the video encoder 200 or the video decoder 300 can collect motion vector information and its corresponding sub-block coordinates. The coordinates can be the independent variables, and the motion vector components can be the dependent variables. Given N motion vectors and their corresponding sub-block center coordinates, the affine model parameters can be derived using the following equations (for example, see R. Ghaznavi-Youvalarim, A. Aminlou, and J. Lainema, "Regression-Based Motion Vector Field for Video Coding," IEEE Transactions on Circuits and Systems for Video Technology, Vol. 31, No. 5, May 2021):

[0110]

[0111] where det(B c,d ) and det(A) are the determinants of matrix B c,d and matrix A, respectively, and both B c,d and A are 3×3 matrices. For a 3×3 matrix, the determinant can be calculated by the following equation: det(M) = (M 0,0 ×M 1,1 ×M 2,2 +M 1,0 ×M 2,1 ×M 0,2 +M 2,0 ×M 0,1 ×M 1 ,2 ), (5)

[0112] -(M 0,0 ×M 1,1 ×M 1,2 +M 1,0 ×M 0,1 ×M 2,2 +M 2,0 ×M 1,1 ×M 0,2 ), (5)

[0113] where M i,j is the element at the matrix position (i, j), and i, j ∈ {0, 1, 2}.

[0114] For the construction of matrices B c,d and A, use the following equations:

[0115]

[0116] A i,j = sumll i,j (8)

[0117]

[0118] Wherein:

[0119] Using this method, the best affine model can be derived to optimally describe the input motion vector by considering its corresponding coordinates in the sense of minimum mean square error.

[0120] For detailed illustration, an example is given here to show how to output a linear model from the input motion vector field. Assume that the video encoder 200 or the video decoder 300 has collected motion information from some motion vector fields, then N motion vectors can be expressed as {(mv x0 , mv y0 ), (mv x1 , mv y1 ), …, (mv xN-1 , mv yN-1 )}, and the corresponding center coordinates are {(x 0 , y 0 ), (x 1 , y 1 ), …, (x N-1 , y N-1 )}.

[0121] In the first step, instead of using (0, 0), which is the upper left coordinate of the entire picture, to avoid (multiple) large values in the calculation, the video encoder 200 or the video decoder 300 decides (or determines) the anchor coordinates used as the origin of the output linear model. After deriving the linear model parameters from the linear regression process, this step is also performed to facilitate the derivation of affine merge candidates. Generally, the video encoder 200 or the video decoder 300 will select the upper left coordinate of the current CU as the origin. Represented by (x tl , y tl ), the relative coordinates are calculated by subtracting (x tl , y tl ) from each sub-block center coordinate. This results in {(x 0 - x tl , y 0 - y tl ), (x 1 - x tl , y 1 - y tl ), …, (x N-1 - x tl,y N-1 -y tl )}. Let

[0122] x i ’ = x i -x tl

[0123] y i ’ = y i -y tl

[0124] where i ∈ {0, 1, …, N - 1}, then we have {(x 0 ’, y 0 ’), (x 1 ’, y 1 ’), …, (x N-1 ’, y N-1 ’)}.

[0125] For the motion vector, the video encoder 200 or the video decoder 300 can also optionally select the initial motion vector to be subtracted in order to also avoid large values in the calculation, but this is not necessary because the motion vector values are relatively small compared to the coordinate values. The motion vector may also have negative values, and subtracting a negative value from a positive value will only result in a larger positive value.

[0126] For N available neighboring MVs, the mean squared error (MSE) minimization method can be used to estimate the output linear model parameters, where the MSE is calculated as the average of the squared differences between the actual values of the estimated MVs {(mv x0 ’, mv y0 ’), (mv x1 ’, mv y1 ’), …, (mv xN-1 ’, mv yN-1 ’)} and the input MVs {(mv x0 , mv y0 ), (mv x1 , mv y1 ), …, (mv xN-1 , mv yN-1 )}.

[0127]

[0128] where c ∈ {x, y} represents the horizontal or vertical component of the motion vector.

[0129] Mathematically, the solution for MSE minimization is given by equation (4) above.

[0130] Taking the derivative of the parameter b x,0 as an example, the matrix A is given by A i,j= suml′l′ i,j Derive, with i, j ∈ {0, 1, 2}, where l′ 0 is x’ of each sub - block, l′ 1 is y’ of each sub - block, for all sub - blocks, l′ 2 = 1. The element of matrix A at position (0, 0) is represented by Similarly, other elements in matrix A can also be derived.

[0131] For matrix B, when deriving b x,0 matrix B is required x,0 . From equation (9), all matrix elements except and are equal to the elements A in matrix A . For the element i,j . Taking as an example Similarly, can be derived and

[0132] Using matrices A and B x,0 , the coefficients of the 3×3 matrix can be calculated using equation (5) and the determinant.

[0133] Applying a similar process to other coefficients, all linear model parameters can be solved

[0134] Using the estimated parameters, equation (2) can be used to derive the affine merge candidate of the current CU, where the CPMVs of the upper - left, upper - right, and lower - left are represented as (mv tl , mv tl ), (mv tr , mv tr ), (mv bl , mv bl ) equal to

[0135] (mv tl , mv tl ) = (b x2 , b y2 )

[0136] (mv tr , mv tr ) = (b x0 W + b x2 , b y0 W + b y2 )

[0137] (mvbl, mvbl) = (bx1 H + b x2 , b y1 H + b y2 )

[0138] Where W and H are the width and height of the current CU. And x and y in Equation (2) are replaced by the relative distances from the upper-left position of the current CU to the positions of the corresponding CPMVs.

[0139] Now discuss the affine merge candidates based on linear regression. In ECM6.0, the affine candidate derivation based on linear regression proposed in Y. Zhang, H. Huang, V. Seregin, M. Coban, and M. Karczewicz, "EE2-2.1: Regression-Based Affine Candidate Derivation", Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO / IEC 1 / SC 29 / WG 11, 27th Meeting: By Teleconference, July 13 - 22, 2022, JVET-AA0107 is adopted. In this proposal, two types of affine merge candidates based on linear regression are derived, namely non-refined candidates and refined candidates. For both types of candidates, the derivation process is the same, only different sub-block motion information is used as input.

[0140] Figure 10 is a conceptual diagram showing an example of searching for non-neighboring affine CUs and using motion information to derive non-refined candidates. For non-refined candidates, only the sub-block motion information from non-neighboring affine CUs is used as the input for the linear regression process. Figure 10 shows an example of the input of the linear regression process to derive the affine merge candidate based on non-refined linear regression for the current block 1000. As mentioned above, certain scan patterns can be used to search for non-neighboring affine CUs. Once a non-neighboring affine CU is identified, such as Figure 10 the block 1002 shown in, including the motion vectors of the sub-blocks represented by {(mv x0 , mv y0 ), (mv x1 , mv y1 ), …, (mv xN-1 , mv yN-1 )} and the motion information of the central coordinates of each sub-block represented by {(x 0 , y 0 ), (x 1 , y 1 ), …, (x N-1 , y N-1 )} are input into the linear regression process to derive non-refined affine merge candidates.

[0141] Figure 11It is a conceptual diagram showing an example of sub-block information for deriving refinement candidates. For refinement candidates, in addition to the motion information from sub-block 1100 with hash padding in a non-neighboring affine CU (representing non-neighboring block 1102), the motion information from template sub-block 1104 represented by the non-padded blocks in Figure 11 can be additionally included as an input to the linear regression process.

[0142] The linear regression process for deriving non-refinement and refinement candidates is the same and follows the mathematical derivation described above. The only difference is the information on which sub-blocks should be used as inputs to the linear regression process. For example, video encoder 200 or video decoder 300 can employ such a linear regression process to derive non-refinement and refinement candidates.

[0143] Generally, when implementing algorithm designs in hardware, integer operations are more preferable than floating-point operations. Within the scope of integer operation designs, only a limited (or reduced) bit length may be available. Generally for integer operations, the maximum bit length used is 64. Considering the maximum allowable values of coordinates x and y, motion vectors, and the number of input sub-blocks, when these variables exceed a certain bit length, in the linear regression process, intermediate results may exceed the maximum allowable bit length. As described above, for matrix B c,d and the construction of A, the following equations can be used:

[0144]

[0145] A i,j = sumll i,j (8)

[0146]

[0147] where:

[0148] In the current ECM design, the maximum allowable bit length of the motion vector components is 18 bits. In the linear regression process, to maintain higher precision during calculations, the input motion vector is left-shifted by 2 bits. Additionally, since incremental motion vector values can be used, incremental calculations will further increase the bit length because video encoder 200 or video decoder 300 can subtract negative values from positive values. Therefore, the input motion vector incremental components can be up to 21 bits.

[0149] For the incremental x and y coordinates, the coordinates can approach the width or height of two CTUs. The maximum allowable CTU width or height is 256, and two CTU widths or heights is 512, which requires a 10-bit binary representation. However, since the incremental x and y can only approach, but not reach, the width or height of two CTUs, the maximum number of bits required to represent the incremental x and y is 9 bits.

[0150] For the number of sub-blocks, the refined candidates require more sub-blocks than the unrefined candidates. In the extreme case, both the affine CU and the current CU are 256x256. If the sub-block width and height are equal to 4, the total number of sub-blocks N=(256 / 4*256 / 4)+(256+128*2) / 4+(256+128) / 4 = 4320. This number requires a 13-bit binary representation.

[0151] Let l 0 =x, l 1 =y and l 2 =1, the matrix A can be derived from the following equation

[0152]

[0153] For a 3×3 matrix, its determinant can be calculated using the following formula: det(A)=(M 0,0 ×M 1,1 ×M 2,2 +M 1,0 ×M 2,1 ×M 0,2 +M 2,0 ×M 0,1 ×M 1,2 )-(M 0,0 ×M 2,1 ×M 1,2 +M 1,0 ×M 0,1 ×M 2,2 +M 2,0 ×M 1,1 ×M 0,2 )

[0154] For each element in the matrix A, the maximum number of bits required to save the calculation result is as follows:

[0155] bits

[0156] Taking M 0,0 =∑x 2 as an example, the maximum number of bits required is 13+9+9 = 31 bits, where 13 is the maximum number of bits of the input sub-block, and 9 is the maximum number of bits of the incremental coordinate x or y.

[0157] Cascaded multiplication M0,0 ×M 1,1 ×M 2,2 results in the addition of the number of bits required to represent each matrix element. M 1,1 and M 2,2 require 31 bits and 13 bits respectively. Therefore, the bit length required to store the result is 31 + 31 + 13 = 75 bits, which has exceeded the 64-bit integer bit length threshold commonly used.

[0158] For matrix B c,d , the situation may be worse because the dynamic range of the incremental motion vector components is much larger than that of the incremental coordinates. As mentioned before, the number of bits required for the incremental motion vector components is 21 bits, while the number of bits required for the incremental coordinates is 9 bits. In one example, given the representation of matrix B x,0 :

[0159]

[0160] where the first column of matrix A is replaced by ∑xmv x , ∑ymv x and ∑mv x . Thus, the number of bits required for each element in matrix B x,0 is

[0161] bits

[0162] The same bit length requirement applies to other matrices B c,d , where c ∈ {x, y} indicates the horizontal and vertical incremental motion vector components, and d ∈ {0, 1, 2} indicates which column in matrix A will be replaced in deriving matrix B c,d . It is easy to see that the maximum number of bits required to store the determinant result of matrix B c,d exceeds 64 bits.

[0163] After the determined values are derived, according to Cramer’s rule, the linear regression parameters can be calculated by the equation:

[0164]

[0165] Here det(B c,d ) and det(A) represent the determinants of matrices B c,d and A. For a given motion vector component, such as the horizontal component, one of the 3 linear regression parameters can be derived without calculating the determinant of the corresponding matrix B x,d . For example, when the linear model mv x = xb x0 + yb x1 + bx2 Calculate d = 2 and b x0 and b x1 When. Cumulate each input data sample point, we have ∑mv x = b x0 ∑x + b x1 ∑y + b x2 ∑1. Denote the total number of input sub - blocks as N, where N = ∑1, we have Thus, the following equation also holds:

[0166]

[0167] According to the above equations, the video encoder 200 or the video decoder 300 can calculate 3 determinants, which are det(A), det(B x,0 ) and det(B x,1 ). ∑mv x is the matrix element of matrix B x,0 or B x,1 . ∑x and ∑y are the matrix elements in matrix A. However, the numerator of the above equation has further multiplications and additions on top of the 3×3 matrix determinant, which will further increase the maximum number of bits required to store the intermediate results.

[0168] In addition, division operations are generally not preferred in hardware implementations and are usually approximated by multiplication and right - shift. Usually, a lookup table for multiplication and a fixed number of right - shifts is used. To reuse the same logic to calculate all the linear regression parameters, the same denominator should be used for all the parameters. Therefore, the derivation of parameters b x0 and b x1 is modified as:

[0169]

[0170] Therefore, each determinant will need to be multiplied by the number of input sub - blocks, which in turn increases the bit length. In addition, as mentioned above, division is approximated by multiplication and right - shift. The multiplication before the right - shift will also end up with a higher bit - length requirement to maintain the intermediate results.

[0171] Based on the above observations, to ensure a feasible hardware implementation, bit length control may be beneficial during the linear regression process. Thus, the present disclosure describes a bit length control solution for affine merge candidate derivation based on linear regression. The bit length control is applied to input variables and intermediate results to meet the bit length thresholds typically defined in a hardware implementation. For example, the video encoder 200 or the video decoder 300 may control the bit length of the input variables of the linear regression. The video encoder 200 or the video decoder 300 may perform a linear regression on the controlled bit length input variables. The video encoder 200 or the video decoder 300 may derive an affine motion model based on performing the linear regression operation. The video encoder 200 or the video decoder 300 may decode a current block of video data based on the affine motion model. In some examples, the video encoder 200 or the video decoder 300 may determine affine motion information based on the affine motion model. In some examples, the affine motion information includes affine motion candidates. For example, the output of the linear regression may be an affine motion model from which affine motion candidates may be derived or determined. In some examples, the output of the linear regression may include affine motion candidates.

[0172] Now discuss the bit length control for the input delta coordinates. As described above, the currently used anchor coordinates are the anchor coordinates of the upper left position of the current CU. Thus, the delta coordinates can be used to approximate the distance between the sub-block and the current CU. A non-neighboring affine CU or template sub-block may not be too far from the current CU because the farther the sub-block is, the less relevant it may be. Thus, the video encoder 200 or the video decoder 300 may set an upper limit threshold for delta x and delta y such that the sub-blocks will be relatively close. At the same time, under such a constraint, the bit lengths of delta x and delta y can also be reduced. In one example, the threshold for the delta coordinates is set to N bits (excluding the sign bit), and only sub-blocks for which both the delta x and delta y values are within the range [-(1<<N), (1<<N)-1] will be used as the input to the linear regression process. If a sub-block has out-of-range delta coordinates, that sub-block will be skipped. In one example, N = 8. In this way, the video encoder 200 or the video decoder 300 can ensure that each sub-block used in the linear regression process is within one CTU distance from the anchor position.

[0173] Now discuss the bit length control for the input incremental motion vector. When searching for a motion vector, for example, through motion estimation, a search range is defined. Only the reference image region within the search range is examined. Therefore, motion vectors with too large values should not normally occur. However, some other techniques may use scaled motion vectors. For example, for TMVP, the motion vector is scaled based on the POC distance. After being selected as TMVP multiple times, cascaded scaling may occur, which may cause the TMVP to end with a very large value. Generally speaking, such motion vectors are usually rare and not very accurate. Based on this, the video encoder 200 or the video decoder 300 may also adopt a threshold to adjust the incremental motion vector component value. In one example, the bit length threshold of the incremental motion vector component is defined as N bits (excluding the sign bit). If the motion vector component value is outside the range of [-(1<<N), (1<<N)-1], the sub-block is not used. In a second example, instead of skipping the sub-block, the motion vector can be clipped to the range of [-(1<<N), (1<<N)-1] and still be used. In a third example, the motion vector can be wrapped by modulo operation. For example, the horizontal incremental motion vector component is defined as deltaMVx. If deltaMVx is greater than (1<<N)-1 or less than -(1<<N), then deltaMVx%(1<<N) is used. In an application example, the video encoder 200 or the video decoder 300 can set N = 12. In this way, the motion vector dynamic range will be [-(1<<12), (1<<12)-1]. In ECM, the current motion vector accuracy is 1 / 16 pixel. Therefore, the motion vector dynamic range according to the number of samples is [-(1<<8), (1<<8)-1], which is a CTU.

[0174] Now discuss the bit length control for the number of input sub-blocks. For the number of input sub-blocks, for those sub-blocks from non-neighboring affine CUs, since they already belong to the same linear model, the video encoder 200 or the video decoder 300 may only need 3 sub-blocks to derive the linear model. For the template sub-blocks of the current CU, they are usually similar to each other within a given region. Therefore, the video encoder 200 or the video decoder 300 may not need all of them. Based on this analysis, by setting the bit length of the number of sub-blocks to N bits, a total of M = (1<<N)-1 sub-blocks can be used. In one example, the sub-blocks from the template region will be used, and the sub-blocks from non-neighboring affine CUs will be used. Different distributions of the number of sub-blocks to be used from non-neighboring affine CUs and the template region can be adopted to emphasize the importance of non-neighboring affine CUs or the template region. In a second example, there are more sub-blocks from non-neighboring affine CUs than from the template. For example, only the sub-blocks from the template region will be used. sub-blocks, and the sub-blocks from non-neighboring affine CUs will be used. sub-blocks. Different distributions of the number of sub-blocks to be used from non-neighboring affine CUs and the template region can be adopted to emphasize the importance of non-neighboring affine CUs or the template region. In a second example, there are more sub-blocks from non-neighboring affine CUs than from the template. For example, only the sub-blocks from the template region will be used. sub - blocks, and sub - blocks from non - adjacent affine CUs can be used sub - blocks. In a third example, first, the number of sub - blocks used in the template region is determined. Define the maximum number of sub - blocks allowed in the template region as T, and the number of available sub - blocks from the template region as T'. S = min(T, T') sub - blocks from the template region can be used. Subsequently, the number of sub - blocks that can be used from non - adjacent affine CUs is set to M – s. In one example, the video encoder 200 or the video decoder 300 can set N = 8, which means there can be up to 255 sub - blocks. Correspondingly, if sub - blocks from the template region are to be used, and sub - blocks from non - adjacent affine CUs are to be used, then the video encoder 200 or the video decoder 300 can use up to 127 sub - blocks from the template region and 128 sub - blocks from non - adjacent affine CUs.

[0175] Now, the selection of input sub - blocks is discussed. As described above, when the total number of available sub - blocks exceeds a predefined upper limit, some sub - blocks can be excluded from the input. Different techniques can be used to perform the selection. In one example, the video encoder 200 or the video decoder 300 can collect sub - blocks in a given scan order until the number of sub - blocks reaches a threshold. In a second example, the video encoder 200 or the video decoder 300 can use subsampling to select sub - blocks with a given subsampling rate. In a third example, a combination of the first two examples can be used. For example, the template sub - blocks are subsampled, and the sub - blocks from non - adjacent affine CUs are selected using the technique described in the first example.

[0176] Now, the bit - length control of the linear regression output parameters is discussed. This section describes the analysis of the output linear regression parameter range. According to the techniques of the present disclosure, the bit - length of the output of the linear regression operation can be controlled. Given that the dynamic range of the input differential motion vector is M bits, and it is also known that the minimum incremental coordinate between the center coordinate of the sub - block and the anchor coordinate (the anchor coordinate is defined as the upper - left coordinate of the current CU) is 2 pixels. Taking the affine parameter a as an example, based on its derivation equation

[0177]

[0178] the maximum bit - length of the linear regression parameter is (M – 1) bits. Because of this, the output linear regression parameter should be clipped within the range of [-(1 << (M – 1)), (1 << (M - 1)) - 1]. In the affine model mv xIn ax + by + c, the parameters a and b represent the scaling and rotation parts, while c represents the translation part. According to the model equation, the translation parameter c is not divided by the CU width or height. Therefore, defining the maximum CU size as N bits, the dynamic range of the parameters is [-(1 << (M + N)), (1 << (M + N)) - 1]. The dynamic ranges of the parameters a and b are different from that of the parameter c. Based on these findings, in one example, all the output linear regression parameters are limited to the range of [-(1 << (M + N)), (1 << (M + N)) - 1]. In a second example, the linear regression parameters a and b are clipped to different ranges, the parameter c is clipped to [-(1 << (M – 1)), (1 << (M - 1)) - 1], and the parameters are clipped to [-(1 << (M + N)), (1 << (M + N)) - 1]. By clipping, the video encoder 200 or the video decoder 300 can not only adjust the linear regression parameters to reasonable values but also prevent bit length overflow in the subsequent part when the parameters are used to derive the affine motion vector. In one example, all the linear regression parameters are clipped to the same dynamic range. When M = 12 and N = 8, the linear regression parameters are clipped to [-(1 << 20), (1 << 20) - 1].

[0179] Now discuss the application of bit length control in the ECM affine RMVF (regression-based motion vector field) derivation. Above, based on the ECM implementation of the affine RMVF derivation process, this disclosure has detailedly discussed those aspects that may lead to bit length overflow. Also above, different techniques have been introduced to adjust the input and output variables from linear regression. This part of this disclosure describes examples of how to solve the aforementioned bit length problem through examples jointly described by using the affine RMVF derivation process used in ECM. For example, the video encoder 200 or the video decoder 300 can adopt the bit length control techniques described herein.

[0180] As described above, matrices A and B c,d The bit depths of each matrix element are as follows: AB c，d

[0181] bits

[0182] bits

[0183] Based on the determinant equation

[0184] det(A) = (M 0,0 ×M 1,1 ×M 2,2 +M 1,0 ×M 2,1 ×M 0,2 +M 2,0 ×M0,1 ×M 1,2 )-(M 0,0 ×M 2,1 ×M 1,2 +M 1,0 ×M 0,1 ×M 2,2 +M 2,0 ×M 1,1 ×M 0,2 )

[0185] The bit length of matrix A is the sum of a series of numbers of (31 + 31 + 13) bits, (31 + 22 + 22) bits, (22 + 31 + 22) bits, (31 + 22 + 22) bits, (31 + 31 + 13) bits, and (22 + 31 + 22) bits, which is equivalent to adding up 6 numbers of 75 bits. Adding 6 numbers with juxtaposed lengths will further increase the bit length of the resulting number by 3 bits. Therefore, the maximum number of bits required for the determinant of matrix A is 78 bits.

[0186] Similarly, for matrix B c,d , the determinant is the sum of a series of numbers of (43 + 31 + 13) bits, (43 + 22 + 22) bits, (34 + 31 + 22) bits, (43 + 22 + 22) bits, (43 + 31 + 13) bits, and (34 + 31 + 13) bits. This results in a bit length requirement of 90 bits.

[0187] To ensure that the maximum number of bits does not exceed the bit length limit of 64 bits, the video encoder 200 or the video decoder 300 can set a certain upper threshold for each input variable, including the incremental x and y coordinates, the incremental horizontal and vertical motion vector components, and the number of input sub-blocks as described above. For example, the video encoder 200 or the video decoder 300 can set a certain upper threshold for each input variable, including the incremental x and y coordinates, the incremental horizontal and vertical motion vector components, and the number of input sub-blocks, in order to reduce or limit the number of bits.

[0188] In one example, the video encoder 200 or the video decoder 300 may reduce or limit the bit lengths of the incremental x and y coordinates to 8 bits. If a sub-block is in a position where the incremental x or y component is greater than 8 bits, the video encoder 200 or the video decoder 300 may skip that sub-block as an input to the linear regression. The bit length limit of the incremental horizontal and vertical motion vector components may be set to 12 bits, and if the incremental motion vector component exceeds the threshold, it will be clipped to the allowed range. For the number of sub-blocks, the bit length threshold may be set to 8 bits. For the number of 8-bit sub-blocks, there can be at most 255 sub-blocks. The number of sub-blocks used in the template region may be decided first. In some examples, the number of sub-blocks used in the template region may be limited to below 127. Based on the pattern of the template region, the total number of sub-blocks from the template region may be calculated by the equation (2*W + 1.5*H) / 4. When the current CU size is 128×128, the number of sub-blocks from the template region is 112, which is still below 127. However, currently in ECM, the maximum allowed CU size is 256. Thus, in the case where the CU width or height is 256, the video encoder 200 or the video decoder 300 may perform subsampling at a subsampling rate of 1 / 2 in the horizontal template row scan or the vertical template column scan accordingly. In this way, the video encoder 200 or the video decoder 300 can ensure that the number of sub-blocks used from the template region does not exceed the limit (e.g., 127). When the number of available sub-blocks from the template region is below a predetermined limit, all sub-blocks may be used. Defining the number of actual sub-blocks found in the template region as T, the maximum number of sub-blocks allowed for non-neighboring affine CUs is 255–T. If the number of available non-neighboring affine sub-blocks is greater than the threshold, the first available 255–T sub-blocks in the raster scan order may be used. With these thresholds defined, the determinant values of matrices A and B c,d require a maximum of 59 bits and 63 bits, which satisfy the bit depth limit.

[0189] The linear regression parameters are calculated by dividing the determinants of two matrices, except for b x2 . In the current implementation, b is calculated using the following formula x2 :

[0190]

[0191] However, using this method, the determinant values are further multiplied by different factors in the numerator and denominator, which may cause the bit length to exceed 64 bits.

[0192] As an example, to keep the bit length not exceeding 64 bits, the video encoder 200 or the video decoder 300 may use Cramer's rule, which has been used to derive b x0and b x1 :

[0193]

[0194] For matrix B x,2 , the bit depth of each element is as follows:

[0195] bits

[0196] From the determinant calculation formula, it can be seen that the maximum bit depth of determinant B x,2 is 71 bits. Even if Cramer's rule can be used to replace the previous derivation formula, its determinant may still exceed the bit depth limit. One solution is to scale the numerator and denominator according to the number of input sub-blocks. Define the number of input sub-blocks as iNum, the bit length of variable x as MSB(x), and the scaling shift of the numerator and denominator as scaleshift, then

[0197]

[0198] Subsequently,

[0199]

[0200] For the denominator, if MSB(det(A)) is not greater than scaleshift, the result after right shift is 0. To avoid division by 0, if MSB(det(A)) ≤ scaleshift, the video encoder 200 or the video decoder 300 can set the denominator to 1.

[0201] As mentioned before, the final division is approximated by multiplication and right shift. The multiplier is taken from a pre-defined look-up table, and the index used to reference the look-up table is determined by the denominator, or equivalently by the determinant of matrix A. In the current design, the size of the look-up table is defined as 64. Subsequently, the 6 most significant bits of det(A) are derived and used as the reference index. Define the bit length of variable x as MSB(x). The calculation formula for the look-up table is as follows:

[0202]

[0203] Using the derived index, the multiplier is defined by referencing the look-up table as lookup[index], which can be used to represent. Corresponding to the bit length of the currently used look-up table, a fixed 15-bit right shift is required. The division result is calculated using the following formula:

[0204] b c,d =(det(B c,d )*lookup[index])>> (15 + shiftA)

[0205] where shiftA = (MSB(det(A)) - 6) < 0? 0 : (MSB(det(A)) - 6), and shiftA needs to be added because the denominator has been right-shifted by shiftA bits, and correspondingly, the numerator should perform the same shift.

[0206] Generally, during the affine parameter derivation process, the left shift bits of MaxCuDepth are executed to maintain the high precision of the affine parameters, where 2^MaxCuDepth is the maximum allowed CTU size. In linear regression, the same method of maintaining the affine parameters with high precision can be used. When this shift is additionally executed, the video encoder 200 or the video decoder 300 can take this into account in the bit length control. Therefore, to derive b c,d The equation becomes

[0207] b c,d = (det(B c,d ) * lookup[index]) >> (15 + shiftA)) << MaxCuDepth

[0208] Currently in ECM, MaxCuDepth is defined as 8. Since MaxCuDepth < 15, we have

[0209] b c,d = (det(B c,d ) * lookup[index]) >> (15 + shiftA – MaxCuDepth)

[0210] The maximum bit length of lookup[index] is 15 bits. To ensure that the intermediate result (det(B c,d ) * lookup[index] remains within the range of 64 bits, det(B c,d ) shall not exceed 48 bits. Therefore, additional bit shifts can be added to both sides of the operator ">>" in the equation. The additional right shift is defined as rightshiftNum

[0211]

[0212] The last equation to be derived is b c,d

[0213] b c,d = ((det(B c,d ) >> rightshiftNum) * lookup[index]) >> (15 + shiftA – MaxCuDepth - rightshiftNum)

[0214] To avoid bit shifting of negative numbers, 15 + shiftA – MaxCuDepth - rightshiftNum can be clipped. Define the final right shift variable as finalshift

[0215]

[0216] In different methods, the video encoder 200 or the video decoder 300 can save the computation of the MSB(det(B c,d )) operation by always shifting det(B c,d ) 15 bits to the right. In this way, the video encoder 200 or the video decoder 300 can also ensure that the numerator remains within the 64 - bit range. Set rightshiftNum = 15,

[0217] b c,d = ((det(B c,d )) >> 15) * lookup[index]) >> (shiftA – MaxCuDepth)

[0218] Similarly, shiftA – MaxCuDepth can also be clipped to a non - negative value.

[0219] Finally, the output linear regression parameters can be restricted to the range of [-(1 << M), (1 << M) - 1], where M is set to 20 in the current solution.

[0220] Figure 12 is a flowchart showing example bit - length control techniques for affine merge candidate derivation based on linear regression according to one or more aspects of the present disclosure. The video encoder 200 or the video decoder 300 can control the bit lengths of the input variables of the linear regression operation, where the input variables include at least one of a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing the number of sub - blocks (1200). For example, the video encoder 200 or the video decoder 300 can control (e.g., reduce or limit) the bit lengths of one or more delta coordinates, one or more delta motion vectors, and / or the value representing the number of sub - blocks to produce one or more reduced - bit - length input variables. For example, if the bit length of a potential input variable is too long (e.g., greater than a threshold), then the video encoder 200 or the video decoder 300 can clip the value of the too - long input variable or skip the use of the input variable associated with certain sub - blocks.

[0221] Video encoder 200 or video decoder 300 may perform a linear regression operation (1202) on a controlled bit length input variable. For example, video encoder 200 or video decoder 300 may use an input variable whose bit length has been controlled as an input to the linear regression operation.

[0222] Video encoder 200 or video decoder 300 may derive an affine motion model (1204) based on performing the linear regression operation. For example, video encoder 200 or video decoder 300 may generate an affine motion candidate (e.g., an affine motion vector prediction value candidate) based on performing the linear regression operation.

[0223] Video encoder 200 or video decoder 300 may decode a current block of video data (1206) based on the affine motion model. For example, video encoder 200 may encode the video data based on the affine motion model, or video decoder 300 may decode the video data based on the affine motion model.

[0224] In some examples, the input variable includes one or more delta coordinates. In some examples, as part of controlling the bit length of the input variable, video encoder 200 or the video decoder may determine that at least one of the bit lengths of the delta x value or the delta y value of one or more delta coordinates is greater than a delta x delta y bit length threshold, where the value of delta x includes a value indicating a distance in the x direction between a current sub-block of the current block and an x anchor coordinate of the current block, and where the value of delta y includes a value indicating a distance in the y direction between the current sub-block and a y anchor coordinate of the current block. Based on at least one of the bit lengths of the delta x value or the delta y value being greater than the delta x delta y bit length threshold, video encoder 200 or video decoder 300 may skip the current sub-block as an input to the linear regression operation. In some examples, the delta x delta y bit length threshold is 8 bits.

[0225] In some examples, the input variables include one or more delta motion vectors. In some examples, as part of controlling the bit lengths of the input variables, video encoder 200 or video decoder 300 may determine that the bit length of a delta motion vector component is greater than a delta motion vector bit length threshold; and based on the bit length of the delta motion vector component being greater than the delta motion vector bit length threshold, skip the current sub-block as an input to the linear regression operation. In some examples, as part of controlling the bit lengths of the input variables, video encoder 200 or video decoder 300 may determine that the bit length of a delta motion vector component is greater than a delta motion vector bit length threshold, and based on the bit length of the delta motion vector component being greater than the delta motion vector bit length threshold, clip the delta motion vector component to a length of the delta motion vector bit length threshold. In some examples, the delta motion vector bit length threshold is 12 bits.

[0226] In some examples, as part of controlling the bit lengths of the input variables, video encoder 200 or video decoder 300 may determine whether the bit length of a delta motion vector component is greater than a first delta motion vector bit length threshold or less than a second delta motion vector bit length threshold. Based on the determination that the bit length of the delta motion vector component is greater than the first delta motion vector bit length threshold or less than the second delta motion vector bit length threshold, video encoder 200 or video decoder 300 may use an alternative delta motion vector component instead of the delta motion vector component as an input to the linear regression operation, where the alternative delta motion vector component has a bit length less than that of the delta motion vector component.

[0227] In some examples, as part of controlling the bit lengths of the input variables, video encoder 200 or video decoder 300 may reduce the bit length of a value representing the number of sub-blocks used in the linear regression operation to a predetermined bit length. In some examples, the predetermined bit length is 8 bits.

[0228] In some examples, as part of controlling the bit lengths of the input variables, video encoder 200 or video decoder 300 may select a subset of sub-blocks of a current block of video data to be used as inputs for one or more input variables of the linear regression operation, where the subset of sub-blocks is less than the total number of sub-blocks within the current block. In some examples, video encoder 200 or video decoder 300 may determine a first number of sub-blocks within a template region and determine a second number of sub-blocks within a non-neighboring affine block, where the non-neighboring affine block is a block of video data that is not adjacent to the current block, and use an affine mode for decoding. In some examples, the first number includes M / 2 and the second number includes M / 2, where M represents the number of sub-blocks used in the linear regression operation. In some examples, the first number includes M / 4 and the second number includes M - M / 4, where M represents the number of sub-blocks used in the linear regression operation.

[0229] In some examples, video encoder 200 or video decoder 300 may determine a maximum allowable number of sub - blocks T for a template region and determine an available number of sub - blocks T' for the template region, where a first quantity S comprises S = min(T, T'), and a second quantity comprises M - S, where M represents the number of sub - blocks used in a linear regression operation.

[0230] In some examples, as part of selecting a subset of sub - blocks, video encoder 200 or video decoder 300 may select sub - blocks in a scan order. In some examples, as part of selecting a subset of sub - blocks, video encoder 200 or video decoder 300 may perform subsampling using a predetermined subsampling rate. In some examples, as part of selecting a subset of sub - blocks, video encoder 200 or video decoder 300 may perform subsampling on the sub - blocks in a template region using a predetermined subsampling rate and select non - adjacent affine sub - blocks in a scan order until the number of selected sub - blocks equals the second quantity.

[0231] In some examples, as part of selecting a subset of sub - blocks, video encoder 200 or video decoder 300 may determine whether at least one of the height or width of a current CU of a current block is equal to 256. In these examples, video encoder 200 or video decoder 300 may perform subsampling in at least one of a horizontal template row scan of the template region or a vertical template column scan of the template region at a subsampling ratio based on the determination that at least one of the height or width of the current CU is equal to 256. Video encoder 200 or video decoder 300 may determine a total number of sub - blocks T for the template region and determine whether the total number of available non - adjacent affine sub - blocks is greater than 255 - T. Video encoder 200 or video decoder 300 may use the first 255 - T available non - adjacent affine sub - blocks in a raster scan order as inputs for a linear regression operation based on the determination that the total number of available non - adjacent affine sub - blocks is greater than 255 - T.

[0232] In some examples, the video encoder 200 or the video decoder 300 may limit the bit length of one or more linear regression operation output parameters. In some examples, as part of limiting the bit length of one or more linear regression operation output parameters, the video encoder 200 or the video decoder 300 may clip one or more linear regression operation output parameters. In some examples, as part of clipping one or more linear regression operation output parameters, the video encoder 200 or the video decoder 300 may clip each of the one or more linear regression operation output parameters to the same number of bits. In some examples, as part of clipping one or more linear regression operation output parameters, the video encoder 200 or the video decoder 300 may clip at least one of the one or more linear regression operation output parameters to a different number of bits than the other parameters of the one or more linear regression operation output parameters. In such examples, as part of clipping at least one of the one or more linear regression operation output parameters to a different number of bits than the other parameters of the one or more linear regression operation output parameters, the video encoder 200 or the video decoder 300 may clip the first linear regression operation output parameter to [-(1 << (M + N)), (1 << (M + N)) - 1] and clip the second and third linear regression operation output parameters to the range of [-(1 << (M - 1)), (1 << (M - 1)) - 1], where M = 12 and N = 8.

[0233] In some examples, the video encoder 200 or the video decoder 300 may determine affine motion candidates based on an affine motion model.

[0234] Figure 13 is a block diagram illustrating an example video encoder 200 that may implement the techniques of the present invention. Figure 13 is provided for explanatory purposes and should not be considered a limitation of the techniques of the broad examples and descriptions in this disclosure. For explanatory purposes, this disclosure describes the video encoder 200 in accordance with the techniques of VVC and HEVC. However, the techniques of the present invention may be performed by video coding devices configured for other video coding standards and video decoding formats (such as AV1 and successors to the AV1 video decoding format).

[0235] In Figure 13In the example, video encoder 200 includes video data memory 230, mode selection unit 202, residual generation unit 204, transform processing unit 206, quantization unit 208, inverse quantization unit 210, inverse transform processing unit 212, reconstruction unit 214, filter unit 216, decoded picture buffer (DPB) 218, and entropy encoding unit 220. Any one or all of video data memory 230, mode selection unit 202, residual generation unit 204, transform processing unit 206, quantization unit 208, inverse quantization unit 210, inverse transform processing unit 212, reconstruction unit 214, filter unit 216, DPB 218, and entropy encoding unit 220 may be implemented in one or more processors or in processing circuitry. By way of example, the units of video encoder 200 may be implemented as one or more circuits or logic elements, as part of a hardware circuit, or as part of a processor, ASIC, or FPGA. Additionally, video encoder 200 may include additional or alternative processors or processing circuitry to perform these and other functions.

[0236] Video data memory 230 may store video data to be encoded by components of video encoder 200. Video encoder 200 may receive the video data stored in video data memory 230 from, for example, video source 104( Figure 1 ). DPB 218 may act as a reference picture memory that stores reference video data for use by video encoder 200 in predicting subsequent video data. Video data memory 230 and DPB 218 may be formed of any of a variety of memory devices, such as dynamic random access memory (DRAM), including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of memory devices. Video data memory 230 and DPB 218 may be provided by the same storage device or separate storage devices. In various examples, video data memory 230 may be on-chip with other components of video encoder 200, as shown, or off-chip relative to those components.

[0237] In the present disclosure, a reference to video data memory 230 should not be construed as being limited to memory internal to video encoder 200, unless so specifically described, or to memory external to video encoder 200, unless so specifically described. Instead, a reference to video data memory 230 should be understood as a reference memory that stores the video data that video encoder 200 receives for encoding (e.g., the video data of the current block to be encoded). Figure 1 Memory 106 may also provide temporary storage of outputs from the various units of video encoder 200.

[0238] Description Figure 13Various units to assist in understanding the operations performed by video encoder 200. These units can be implemented as fixed-function circuits, programmable circuits, or a combination thereof. Fixed-function circuits refer to circuits that provide a specific function and are preset with the operations that can be performed. Programmable circuits are circuits that can be programmed to perform various tasks and provide flexible functionality among the operations that can be performed. For example, a programmable circuit can execute software or firmware that causes the programmable circuit to operate in a manner defined by the instructions of the software or firmware. Fixed-function circuits can execute software instructions (e.g., receive parameters or output parameters), but the types of operations performed by fixed-function circuits are generally immutable. In some examples, one or more units can be different circuit blocks (fixed-function or programmable), and in some examples, one or more units can be integrated circuits.

[0239] Video encoder 200 can include an arithmetic logic unit (ALU), a basic function unit (EFU), digital circuits, analog circuits, and / or a programmable core formed by programmable circuits. In an example where software executed by programmable circuits is used to perform the operations of video encoder 200, memory 106( Figure 1 ) can store the instructions (e.g., object code) of the software received and executed by video encoder 200, or another memory (not shown) within video encoder 200 can store such instructions.

[0240] Video data memory 230 is configured to store the received video data. Video encoder 200 can retrieve pictures of the video data from video data memory 230 and provide the video data to residual generation unit 204 and mode selection unit 202. The video data in video data memory 230 can be the original video data to be encoded.

[0241] Mode selection unit 202 includes a motion estimation unit 222, a motion compensation unit 224, and an intra prediction unit 226. Mode selection unit 202 can include additional functional units to perform video prediction according to other prediction modes. As an example, mode selection unit 202 can include a palette unit, a block copy unit (which can be part of motion estimation unit 222 and / or motion compensation unit 224), an affine unit, a linear model (LM) unit, etc.

[0242] Mode selection unit 202 generally coordinates multiple encoding processes to test combinations of encoding parameters and the resulting rate-distortion values of these combinations. The encoding parameters can include splitting a CTU into CUs, the prediction mode of a CU, the transform type of the residual data of a CU, the quantization parameter of the residual data of a CU, etc. Mode selection unit 202 can ultimately select a combination of encoding parameters that has a better rate-distortion value than other tested combinations.

[0243] Video encoder 200 may split pictures retrieved from video data memory 230 into a series of CTUs and encapsulate one or more CTUs within a slice. Pattern selection unit 202 may split the CTUs of a picture according to a tree structure (e.g., MTT structure, QTBT structure), superblock structure, or the quadtree structure described above. As described above, video encoder 200 may form one or more CUs by splitting CTUs according to a tree structure. This CU may also generally be referred to as a “video block” or “block”.

[0244] Generally, pattern selection unit 202 also controls its components (e.g., motion estimation unit 222, motion compensation unit 224, and intra prediction unit 226) to generate a predicted block for a current block (e.g., current CU, or in HEVC, the overlapping portion of a PU and a TU). For inter prediction of a current block, motion estimation unit 222 may perform a motion search to identify one or more reference blocks in one or more reference pictures (e.g., one or more previously decoded pictures stored in DPB 218) that closely match. Specifically, motion estimation unit 222 may calculate values representing how similar a potential reference block is to the current block, e.g., according to sum of absolute differences (SAD), sum of squared differences (SSD), mean absolute difference (MAD), mean squared difference (MSD), etc. Motion estimation unit 222 generally may perform these calculations using the sample-by-sample differences between the current block and the reference block being considered. Motion estimation unit 222 may identify the reference block having the lowest value produced by these calculations, indicating the reference block that most closely matches the current block.

[0245] Motion estimation unit 222 may form one or more motion vectors (MVs) that define the position of a reference block in a reference picture relative to the position of the current block in the current picture. In some examples, when forming the motion vectors, motion estimation unit 222 may perform Figure 12 techniques. Motion estimation unit 222 may then provide the motion vectors to motion compensation unit 224. For example, for uni-directional inter prediction, motion estimation unit 222 may provide a single motion vector, and for bi-directional inter prediction, motion estimation unit 222 may provide two motion vectors. Motion compensation unit 224 may then use the motion vectors to generate the predicted block. For example, motion compensation unit 224 may retrieve the data of the reference block using the motion vectors. As another example, if the motion vectors have fractional sample accuracy, then motion compensation unit 224 may interpolate the values of the predicted block according to one or more interpolation filters. Additionally, for bi-directional inter prediction, motion compensation unit 224 may retrieve the data of the two reference blocks identified by the respective motion vectors and combine the retrieved data, e.g., by sample-by-sample averaging or weighted averaging.

[0246] When operating according to the AV1 video coding format, the motion estimation unit 222 and the motion compensation unit 224 may be configured to use translational motion compensation, affine motion compensation, overlapping block motion compensation (OBMC), and / or combined inter-intra prediction to decode blocks of encoded video data (e.g., both luminance and chrominance decoded blocks).

[0247] As another example, for intra prediction or intra prediction coding, the intra prediction unit 226 may generate a prediction block from samples adjacent to the current block. For example, for the directional mode, the intra prediction unit 226 may typically mathematically combine the values of adjacent samples and fill in the calculated values in a defined direction on the current block to generate the prediction block. As another example, for the DC mode, the intra prediction unit 226 may calculate the average of the adjacent samples of the current block and generate a prediction block to contain this resulting average for each sample of the prediction block.

[0248] When operating according to the AV1 video coding format, the intra prediction unit 226 may be configured to use directional intra prediction, non-directional intra prediction, recursive filter intra prediction, chroma format luma (CFL) prediction, intra block copy (IBC), and / or palette mode to decode blocks of encoded video data (e.g., both luminance and chrominance decoded blocks). The mode selection unit 202 may include additional functional units to perform video prediction according to other prediction modes.

[0249] The mode selection unit 202 provides the prediction block to the residue generation unit 204. The residue generation unit 204 receives the original uncoded version of the current block from the video data memory 230 and receives the prediction block from the mode selection unit 202. The residue generation unit 204 calculates the sample-by-sample difference between the current block and the prediction block. The resulting sample-by-sample difference defines the residue block of the current block. In some examples, the residue generation unit 204 may also determine the differences between the sample values in the residue block to generate the residue block using residue differential pulse code modulation (RDPCM). In some examples, the residue generation unit 204 may be formed using one or more subtractor circuits that perform binary subtraction.

[0250] In an example where the mode selection unit 202 divides a CU into PUs, each PU may be associated with a luminance prediction unit and a corresponding chrominance prediction unit. The video encoder 200 and the video decoder 300 may support PUs of various sizes. As described above, the size of a CU may refer to the size of the luminance decoding block of the CU, and the size of a PU may refer to the size of the luminance prediction unit of the PU. Assuming that the size of a specific CU is 2Nx2N, the video encoder 200 may support PU sizes of 2Nx2N or NxN for intra prediction, and 2Nx2N, 2NxN, Nx2N, NxN, or similar symmetric PU sizes for inter prediction. The video encoder 200 and the video decoder 300 may also support asymmetric division of PU sizes of 2NxnU, 2NxnD, nLx2N, and nRx2N for inter prediction.

[0251] In an example where the mode selection unit 202 does not further divide a CU into PUs, each CU may be associated with a luminance decoding block and a corresponding chrominance decoding block. As described above, the size of a CU may refer to the size of the luminance decoding block of the CU. The video encoder 200 and the video decoder 300 may support CU sizes of 2Nx2N, 2NxN, or Nx2N.

[0252] For other video coding techniques, such as intra block copy mode coding, affine mode coding, and linear model (LM) mode coding, as some examples, the mode selection unit 202 generates a predicted block of the current block being encoded via a corresponding unit associated with the coding technique. In some examples, such as palette mode coding, the mode selection unit 202 may not generate a predicted block, but instead generates syntax elements indicating the manner in which the block is to be reconstructed based on a selected palette. In such modes, the mode selection unit 202 may provide these syntax elements to the entropy coding unit 220 for coding.

[0253] As described above, the residual generation unit 204 receives the video data of the current block and the corresponding predicted block. The residual generation unit 204 then generates a residual block of the current block. To generate the residual block, the residual generation unit 204 calculates the sample-by-sample difference between the predicted block and the current block.

[0254] The transform processing unit 206 applies one or more transforms to the residual block to generate a transform coefficient block (referred to herein as "transform coefficient block"). The transform processing unit 206 may apply various transforms to the residual block to form the transform coefficient block. For example, the transform processing unit 206 may apply a discrete cosine transform (DCT), a directional transform, a Karhunen-Loeve transform (KLT), or a conceptually similar transform to the residual block. In some examples, the transform processing unit 206 may perform multiple transforms on the residual block, such as a primary transform and a secondary transform, such as a rotation transform. In some examples, the transform processing unit 206 does not apply a transform to the residual block.

[0255] When operating according to AV1, the transform processing unit 206 may apply one or more transforms to the residual block to produce a transform coefficient block (referred to herein as the "transform coefficient block"). The transform processing unit 206 may apply various transforms to the residual block to form the transform coefficient block. For example, the transform processing unit 206 may apply a horizontal / vertical transform combination, which may include a discrete cosine transform (DCT), an asymmetric discrete sine transform (ADST), a flipped ADST (e.g., reverse-order ADST), and an identity transform (IDTX). When using the identity transform, the transform is skipped in the vertical or horizontal direction. In some examples, the transform processing may be skipped.

[0256] The quantization unit 208 may quantize the transform coefficients in the transform coefficient block to produce a quantized transform coefficient block. The quantization unit 208 may quantize the transform coefficients of the transform coefficient block according to the quantization parameter (QP) value associated with the current block. The video encoder 200 (e.g., via the mode selection unit 202) may adjust the degree of quantization applied to the transform coefficient block associated with the current block by adjusting the QP value associated with the CU. Quantization may introduce information loss, and thus, the quantized transform coefficients may have lower precision than the original transform coefficients produced by the transform processing unit 206.

[0257] The inverse quantization unit 210 and the inverse transform processing unit 212 may apply inverse quantization and inverse transform to the quantized transform coefficient block, respectively, to reconstruct the residual block from the transform coefficient block. The reconstruction unit 214 may produce a reconstructed block corresponding to the current block (although there may be some degree of distortion) based on the reconstructed residual block and the prediction block produced by the mode selection unit 202. For example, the reconstruction unit 214 may add the samples of the reconstructed residual block to the corresponding samples of the prediction block produced by the mode selection unit 202 to produce the reconstructed block.

[0258] The filter unit 216 may perform one or more filtering operations on the reconstructed block. For example, the filter unit 216 may perform a deblocking operation to reduce block effect artifacts along the edges of the CU. In some examples, the operation of the filter unit 216 may be skipped.

[0259] When operating according to AV1, the filter unit 216 may perform one or more filter operations on the reconstructed blocks. For example, the filter unit 216 may perform a deblocking operation to reduce block - effect artifacts along the edges of the CUs. In other examples, the filter unit 216 may apply a Constrained Directional Enhancement Filter (CDEF), which may be applied after deblocking and may include the application of a non - separable, non - linear, low - pass directional filter based on the estimated edge direction. The filter unit 216 may also include a loop - restoration filter applied after the CDEF and may include a separable symmetric normalized Wiener filter or a bi - self - guiding filter.

[0260] The video encoder 200 stores the reconstructed blocks in the DPB 218. For example, in an example where the operations of the filter unit 216 are not performed, the reconstruction unit 214 may store the reconstructed blocks into the DPB 218. In an example where the operations of the filter unit 216 are performed, the filter unit 216 may store the filtered reconstructed blocks into the DPB 218. The motion - estimation unit 222 and the motion - compensation unit 224 may retrieve the reference pictures formed by the reconstructed (and possibly filtered) blocks from the DPB 218 to perform inter - frame prediction on the blocks of the subsequent pictures to be encoded. Additionally, the intra - prediction unit 226 may use the reconstructed blocks in the DPB 218 of the current picture to perform intra - frame prediction on other blocks in the current picture.

[0261] Generally, the entropy - coding unit 220 may perform entropy coding on the syntax elements received from other functional components of the video encoder 200. For example, the entropy - coding unit 220 may perform entropy coding on the quantized transform - coefficient blocks from the quantization unit 208. As another example, the entropy - coding unit 220 may perform entropy coding on the prediction syntax elements (e.g., motion information for inter - frame prediction or intra - frame mode information for intra - frame prediction) from the mode - selection unit 202. The entropy - coding unit 220 may perform one or more entropy - coding operations on the syntax elements as another example of video data to produce the entropy - coded data. For example, the entropy - coding unit 220 may perform Context - Adaptive Variable - Length Coding (CAVLC) operations, CABAC operations, Variable - to - Variable (V2V) length coding operations, Syntax - Based Context - Adaptive Binary Arithmetic Coding (SBAC) operations, Probability Interval Partitioning Entropy (PIPE) coding operations, Exponential - Golomb coding operations, or another type of entropy - coding operation on the data. In some examples, the entropy - coding unit 220 may operate in a bypass mode where no entropy coding is performed on the syntax elements.

[0262] The video encoder 200 may output a bitstream containing the entropy - coded syntax elements required to reconstruct the strips or blocks of the pictures. Specifically, the entropy - coding unit 220 may output the bitstream.

[0263] According to AV1, the entropy coding unit 220 can be configured as a symbol-to-symbol adaptive multi-symbol arithmetic decoder. The syntax elements in AV1 include an alphabet of N elements, and the context (e.g., probability model) includes a set of N probabilities. The entropy coding unit 220 can store the probabilities as an n-bit (e.g., 15-bit) cumulative distribution function (CDF). The entropy coding unit 220 can perform recursive scaling using an update factor based on the alphabet size to update the context.

[0264] The operations described above are described with respect to blocks. Such description should be understood as operations on the luma decoding block and / or the chroma decoding block. As described above, in some examples, the luma decoding block and the chroma decoding block are the luma and chroma components of a CU. In some examples, the luma decoding block and the chroma decoding block are the luma and chroma components of a PU.

[0265] In some examples, for the chroma decoding block, it is not necessary to repeat the operations performed for the luma decoding block. As an example, the operations of identifying the motion vector (MV) and the reference picture of the luma decoding block do not need to be repeated for identifying the MV and the reference picture of the chroma block. Instead, the MV of the luma decoding block can be scaled to determine the MV of the chroma block, and the reference picture can be the same. As another example, for the luma decoding block and the chroma decoding block, the intra prediction process can be the same.

[0266] Video encoder 200 represents an example of a device configured to encode video data, which includes a memory configured to store video data, and one or more processing units implemented in circuitry and configured to control (e.g., reduce or limit) the bit length of the input variables of a linear regression operation; perform a linear regression operation on the controlled bit length input variables; derive an affine motion model based on performing the linear regression operation; and encode a current block of video data based on the affine motion model.

[0267] Figure 14 is a block diagram illustrating an example video decoder 300 that can implement the techniques of the present invention. Figure 14 is provided for explanatory purposes and is not limited to the techniques widely exemplified and described in this disclosure. For explanatory purposes, this disclosure describes a video decoder 300 according to the techniques of VVC and HEVC. However, the techniques of the present invention can be performed by video coding devices configured to conform to other video coding standards.

[0268] In Figure 14In the example, the video decoder 300 includes a coded picture buffer (CPB) memory 320, an entropy decoding unit 302, a prediction processing unit 304, an inverse quantization unit 306, an inverse transform processing unit 308, a reconstruction unit 310, a filter unit 312, and a DPB 314. Any one or all of the CPB memory 320, the entropy decoding unit 302, the prediction processing unit 304, the inverse quantization unit 306, the inverse transform processing unit 308, the reconstruction unit 310, the filter unit 312, and the DPB 314 can be implemented in one or more processors or in processing circuitry. For example, the units of the video decoder 300 can be implemented as one or more circuits or logic elements, as part of a hardware circuit, or as part of a processor, ASIC, or FPGA. Additionally, the video decoder 300 can include additional or alternative processors or processing circuitry to perform these and other functions.

[0269] The prediction processing unit 304 includes a motion compensation unit 316 and an intra prediction unit 318. The prediction processing unit 304 can include additional units to perform prediction according to other prediction modes. As an example, the prediction processing unit 304 can include a palette unit, a block copy unit (which can form part of the motion compensation unit 316), an affine unit, a linear model (LM) unit, etc. In other examples, the video decoder 300 can include more, fewer, or different functional components.

[0270] When operating according to AV1, the motion compensation unit 316 can be configured to decode coded blocks of video data (e.g., both luminance and chrominance coded blocks) using translational motion compensation, affine motion compensation, OBMC, and / or combined inter-intra prediction, as described above. As described above, the intra prediction unit 318 can be configured to decode coded blocks of video data (e.g., both luminance and chrominance coded blocks) using directional intra prediction, non-directional intra prediction, recursive filter intra prediction, CFL, IBC, and / or palette mode.

[0271] The CPB memory 320 can store video data to be decoded by components of the video decoder 300, such as an encoded video bitstream. The video data stored in the CPB memory 320 can be, for example, from a computer-readable medium 110( Figure 1) obtained from. The CPB memory 320 may include a CPB that stores encoded video data (e.g., syntax elements) from the encoded video bitstream. Additionally, the CPB memory 320 may store video data other than the syntax elements of decoded pictures, such as temporary data representing the outputs of the respective units from the video decoder 300. The DPB 314 generally stores decoded pictures, and the video decoder 300 may output and / or use the decoded pictures as reference video data when decoding subsequent data or pictures of the encoded video bitstream. The CPB memory 320 and the DPB 314 may be formed of any of a variety of memory devices, such as DRAM, including sDRAM, MRAM, RRAM, or other types of memory devices. The CPB memory 320 and the DPB 314 may be provided by the same storage device or separate storage devices. In various examples, the CPB memory 320 may be on-chip with other components of the video decoder 300 or off-chip relative to those components.

[0272] Additionally or alternatively, in some examples, the video decoder 300 may retrieve decoded video data from the memory 120( Figure 1 ). That is, the memory 120 may store the data discussed above with respect to the CPB memory 320. Similarly, when some or all of the functions of the video decoder 300 are implemented in software executed by the processing circuitry of the video decoder 300, the memory 120 may store instructions executed by the video decoder 300.

[0273] is shown Figure 14 the various units shown in to assist in understanding the operations performed by the video decoder 300. These units may be implemented as fixed-function circuitry, programmable circuitry, or a combination thereof. Similar to Figure 13 , fixed-function circuitry refers to circuitry that provides a specific function and is preset on the operations that can be performed. Programmable circuitry refers to circuitry that can be programmed to perform various tasks and provides flexible functionality in the operations that can be performed. For example, programmable circuitry may execute software or firmware that causes the programmable circuitry to operate in a manner defined by the instructions of the software or firmware. Fixed-function circuitry may execute software instructions (e.g., receive parameters or output parameters), but the types of operations performed by the fixed-function circuitry are generally immutable. In some examples, one or more units may be different circuit blocks (fixed-function or programmable), and in some examples, one or more units may be integrated circuits.

[0274] The video decoder 300 may include an ALU, an EFU, digital circuits, analog circuits, and / or a programmable core formed by programmable circuits. In an example where the operation of the video decoder 300 is performed by software executed on the programmable circuits, on-chip or off-chip memory may store instructions (e.g., object code) of the software that the video decoder 300 receives and executes.

[0275] The entropy decoding unit 302 may receive encoded video data from the CPB and perform entropy decoding on the video data to reproduce syntax elements. The prediction processing unit 304, the inverse quantization unit 306, the inverse transform processing unit 308, the reconstruction unit 310, and the filter unit 312 may generate decoded video data based on the syntax elements extracted from the bitstream.

[0276] Generally, the video decoder 300 reconstructs images on a block-by-block basis. The video decoder 300 may perform the reconstruction operation separately for each block (where the block that is currently being reconstructed, i.e., decoded, may be referred to as the "current block").

[0277] The entropy decoding unit 302 may entropy decode the syntax elements that define the quantized transform coefficients of the quantized transform coefficient block, as well as transform information, such as the quantization parameter (QP) and / or the transform mode indication. The inverse quantization unit 306 may use the QP associated with the quantized transform coefficient block to determine the quantization level, and similarly, determine the inverse quantization level to be applied by the inverse quantization unit 306. The inverse quantization unit 306 may (e.g.) perform a bitwise left shift operation to inverse quantize the quantized transform coefficients. The inverse quantization unit 306 may thereby form a transform coefficient block that contains the transform coefficients.

[0278] After the inverse quantization unit 306 forms the transform coefficient block, the inverse transform processing unit 308 may apply one or more inverse transforms to the transform coefficient block to generate a residual block associated with the current block. For example, the inverse transform processing unit 308 may apply an inverse DCT, an inverse integer transform, an inverse Karhunen-Loeve transform (KLT), an inverse rotation transform, an inverse direction transform, or another inverse transform to the transform coefficient block.

[0279] In addition, the prediction processing unit 304 generates a prediction block according to the prediction information syntax elements entropy decoded by the entropy decoding unit 302. For example, if the prediction information syntax elements indicate that the current block is inter-predicted, then the motion compensation unit 316 may generate the prediction block. In this case, the prediction information syntax elements may indicate a reference picture in the DPB 314, retrieve a reference block from the reference picture, and identify a motion vector that indicates the position of the reference block in the reference picture relative to the current block in the current picture. The motion compensation unit 316 may generally be substantially similar to the motion compensation unit 224 ( Figure 13)perform the inter - frame prediction process in the manner described. In some examples, during the execution of the inter - frame prediction process, the motion compensation unit 316 may perform Figure 12 techniques.

[0280] As another example, if the prediction information syntax element indicates that the current block is intra - frame predicted, then the intra - frame prediction unit 318 may generate a prediction block according to the intra - frame prediction mode indicated by the prediction information syntax element. Additionally, the intra - frame prediction unit 318 can generally perform the intra - frame prediction process in a manner substantially similar to that described for the intra - frame prediction unit 226( Figure 13 ). The intra - frame prediction unit 318 may retrieve data of neighboring samples of the current block from the DPB 314.

[0281] The reconstruction unit 310 may use the prediction block and the residual block to reconstruct the current block. For example, the reconstruction unit 310 may add the samples of the residual block to the corresponding samples of the prediction block to reconstruct the current block.

[0282] The filter unit 312 may perform one or more filtering operations on the reconstructed block. For example, the filter unit 312 may perform a de - blocking operation to reduce blocking - effect artifacts along the edges of the reconstructed block. The operation of the filter unit 312 is not necessarily performed in all examples.

[0283] The video decoder 300 may store the reconstructed block in the DPB 314. For example, in an example where the operation of the filter unit 312 is not performed, the reconstruction unit 310 may store the reconstructed block into the DPB 314. In an example where the operation of the filter unit 312 is performed, the filter unit 312 may store the filtered reconstructed block into the DPB 314. As discussed above, the DPB 314 may provide reference information to the prediction processing unit 304, such as the current picture for intra - frame prediction and the samples of the previously decoded pictures for subsequent motion compensation. Additionally, the video decoder 300 may output the decoded picture (e.g., decoded video) from the DPB 314 for subsequent presentation on a display device (e.g., Figure 1 display device 118).

[0284] In this way, the video decoder 300 represents an example of a video decoding device that includes a memory configured to store video data, and one or more processing units implemented in circuitry and configured to control (e.g., reduce or limit) the bit - length of the input variables of a linear regression operation; apply a linear regression operation to the controlled bit - length input variables; derive an affine motion model based on the execution of the linear regression operation; and decode a current block of video data based on the affine motion model.

[0285] Figure 15is a flowchart showing an example method for encoding a current block according to the techniques of the present disclosure. The current block may be or include a current CU. Although described with respect to video encoder 200 ( Figure 1 and 13 ), it should be understood that other devices may be configured to perform methods similar to Figure 15 .

[0286] In this example, video encoder 200 initially predicts the current block (350). For example, video encoder 200 may form a predicted block of the current block. When forming the predicted block, video encoder 200 (e.g., motion estimation unit 222) may perform Figure 12 . Video encoder 200 may then compute a residual block (352) of the current block. To compute the residual block, video encoder 200 may compute the difference between the original uncoded block and the predicted block of the current block. Video encoder 200 may then transform the residual block and quantize the transform coefficients of the residual block (354). Next, video encoder 200 may scan the quantized transform coefficients of the residual block (356). During or after the scan, video encoder 200 may entropy encode the transform coefficients (358). For example, video encoder 200 may use CAVLC or CABAC to encode the transform coefficients. Video encoder 200 may then output the entropy encoded data of the block (360).

[0287] Figure 16 is a flowchart illustrating an example method for decoding a current video data block according to the techniques of the present invention. The current block may be or include a current CU. Although described with respect to video decoder 300 ( Figure 1 and 14 ), it should be understood that other devices may be configured to perform methods similar to Figure 16 .

[0288] Video decoder 300 may receive the entropy encoded data of the current block, e.g., entropy encoded prediction information and entropy encoded data of transform coefficients corresponding to the residual block of the current block (370). Video decoder 300 may entropy decode the entropy encoded data to determine the prediction information of the current block and reproduce the transform coefficients of the residual block (372). Video decoder 300 may predict the current block (374), e.g., compute a predicted block of the current block using an intra or inter prediction mode as indicated by the prediction information of the current block. When predicting the current block, video decoder 300 (e.g., motion compensation unit 316) may perform Figure 12technique. The video decoder 300 may then reverse scan the reproduced transform coefficients (376) to produce a quantized transform coefficient block. The video decoder 300 may then inverse quantize the transform coefficients and apply an inverse transform to the transform coefficients to produce a residual block (378). The video decoder 300 may finally decode the current block (380) by combining a prediction block and the residual block.

[0289] The following numbered clauses illustrate one or more aspects of the devices and techniques described in this disclosure.

[0290] Article 1A. A method of decoding video data, the method comprising: reducing the bit lengths of one or more input variables of a linear regression; performing a linear regression on the one or more input variables having reduced bit lengths; deriving an affine motion model based on performing the linear regression on the one or more input variables having reduced bit lengths; and decoding the video data based on the affine motion model.

[0291] Article 2A. The method according to Article 1A, further comprising determining affine motion information based on the affine motion model.

[0292] Article 3A. The method according to Article 2A, wherein the affine motion information includes an affine motion candidate.

[0293] Article 4A. The method according to any one of Articles 1A - 3A, wherein the one or more input variables include at least one of incremental coordinates, incremental motion vectors, number of sub - blocks, or selected sub - blocks.

[0294] Article 5A. The method according to any one of Articles 1A - 4A, wherein reducing the bit lengths of one or more input variables includes: determining that at least one of the bit lengths of the value of incremental x or the value of incremental y is greater than an incremental x incremental y bit length threshold, wherein the value of incremental x includes a value indicating a distance in the x - direction between a current sub - block of a current block and an x - anchor coordinate of the current block, and wherein the value of incremental y includes a value indicating a distance in the y - direction between the current sub - block and a y - anchor coordinate of the current block; and based on at least one of the bit lengths of the value of incremental x or the value of incremental y being greater than the incremental x incremental y bit length threshold, skipping the current sub - block as an input to the one or more input variables of the linear regression.

[0295] Article 6A. The method according to Article 5A, wherein the incremental x incremental y bit length threshold is 8 bits.

[0296] Article 7A. For the method according to any one of Articles 1A - 4A, wherein reducing the bit length of one or more input variables includes: determining that the bit length of the incremental motion vector component is greater than the incremental motion vector bit length threshold; and based on the bit length of the incremental motion vector component being greater than the incremental motion vector bit length threshold, skipping the current sub - block as an input for one or more input variables of the linear regression.

[0297] Article 8A. For the method according to Article 7A, wherein the incremental motion vector bit length threshold is 12 bits.

[0298] Article 9A. For the method according to any one of Articles 1A - 8A, wherein reducing the bit length of the one or more input variables includes reducing the number of sub - blocks used in the linear regression from at least one of a template region or a non - adjacent affine block, wherein the non - adjacent affine block is a video data block that is not adjacent to the current block and uses an affine mode for decoding.

[0299] Article 10A. For the method according to any one of Articles 1A - 9A, wherein reducing the bit length of one or more input variables includes selecting a subset of sub - blocks of the current block of the video data to be used as inputs for one or more input variables of the linear regression, and the subset of sub - blocks is less than the total number of sub - blocks within the current block.

[0300] Article 11A. For the method according to any one of Articles 1A - 10A, further includes reducing the bit length of one or more intermediate values of the linear interpolation.

[0301] Article 12A. For the method according to Article 11A, wherein reducing the bit length of one or more intermediate values of the linear interpolation includes right - shifting the denominator of the equation and right - shifting the numerator of the equation.

[0302] Article 13A. For the method according to any one of Articles 1A - 12A, further includes restricting the bit length of one or more linear regression output parameters.

[0303] Article 14A. For the method according to Article 13A, wherein restricting the bit length of one or more linear regression output parameters includes clipping one or more linear regression output parameters.

[0304] Article 15A. For the method according to Article 14A, wherein clipping one or more linear regression output parameters includes clipping each of one or more linear regression output parameters to the same number of bits.

[0305] Article 16A. For the method according to Article 14A, wherein clipping one or more linear regression output parameters includes clipping at least one of one or more linear regression output parameters to a different number of bits than the other parameters of one or more linear regression output parameters.

[0306] Article 17A. The method according to any one of 1A - 16A, wherein encoding includes decoding.

[0307] Article 18A. The method according to any one of 1A - 17A, wherein encoding includes encoding.

[0308] Article 19A. An apparatus for decoding video data, the apparatus including one or more devices for performing the method according to any one of Articles 1A - 18A.

[0309] Article 20A. The apparatus according to Article 19A, wherein the one or more devices include one or more processors implemented in a circuit.

[0310] Article 21A. The apparatus according to any one of 19A or 20A, further including a memory for storing the video data.

[0311] Article 22A. The apparatus according to any one of 19A - 21A, further including a display configured to display the decoded video data.

[0312] Article 23A. The apparatus according to any one of 19A - 22A, wherein the apparatus includes one or more of a camera, a computer, a mobile device, a broadcast receiver device, or a set - top box.

[0313] Article 24A. The apparatus according to any one of Articles 19A - 23A, wherein the apparatus includes a video decoder.

[0314] Article 25A. The apparatus according to any one of 19A - 24A, wherein the apparatus includes a video encoder.

[0315] Article 26A. A computer - readable storage medium having instructions stored thereon, which when executed cause one or more processors to perform the method according to any one of Articles 1A - 18A.

[0316] Article 1B. A method for decoding video data, the method including: controlling a bit length of an input variable of a linear regression operation, the input variable including at least one of a) one or more incremental coordinates, b) one or more incremental motion vectors, or c) a value representing a number of sub - blocks; performing a linear regression operation on the input variable with the controlled bit length; deriving an affine motion model based on performing the linear regression operation; and encoding a current block of the video data based on the affine motion model.

[0317] Article 2B. The method according to 1B, wherein controlling the bit length of an input variable comprises: determining that the bit length of at least one of an incremental x value or an incremental y value of one or more incremental coordinates is greater than an incremental x incremental y bit length threshold, wherein the incremental x value comprises a value indicating a distance in the x direction between a current sub-block of a current block and an x anchor coordinate of the current block, and wherein the incremental y value comprises a value indicating a distance in the y direction between the current sub-block and a y anchor coordinate of the current block, and skipping the current sub-block as an input to a linear regression operation based on the bit length of at least one of the incremental x value or the incremental y value being greater than the incremental x incremental y bit length threshold.

[0318] Article 3B. The method according to Article 2B, wherein the incremental x incremental y bit length threshold is 8 bits.

[0319] Article 4B. The method according to any one of Articles 1B - 3B, wherein controlling the bit length of an input variable comprises: determining that the bit length of an incremental motion vector component is greater than an incremental motion vector bit length threshold; and skipping the current sub-block as an input to a linear regression operation based on the bit length of the incremental motion vector component being greater than the incremental motion vector bit length threshold.

[0320] Article 5B. The method according to any one of Articles 1B - 3B, wherein controlling the bit length of an input variable comprises: determining that the bit length of an incremental motion vector component is greater than an incremental motion vector bit length threshold; and clipping the incremental motion vector component to a length of the incremental motion vector bit length threshold based on the bit length of the incremental motion vector component being greater than the incremental motion vector bit length threshold.

[0321] Article 6B. The method according to Article 5B, wherein the incremental motion vector bit length threshold is 12 bits.

[0322] Article 7B. The method according to any one of Articles 1B - 3B, wherein controlling the bit length of an input variable comprises: determining whether the bit length of an incremental motion vector component is greater than a first incremental motion vector bit length threshold or less than a second incremental motion vector bit length threshold; and using an alternative incremental motion vector component instead of the incremental motion vector component as an input to a linear regression operation based on the determination that the bit length of the incremental motion vector component is greater than the first incremental motion vector bit length threshold or less than the second incremental motion vector bit length threshold, the alternative incremental motion vector component having a bit length less than that of the incremental motion vector component.

[0323] Article 8B. The method according to any one of 1B - 7B, wherein controlling the bit length of an input variable comprises reducing the bit length of a value representing the number of sub-blocks used in a linear regression operation to a predetermined bit length.

[0324] Article 9B. The method according to Article 8B, wherein the predetermined bit length is 8 bits.

[0325] Article 10B. The method according to 8B or 9B, wherein controlling the bit length of an input variable includes selecting a subset of sub-blocks of a current block of video data for a linear regression operation, the subset of sub-blocks being less than the total number of sub-blocks in the current block, and wherein the method further includes: determining a first number of sub-blocks within a template region; and determining a second number of sub-blocks within a non-neighboring affine block, wherein the non-neighboring affine block is a block of video data that is not adjacent to the current block and that is decoded using an affine mode.

[0326] Article 11B. The method according to 10B, wherein the first number includes M / 2 and the second number includes M / 2, where M represents the number of sub-blocks used in the linear regression operation.

[0327] Article 12B. The method according to 10B, wherein the first number includes M / 4 and the second number includes M - M / 4, where M represents the number of sub-blocks used in the linear regression operation.

[0328] Article 13B. The method according to 10B, further including: determining T, the maximum number of sub-blocks allowed in the template region; and determining the number T' of available sub-blocks from the template region, wherein the first number S is equal to min(T, T') and the second number is equal to M – S, where M represents the number of sub-blocks used in the linear regression operation.

[0329] Article 14B. The method according to any one of Articles 10B - 13B, wherein selecting the subset of sub-blocks includes selecting the sub-blocks in a scan order.

[0330] Article 15B. The method according to any one of Articles 10B - 13B, wherein selecting the subset of sub-blocks includes subsampling using a predetermined subsampling ratio.

[0331] Article 16B. The method according to any one of 10B - 13B, wherein selecting the subset of sub-blocks includes: subsampling the sub-blocks in the template region using a predetermined subsampling ratio; and selecting non-neighboring affine sub-blocks in a scan order until the number of selected sub-blocks is equal to the second number.

[0332] Article 17B. The method according to any one of 10B - 13B, wherein selecting a subset of sub - blocks includes: determining whether at least one of the height or width of the current CU of the current block is equal to 256; based on the determination that at least one of the height or width of the current CU is equal to 256, performing subsampling in at least one of a horizontal template row scan of the template region or a vertical template column scan of the template region at a subsampling ratio; determining the total number T of sub - blocks in the template region; determining whether the total number of available non - adjacent affine sub - blocks is greater than 255 - T; and based on the determination that the total number of available non - adjacent affine sub - blocks is greater than 255 - T, using the first 255 - T available non - adjacent affine sub - blocks in raster scan order as the input for the linear regression operation.

[0333] Article 18B. The method according to any one of 1B - 17B, further comprising restricting the bit length of one or more linear regression operation output parameters.

[0334] Article 19B. The method according to Article 18B, wherein restricting the bit length of one or more linear regression operation output parameters includes clipping one or more linear regression operation output parameters.

[0335] Article 20B. The method according to Article 19B, wherein clipping one or more linear regression operation output parameters includes clipping each of one or more linear regression operation output parameters to the same number of bits.

[0336] Article 21B. The method according to Article 19B, wherein clipping one or more linear regression operation output parameters includes clipping at least one of one or more linear regression operation output parameters to a different number of bits than the other parameters of one or more linear regression operation output parameters.

[0337] Article 22B. The method according to 21B, wherein clipping at least one of one or more linear regression operation output parameters to a different number of bits than the other parameters of one or more linear regression operation output parameters includes: clipping the first linear regression operation output parameter to the range of [-(1<<(M + N)), (1<<(M + N)) - 1]; and clipping the second and third linear regression operation output parameters to the range of [-(1<<(M - 1)), (1<<(M - 1)) - 1], where M = 12 and N = 8.

[0338] Article 23B. The method according to any one of Articles 1B - 22B, further comprising determining an affine motion candidate based on an affine motion model.

[0339] Article 24B. An apparatus for decoding video data, the apparatus comprising: a memory configured to store video data; and one or more processors communicatively coupled to the memory, the one or more processors being configured to: control a bit length of an input variable for a linear regression operation, the input variable including at least one of a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing a number of sub-blocks; perform a linear regression operation on the input variable with the controlled bit length; derive an affine motion model based on performing the linear regression operation; and decode a current block of the video data based on the affine motion model.

[0340] Article 25B. The apparatus according to Article 24B, wherein as part of controlling the bit length of the input variable, the one or more processors are configured to: determine that a bit length of at least one of a delta x value or a delta y value of the one or more delta coordinates is greater than a delta x delta y bit length threshold, wherein the delta x value includes a value indicating a distance in the x direction between a current sub-block of the current block and an x anchor coordinate of the current block, and wherein the delta y value includes a value indicating a distance in the y direction between the current sub-block and a y anchor coordinate of the current block; and skip the current sub-block as an input to the linear regression operation based on the bit length of at least one of the delta x value or the delta y value being greater than the delta x delta y bit length threshold.

[0341] Article 26B. The apparatus according to clause 25B, wherein the delta x delta y bit length threshold is 8 bits.

[0342] Article 27B. The apparatus according to any one of clauses 24B-26B, wherein as part of controlling the bit length of the input variable, the one or more processors are configured to: determine that a bit length of a delta motion vector component is greater than a delta motion vector bit length threshold; and skip the current sub-block as an input to the linear regression operation based on the bit length of the delta motion vector component being greater than the delta motion vector bit length threshold.

[0343] Article 28B. The apparatus according to any one of clauses 24B-26B, wherein as part of controlling the bit length of the input variable, the one or more processors are configured to: determine that a bit length of a delta motion vector component is greater than a delta motion vector bit length threshold; and clip the delta motion vector component to a length of the delta motion vector bit length threshold based on the bit length of the delta motion vector component being greater than the delta motion vector bit length threshold.

[0344] Article 29B. The apparatus according to Article 28B, wherein the delta motion vector bit length threshold is 12 bits.

[0345] Article 30B. For the device according to any one of Articles 24B - 26B, wherein as part of the bit length of the control input variable, one or more processors are configured to: determine whether the bit length of the incremental motion vector component is greater than a first incremental motion vector bit length threshold or less than a second incremental motion vector bit length threshold; and based on the determination that the bit length of the incremental motion vector component is greater than the first incremental motion vector bit length threshold or less than the second incremental motion vector bit length threshold, use an alternative incremental motion vector component with a bit length less than that of the incremental motion vector component to replace the incremental motion vector component as the input for the linear regression operation.

[0346] Article 31B. For the device according to any one of Articles 24B - 30B, wherein as part of the bit length of the control input variable, the one or more processors are configured to reduce the bit length of the value representing the number of sub - blocks used in the linear regression operation to a predetermined bit length.

[0347] Article 32B. For the device according to Article 31B, wherein the predetermined bit length is 8 bits.

[0348] Article 33B. For the device according to Article 31B or Article 32B, wherein as part of the bit length of the control input variable, the one or more processors are configured to select a subset of the sub - blocks of the current block of video data to be used as inputs for one or more input variables of the linear regression operation, the subset of sub - blocks being less than the total number of sub - blocks within the current block, and wherein the one or more processors are further configured to: determine a first number of sub - blocks within the template region; and determine a second number of sub - blocks within non - adjacent affine blocks, where non - adjacent affine blocks are video data blocks that are not adjacent to the current block and use an affine mode for decoding.

[0349] Article 34B. For the device according to Article 33B, wherein the first number includes M / 2, and the second number includes M / 2, where M represents the number of sub - blocks used in the linear regression operation.

[0350] Article 35B. For the device according to Article 33B, wherein the first number includes M / 4, and the second number includes M - M / 4, where M represents the number of sub - blocks used in the linear regression operation.

[0351] Article 36B. For the device according to Article 33B, wherein the one or more processors are further configured to: determine T, the maximum number of sub - blocks allowed in the template region; and determine T’, the number of available sub - blocks from the template region, where the first number S is equal to min(T, T’), and the second number is equal to M – S, where M represents the number of sub - blocks used in the linear regression operation.

[0352] Article 37B. The apparatus according to any one of Articles 33B - 36B, wherein as part of a subset of selected sub - blocks, the one or more processors are configured to select sub - blocks in a scan order.

[0353] Article 38B. The apparatus according to any one of Articles 33B - 36B, wherein as part of a subset of selected sub - blocks, the one or more processors are configured to perform subsampling using a predetermined subsampling rate.

[0354] Article 39B. The apparatus according to any one of Articles 33B - 36B, wherein as part of a subset of selected sub - blocks, the one or more processors are configured to: perform subsampling on sub - blocks in a template region using a predetermined subsampling rate; and select non - adjacent affine sub - blocks in a scan order until the number of selected sub - blocks is equal to a second number.

[0355] Article 40B. The apparatus according to any one of Articles 33B - 36B, wherein as part of a subset of selected sub - blocks, one or more processors are configured to: determine whether at least one of the height or width of the current CU of the current block is equal to 256; based on the determination that at least one of the height or width of the current CU is equal to 256, perform subsampling in at least one of a horizontal template row scan or a vertical template column scan of the template region at a subsampling ratio; determine the total number T of sub - blocks in the template region; determine whether the total number of available non - adjacent affine sub - blocks is greater than 255 - T; and based on the determination that the total number of available non - adjacent affine sub - blocks is greater than 255 - T, use the first 255 - T available non - adjacent affine sub - blocks in a raster scan order as inputs to a linear regression operation.

[0356] Article 41B. The apparatus according to any one of Articles 24B - 40B, wherein the one or more processors are further configured to limit the bit length of one or more linear regression operation output parameters.

[0357] Article 42B. The apparatus according to Article 41B, wherein as part of limiting the bit length of one or more linear regression operation output parameters, the one or more processors are configured to clip the one or more linear regression operation output parameters.

[0358] Article 43B. The apparatus according to Article 42B, wherein as part of clipping the one or more linear regression operation output parameters, the one or more processors are configured to clip each of the one or more linear regression operation output parameters to the same number of bits.

[0359] Article 44B. The apparatus according to clause 42B, wherein as part of clipping the output parameters of the one or more linear regression operations, the one or more processors are configured to clip at least one of the output parameters of the one or more linear regression operations to a different number of bits than the other output parameters of the one or more linear regression operations.

[0360] Article 45B. The apparatus according to clause 44B, wherein as part of clipping at least one of the output parameters of the one or more linear regression operations to a different number of bits than the other output parameters of the one or more linear regression operations, the one or more processors are configured to: clip a first linear regression operation output parameter to a range of [-(1 << (M + N)), (1 << (M + N)) - 1]; and clip a second linear regression operation output parameter and a third linear regression operation output parameter to a range of [-(1 << (M - 1)), (1 << (M - 1)) - 1], where M = 12 and N = 8.

[0361] Article 46B. The apparatus according to any one of clauses 24B - 45B, wherein the one or more processors are further configured to determine an affine motion candidate based on an affine motion model.

[0362] Article 47B. The apparatus according to any one of clauses 24B - 46B, further comprising a display configured to display decoded video data.

[0363] Article 48B. The apparatus according to any one of clauses 24B - 47B, wherein the apparatus includes one or more of a camera, a computer, a mobile device, a broadcast receiver device, or a set - top box.

[0364] Article 49B. A non - transitory computer - readable storage medium having instructions stored thereon that, when executed, cause one or more processors to: control the bit lengths of input variables of a linear regression operation to generate one or more input variables with reduced bit lengths, the input variables including at least one of a) one or more incremental coordinates, b) one or more incremental motion vectors, or c) a value representing the number of sub - blocks; perform a linear regression operation on the input variables with controlled bit lengths; derive an affine motion model based on performing the linear regression operation; and decode a current video data block based on the affine motion model.

[0365] Article 50B. An apparatus for decoding video data, the apparatus comprising: an apparatus for controlling a bit length of input variables of a linear regression operation to generate one or more input variables with reduced bit lengths, the one or more input variables including at least one of a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing a number of sub-blocks; an apparatus for performing a linear regression operation on the input variables with controlled bit lengths; an apparatus for deriving an affine motion model based on performing the linear regression operation; and an apparatus for decoding a current block of video data based on the affine motion model.

[0366] It should be appreciated that depending on the example, certain actions or events of any of the techniques described herein may be performed in a different order, may be added, combined, or entirely omitted (e.g., not all described actions or events are necessary for the practice of the technique). Additionally, in some examples, the actions or events may be performed concurrently, such as by multithreaded processing, interrupt processing, or multi-processor, rather than sequentially.

[0367] In one or more examples, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored on or transmitted over as one or more instructions or code on a computer-readable medium and executed by a hardware-based processing unit. The computer-readable medium may include a computer-readable storage medium corresponding to a tangible medium such as a data storage medium, or a communication medium including any medium that facilitates transfer of a computer program from one place to another, for example, according to a communication protocol. In this manner, the computer-readable medium generally may correspond to (1) a tangible non-transitory computer-readable storage medium, or (2) a communication medium such as a signal or carrier wave. The data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and / or data structures for implementing the techniques described in this disclosure. A computer program product may include a computer-readable medium.

[0368] By way of example, and not limitation, such a computer-readable storage medium can include one or more of RAM, ROM, EEPROM, CD-ROM, or other optical disk storage, magnetic disk storage, or other magnetic storage devices, flash memory, or any other medium that can be used to store the desired program code in the form of instructions or data structures and that can be accessed by a computer. Similarly, any connection is properly termed a computer-readable medium. For example, if instructions are transmitted using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of the medium. However, it should be understood that computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transient media, but rather refer to non-transitory, tangible storage media. As used herein, disk and optical disks include compact disk (CD), laser disk, optical disk, digital versatile disk (DVD), floppy disk, and Blu-ray disk, where disks typically reproduce data magnetically, while optical disks reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0369] The instructions can be executed by one or more processors, such as one or more DSPs, general-purpose microprocessors, ASICs, FPGAs, or other equivalent integrated or discrete logic circuitry. Thus, the terms "processor" and "processing circuitry" as used herein can refer to any of the foregoing structures or any other structure suitable for implementing the techniques described herein. In addition, in some aspects, the functions described herein can be provided in dedicated hardware and / or software modules configured for encoding and decoding, or incorporated in a combined codec. Similarly, these techniques can be implemented entirely in one or more circuits or logic elements.

[0370] The techniques of the present disclosure can be implemented in a variety of devices or apparatuses, including wireless handsets, integrated circuits (ICs), or a group of ICs (e.g., a chipset). Various components, modules, or units are described in the present disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but need not necessarily be implemented by different hardware units. Instead, as described above, the various units can be combined in a codec hardware unit with appropriate software and / or firmware, or provided by a collection of interoperating hardware units, including one or more processors as described above.

[0371] Various examples have been described. These and other examples are within the scope of the following claims.

Claims

1. A method for decoding video data, the method comprising: Controlling a bit length of an input variable of a linear regression operation, the input variable including at least one of a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing a number of sub - blocks; Performing a linear regression operation on the input variable with the controlled bit length; Deriving an affine motion model based on performing the linear regression operation; and Decoding a current block of the video data based on the affine motion model.

2. The method according to claim 1, wherein controlling the bit length of the input variable includes: Determining that a bit length of at least one of a delta x value or a delta y value of one or more delta coordinates is greater than a delta x delta y bit length threshold, wherein the delta x value includes a value indicating a distance in the x - direction between a current sub - block of the current block and an x - anchor coordinate of the current block, and wherein the delta y value includes a value indicating a distance in the y - direction between the current sub - block and a y - anchor coordinate of the current block, and Based on the bit length of at least one of the delta x value or the delta y value being greater than the delta x delta y bit length threshold, skipping the current sub - block as an input to the linear regression operation.

3. The method according to claim 2, wherein the delta x delta y bit length threshold is 8 bits.

4. The method according to claim 1, wherein controlling the bit length of the input variable includes: Determining that a bit length of a delta motion vector component is greater than a delta motion vector bit length threshold; and Based on the bit length of the delta motion vector component being greater than the delta motion vector bit length threshold, skipping the current sub - block as an input to the linear regression operation.

5. The method according to claim 1, wherein controlling the bit length of the input variable includes: Determining that a bit length of a delta motion vector component is greater than a delta motion vector bit length threshold; and Based on the bit length of the delta motion vector component being greater than the delta motion vector bit length threshold, clipping the delta motion vector component to a length of the delta motion vector bit length threshold.

6. The method according to claim 5, wherein the delta motion vector bit length threshold is 12 bits.

7. The method according to claim 1, wherein controlling the bit length of the input variable includes: Determining whether a bit length of a delta motion vector component is greater than a first delta motion vector bit length threshold or less than a second delta motion vector bit length threshold; and Based on the determination that the bit length of the delta motion vector component is greater than the first delta motion vector bit length threshold or less than the second delta motion vector bit length threshold, using a substitute delta motion vector component instead of the delta motion vector component as an input to the linear regression operation, the substitute delta motion vector component having a bit length less than that of the delta motion vector component.

8. The method according to claim 1, wherein controlling the bit length of the input variable includes reducing a bit length of a value representing a number of sub - blocks used in the linear regression operation to a predetermined bit length.

9. The method according to claim 8, wherein, the predetermined bit length is 8 bits.

10. The method according to claim 8, wherein controlling the bit length of the input variable includes selecting a subset of sub-blocks of the current block of the video data for the linear regression operation, the subset of sub-blocks being less than the total number of sub-blocks within the current block, and wherein the method further comprises: determining a first number of sub-blocks within a template region; and determining a second number of sub-blocks within a non-neighboring affine block, wherein the non-neighboring affine block is a video data block that is not adjacent to the current block and is decoded using an affine mode.

11. The method according to claim 10, wherein the first number includes M / 2 and the second number includes M / 2, where M represents the number of sub-blocks used in the linear regression operation.

12. The method according to claim 10, wherein the first number includes M / 4 and the second number includes M - M / 4, where M represents the number of sub-blocks used in the linear regression operation.

13. The method according to claim 10, further comprising: determining a maximum number T of sub-blocks allowed in the template region; and determining T′, the number of available sub-blocks from the template region, where the first number S is equal to min(T, T′) and the second number is equal to M – S, where M represents the number of sub-blocks used in the linear regression operation.

14. The method according to claim 10, wherein selecting the subset of sub-blocks includes selecting the sub-blocks in a scan order.

15. The method according to claim 10, wherein selecting the subset of sub-blocks includes subsampling using a predetermined subsampling rate.

16. The method according to claim 10, wherein selecting the subset of sub-blocks includes: subsampling the sub-blocks in the template region using a predetermined subsampling rate; and selecting non-neighboring affine sub-blocks in a scan order until the number of selected sub-blocks is equal to the second number.

17. The method according to claim 10, wherein selecting the subset of sub-blocks includes: determining whether at least one of the height and width of the current CU of the current block is equal to 256; based on determining that at least one of the height or width of the current CU is equal to 256, performing subsampling in at least one of a horizontal template row scan or a vertical template column scan of the template region at the subsampling ratio; determining the total number T of sub-blocks in the template region; determining whether the total number of available non-neighboring affine sub-blocks is greater than 255 – T; and based on the determination that the total number of available non-neighboring affine sub-blocks is greater than 255 – T, using the first 255 – T available non-neighboring affine sub-blocks in a raster scan order as inputs to the linear regression operation.

18. The method according to claim 1, further comprising restricting the bit length of one or more output parameters of the linear regression operation.

19. The method according to claim 18, wherein restricting the bit length of one or more output parameters of the linear regression operation includes clipping the one or more output parameters of the linear regression operation.

20. The method as claimed in claim 19, characterized in that clipping the one or more output parameters of the linear regression operation includes clipping each of the one or more output parameters of the linear regression operation to the same number of bits.

21. The method according to claim 19, wherein clipping the output parameters of the one or more linear regression operations includes clipping at least one of the output parameters of the one or more linear regression operations to a number of bits different from the other parameters of the output parameters of the one or more linear regression operations.

22. The method according to claim 21, wherein clipping at least one of the output parameters of the one or more linear regression operations to a number of bits different from the other parameters of the output parameters of the one or more linear regression operations includes: Clipping the output parameter of the first linear regression operation to the range of [-(1 << (M + N)), (1 << (M + N)) - 1]; and Clipping the output parameters of the second linear regression operation and the third linear regression operation to the range of [-(1 << (M - 1)), (1 << (M - 1)) - 1], where M = 12 and N = 8.

23. The method according to claim 1, further comprising determining an affine motion candidate based on an affine motion model.

24. An apparatus for decoding video data, the apparatus comprising: a memory configured to store video data ； and one or more processors communicatively coupled to the memory, the one or more processors being configured to: control the bit length of input variables of a linear regression operation, the input variables including at least one of a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing the number of sub - blocks; perform a linear regression operation on the input variables with the controlled bit length; derive an affine motion model based on performing the linear regression operation; and encode a current block of the video data based on the affine motion model.

25. The apparatus according to claim 24, wherein, as part of controlling the bit length of the input variables, the one or more processors are configured to: determine that the bit length of at least one of the delta x value or the delta y value of the one or more delta coordinates is greater than a delta x delta y bit length threshold, where the delta x value includes a value indicating the distance in the x - direction between the current sub - block of the current block and the x - anchor coordinate of the current block, and where the delta y value includes a value indicating the distance in the y - direction between the current sub - block and the y - anchor coordinate of the current block; and based on the bit length of at least one of the delta x value or the delta y value being greater than the delta x delta y bit length threshold, skip the current sub - block as an input to the linear regression operation.

26. The apparatus according to claim 25, wherein the delta x delta y bit length threshold is 8 bits.

27. The apparatus according to claim 24, wherein, as part of controlling the bit length of the input variables, the one or more processors are configured to: determine that the bit length of the delta motion vector component is greater than a delta motion vector bit length threshold; and based on the bit length of the delta motion vector component being greater than the delta motion vector bit length threshold, skip the current sub - block as an input to the linear regression operation.

28. The apparatus according to claim 24, wherein, As part of controlling the bit length of the input variable, the one or more processors are configured to: Determine that the bit length of the incremental motion vector component is greater than an incremental motion vector bit length threshold; And Based on the bit length of the incremental motion vector component being greater than the incremental motion vector bit length threshold, clip the incremental motion vector component to the length of the incremental motion vector bit length threshold.

29. The apparatus according to claim 28, Wherein, The incremental motion vector bit length threshold is 12 bits.

30. The apparatus according to claim 24, Wherein, As part of controlling the bit length of the input variable, the one or more processors are configured to: Determine whether the bit length of the incremental motion vector component is greater than a first incremental motion vector bit length threshold or less than a second incremental motion vector bit length threshold; And Based on the determination that the bit length of the incremental motion vector component is greater than the first incremental motion vector bit length threshold or less than the second incremental motion vector bit length threshold, use an alternative incremental motion vector component instead of the incremental motion vector component as the input to the linear regression operation, the alternative incremental motion vector component having a bit length less than that of the incremental motion vector component.

31. The apparatus according to claim 24, Wherein, As part of controlling the bit length of the input variable, the one or more processors are configured to reduce the bit length of the value representing the number of sub - blocks used in the linear regression operation to a predetermined bit length.

32. The apparatus according to claim 31, Wherein, The predetermined bit length is 8 bits.

33. The apparatus according to claim 31, Wherein, As part of controlling the bit length of the input variable, the one or more processors are configured to select a subset of sub - blocks of the current block of the video data to be used as the input of the one or more input variables of the linear regression operation, the subset of sub - blocks being less than the total number of sub - blocks within the current block, and wherein the one or more processors are further configured to: Determine a first number of sub - blocks within the template region; and Determine a second number of sub - blocks within a non - neighboring affine block, where the non - neighboring affine block is a video data block that is not adjacent to the current block and is decoded using an affine mode.

34. The apparatus according to claim 33, wherein the first number includes M / 2, the second number includes M / 2, where M represents the number of sub - blocks used in the linear regression operation.

35. The apparatus according to claim 33, wherein the first number includes M / 4, the second number includes M - M / 4, where M represents the number of sub - blocks used in the linear regression operation.

36. The apparatus according to claim 33, Wherein, The one or more processors are further configured to: Determine T, the maximum number of sub - blocks allowed in the template region; and Determine T′, the number of available sub - blocks from the template region, Where the first number S is equal to min(T, T′), and the second number is equal to M – S, where M represents the number of sub - blocks used in the linear regression operation.

37. The apparatus according to claim 33, wherein, as part of a subset of selected sub - blocks, the one or more processors are configured to select sub - blocks in a scan order.

38. The apparatus according to claim 33, wherein, as part of a subset of selected sub - blocks, the one or more processors are configured to subsample using a predetermined subsampling rate.

39. The apparatus according to claim 33, wherein, as part of a subset of selected sub - blocks, the one or more processors are configured to: subsample sub - blocks in a template region using a predetermined subsampling rate; and select non - adjacent affine sub - blocks in a scan order until the number of selected sub - blocks is equal to a second number.

40. The apparatus according to claim 33, wherein, as part of a subset of selected sub - blocks, the one or more processors are configured to: determine whether at least one of the height and width of the current CU of the current block is equal to 256; based on determining that at least one of the height or width of the current CU is equal to 256, perform subsampling in at least one of a horizontal template row scan or a vertical template column scan of the template region at a subsampling ratio; determine the total number T of sub - blocks in the template region; determine whether the total number of available non - adjacent affine sub - blocks is greater than 255 - T; and based on the determination that the total number of available non - adjacent affine sub - blocks is greater than 255 - T, use the first 255 - T available non - adjacent affine sub - blocks in a raster scan order as input for a linear regression operation.

41. The apparatus according to claim 24, wherein, the one or more processors are further configured to limit the bit length of one or more linear regression operation output parameters.

42. The apparatus according to claim 41, wherein, as part of limiting the bit length of one or more linear regression operation output parameters, the one or more processors are configured to clip the one or more linear regression operation output parameters.

43. The apparatus according to claim 42, wherein, as part of clipping the one or more linear regression operation output parameters, the one or more processors are configured to clip each of the one or more linear regression operation output parameters to the same number of bits.

44. The apparatus as claimed in claim 42, characterized in that, as part of clipping the one or more linear regression operation output parameters, the one or more processors are configured to clip at least one of the one or more linear regression operation output parameters to a different number of bits than the other parameters of the one or more linear regression operation output parameters.

45. The apparatus according to claim 44, wherein as part of clipping at least one of the one or more linear regression operation output parameters to a different number of bits than the other parameters of the one or more linear regression operation output parameters, the one or more processors are configured to: clip a first linear regression operation output parameter to a range of [-(1<<(M + N)), (1<<(M + N)) - 1]; and Clip the second linear regression operation output parameter and the third linear regression operation output parameter to the range of [-(1 << (M - 1)), (1 << (M - 1)) - 1], where M = 12 and N = 8.

46. The apparatus according to claim 24, wherein, the one or more processors are further configured to determine an affine motion candidate based on an affine motion model.

47. The apparatus according to claim 24, further comprising a display configured to display decoded video data.

48. The apparatus according to claim 24, wherein, the apparatus includes one or more of a camera, a computer, a mobile device, a broadcast receiver device, or a set-top box.

49. A non-transitory computer-readable storage medium having instructions stored thereon that, when executed, cause one or more processors to: control a bit length of an input variable of a linear regression operation to generate one or more input variables with a reduced bit length, the input variables including at least one of a) one or more incremental coordinates, b) one or more incremental motion vectors, or c) a value representing a number of sub-blocks; perform a linear regression operation on the input variables with the controlled bit length; derive an affine motion model based on performing the linear regression operation; and encode a current video data block based on the affine motion model.

50. An apparatus for decoding video data, the apparatus comprising: means for controlling a bit length of an input variable of a linear regression operation to generate one or more input variables with a reduced bit length, the one or more input variables including at least one of a) one or more incremental coordinates, b) one or more incremental motion vectors, or c) a value representing a number of sub-blocks; means for performing a linear regression operation on the input variables with the controlled bit length; means for deriving an affine motion model based on performing the linear regression operation; and means for decoding a current block of video data based on the affine motion model.

Images