Method for improving accuracy of simulation frequency sweeping power

Abstract

The invention belongs to the technical field of analog frequency sweeping, and particularly relates to a method for improving the accuracy of analog frequency sweeping power, which comprises the following steps: after scanning is started, a timer starts timing, a frequency divider starts to accumulate according to a frequency division clock and a step Fstep, and outputs a current frequency division ratio, when time reaches T1, the timer stops working, and the frequency divider stops accumulating at the same time, at the moment, the frequency dividing ratio of the frequency divider is Nstop, scanning is stopped, compensation data output is controlled through the frequency dividing ratio, it is always guaranteed that the current scanning frequency corresponds to the current compensation power data, and the method is very accurate.

Description

Technical Field

[0001] This application belongs to the technical field of analog sweep frequency, and particularly relates to a method for improving the power accuracy of analog sweep frequency. Background Art

[0002] Analog sweep frequency has a wide range of applications in many fields. In vector network analysis instruments, it is necessary to perform frequency sweeping on the frequency band to be measured to obtain the frequency characteristics of the device under test; in the test of the tracking performance of a phase-locked loop, an analog sweep frequency signal is also required to simulate the Doppler effect of the actual signal.

[0003] Analog sweep frequency has a trigger output that outputs a trigger signal at regular intervals. When the power buffer receives the trigger signal, it will output the power compensation data at the current frequency. Since there is a certain error between the trigger signal and the actual output frequency, there is an error between the output frequency and the trigger signal during high-speed scanning, resulting in a certain error in the power during analog sweep frequency. Especially at the band switching point, the compensation data may retrieve the data of the next band point, resulting in a large error. Summary of the Invention

[0004] Based on the above problems, without changing the traditional hardware circuit, this application only changes the internal algorithm of its FPGA to improve the accuracy. The technical solution is as follows:

[0005] A method for improving the power accuracy of analog sweep frequency, including a frequency divider accumulator, a reference clock, a timer, and an FPGA. The reference clock F clock is divided into two paths. One path is the phase discrimination reference signal, and the other path is the clock signal of the FPGA. The coupled output of the YTO signal is phase discriminated with the reference signal through the frequency divider. The phase discrimination output signal is integrated to control the YTO. The YTO output signal is output through any channel according to the current frequency. One path of the channel output signal is output as a whole machine, and the other path controls the linear modulator through detection integration to control the power of the entire path. The frequency divider accumulator determines whether to output compensation data according to the current frequency point. The FPGA controls the division ratio of the starting frequency Fstart and uses the division ratio to determine the compensation data (innovative part).

[0006] Preferably, the power compensation data is determined by the actual output channel: according to the band setting, directly call all the power compensation data of the current channel;

[0007] The compensation data is determined by the division ratio: judge the current sweep frequency according to the current division ratio. Since the power compensation is carried out in a certain frequency step, if the sweep frequency exceeds the current step, new power compensation data is output.

[0008] Preferably, when starting to scan:

[0009] S1. Control the starting frequency F through FPGA start division ratio, division ratio N start = F start / F clock ;

[0010] S2. FPGA configures YTO, phase discriminator, power compensation data, etc.;

[0011] S3. Configure the scanning time of this section to T according to the scanning time T 1 ;

[0012] S4. Calculate the division ratio step of the frequency divider according to the divided clock frequency F clock F = (F step - F stop ) / (T start * F 1 ) clock ;

[0013] S5. Calculate the scanning time step according to the total time T, T step = T / 1024, time is measured through the reference clock to obtain the power compensation clock frequency F powersteep = 1 / T step ;

[0014] S6. Calculate the power compensation data according to the scanning start frequency, stop frequency and frequency band, store all the compensation data in the register, and select the compensation data according to the current division ratio and frequency band to ensure that the output frequency depends on the division ratio and frequency band.

[0015] Preferably, after the scanning starts, the timer starts timing, and at the same time the frequency divider starts to accumulate according to the divided clock at the step F step and outputs the current division ratio at the same time. When the time reaches T 1 , the timer stops working, and the frequency divider terminates the accumulation at the same time. At this time, the division ratio of the frequency divider is N stop , and the scanning stops.

[0016] Preferably, during the scanning process, the compensation data is triggered according to the divided clock frequency F clock so that the power compensation data is output every other section.

[0017] Compared with the prior art, the beneficial effects of this application are as follows:

[0018] 1. This application innovatively controls the call of power compensation data through channel selection. When the current frequency band is within one channel, the compensation data of the next frequency band is not called, and large power deviation will not be caused.

[0019] 2. The innovation of this application controls the output of compensation data through the frequency division ratio, always ensuring that the current scanning frequency corresponds to the current compensation power data, which is very accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a traditional analog sweep frequency hardware circuit;

[0021] Figure 2 is the schematic diagram of the power compensation FPGA of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0023] A method for improving the power accuracy of analog sweep frequency includes a frequency divider accumulator, a reference clock, a timer, and a PFGA. The reference clock Fclock is divided into two paths. One path is the phase discrimination reference signal, and the other path is the clock signal of the FPGA. The coupled output of the YTO signal is phase discriminated with the reference signal through the frequency divider. The phase discrimination output signal controls the YTO after integration. The output signal of the YTO is output through any channel according to the current frequency. One path of the channel output signal is output as a whole machine, and the other path controls the linear modulator through detection and integration to control the power of the entire path. The frequency divider accumulator determines whether to output compensation data according to the current frequency point. The FPGA controls the frequency division ratio of the starting frequency Fstart and uses the frequency division ratio to determine the compensation data.

[0024] Determine the power compensation data by the actual output channel: directly call all the power compensation data of the current channel according to the band setting;

[0025] Determine the compensation data by the frequency division ratio: judge the current sweep frequency according to the current frequency division ratio. Since the power compensation is carried out according to a certain frequency step, if the sweep frequency exceeds the current step, new power compensation data is output.

[0026] When starting to scan:

[0027] 1) Control the frequency division ratio of the starting frequency Fstart through the FPGA (the frequency division ratio Nstart is Fstart / Fclock);

[0028] 2) The FPGA configures the YTO, phase discriminator, power compensation data, etc.;

[0029] 3) Configure the scanning time of this paragraph as T according to the scanning time T 1 ;

[0030] 4) Calculate the frequency division ratio step of the frequency divider according to the divided clock frequency Fclock

[0031] Fstep = (Fstop - Fstart) / (T1 * Fclock);

[0032] 5) Calculate the scanning time step according to the total time T, Tstep = T / 1024, time the reference clock to obtain the power compensation clock frequency Fpowersteep = 1 / Tstep;

[0033] 6) Calculate the power compensation data according to the scanning start frequency, stop frequency and frequency band, store all the compensation data in the register, and judge the power compensation data according to the current frequency division ratio and frequency band to ensure that the output power depends on the frequency division ratio and the current frequency band.

[0034] After starting the scan, the timer starts timing. At the same time, the frequency divider starts to accumulate according to the divided clock starting from the step Fstep, and outputs the current frequency division ratio at the same time. When the time reaches T1, the timer stops working, and the frequency divider terminates the accumulation at the same time. At this time, the frequency division ratio of the frequency divider is Nstop, and the scan ends at this time.

[0035] During the scan, trigger the compensation data according to the divided clock frequency Fclock so that the power compensation data is output every other period.

[0036] When starting the next frequency band scan, restart steps 1, 2, 3, 4, and 5.

[0037] In the traditional design scheme, calculate the scanning time step, Tstep = T / 1024. When the scanning frequency span is large, such as 67 GHz, the frequency span is 67 GHz / 1024, which will cause poor power accuracy at the intermediate frequency points; due to the error caused by cross-channel: assume that the frequency band of channel 1 is F1 and F2. If the sweep stop frequency Fstop satisfies the following relationship, (Fstop - F2) << (F2 - F1), then the entire scan will go through channel 1. When performing power compensation, the power data of channel 2 will be called for the section from F2 to Fstop, resulting in a large power error. In this application, the power compensation data is controlled by channel selection. When the current frequency band is within one channel, the compensation data of the next frequency band is not called, and no large power deviation will be caused.

[0038] Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirits of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for improving the accuracy of analog frequency sweep power, characterized in that: Including divider accumulator, reference clock, timer and PFGA, reference clock F clock It is divided into two paths, one is the phase-locked reference signal, and the other is the FPGA clock signal; the YTO signal coupling output is phase-locked with the reference signal through a divider, and the phase-locked output signal controls the YTO after integration. The YTO output signal is output through any channel according to the current frequency. One channel output signal is output as a whole, and the other controls the linear modulator through detection integration to control the power of the entire channel. The divider accumulator determines whether the compensation data needs to be output according to the current frequency point. The FPGA controls the division ratio of the starting frequency Fstart, and uses the division ratio to determine the compensation data (innovative part).

2. The method for improving the accuracy of analog frequency sweep power according to claim 1, characterized in that: The power compensation data is determined by the actual output channel: according to the band setting, all power compensation data of the current channel are directly called; The compensation data is determined by the frequency division ratio: the current sweep frequency is determined according to the current frequency division ratio. Since the power compensation is performed according to a certain frequency step, if the sweep frequency exceeds the current step, new power compensation data is output.

3. The method for improving the accuracy of analog frequency sweep power according to claim 1, characterized in that: When starting a scan: S1. Control the starting frequency F through FPGA start The division ratio, division ratio N start =F start / F clock ; S2.FPGA configures YTO, phase detector and power compensation data, etc.; S3. According to the scanning time T, configure the scanning time of this section to T1; S4. According to the divided clock frequency F clock Calculate the frequency divider ratio step F step =(F stop -F start ) / (T1*F clock ); S5. Calculate the scan time step, T, based on the total time T step =T / 1024, the power compensation clock frequency F is obtained by timing with the reference clock powersteep =1 / T step ; S6. Calculate the power compensation data according to the scanning start frequency, end frequency and band, store all the compensation data in the register, select the compensation data according to the current division ratio and band, and ensure that the output frequency depends on the division ratio and band.

4. The method for improving the accuracy of analog frequency sweep power according to claim 1, characterized in that: After the scan starts, the timer starts timing, and the frequency divider starts to step F according to the frequency division clock. step Start accumulating and output the current frequency division ratio at the same time. When the time reaches T1, the timer stops working and the frequency divider stops accumulating at the same time. At this time, the frequency division ratio of the frequency divider is N stop , the scan ends.

5. The method for improving the accuracy of analog frequency sweep power according to claim 1, characterized in that: During the scanning process, according to the divided clock frequency F clock The compensation data is triggered so that power compensation data is output every other period.

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