Chip power supply noise influence test method and device

Abstract

The invention relates to the technical field of chip testing, and discloses a chip power supply noise influence testing method and device. The method comprises the following steps: carrying out multi-dimensional data acquisition on a chip power supply by utilizing a multi-mode sensing array to obtain original sensing data, and carrying out time synchronization calibration and signal preprocessing to obtain high-quality multi-dimensional data; carrying out time-frequency domain decomposition and correlation calculation on the processed data, and carrying out time delay and position calculation to determine noise source distribution; noise source distribution is mapped to a chip layout, multi-physical field calculation is carried out, a coupling propagation matrix is generated, and a noise propagation characteristic spectrum is obtained through characteristic value decomposition and path calculation; and designing a test condition based on the propagation characteristic spectrum, performing a chip function module performance test, establishing a response relationship between noise and function performance, determining a function failure noise critical value and a tolerance boundary, and forming a complete power supply noise influence test result. According to the method, the accurate positioning of the chip power supply noise is realized, and the evaluation accuracy of the power supply noise influence is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and particularly to a method and device for testing the influence of chip power supply noise. Background Art

[0002] In the technical field of chip design and verification, the test of the influence of power supply noise is an important link in product R & D and quality control, and the extraction of multi-dimensional noise characteristics and the analysis of propagation paths are the most critical and challenging stages in the test process. Accurately evaluating the distribution characteristics and influence mechanism of chip power supply noise is crucial for integrated circuit manufacturers, design institutions, and verification centers, directly affecting the performance stability, reliability evaluation, and power consumption optimization of chips. Therefore, an effective method for testing the influence of power supply noise to monitor noise characteristic parameters is crucial for ensuring the functional integrity and long-term reliability of chips.

[0003] Currently, time-domain analysis techniques are mainly used to process sampled data, establish a simplified noise model to evaluate the influence degree, or attempt to apply a single frequency-domain feature to the noise source tracing process to evaluate the noise type and propagation trend. However, these methods still face challenges in integrating multi-physical field coupling effects, dealing with non-linear noise characteristics, and adapting to dynamic load conditions, and these test methods often ignore some unique characteristics of chip power supply noise, such as multi-physical field coupling, temperature-noise interaction, electromagnetic interference propagation, etc., and these factors may have a significant impact on noise influence evaluation and fault location. That is, the existing methods for testing the influence of chip power supply noise ignore multi-dimensional noise characteristics and the physical coupling characteristics of the chip power supply network, resulting in a low accuracy of the final noise influence evaluation result. Summary of the Invention

[0004] The main object of the present invention is to solve the problem that the existing methods for testing the influence of chip power supply noise ignore multi-dimensional noise characteristics and the physical coupling characteristics of the chip power supply network, resulting in a low accuracy of the final noise influence evaluation result.

[0005] The first aspect of the present invention provides a method for testing the influence of chip power supply noise. The method for testing the influence of chip power supply noise includes: collecting multi-dimensional data of a target chip power supply by using a preset multi-modal sensing array to obtain original multi-dimensional sensing data, and performing time synchronization calibration and signal preprocessing on the original multi-dimensional sensing data to obtain preprocessed multi-dimensional sensing data; performing time-frequency domain decomposition operation and correlation calculation of multi-layer sensing parameters on the preprocessed multi-dimensional sensing data to obtain a hierarchical feature vector set, and calculating the noise time delay and noise spatial position of the hierarchical feature vector set to obtain a noise source spatio-temporal distribution map; performing target chip layout mapping and multi-physical field numerical calculation on the noise source spatio-temporal distribution map to generate a multi-physical field coupling propagation matrix of power supply noise, and performing noise eigenvalue decomposition and propagation path calculation on the multi-physical field coupling propagation matrix to obtain a noise propagation feature map of the power network; based on preset noise propagation test condition data and the noise propagation feature map, performing performance parameter testing on each chip function module in the target chip to obtain a noise function response relationship between power supply noise and chip function performance, and based on the noise function response relationship, determining noise critical values and power supply noise tolerance boundary surfaces corresponding to multiple chip function failures of the target chip, and generating a power supply influence test result of the target chip.

[0006] Optionally, in the first implementation manner of the first aspect of the present invention, the original multi-dimensional sensing data includes original voltage waveform data, original current waveform data, original temperature distribution data, original displacement data, and original three-dimensional electromagnetic field intensity data. The collecting of multi-dimensional data of a target chip power supply by using a preset multi-modal sensing array to obtain original multi-dimensional sensing data includes: collecting voltage waveform data of multiple voltage test points in the target chip by using a preset multi-modal sensing array to obtain original voltage waveform data, and collecting dynamic current change data of each power supply domain in the target chip by using a preset multi-modal sensing array to obtain original current waveform data, and collecting temperature field distribution data on the surface of the target chip by using a preset multi-modal sensing array to obtain original temperature distribution data, and collecting micro-mechanical displacement data of the target chip by using a preset multi-modal sensing array to obtain original displacement data, and collecting electromagnetic field distribution data in the space above the target chip by using a preset multi-modal sensing array to obtain original three-dimensional electromagnetic field intensity data.

[0007] Optionally, in the second implementation manner of the first aspect of the present invention, the time synchronization calibration and signal preprocessing of the original multi-dimensional sensing data to obtain preprocessed multi-dimensional sensing data include: calculating the contact impedance between the test point probe and the chip for the original voltage waveform data and the original current waveform data to obtain a contact impedance change value, and based on the contact impedance change value, compensating the amplitude of the original voltage waveform data to obtain compensated voltage waveform data; performing time-frequency transformation and frequency response compensation on the original current waveform data based on the probe transfer function corresponding to the multi-modal sensing array to obtain compensated current waveform data, performing spatial pixel resampling and temperature value correction calculation for the chip surface area on the original temperature distribution data to obtain calibrated temperature field data, performing PCB inherent resonance filtering and mechanical decoupling calculation on the original displacement data to obtain calibrated displacement data, and performing spatial deconvolution calculation on the original three-dimensional electromagnetic field intensity data to obtain high-resolution electromagnetic field distribution data; performing time synchronization calibration of multiple sensors on the compensated voltage waveform data, the compensated current waveform data, the calibrated temperature field data, the calibrated displacement data, and the high-resolution electromagnetic field distribution data to obtain time calibration noise data, and performing multi-dimensional abnormal data detection and spatio-temporal interpolation of abnormal points on the time calibration noise data to obtain preprocessed multi-dimensional sensing data.

[0008] Optionally, in the third implementation manner of the first aspect of the present invention, the time-frequency domain decomposition operation and correlation calculation of multi-layer sensing parameters for the preprocessed multi-dimensional sensing data to obtain a hierarchical feature vector set include: based on the power supply voltage noise characteristics corresponding to the voltage data in the preprocessed multi-dimensional sensing data, performing segmented window calculation on the voltage data in the preprocessed multi-dimensional sensing data to obtain a voltage segmented window data set, and calculating preset microscopic time-domain characteristic parameters for each window data segment in the voltage segmented window data set to obtain a voltage microscopic time-domain feature vector; performing spatial gradient calculation of the surface hot spot area and heat conduction time series calculation on the temperature field data in the preprocessed multi-dimensional sensing data to obtain a temperature field feature vector, and performing modal decomposition and harmonic resonance feature extraction on the displacement data in the preprocessed multi-dimensional sensing data to obtain a mechanical displacement feature vector, and performing spatial harmonic decomposition and field strength distribution calculation on the electromagnetic field distribution data in the preprocessed multi-dimensional sensing data to obtain an electromagnetic field feature vector, and performing decomposition calculation of the power network impedance spectrum on the voltage data and current data in the preprocessed multi-dimensional sensing data to obtain a power network impedance feature vector; performing feature dimension alignment and feature space position matching on the voltage microscopic time-domain feature vector, the temperature field feature vector, the mechanical displacement feature vector, the electromagnetic field feature vector, and the power network impedance feature vector to obtain a multi-physical quantity correlation data set, and performing multi-modal feature fusion and principal component dimensionality reduction calculation on the multi-physical quantity correlation data set to obtain a hierarchical feature vector set.

[0009] Optionally, in the fourth implementation manner of the first aspect of the present invention, the calculation of the noise time delay and noise spatial position for the hierarchical feature vector set to obtain a noise source spatio-temporal distribution map includes: classifying the noise feature types of the hierarchical feature vectors to obtain a power supply noise type classification result, and performing similarity matching calculation on various power supply noise characteristics in the power supply noise type classification result based on a preset power supply noise template library to obtain a power supply noise feature recognition result; calculating the time difference of wavefront arrival for the power supply noise feature recognition result based on the voltage waveform data in the preprocessed multi-dimensional sensing data to obtain noise propagation time data, and performing triangulation calculation of the power network time delay difference on the noise propagation time data and the power supply noise feature recognition result to obtain preliminary noise source position data; calculating the maximum intensity point and propagation direction of the power supply noise radiation for the electromagnetic field distribution data and the preliminary noise source position data in the preprocessed multi-dimensional sensing data to obtain accurate noise source position data, and performing chip space mapping and noise confidence evaluation of each noise source on the accurate noise source position data based on the power supply noise feature recognition result to obtain a noise source spatio-temporal distribution map.

[0010] Optionally, in the fifth implementation manner of the first aspect of the present invention, the target chip layout mapping and multi-physical field numerical calculation of the noise source spatio-temporal distribution map to generate a multi-physical field coupling propagation matrix of the power supply noise includes: based on the chip design layout corresponding to the target chip, performing coordinate mapping calculation of each noise source and the chip component area on the noise source spatio-temporal distribution map to obtain a noise source-component correspondence table, and using the noise source-component correspondence table and the power supply noise feature recognition result to construct an electric field distribution model of the power supply of the target chip to obtain an electric field distribution function; performing Joule heat calculation inside the chip on the electric field distribution function and the current data in the preprocessed multi-dimensional sensing data to obtain a temperature field distribution function, and performing thermal stress calculation on the temperature field distribution function and the preset chip material parameters to obtain a chip stress field function and a chip strain field function; performing deformation parameter conversion calculation on the strain field function and the preset power supply electrical network parameters to obtain an electrical parameter change function, and performing multi-physical field coupling matrix operation on the electric field distribution function, the temperature field distribution function, the stress field function, the strain field function and the electrical parameter change function to obtain a multi-physical field coupling propagation matrix.

[0011] Optionally, in the sixth implementation manner of the first aspect of the present invention, the noise eigenvalue decomposition and propagation path calculation of the multi-physical field coupling propagation matrix to obtain a noise propagation characteristic map of the power supply network includes: performing decomposition operation of the noise transfer intensity and propagation eigenvectors on the multi-physical field coupling propagation matrix to obtain a set of noise propagation eigenvectors, and constructing a power supply noise propagation network diagram of the target chip based on the set of noise propagation eigenvectors; performing power supply noise energy transmission path calculation on the power supply noise propagation network diagram to obtain a set of power supply noise propagation paths, and performing power supply network impedance transmission characteristic calculation on the noise transfer coefficients in the set of power supply noise propagation paths and the set of noise propagation eigenvectors to obtain a set of power supply noise path transfer functions; performing convolution operation of the power supply interference waveform propagation on the set of power supply noise path transfer functions and the power supply noise feature recognition result to obtain an endpoint noise prediction result, and performing mapping integration of the power supply noise propagation relationship on the power supply noise propagation network diagram, the set of noise propagation paths, the set of path transfer functions and the endpoint noise prediction result to obtain a noise propagation characteristic map of the power supply network.

[0012] Optionally, in the seventh implementation manner of the first aspect of the present invention, based on the preset noise propagation test condition data and the noise propagation characteristic map, performance parameter tests are performed on each chip function module in the target chip to obtain the noise function response relationship between the power supply noise and the chip function performance. Based on the noise function response relationship, noise critical values and power supply noise tolerance boundary surfaces corresponding to multiple chip function failures of the target chip are determined, and the power supply impact test result of the target chip is generated, including: calculating test conditions for multiple frequency bands of the noise propagation characteristic map based on the preset noise propagation test condition data to obtain a power supply noise test condition matrix, and determining a power supply noise injection test data set for the power supply end test corresponding to the target chip based on the power supply noise test condition matrix; performing performance parameter tests with multiple controlled noise signal injections on each chip function module in the target chip based on the power supply noise injection test data set to obtain a function module performance parameter response data set, and performing threshold detection calculations for multiple function modules on the function module performance parameter response data set to obtain a function module noise threshold data set; performing correlation regression calculations for power supply noise and function degradation mapping on the function module noise threshold data set and the power supply noise injection test data set to obtain the noise function response relationship between the power supply noise and the chip function performance, and performing critical condition boundary calculations for function module failures on the noise function response relationship to obtain the power supply noise tolerance boundary surface; performing power supply noise sensitivity classification and integration on the power supply noise tolerance boundary surface, the noise source spatio-temporal distribution map, and the noise propagation characteristic map to obtain the power supply noise impact test result of the target chip.

[0013] In a second aspect of the present invention, a chip power supply noise impact test device is provided. The chip power supply noise impact test device includes: a data acquisition module, configured to collect multi-dimensional data of a target chip power supply by using a preset multi-modal sensing array, obtain original multi-dimensional sensing data, and perform time synchronization calibration and signal preprocessing on the original multi-dimensional sensing data to obtain preprocessed multi-dimensional sensing data; a noise localization module, configured to perform time-frequency domain decomposition operation and correlation calculation on multi-layer sensing parameters of the preprocessed multi-dimensional sensing data to obtain a hierarchical feature vector set, and perform noise time delay and noise spatial position calculation on the hierarchical feature vector set to obtain a noise source spatio-temporal distribution map; a propagation analysis module, configured to perform target chip layout mapping and multi-physical field numerical calculation on the noise source spatio-temporal distribution map, generate a multi-physical field coupling propagation matrix of power supply noise, and perform noise eigenvalue decomposition and propagation path calculation on the multi-physical field coupling propagation matrix to obtain a noise propagation feature map of the power network; an impact evaluation module, configured to perform performance parameter testing on each chip function module in the target chip based on preset noise propagation test condition data and the noise propagation feature map, obtain a noise function response relationship between power supply noise and chip function performance, and based on the noise function response relationship, determine noise critical values and a power supply noise tolerance boundary surface corresponding to multiple chip function failures of the target chip, and generate a power supply impact test result of the target chip.

[0014] The above chip power supply noise impact test method and device. In an embodiment of the present invention, by collecting and preprocessing multi-modal sensing data of a target chip power supply, a multi-dimensional measurement data system of voltage, current, temperature, displacement, and electromagnetic field with spatio-temporal synchronization is constructed. Then, multi-level time-frequency domain decomposition and feature extraction are performed on these data to obtain a hierarchical feature vector set characterizing the characteristics of power supply noise. Next, the noise source position is determined through time delay analysis and spatial positioning technology, and combined with the chip layout, multi-physical field coupling analysis is performed to construct an electro-thermal-mechanical-magnetic propagation matrix, thereby analyzing the propagation mechanism of noise inside the chip. Finally, by designing a dedicated test condition to verify the impact degree of noise on each function module, the performance degradation threshold is measured, a noise tolerance boundary surface is formed, and a comprehensive power supply noise impact test result is output. Through multi-level sensing data processing and physical field coupling analysis, the accuracy problem of chip power supply noise localization and impact evaluation is solved. Especially in aspects such as high-frequency noise propagation, cross-domain noise coupling, and performance degradation prediction, the non-linear characteristics of the power network and multi-physical field interaction are fully considered, effectively improving the noise source localization accuracy; and a multi-dimensional feature decoupling and propagation path analysis strategy is adopted, which not only realizes accurate identification of noise types but also enhances the reliability of impact evaluation; in addition, through the construction of a noise-performance response relationship and the determination of critical thresholds, the functional safety margin is accurately evaluated, thus overall realizing the comprehensive and accurate evaluation of chip power supply noise impact.

[0015] Other features and advantages of the present invention will be set forth in the following description, and in part will be obvious from the description, or may be learned by practice of the present invention. The objectives and other advantages of the present invention are achieved and obtained by the structure particularly pointed out in the description, claims and drawings.

[0016] To make the above objectives, features and advantages of the present invention more obvious and understandable, the following provides preferred embodiments in conjunction with the accompanying drawings and describes them in detail as follows. Description of the Drawings

[0017] Figure 1 It is a schematic diagram of the first embodiment of the method for testing the influence of chip power supply noise in the embodiments of the present invention; Figure 2 It is a schematic diagram of an embodiment of the device for testing the influence of chip power supply noise in the embodiments of the present invention. Detailed Embodiments

[0018] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present invention.

[0019] The terms "including" and "having" and any variations thereof mentioned in the embodiments of the present invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but optionally further includes other unlisted steps or units, or optionally further includes other steps or units inherent to these processes, methods, products or devices.

[0020] For ease of understanding of this embodiment, the following describes the specific process of the embodiments of the present invention. Please refer to Figure 1 , the first embodiment of the method for testing the influence of chip power supply noise in the embodiments of the present invention includes: 101. Use a preset multimodal sensing array to collect multi-dimensional data of the target chip power supply, obtain the original multi-dimensional sensing data, and perform time synchronization calibration and signal preprocessing on the original multi-dimensional sensing data to obtain the preprocessed multi-dimensional sensing data; The embodiments of the present application can acquire and process relevant data based on artificial intelligence technology. Among them, Artificial Intelligence (AI) is a theory, method, technology, and application system that uses digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use knowledge to obtain the best results.

[0021] Artificial intelligence basic technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technology, operation / interaction systems, and mechatronics. Artificial intelligence software technologies mainly include several major directions such as computer vision technology, robotics, biometric technology, speech processing technology, natural language processing technology, and machine learning / deep learning.

[0022] In this embodiment, the original multi-dimensional sensing data includes original voltage waveform data, original current waveform data, original temperature distribution data, original displacement data, and original three-dimensional electromagnetic field intensity data; the original voltage waveform data is obtained by using a preset multi-modal sensing array to collect the voltage waveform data of multiple voltage test points in the target chip, and the original current waveform data is obtained by using the preset multi-modal sensing array to collect the dynamic current change data of each power domain in the target chip, and the original temperature distribution data is obtained by using the preset multi-modal sensing array to collect the temperature field distribution data on the surface of the target chip, and the original displacement data is obtained by using the preset multi-modal sensing array to collect the micro-mechanical displacement data of the target chip, and the original three-dimensional electromagnetic field intensity data is obtained by using the preset multi-modal sensing array to collect the electromagnetic field distribution data in the space above the target chip; the contact impedance between the test point probe and the chip is calculated for the original voltage waveform data and the original current waveform data to obtain the contact impedance change value, and based on the contact impedance change value, the amplitude of the original voltage waveform data is compensated to obtain the compensated voltage waveform data; based on the probe transfer function corresponding to the multi-modal sensing array, time-frequency transformation and frequency response compensation are performed on the original current waveform data to obtain the compensated current waveform data, and spatial pixel resampling and temperature value correction calculation for the chip surface area are performed on the original temperature distribution data to obtain the calibrated temperature field data, and PCB inherent resonance filtering and mechanical decoupling calculation are performed on the original displacement data to obtain the calibrated displacement data, and spatial deconvolution calculation is performed on the original three-dimensional electromagnetic field intensity data to obtain the high-resolution electromagnetic field distribution data; time synchronization calibration of multiple sensors is performed on the compensated voltage waveform data, the compensated current waveform data, the calibrated temperature field data, the calibrated displacement data, and the high-resolution electromagnetic field distribution data to obtain the time calibration noise data, and multi-dimensional anomaly data detection and spatio-temporal interpolation of anomaly points are performed on the time calibration noise data to obtain the preprocessed multi-dimensional sensing data; the multi-modal sensing array here refers to a measurement system integrating multiple different types of sensors, which is specifically used for the comprehensive measurement of chip power supply noise, and the system includes but is not limited to five main sensor components: high-precision differential voltage probe array, high-bandwidth current probe, infrared thermal imaging array, piezoelectric displacement sensor, and near-field electromagnetic scanning probe, etc.

[0023] In practical applications, first, a preset multi-modal sensing array is used to collect multi-dimensional data of the target chip. That is, a high-precision differential probe array is first deployed at key nodes of the chip power network, including positions such as VDD / VSS pins, decoupling capacitor connection points, and load ends. Voltage waveform data of multiple test points are synchronously collected through these probes, with a sampling rate of up to 10 GS / s and a dynamic range of up to 90 dB, so as to obtain the original voltage waveform data; and current probes with high-bandwidth characteristics are installed on the chip power path. These probes can accurately capture the dynamic current changes in each power domain from the microampere level to the ampere level, record the complete current waveform including burst loads, switching transients, and steady-state currents, and form the original current waveform data; and an infrared thermal imaging array with a resolution of 32×32 pixels and a temperature sensitivity of 0.1 °C is used to perform real-time thermal distribution scanning on the chip surface, with a scanning frequency not lower than 100 Hz to ensure that transient temperature changes caused by power noise can be captured, thereby generating the original temperature distribution data; and piezoelectric sensors with a sensitivity of 1 μm / V are installed on the chip package surface and PCB fixed points. These sensors can detect the minute mechanical displacements caused by noise, especially high-frequency vibration modes and package resonances, and convert this displacement information into electrical signals to form the original displacement data; and a near-field scanning probe controlled by a three-axis stepper motor performs three-dimensional XYZ scanning in the space above the chip according to a preset grid to collect the electromagnetic field intensity distribution in the DC-6 GHz frequency range, with a spatial resolution of up to 0.5 mm, so as to obtain the original three-dimensional electromagnetic field intensity data. The data collected by these multi-modal sensors are time-stamped through a high-precision clock distribution network, with a time-stamp accuracy better than 100 ps. At the same time, an accurate mapping relationship between the measurement coordinates and the chip physical layout is established. Finally, the original voltage waveform data, original current waveform data, original temperature distribution data, original displacement data, and original three-dimensional electromagnetic field intensity data are integrated into the original multi-dimensional sensing data with complete spatio-temporal information. For example, when a certain processor chip operates at a clock frequency of 2 GHz, its power noise may generate a ripple with a peak of about 100 mV at the VDD pin, a current change rate of up to 1 A / ns, a local hot spot temperature increase of 10 °C, a package vibration of about 2 μm, and the near-field electromagnetic field intensity measured 3 mm above the chip can reach 0.1 V / m. These multi-dimensional data are time-stamped through a unified time synchronization system (with an accuracy better than 100 ps) and a physical space coordinate mapping relationship is established to form a complete original multi-dimensional sensing data matrix.

[0024] Secondly, perform a test point contact quality assessment on the acquired original voltage waveform data and original current waveform data. By real-time monitoring the impedance change at the contact interface between the probe and the chip, calculate the contact impedance change value that fluctuates with time, which is obtained by applying a small known test signal to the probe and then, based on the deviation between the measured voltage response and the theoretical response, inversely derived in combination with Ohm's law to detect impedance fluctuations as small as 0.1 mΩ. Furthermore, once the contact impedance change value is obtained, immediately apply an adaptive impedance compensation algorithm to the original voltage waveform data. By calculating the voltage amplitude attenuation caused by the impedance change and according to the formula V 补偿 =V 原始×(1 + ΔZ / Z0) (where ΔZ represents the change in contact impedance and Z0 represents the standard contact impedance or the initial contact impedance value) to correct the original voltage value, thereby obtaining compensated voltage waveform data that eliminates the influence of poor contact. The compensation accuracy can reach ±0.5 dB, ensuring accurate measurement results even in weak noise (as low as 10 mV); and for the original current waveform data, the time-domain current data is converted to the frequency domain by performing a Fourier transform in the frequency domain, and then the inverse operation of the transfer function is applied. Since the frequency response distortion of the current probe in high-frequency noise analysis will seriously affect the data accuracy, mathematical frequency response compensation can effectively restore the high-frequency components limited by the probe to compensate for the attenuation of high-frequency components and phase lag caused by the bandwidth limitation of the probe. Then, the compensated frequency-domain data is converted back to the time domain through an inverse Fourier transform to obtain compensated current waveform data, increasing the effective bandwidth of the current data from the original dozens of MHz to hundreds of MHz, ensuring the accurate capture of switch transient currents; furthermore, for the original temperature distribution data, due to the spatial resolution limitation of the infrared thermal imager, spatial pixel resampling is first performed through a bicubic interpolation algorithm to interpolate and improve the temperature data of the original 32×32 pixels to a higher resolution. At the same time, combined with the emissivity parameters of various surface materials stored in the chip material database, the temperature values of different regions are calculated and corrected. Because different materials (such as silicon, metal interconnects, polymer packages) have different infrared emission characteristics, this difference will result in different infrared signal intensities at the same temperature. Through temperature value correction calculation, the measurement error caused by the difference in material emissivity is eliminated, and calibrated temperature field data is obtained, with the temperature measurement accuracy improved to ±0.3 °C; and applying a digital notch filter to the original displacement data to filter out the PCB's inherent resonance frequency components (where these inherent resonances are usually determined by the physical dimensions and support methods of the PCB board and are independent of noise). Then, by establishing a mechanical coupling model of the chip - package - PCB and performing mechanical decoupling calculations, the total displacement is separated into the background displacement caused by external environmental vibrations and the effective displacement caused by chip noise. Only the latter is retained to obtain calibrated displacement data, enabling the detection of minute displacements caused by noise with a sensitivity reaching the sub - micron level; and applying a spatial deconvolution algorithm to the original three - dimensional electromagnetic field intensity data, establishing a spatial convolution kernel model based on the physical dimensions and electromagnetic characteristics of the scanning probe, and then through iterative deconvolution operations, eliminating the spatial resolution blurring effect caused by the probe size and restoring a more refined electromagnetic field distribution. Thus, the high - resolution electromagnetic field distribution data obtained can clearly display electromagnetic field changes at the sub - millimeter level; furthermore, perform time synchronization calibration for multi - sensors on the compensated voltage waveform data, compensated current waveform data, calibrated temperature field data, calibrated displacement data, and high - resolution electromagnetic field distribution data. By unifying the clock source and timestamp matching, establish the time correspondence relationship between the measurement data of different physical quantities, ensure that all data are completely aligned in the time dimension, and control the time error within 1 ns to obtain time - calibrated noise data; and perform a multi - dimensional anomaly detection algorithm on these time - calibrated noise data. By calculating the multi - variable Mahalanobis distance and local density estimation, identify the outliers that deviate significantly from the surrounding data points. These outliers may be caused by probe jitter, power outages, or external interference. Thus, determine whether to mark them as real noise events or measurement anomalies based on the nature of the outliers. For the data points confirmed as measurement anomalies, apply a spatio - temporal interpolation method to repair data missingness. By considering the information of time and space neighboring points, generate reasonable replacement values, and finally obtain continuous, consistent, and high - fidelity pre - processed multi - dimensional sensing data.

[0025] 102. Perform time - frequency domain decomposition operations and correlation calculations on the multi - layer sensing parameters of the pre - processed multi - dimensional sensing data to obtain a hierarchical feature vector set, and calculate the noise time delay and noise spatial position for the hierarchical feature vector set to obtain a spatio - temporal distribution map of the noise source; In this embodiment, based on the power supply voltage noise characteristics corresponding to the voltage data in the preprocessed multi-dimensional sensing data, the voltage data in the preprocessed multi-dimensional sensing data is subjected to segmented windowing calculation to obtain a voltage segmented window data set, and preset micro-time domain characteristic parameters are calculated for each window data segment in the voltage segmented window data set to obtain a voltage micro-time domain characteristic vector; the spatial gradient calculation of the surface hot spot area and the heat conduction time series calculation are performed on the temperature field data in the preprocessed multi-dimensional sensing data to obtain a temperature field characteristic vector, and the modal decomposition and harmonic resonance feature extraction are performed on the displacement data in the preprocessed multi-dimensional sensing data to obtain a mechanical displacement characteristic vector, and the spatial harmonic decomposition and field strength distribution calculation are performed on the electromagnetic field distribution data in the preprocessed multi-dimensional sensing data to obtain an electromagnetic field characteristic vector, and the decomposition calculation of the power supply network impedance spectrum is performed on the voltage data and current data in the preprocessed multi-dimensional sensing data to obtain a power supply network impedance characteristic vector; the voltage micro-time domain characteristic vector, the temperature field characteristic vector, the mechanical displacement characteristic vector, the electromagnetic field characteristic vector, and the power supply network impedance characteristic vector are subjected to feature dimension alignment and feature space position matching to obtain a multi-physical quantity correlation data set, and multi-modal feature fusion and principal component dimensionality reduction calculation are performed on the multi-physical quantity correlation data set to obtain a hierarchical feature vector set; the hierarchical feature vectors are classified according to the noise feature types to obtain a power supply noise type classification result, and based on a preset power supply noise template library, similarity matching calculation is performed on various power supply noise characteristics in the power supply noise type classification result to obtain a power supply noise feature recognition result; based on the voltage waveform data in the preprocessed multi-dimensional sensing data, the time difference of the wavefront arrival is calculated for the power supply noise feature recognition result to obtain noise propagation time data, and the triangular positioning calculation of the power supply network time delay difference is performed on the noise propagation time data and the power supply noise feature recognition result to obtain preliminary noise source position data; the maximum intensity point and propagation direction of the power supply noise radiation are calculated for the electromagnetic field distribution data and the preliminary noise source position data in the preprocessed multi-dimensional sensing data to obtain accurate noise source position data, and based on the power supply noise feature recognition result, chip space mapping and noise confidence evaluation are performed on the accurate noise source position data to obtain a noise source spatio-temporal distribution map.

[0026] In practical applications, firstly, based on the power supply voltage noise characteristics corresponding to the voltage data in the preprocessed multi-dimensional sensor data, an intelligent segmented windowing strategy is used to process the voltage data, that is, the window length is adaptively adjusted according to the time characteristics of the noise. For high-frequency transient noise, a short window of 100ns-1μs is used, while for low-frequency drift noise, a long window of 1μs-10μs is used. At the same time, an appropriate window function is dynamically selected according to the signal characteristics. For example, a Hanning window is used for periodic noise to reduce spectrum leakage, and a Kaiser window is used for transient noise to retain the integrity of the time domain characteristics. The overlap rate of adjacent windows is maintained at 75% to ensure that the transient characteristics are not overwhelmed by the window boundary effect. In this way, the power supply voltage noise is obtained. The voltage segmented window data set is used to perform fine calculation of the microscopic time domain characteristic parameters for each window data segment in the voltage segmented window data set. The microscopic time domain characteristic parameters include the rise time (the time interval from 10% to 90% amplitude), fall time, peak moment, duration, overshoot ratio (the ratio of overshoot amplitude to steady-state value), ringing attenuation coefficient (exponential decay rate of ringing envelope) and ringing frequency (the main resonant frequency of ringing waveform) of the noise pulse. These parameters fully characterize the microscopic behavioral characteristics of power supply noise in the time domain, and are especially valuable for distinguishing switching noise from ground bounce noise. Therefore, by performing statistical analysis and feature vector quantization on these parameters, the voltage microscopic time domain feature vector is finally generated; and the temperature The temperature field data uses a two-dimensional Gaussian gradient operator to calculate the temperature gradient distribution on the chip surface, identify hot spots with drastic temperature changes, which are usually related to high-power circuits or noise sources, and then solve the heat conduction equation to analyze the time series characteristics of temperature changes, including the hot spot formation speed, thermal diffusion coefficient and cooling time constant (these parameters reflect how the power consumption changes caused by noise affect the thermal behavior of the chip), so as to organize these temperature field spatiotemporal characteristics into structured temperature field feature vectors; and for displacement data, the empirical mode decomposition algorithm is used for modal decomposition, decomposing the complex displacement signal into a series of physically meaningful intrinsic mode functions (these modes each represent a vibration mode), and then extracting the resonant frequency of each mode. frequency, amplitude, phase and quality factor (these characteristic parameters reflect the characteristics of power supply noise that stimulates chips and packages to generate mechanical vibrations through electromagnetic force or thermal stress), all of which are organized into mechanical displacement characteristic vectors; and applying three-dimensional Fourier transform to electromagnetic field distribution data for spatial harmonic decomposition, converting the spatial electromagnetic field distribution into spatial frequency domain representation (to reveal the spatial periodic structure of the electromagnetic field), and then calculating the energy distribution and phase relationship of each spatial frequency component, and at the same time calculating the spatial distribution characteristics of the electric field and magnetic field in real space, including field intensity gradient, divergence, curl and energy density (these electromagnetic field characteristics reflect the radiation mode and propagation characteristics of noise), so as to organize these electromagnetic field spatiotemporal characteristics into electromagnetic field characteristic vectors;For voltage data and current data, by calculating the frequency-dependent transient impedance spectrum Z(jω,t) = V(jω,t) / I(jω,t), the dynamic impedance characteristics of the power supply network at different frequencies and time points are obtained. Then, the impedance spectrum is decomposed into the magnitude spectrum |Z(jω,t)| and the phase spectrum arg[Z(jω,t)]. The resonance peaks, damping characteristics, and frequency responses of the impedance spectrum are further extracted (these features reveal the response and filtering characteristics of the power supply network to different frequency noises), and thus these impedance features are organized into a power supply network impedance feature vector. Furthermore, feature dimension alignment and spatial position matching are performed on the voltage microscopic time-domain feature vector, temperature field feature vector, mechanical displacement feature vector, electromagnetic field feature vector, and power supply network impedance feature vector, that is, dimensional normalization is performed on all feature vectors to ensure the comparability of features of different physical quantities. Then, a chip physical coordinate system is established, and the spatial distribution characteristics of each physical quantity are mapped into a unified coordinate system, so that the correlation of different physical quantities at the same spatial position (for example, identifying the spatial coincidence relationship between the voltage noise peak and the temperature hot spot) is obtained. Through this spatio-temporal alignment process, a multi-physical quantity correlation dataset is generated. Furthermore, a multi-modal feature fusion algorithm is applied to the multi-physical quantity correlation dataset, and the tensor decomposition method is adopted:; ; where T is the original multi-modal feature tensor, G is the core tensor, is the factor matrix of the nth mode, is the total number of modes. By this decomposition, the common patterns and interrelationships between modes are extracted. Finally, principal component analysis is applied for dimensionality reduction, and the feature components with a cumulative contribution rate exceeding 98% are retained. Ultimately, a hierarchical feature vector set containing the comprehensive multi-physical field characterization of power supply noise is generated. This feature set not only retains the key features of each physical quantity but also establishes the correlation relationships between different physical quantities.

[0027] Secondly, an analysis strategy combining supervised learning and unsupervised learning is adopted to classify the noise feature types of the hierarchical feature vectors. That is, first, an algorithm based on spectral clustering is applied to the feature space to automatically group the feature vectors according to similarity, and prior knowledge is combined to label and verify the clustering results. Then, an ensemble classification model is constructed based on multiple classifiers such as SVM (Support Vector Machine) and random forest. Considering the discriminative ability of each feature dimension comprehensively, the noise is accurately classified and divided into different types such as switching noise (with high-frequency spikes and fast ringing characteristics), LC resonance noise (with fixed-frequency oscillation characteristics), ground bounce noise (with high-low frequency coupling characteristics), crosstalk noise (with time delay and waveform similarity), etc. Finally, the power supply noise type classification result is generated; and similarity matching calculations are performed on the characteristics of various power supply noises based on a preset power supply noise template library. This template library stores standard feature templates of various typical noises (including noise waveforms and feature vectors under different process nodes, different circuit structures, and different working conditions). By using the multi-dimensional dynamic time warping algorithm (DTW) to calculate the similarity between the feature vector and the template, the similarity calculation expression is: ; where X is the feature vector to be matched, Y is the template feature vector, is the distance metric between feature points, is the weight coefficient, π(i) is the optimal path mapping function, and min is to find the optimal alignment path that minimizes the distance (for example, when analyzing a voltage waveform that rapidly rises from 10 mV to 85 mV and then oscillates and decays, the DTW distance from the LC oscillation template may be 0.13, while the DTW distance from the switching noise template may be only 0.05, indicating that this noise is more in line with the characteristics of switching noise, so it is identified as switching noise and its detailed parameters are recorded). At the same time, considering multiple factors such as frequency characteristics, amplitude characteristics, and time-domain morphology, the most matching noise type and electrical characteristics are determined through comprehensive scoring, including the frequency composition, energy distribution, impedance characteristics, and propagation characteristics of the noise, so as to calculate and form the power supply noise feature recognition result; furthermore, based on the voltage waveform data in the preprocessed multi-dimensional sensing data, the time difference of arrival of the wavefront of the power supply noise feature recognition result is calculated, that is, using the voltage waveform data synchronously collected at multiple measurement points arranged in the chip power supply network, through methods such as cross-correlation analysis or threshold-triggered detection, the time difference of the noise waveform arriving at different measurement points is accurately calculated. For high-frequency noise, wavelet transform is used to enhance the characteristics of the noise front and improve the time difference detection accuracy, while for low-frequency noise, envelope analysis method is used to extract the starting point of the noise. At the same time, considering the non-uniformity of the signal propagation speed in the power supply network, a propagation speed model is established according to the impedance distribution and structural characteristics of the power supply plane. Through these processes, noise propagation time data is generated, and then the triangulation calculation of the time delay difference of the power supply network is performed on the noise propagation time data and the power supply noise feature recognition result (similar to the GPS positioning principle, but the particularity of the power distribution network needs to be considered, including factors such as impedance non-uniformity, propagation path diversity, and boundary reflection effects). By using the weighted least squares method to solve the non-linear equations, the most likely noise source coordinates are determined, and at the same time, the uncertainty of the positioning result is evaluated through Monte Carlo simulation to generate the preliminary position data of the noise source, and the positioning accuracy can usually reach ±0.5 mm; furthermore, the maximum intensity point and propagation direction of the power supply noise radiation are calculated for the electromagnetic field distribution data and the preliminary position data of the noise source in the preprocessed multi-dimensional sensing data, that is, using the three-dimensional electromagnetic field distribution data obtained by near-field scanning, first calculate the electromagnetic field energy density distribution, find the spatial position with the maximum field strength, and then calculate the Poynting vector by analyzing the phase relationship between the electric field and the magnetic field to determine the direction of electromagnetic energy flow. Then, apply the electromagnetic inverse tracking algorithm to trace the propagation path of the electromagnetic wave downward from the measurement plane to determine the radiation source position, which is particularly suitable for detecting high-frequency switching noise and interference sources with strong radiation. By cross-verifying with the preliminary position data, possible positioning ambiguities are eliminated, and the noise source position is further accurately determined to generate the accurate position data of the noise source, and the positioning accuracy can be improved to ±0.3 mm; furthermore, based on the power supply noise feature recognition results, perform chip space mapping and noise confidence evaluation for each noise source on the precise position data of the noise source. Chip space mapping is to convert the position of the noise source in the physical coordinate system into the chip design coordinate system, accurately corresponding to the chip layout, determining the specific circuit components or regions corresponding to the noise source. At the same time, calculate the confidence score for each noise source, comprehensively considering factors such as the convergence of the positioning algorithm, the consistency of multi-method cross-validation, the degree of compliance with the expected noise mechanism, and the signal-to-noise ratio, etc., assign a credibility coefficient and a relative intensity value to each noise source, and integrate all noise sources and their attribute information into a visualized spatio-temporal distribution map of the noise source. This distribution map not only shows the spatial position of the noise source, but also represents the noise type through color coding, the relative intensity through brightness, the confidence through the symbol size, and marks the time information to indicate the timing relationship of the noise, achieving high-precision positioning of different types of power supply noise sources.

[0028] 103. Perform target chip layout mapping and multi-physics field numerical calculation on the spatio-temporal distribution map of the noise source, generate a multi-physics field coupling propagation matrix of the power supply noise, and perform noise eigenvalue decomposition and propagation path calculation on the multi-physics field coupling propagation matrix to obtain the noise propagation feature map of the power network; In this embodiment, based on the chip design layout corresponding to the target chip, coordinate mapping calculations are performed between each noise source and the chip component area on the spatio-temporal distribution map of the noise sources to obtain a correspondence table between the noise sources and the components. Then, using the correspondence table between the noise sources and the components and the power noise feature recognition results, an electric field distribution model of the power supply of the target chip is constructed to obtain an electric field distribution function. Joule heat calculations inside the chip are performed on the electric field distribution function and the current data in the preprocessed multi-dimensional sensing data to obtain a temperature field distribution function. Thermal stress calculations are carried out on the temperature field distribution function and the preset chip material parameters to obtain a chip stress field function and a chip strain field function. Deformation parameter conversion calculations are performed on the strain field function and the preset power supply electrical network parameters to obtain an electrical parameter change function. Multi-physical field coupling matrix operations are carried out on the electric field distribution function, the temperature field distribution function, the stress field function, the strain field function, and the electrical parameter change function to obtain a multi-physical field coupling propagation matrix. Decomposition operations on the noise transfer intensity and propagation eigenvectors are performed on the multi-physical field coupling propagation matrix to obtain a set of noise propagation eigenvectors. Based on the set of noise propagation eigenvectors, a power supply noise propagation network diagram of the target chip is constructed. Power supply noise energy transmission path calculations are performed on the power supply noise propagation network diagram to obtain a set of power supply noise propagation paths. Power network impedance transmission feature calculations are carried out on the noise transfer coefficients in the set of power supply noise propagation paths and the set of noise propagation eigenvectors to obtain a set of power supply noise path transfer functions. Convolution operations on the power supply interference waveform propagation are performed on the set of power supply noise path transfer functions and the power noise feature recognition results to obtain an endpoint noise prediction result. Mapping integration of the power supply noise propagation relationships is carried out on the power supply noise propagation network diagram, the set of noise propagation paths, the set of path transfer functions, and the endpoint noise prediction result to obtain a noise propagation feature map of the power supply network. The above-mentioned chip material parameters mainly refer to material physical quantities related to the physical properties of the chip (including: thermophysical parameters, elastomechanics parameters, thermodynamics parameters, density, and temperature coefficients, etc.); the above-mentioned power supply electrical network parameters refer to the electrical characteristic parameters of the chip power supply distribution network (including distributed resistance parameters, distributed capacitance parameters, distributed inductance parameters, impedance characteristics, and network topology parameters, etc.).

[0029] In practical applications, first, based on the chip design layout corresponding to the target chip (referring to the complete design layout data of the chip, which contains all the physical structure information of the chip), coordinate mapping calculations are performed between each noise source and the chip component area in the spatio-temporal distribution map of the noise sources. That is, a coordinate transformation matrix is established by identifying feature points (such as chip corners, fiducial marks, or specific pins), and then the positions of the noise sources determined in the physical measurement space are transformed into the chip design coordinate system and accurately mapped to specific circuit structures (for example, associating the noise sources with specific clock buffers, power switches, high-speed I / O units, or power wiring bottlenecks, etc. This mapping not only includes planar position correspondence but also considers the three-dimensional structure information of the chip, such as the vertical positioning of metal interconnect layers, active regions, and substrate layers). Through this accurate mapping, a detailed noise source-component correspondence table is generated (which records the coordinates, types, intensities of each noise source, and the complete information of its corresponding circuit component or area). Furthermore, using the noise source-component correspondence table and the results of power noise feature recognition, an electric field distribution model of the target chip's power supply is constructed. This model adopts a hybrid modeling method combining circuit theory and electromagnetic field theory, considering the actual topological structure, conductor size, material properties, and load distribution of the chip power supply network. During the modeling process, each noise source is regarded as an excitation source, and corresponding source terms are set according to its characteristics (frequency, amplitude, waveform). Then, by solving Maxwell's equations (including Gauss's law, Faraday's law of induction, etc.), the distribution and propagation of the electric field in the power supply network are calculated. This calculation is performed numerically using the finite element method or the finite-difference time-domain method, considering boundary conditions and material parameters, to generate an electric field distribution function E(x, y, z, t) that characterizes the spatial distribution and temporal evolution of the electric field. Furthermore, Joule heat calculations are performed inside the chip for the electric field distribution function and the current data in the preprocessed multi-dimensional sensing data. According to Ohm's law and Joule's law, the heat power density generated by current passing through a conductor with resistance is P = J²×ρ (J is the current density, ρ is the resistivity). The current density distribution J(x, y, z, t) is calculated using the electric field distribution and the impedance characteristics of the power supply network, and then the heat source distribution Q(x, y, z, t) is calculated in combination with the resistivity characteristics of the material (note that the resistivity usually changes with temperature, and the temperature coefficient needs to be considered). These heat sources are substituted into the heat conduction equation T / t=α ²T+Q / ρCp (where α is the thermal diffusivity, ρ is the density, and Cp is the specific heat capacity). By numerically solving, the spatio-temporal distribution of the temperature field is obtained, and the heat conduction mechanism, heat dissipation path, and boundary conditions inside the chip are considered during the calculation process. Finally, a temperature field distribution function T(x, y, z, t) is generated, which comprehensively describes the dynamic distribution of the temperature field caused by noise. Furthermore, thermal stress calculations are performed for the temperature field distribution function and the preset chip material parameters (including the coefficient of thermal expansion, Young's modulus, Poisson's ratio, etc.). The strain caused by thermal expansion is ε thermal=α×ΔT, where α is the thermal expansion coefficient of the material, and considering the thermal expansion differences of different material layers in the chip (such as silicon, oxide, metal layers, etc.), the differential thermal expansion caused by the temperature gradient is calculated. Then, by solving the equations of elasticity, the stress distribution caused by the temperature change is determined, and the elastic properties of the material, the interlayer constraint conditions, and the boundary conditions are considered in the calculation process. Finally, the chip stress field function σ(x, y, z, t) and the chip strain field function ε(x, y, z, t) are generated to describe the situation where noise affects the mechanical state of the chip through thermo-mechanical coupling; furthermore, the deformation parameter conversion calculation is performed on the strain field function and the preset power electrical network parameters, that is, by establishing the correlation relationship between mechanical deformation and electrical characteristics (for example: conductor deformation will cause resistance change: ΔR / R≈(1 + 2ν)ε thermal +ρ' / ρ (where ν is the Poisson's ratio and ρ' / ρ is the sensitivity of resistivity to strain). Similarly, the capacitance is also affected by the change in the electrode spacing: ΔC / C≈-εnormal (the strain component perpendicular to the electrode), and the inductance is also affected by the change in the geometry), so through these physical relationships, the changes in electrical parameters such as resistance, capacitance, and inductance caused by the strain field are calculated to form the electrical parameter change functions ΔR(x, y, z, t), ΔC(x, y, z, t), ΔL(x, y, z, t) (to describe the feedback effect of noise on the electrical characteristics of the power network through thermo-mechanical-electrical coupling). Furthermore, the multi-physical field coupling matrix operation is performed on the electric field distribution function, the temperature field distribution function, the stress field function, the strain field function, and the electrical parameter change function, so as to integrate the interactions between the physical fields into a unified mathematical description, construct the coupled matrix equations, describe how the electric field change causes the temperature change, how the temperature change leads to stress and strain, and how the stress and strain in turn affect the electrical parameters and ultimately affect the electric field distribution, forming a complete closed-loop coupling relationship. This coupling matrix contains the transfer coefficients, time lags, and spatial attenuation characteristics between the field quantities, is a high-dimensional tensor, and comprehensively characterizes the propagation and amplification mechanism of power supply noise in multi-physical fields, and finally generates the multi-physical field coupling propagation matrix.

[0030] Secondly, the eigenvalue decomposition technology is used to perform the decomposition operation of the noise transfer intensity and the propagation eigenvector on the multi-physical field coupling propagation matrix, that is, calculate the eigenvalues of the matrix , , ..., and the corresponding eigenvectors , ,..., , each eigenvalue represents the gain or attenuation coefficient of a noise propagation mode, while the corresponding eigenvector represents the relative response intensity of each physical quantity and spatial position in that mode. The Arnoldi iteration algorithm is used to efficiently process large-scale sparse matrices during the calculation process, so as to sort all modes according to the magnitude of the eigenvalues, and retain the top k eigenvalues and eigenvectors with the largest contributions. These dominant modes usually account for more than 95% of the total response energy. Through this mathematical dimensionality reduction, the essential characteristics of noise propagation are extracted to form a noise propagation eigenvector set. Then, based on the noise propagation eigenvector set and combined with the previously obtained correspondence table between noise sources and components, a power noise propagation network graph of the target chip is constructed using the graph theory representation method (this network graph intuitively shows the possible propagation paths and relative intensities of noise from the source to each impact point), that is, the noise source, key power nodes, and sensitive functional modules are represented as nodes, the propagation paths are represented as edges, and the weight of the edge is determined by the corresponding transfer coefficient in the eigenvector. The graph not only contains the electrical connection topology but also integrates the heat conduction path and mechanical coupling relationship to form a complex network structure of multi-physical domain coupling; furthermore, the power noise energy transmission path of the power noise propagation network graph is calculated, that is, the improved Dijkstra algorithm is used, considering the energy transfer efficiency rather than simply the topological distance, and the path gain function G(p)= we(f) represents the transfer gain along path p, where we(f) is the complex transfer coefficient of each edge on the path at the characteristic frequency f, so as to identify the main propagation paths from each noise source to each functional module, and to identify the maximum interference propagation paths from each noise source to each functional module (these paths are not necessarily the shortest in physical distance, but the channels with the strongest noise energy transfer. For example, they may achieve efficient long-distance propagation through the coupling between power domains or shared decoupling capacitors. Summarize all the key propagation paths to form a power supply noise propagation path set); then, use the transmission line theory and network analysis method to calculate the power network impedance transmission characteristics of the noise transfer coefficients in the power supply noise propagation path set and the noise propagation eigenvector set, that is, calculate the frequency-dependent transfer function H(f) of each key path (this function describes how the noise propagating along the path attenuates or amplifies with frequency changes). By considering the distributed impedance characteristics, resonance points, and bandwidth limitations of the power network, calculate the complete transfer characteristics including the amplitude-frequency response |H(f)| and the phase-frequency response arg[H(f)], and pay special attention to the amplification effect at the common LC resonance frequency of the power distribution network and the attenuation characteristics in the high-frequency band. Through these calculations, generate a set of power supply noise path transfer functions characterizing the transmission characteristics of each key path; then perform a convolution operation on the power supply noise path transfer function set and the power supply noise characteristic identification results for the propagation of the power supply interference waveform, that is, combine the characteristics of the noise source with the response of the propagation path to predict the actual waveform and spectrum after the noise reaches each functional module. For time-domain analysis, perform the convolution operation y(t)=∫x(τ)h(t-τ)dτ, where x(τ) is the noise source waveform, h(t-τ) is the path impulse response (the time-domain representation of the transfer function), y(t) is the received waveform, τ is the integration variable representing time, and t is the current time point under consideration; for frequency-domain analysis, perform the product operation Y(f)=X(f)·H(f), where X(f) is the noise source spectrum, H(f) is the path transfer function, and Y(f) is the received spectrum. Perform calculations for each combination of each key noise source and each sensitive functional module to predict the time-domain waveform, spectrum distribution, peak amplitude, and effective value at each functional module after the noise propagates, forming the endpoint noise prediction results; then use multi-level visualization technology to map and integrate the power supply noise propagation network diagram, the noise propagation path set, the path transfer function set, and the endpoint noise prediction results for the power supply noise propagation relationship. The top layer shows the overall network topology and key hotspots, the middle layer shows the main propagation paths and transfer characteristics, and the bottom layer provides detailed waveform and spectrum analysis. At the same time, perform semantic annotation on the integrated data to associate the mathematical model with the actual circuit structure, and construct a complete power network hierarchical structure including the noise source location, propagation path, impedance characteristics, and influence amplitude (such as associating the resonance frequency with the corresponding LC network parameters, and associating the propagation bottleneck with the actual power grid structure), and finally generate a noise propagation characteristic map of the power network.

[0031] 104. Based on the preset noise propagation test condition data and the noise propagation characteristic map, perform performance parameter tests on each chip functional module in the target chip to obtain the noise functional response relationship between the power supply noise and the chip functional performance. And based on the noise functional response relationship, determine the noise critical values and the power supply noise tolerance boundary surface corresponding to various chip functional failures of the target chip, and generate the power supply impact test result of the target chip.

[0032] In this embodiment, based on the preset noise propagation test condition data, perform test condition calculations for multiple frequency bands on the noise propagation characteristic map to obtain the power supply noise test condition matrix. And based on the power supply noise test condition matrix, determine the power supply noise injection test data set corresponding to the power supply terminal test of the target chip; based on the power supply noise injection test data set, perform performance parameter tests with multiple controlled noise signal injections on each chip functional module in the target chip to obtain the functional module performance parameter response data set, and perform threshold detection calculations for multiple functional modules on the functional module performance parameter response data set to obtain the functional module noise threshold data set; perform correlation regression calculations on the power supply noise and functional degradation mapping for the functional module noise threshold data set and the power supply noise injection test data set to obtain the noise functional response relationship between the power supply noise and the chip functional performance, and perform critical condition boundary calculations for functional module failures on the noise functional response relationship to obtain the power supply noise tolerance boundary surface; perform power supply noise sensitivity classification and integration on the power supply noise tolerance boundary surface, the noise source spatio-temporal distribution map, and the noise propagation characteristic map to obtain the power supply noise impact test result of the target chip. Here, the noise propagation test condition data refers to a series of test conditions and parameter combinations (such as noise signal parameters in different frequency bands, noises of different waveform types, noises of different amplitude sizes, different load conditions, noise duration, and repetition patterns, etc.) preset for testing the sensitivity of the chip to the power supply noise.

[0033] In practical applications, based on the key frequency points and sensitive propagation paths identified in the noise propagation characteristic spectrum, and the targeted test conditions designed in the preset noise propagation test condition data, analyze the main propagation modes in the noise propagation characteristic spectrum, extract the resonant frequency points, high-gain frequency bands, and sensitive load conditions, and based on the pre-designed typical working conditions including low-frequency large current jumps (0.1 - 10 MHz, current change rate 0.1 - 1 A / μs), medium-frequency power supply oscillations (10 - 100 MHz, ±30% rated current), and high-frequency switching noise (>100 MHz, ±10% rated current), as well as the composite modes of these basic working conditions, these test working conditions cover various power supply noise situations that the chip may encounter in practical applications. Arrange these test conditions according to frequency, amplitude, and load characteristics to form a structured power supply noise test condition matrix; then, based on the power supply noise test condition matrix, determine the power supply noise injection test data set for the corresponding power supply terminal test of the target chip, that is, convert the test working conditions into actual executable test signals and configuration parameters, and achieve precise noise waveform synthesis through a programmable power supply and load controller, including noise signals with different frequencies, amplitudes, phases, and durations, as well as test parameters under different load conditions. These signals and parameters form the power supply noise injection test data set; then, based on the power supply noise injection test data set, conduct performance parameter tests on various chip functional modules in the target chip by injecting controlled noise signals, that is, by applying controlled noise signals to the chip's power supply terminal and simultaneously monitoring the performance parameters of each chip functional module. The tests cover the key functional units of the chip, including digital logic circuits (monitoring timing margin and flip error rate), memory units (monitoring read / write stability and hold time), clock distribution networks (monitoring jitter and phase noise), analog / digital conversion circuits (monitoring effective number of bits and signal-to-noise ratio), etc. While applying different noise conditions, monitor and record these performance parameters in real time. The test program starts with small-amplitude noise and gradually increases until performance degradation or functional failure is observed, while recording the change trends of various performance parameters, and finally generates a functional module performance parameter response data set (this data set contains the complete correspondence between noise conditions and performance parameters); then, perform threshold detection calculations for multiple functional modules on the functional module performance parameter response data set. By analyzing the change curves of performance parameters, determine two key threshold points: the initial degradation point (the noise level at which the performance parameter starts to deviate significantly from the reference value, usually defined as a 5% - 10% performance drop) and the critical failure point (the noise level at which the function completely fails or the performance drops to an unacceptable level, usually defined as a 30% - 50% performance drop or the functional error rate exceeds the allowable range). By marking and recording these threshold points for each functional module under various noise frequencies and load conditions, form a functional module noise threshold data set;Furthermore, the multiple statistical regression method is adopted to conduct the correlation regression calculation of the power supply noise and function degradation mapping for the functional module noise threshold data set and the power supply noise injection test data set. That is, by establishing a quantitative mathematical relationship between the noise parameter vector (including noise frequency f, amplitude A, duration τ, and load condition L) and the performance degradation degree ΔP of each functional module, this relationship can be expressed as ΔP = F(f, A, τ, L). And through techniques such as piecewise linear regression or support vector regression, this non-linear mapping relationship is fitted, and at the same time, the sensitivity coefficients of key parameters are calculated, such as; ΔP / f (frequency sensitivity), ΔP / fA (amplitude sensitivity), etc. (these coefficients reflect the relative importance of each noise parameter on the performance). Through this regression analysis, an accurate mapping model between noise and performance is established, forming a noise-functional response relationship between the power supply noise and the chip functional performance. Furthermore, the critical condition boundary calculation of the functional module failure is carried out for the noise-functional response relationship. Taking the noise frequency, amplitude, and load current as the coordinate axes of the three-dimensional space, and using the performance degradation degree of the functional module as the isosurface variable, the gradient search and boundary tracking algorithms are adopted to determine the noise parameter combinations that cause each functional module to reach the critical failure state. These critical points form a closed boundary surface in the parameter space (i.e., the power supply noise tolerance boundary surface, which intuitively represents the tolerance ability of the chip to the power supply noise under different working conditions); furthermore, the power supply noise sensitivity grading and classification integration are carried out for the power supply noise tolerance boundary surface, the noise source spatio-temporal distribution map, and the noise propagation characteristic map. That is, first, according to the noise tolerance boundary surface, the noise sensitivity levels of each functional module are determined, divided into highly sensitive (noise tolerance lower than 20% of the industry standard), moderately sensitive (noise tolerance between 20% and 80% of the industry standard), and lowly sensitive (noise tolerance higher than 80% of the industry standard) levels. Then, these sensitivity levels are associated with the key noise sources in the noise source distribution map to identify which noise sources have the greatest impact on the key functional modules. Combining the propagation path information in the noise propagation characteristic map, the main propagation channels and possible optimization points of the noise from the source to the sensitive module are determined, and "hypothesis-verification" analysis is carried out to evaluate the potential effects of different optimization schemes (such as adding decoupling capacitors, improving the power grid, adjusting the position of sensitive circuits, etc.). Finally, all the analysis results are integrated into a structured test report, including noise source location, propagation path, sensitive module identification, critical working conditions, and improvement suggestions, etc., forming the power supply noise impact test results of the target chip. This result not only details the power supply noise sensitive characteristics of the chip but also provides targeted optimization directions.

[0034] In the embodiments of the present invention, by collecting and preprocessing multi-modal sensing data of the target chip power supply, a multi-dimensional measurement data system of voltage, current, temperature, displacement, and electromagnetic field with spatio-temporal synchronization is constructed. Then, these data are subjected to multi-level time-frequency domain decomposition and feature extraction to obtain a hierarchical feature vector set representing the power supply noise characteristics. Next, the noise source location is determined through time delay analysis and spatial positioning technology, and combined with the chip layout, multi-physical field coupling analysis is carried out to construct an electro-thermal-mechanical-magnetic propagation matrix, thereby analyzing the propagation mechanism of noise inside the chip. Finally, by designing special test conditions, the influence degree of noise on each functional module is verified, the performance degradation threshold is measured, a noise tolerance boundary surface is formed, and a comprehensive power supply noise influence test result is output. Through multi-level sensing data processing and physical field coupling analysis, the accuracy problem of chip power supply noise location and influence assessment is solved. Especially in aspects such as high-frequency noise propagation, cross-domain noise coupling, and performance degradation prediction, the non-linear characteristics of the power supply network and multi-physical field interaction are fully considered, effectively improving the noise source location accuracy. And by adopting a multi-dimensional feature decoupling and propagation path analysis strategy, both accurate identification of noise types and enhanced reliability of influence assessment are achieved. In addition, through the construction of the noise-performance response relationship and the determination of critical thresholds, the functional safety margin is accurately evaluated, thus overall realizing the comprehensive and accurate evaluation and assessment of the influence of chip power supply noise.

[0035] The above describes the chip power supply noise influence test method in the embodiments of the present invention. Next, the chip power supply noise influence test device in the embodiments of the present invention will be described. Please refer to Figure 2 , an embodiment of the chip power supply noise influence test device in the embodiments of the present invention includes: A data acquisition module 201, configured to collect multi-dimensional data of the target chip power supply by using a preset multi-modal sensing array, obtain original multi-dimensional sensing data, and perform time synchronization calibration and signal preprocessing on the original multi-dimensional sensing data to obtain preprocessed multi-dimensional sensing data; A noise location module 202, configured to perform time-frequency domain decomposition operation and correlation calculation of multi-level sensing parameters on the preprocessed multi-dimensional sensing data to obtain a hierarchical feature vector set, and perform noise time delay and noise spatial position calculation on the hierarchical feature vector set to obtain a spatio-temporal distribution map of the noise source; A propagation analysis module 203, configured to perform target chip layout mapping and multi-physical field numerical calculation on the spatio-temporal distribution map of the noise source, generate a multi-physical field coupling propagation matrix of the power supply noise, and perform noise eigenvalue decomposition and propagation path calculation on the multi-physical field coupling propagation matrix to obtain a noise propagation feature map of the power supply network; An impact assessment module 204 is configured to perform performance parameter tests on each chip functional module in the target chip based on preset noise propagation test condition data and the noise propagation characteristic map, obtain the noise-functional performance response relationship between the power supply noise and the chip functional performance, and determine the noise critical values and the power supply noise tolerance boundary surface corresponding to various chip functional failures of the target chip based on the noise-functional performance response relationship, and generate the power supply impact test result of the target chip.

[0036] In the embodiments of the present invention, by collecting and preprocessing multi-modal sensing data of the power supply of the target chip, a multi-dimensional measurement data system of voltage, current, temperature, displacement, and electromagnetic field with spatio-temporal synchronization is constructed. Then, these data are subjected to multi-level time-frequency domain decomposition and feature extraction to obtain a hierarchical feature vector set characterizing the power supply noise characteristics. Next, the noise source location is determined through time delay analysis and spatial positioning technology, and combined with the chip layout, multi-physical field coupling analysis is carried out to construct an electro-thermal-mechanical-magnetic propagation matrix, thereby analyzing the noise propagation mechanism inside the chip. Finally, by designing a dedicated test condition to verify the influence degree of the noise on each functional module, the performance degradation threshold is measured, the noise tolerance boundary surface is formed, and a comprehensive power supply noise impact test result is output. Through multi-level sensing data processing and physical field coupling analysis, the accuracy problem of chip power supply noise location and impact assessment is solved. Especially in aspects such as high-frequency noise propagation, cross-domain noise coupling, and performance degradation prediction, the non-linear characteristics of the power supply network and the multi-physical field interaction are fully considered, effectively improving the noise source location accuracy. And by adopting a multi-dimensional feature decoupling and propagation path analysis strategy, both the accurate identification of the noise type and the reliability of the impact assessment are achieved. In addition, through the construction of the noise-performance response relationship and the determination of the critical threshold, the functional safety margin is accurately evaluated, thus overall realizing the comprehensive and accurate evaluation and assessment of the chip power supply noise impact.

[0037] This application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld devices or portable devices, tablet devices, multi-processor systems, microprocessor-based systems, set-top boxes, programmable consumer electronic devices, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, and so on. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. This application can also be practiced in a distributed computing environment, where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0038] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip power supply noise impact test method, characterized in that: The chip power supply noise impact test method includes: Using a preset multi-modal sensor array to collect multi-dimensional data of a target chip power supply to obtain original multi-dimensional sensor data, and performing time synchronization calibration and signal preprocessing on the original multi-dimensional sensor data to obtain preprocessed multi-dimensional sensor data; Performing time-frequency domain decomposition and correlation calculation of multi-layer sensing parameters on the preprocessed multi-dimensional sensing data to obtain a hierarchical feature vector set, and performing noise delay and noise spatial position calculation on the hierarchical feature vector set to obtain a temporal and spatial distribution map of noise sources; Performing target chip layout mapping and multi-physics field numerical calculation on the spatiotemporal distribution diagram of the noise source to generate a multi-physics field coupled propagation matrix of the power supply noise, and performing noise eigenvalue decomposition and propagation path calculation on the multi-physics field coupled propagation matrix to obtain a noise propagation characteristic spectrum of the power supply network; Based on the preset noise propagation test condition data and the noise propagation characteristic map, performance parameter tests are performed on each chip function module in the target chip to obtain the noise function response relationship between power supply noise and chip functional performance, and based on the noise function response relationship, the noise critical values ​​and power supply noise tolerance boundary surfaces corresponding to various chip function failures of the target chip are determined to generate the power supply impact test results of the target chip.

2. The chip power supply noise impact testing method according to claim 1, characterized in that: The original multi-dimensional sensing data includes voltage waveform original data, current waveform original data, temperature distribution original data, displacement original data and three-dimensional electromagnetic field strength original data. The multi-dimensional data of the target chip power supply is collected by using a preset multi-modal sensing array to obtain the original multi-dimensional sensing data, including: The voltage waveform data of multiple voltage test points in the target chip are collected by using a preset multimodal sensor array to obtain the voltage waveform raw data, and the dynamic current change data of each power domain in the target chip are collected by using the preset multimodal sensor array to obtain the current waveform raw data, and the temperature field distribution data on the surface of the target chip are collected by using the preset multimodal sensor array to obtain the temperature distribution raw data, and the micro-mechanical displacement data of the target chip are collected by using the preset multimodal sensor array to obtain the displacement raw data, and the electromagnetic field distribution data in the space above the target chip are collected by using the preset multimodal sensor array to obtain the three-dimensional electromagnetic field intensity raw data.

3. The chip power supply noise impact testing method according to claim 2, characterized in that: The performing time synchronization calibration and signal preprocessing on the original multi-dimensional sensing data to obtain preprocessed multi-dimensional sensing data includes: Calculating the contact impedance between the test point probe and the chip on the voltage waveform raw data and the current waveform raw data to obtain a contact impedance change value, and performing amplitude compensation on the voltage waveform raw data based on the contact impedance change value to obtain compensated voltage waveform data; Based on the probe transfer function corresponding to the multimodal sensor array, the current waveform raw data is subjected to time-frequency transformation and frequency response compensation to obtain compensated current waveform data, and the temperature distribution raw data is subjected to spatial pixel resampling and temperature value correction calculation of the chip surface area to obtain calibrated temperature field data, and the displacement raw data is subjected to PCB inherent resonance filtering and mechanical decoupling calculation to obtain calibrated displacement data, and the three-dimensional electromagnetic field intensity raw data is subjected to spatial deconvolution calculation to obtain high-resolution electromagnetic field distribution data; The compensated voltage waveform data, the compensated current waveform data, the calibrated temperature field data, the calibrated displacement data and the high-resolution electromagnetic field distribution data are calibrated in time synchronization with multiple sensors to obtain time-calibrated noise data, and the time-calibrated noise data is subjected to multi-dimensional abnormal data detection and spatiotemporal interpolation of abnormal points to obtain pre-processed multi-dimensional sensing data.

4. The chip power supply noise impact testing method according to claim 3 is characterized in that: The step of performing time-frequency domain decomposition and correlation calculation of multi-layer sensing parameters on the pre-processed multi-dimensional sensing data to obtain a hierarchical feature vector set includes: Based on the power supply voltage noise characteristics corresponding to the voltage data in the preprocessed multidimensional sensor data, segmented windowing calculation is performed on the voltage data in the preprocessed multidimensional sensor data to obtain a voltage segmented window data set, and preset microscopic time-domain characteristic parameters are calculated for each window data segment in the voltage segmented window data set to obtain a voltage microscopic time-domain characteristic vector; Performing spatial gradient calculation and heat conduction time series calculation on the surface hot spot area of ​​the temperature field data in the preprocessed multidimensional sensing data to obtain a temperature field characteristic vector, performing modal decomposition and resonance feature extraction on the displacement data in the preprocessed multidimensional sensing data to obtain a mechanical displacement characteristic vector, performing spatial harmonic decomposition and field intensity distribution calculation on the electromagnetic field distribution data in the preprocessed multidimensional sensing data to obtain an electromagnetic field characteristic vector, and performing power supply network impedance spectrum decomposition and calculation on the voltage data and current data in the preprocessed multidimensional sensing data to obtain a power supply network impedance characteristic vector; The voltage microscopic time-domain feature vector, the temperature field feature vector, the mechanical displacement feature vector, the electromagnetic field feature vector and the power supply network impedance feature vector are aligned in feature dimensions and matched in feature space positions to obtain a multi-physical quantity associated data set, and multi-modal feature fusion and principal component dimensionality reduction calculation are performed on the multi-physical quantity associated data set to obtain a hierarchical feature vector set.

5. The chip power supply noise impact testing method according to claim 1, characterized in that: The step of calculating the noise delay and the noise spatial position of the hierarchical feature vector set to obtain a temporal and spatial distribution diagram of the noise source includes: Classifying the noise feature types of the hierarchical feature vector to obtain a power supply noise type classification result, and performing similarity matching calculation on various types of power supply noise features in the power supply noise type classification result based on a preset power supply noise template library to obtain a power supply noise feature recognition result; Based on the voltage waveform data in the pre-processed multi-dimensional sensing data, the wavefront arrival time difference is calculated for the power supply noise feature recognition result to obtain noise propagation time data, and the power supply noise feature recognition result is triangulated to calculate the power supply network delay difference to obtain preliminary position data of the noise source; The maximum intensity point and propagation direction of power supply noise radiation are calculated for the electromagnetic field distribution data in the preprocessed multidimensional sensing data and the preliminary position data of the noise source to obtain precise position data of the noise source, and based on the power supply noise feature recognition result, chip space mapping and noise confidence evaluation are performed on the precise position data of the noise source to obtain a spatiotemporal distribution diagram of the noise source.

6. The chip power supply noise impact testing method according to claim 5, characterized in that: The target chip layout mapping and multi-physics field numerical calculation are performed on the spatiotemporal distribution diagram of the noise source to generate a multi-physics field coupling propagation matrix of the power supply noise, including: Based on the chip design layout corresponding to the target chip, coordinate mapping calculation is performed on the noise source spatiotemporal distribution diagram between each noise source and the chip component area to obtain a noise source and component correspondence table, and the electric field distribution model of the target chip power supply is constructed by using the noise source and component correspondence table and the power supply noise feature recognition result to obtain an electric field distribution function; Performing Joule heat calculation inside the chip on the electric field distribution function and the current data in the preprocessed multi-dimensional sensing data to obtain a temperature field distribution function, and performing thermal stress calculation on the temperature field distribution function and preset chip material parameters to obtain a chip stress field function and a chip strain field function; The strain field function and the preset power supply electrical network parameters are subjected to deformation parameter conversion calculation to obtain the electrical parameter change function, and the electric field distribution function, the temperature field distribution function, the stress field function, the strain field function and the electrical parameter change function are subjected to multi-physical field coupling matrix operation to obtain the multi-physical field coupling propagation matrix.

7. The chip power supply noise impact testing method according to claim 6, characterized in that: The performing noise eigenvalue decomposition and propagation path calculation on the multi-physical field coupling propagation matrix to obtain a noise propagation characteristic spectrum of the power supply network includes: Decomposing the noise transmission intensity and propagation characteristic vector of the multi-physics field coupling propagation matrix to obtain a noise propagation characteristic vector set, and constructing a power supply noise propagation network diagram of the target chip based on the noise propagation characteristic vector set; Calculating the power supply noise energy transmission path on the power supply noise propagation network diagram to obtain a power supply noise propagation path set, and calculating the power supply network impedance transmission characteristics on the power supply noise propagation path set and the noise transfer coefficients in the noise propagation feature vector set to obtain a power supply noise path transfer function set; A convolution operation of power supply interference waveform propagation is performed on the power supply noise path transfer function set and the power supply noise feature identification result to obtain an endpoint noise prediction result, and a mapping and integration of power supply noise propagation relationships is performed on the power supply noise propagation network diagram, the noise propagation path set, the path transfer function set and the endpoint noise prediction result to obtain a noise propagation feature map of the power supply network.

8. The chip power supply noise impact testing method according to claim 1, characterized in that: Based on the preset noise propagation test condition data and the noise propagation characteristic map, a performance parameter test is performed on each chip function module in the target chip to obtain a noise function response relationship between power supply noise and chip function performance, and based on the noise function response relationship, noise critical values ​​and power supply noise tolerance boundary surfaces corresponding to multiple chip function failures of the target chip are determined to generate a power supply impact test result of the target chip, including: Based on the preset noise propagation test condition data, the noise propagation characteristic spectrum is subjected to test condition calculations of multiple frequency bands to obtain a power supply noise test condition matrix, and based on the power supply noise test condition matrix, a power supply noise injection test data set for the power supply end test corresponding to the target chip is determined; Based on the power supply noise injection test data set, a performance parameter test of each chip function module in the target chip is performed with multiple controlled noise signal injections to obtain a function module performance parameter response data set, and a threshold detection calculation of a multi-function module is performed on the function module performance parameter response data set to obtain a function module noise threshold data set; Performing correlation regression calculation of power supply noise and function degradation mapping on the function module noise threshold data set and the power supply noise injection test data set to obtain a noise function response relationship between power supply noise and chip functional performance, and performing critical condition boundary calculation of function module failure on the noise function response relationship to obtain a power supply noise tolerance boundary surface; The power supply noise tolerance boundary surface, the noise source spatiotemporal distribution diagram and the noise propagation characteristic spectrum are integrated by grading and classifying the power supply noise sensitivity to obtain the power supply noise impact test result of the target chip.

9. A chip power supply noise impact test device, characterized in that: The chip power supply noise impact testing device comprises: A data acquisition module is used to collect multi-dimensional data of the target chip power supply using a preset multi-modal sensor array to obtain original multi-dimensional sensor data, and to perform time synchronization calibration and signal preprocessing on the original multi-dimensional sensor data to obtain preprocessed multi-dimensional sensor data; A noise localization module is used to perform time-frequency domain decomposition and correlation calculation of multi-layer sensing parameters on the pre-processed multi-dimensional sensing data to obtain a hierarchical feature vector set, and to perform noise delay and noise spatial position calculation on the hierarchical feature vector set to obtain a temporal and spatial distribution map of the noise source; A propagation analysis module is used to perform target chip layout mapping and multi-physics field numerical calculation on the spatiotemporal distribution diagram of the noise source, generate a multi-physics field coupled propagation matrix of the power supply noise, and perform noise eigenvalue decomposition and propagation path calculation on the multi-physics field coupled propagation matrix to obtain a noise propagation characteristic spectrum of the power supply network; The impact assessment module is used to perform performance parameter tests on each chip function module in the target chip based on preset noise propagation test condition data and the noise propagation characteristic map, obtain the noise function response relationship between power supply noise and chip functional performance, and determine the noise critical values ​​and power supply noise tolerance boundary surfaces corresponding to multiple chip function failures of the target chip based on the noise function response relationship, and generate the power supply impact test results of the target chip.

Images