MCU circuit implementation method for synchronous control of large-scale discrete neural network

Abstract

The invention discloses an MCU circuit implementation method for synchronous control of a large-scale discrete neural network, and aims to solve the problems of difficulty in synchronous detection of an existing neural network, high occupation of FPGA resources, insufficient deployment of a large-scale circuit and the like. Firstly, a large-scale neural network is constructed through chemical synaptic coupling, the synchronous manifold stability is analyzed by using a main stability function, and the neural network is synchronously regulated and controlled. Then a hardware circuit is designed based on an AT32 microcontroller, high-dimensional network efficient deployment is completed with low hardware cost by optimizing DMA data transmission and a 12-bit DAC module, finally a 200-dimensional Aihara neural network circuit is successfully achieved, hardware feasibility is verified, a hardware basis is provided for the fields of brain disease mechanism research, the Internet of Things, secret communication and the like, and engineering application potential is achieved.

Description

Technical Field

[0001] The present invention belongs to the field of complex network regulation and hardware implementation, and particularly relates to an MCU circuit implementation method for synchronous control of a large-scale discrete neural network. After analyzing by using the master stability function analysis method, the coupling parameters are adjusted to achieve complete synchronous control of the neural network, and different spatio-temporal patterns of the neural network are obtained. Finally, a large-scale neural network circuit implementation method is given based on the microcontroller (MCU) platform. Background Art

[0002] Since the synchronization phenomenon in complex networks has broad application prospects in multiple disciplines, including information science, secure communication, and biochemistry, etc., this research has received the attention of many scholars. As a typical representative subclass of complex networks, the research on the synchronization mechanism and stability of neural networks is also worthy of in-depth exploration. It not only supports the information encoding and computing functions of neural networks, but also provides a key bionic foundation for the development of artificial intelligence systems and synchronous control applications.

[0003] The discrete neuron model has high computational efficiency, simple model structure, and strong numerical stability, providing feasibility for large-scale complex calculations. Discrete neurons are connected through electrical and chemical synapse couplings to form a large-scale discrete neural network. There are also many types of neural network synchronization states, including complete synchronization, where all neurons are in the same state; phase synchronization, where phase oscillations occur while maintaining the amplitude difference; cluster synchronization, where subsets of nodes are synchronized within the cluster. Another remarkable pattern is the chimera state, where synchronous and asynchronous populations coexist in the same network. Analyzing the behaviors of the above neural networks is the key to understanding the mechanisms of functional brain diseases such as epilepsy, Parkinson's disease, and Alzheimer's disease.

[0004] The hardware implementation of neural networks can apply neural networks to engineering practice. Currently, the hardware implementation of neural networks is mainly divided into two types of solutions: analog circuits and digital circuits. Due to the influence of environmental factors such as temperature drift and device nonlinearity in analog circuits, the parameters of electronic components are prone to shift, resulting in a significant decrease in signal processing accuracy and higher implementation difficulty. In contrast, digital circuits adopt a discretized signal processing method, with advantages such as strong anti-interference ability and flexible programmability. Among them, the Field Programmable Gate Array (FPGA) is often used to accelerate neural network operations due to its parallel computing characteristics. However, when the scale of the neural network expands, the FPGA needs to consume a large number of logic units and storage resources, and the occupancy rate of hardware resources climbs sharply, making it difficult to meet the requirements of large-scale network deployment. At the same time, due to the limited channels of the oscilloscope, it is impossible to parallelly output the membrane potentials of neurons in a large-scale network. Therefore, researchers have turned to the MCU solution with higher resource utilization and stronger software configurability. By optimizing the algorithm compression and hardware scheduling strategy, while ensuring the accuracy of neuron state detection, the operation efficiency and hardware cost are effectively balanced. By implementing the synchronous anomaly detection of neural networks on the MCU digital hardware platform, this not only helps to understand the spatio-temporal patterns of neural networks but also provides a direction for solving problems in the field of medical diseases.

[0005] The technical differences between this application and the prior art are as follows: Technical comparison with the published number CN108768904A, "Signal Blind Detection Method Based on Amplitude-Phase Discrete Hopfield Neural Network with Perturbation". In view of the problems such as slow convergence speed and easy to fall into local minimum in signal blind detection in wireless communication, the published number CN108768904A realizes efficient optimization by improving the Hopfield neural network structure and introducing a perturbation factor. According to the output of the Hopfield neural network structure, an acceptance data matrix is constructed. After applying fixed perturbation, self-perturbation, and annealing perturbation, the dynamic equation of the amplitude-phase discrete Hopfield neural network is constructed. If the following holds it is considered that the network reaches the equilibrium network transmission signal. And this invention proposes the master stability function analysis method. By analyzing the stability of the synchronous manifold, the maximum Lyapunov exponent of the perturbation equation and the synchronous error of the network are deduced, and the interval of complete synchronization is accurately obtained. Although both involve the solution of network balance, the methods used are different and the focuses are also different. This invention mainly uses the master stability function analysis to obtain the state characteristics of each node in the neural network, and can obtain accurate coupling strength values to regulate large-scale neural networks. However, the published number CN108768904A emphasizes the dependence of different perturbations on the length of the input signal data.

[0006] Technical comparison with the patent "A memristive coupled heterogeneous discrete neuron system with synaptic crosstalk" with publication number CN116415638A; The patent with publication number CN116415638A designed a simulation model of a heterogeneous discrete neural network circuit with synaptic crosstalk, using discrete memristors as synapses to couple two heterogeneous discrete neurons, and studied the phase synchronization and synchronization transition of the system. Simulink was selected for simulation experiment platform simulation, and various coexisting attractor phenomena and phase synchronization phenomena could be obtained by adjusting the corresponding circuit parameters. However, the present invention mainly focuses on large-scale discrete neural networks, and the object of study is the spatio-temporal pattern analysis of a 200-dimensional system, and the analysis objects are different. In the implementation of the hardware circuit, the present invention mainly uses a microcontroller platform and observes through an oscilloscope platform, and the experimental results can be intuitively observed, and the implementation platforms are also different. The present invention is implemented using a microcontroller digital platform, demonstrating the feasibility of applying large-scale neural networks to reality.

[0007] Aiming at the problems of existing neural networks, such as too many nodes, the need to detect the synchronization state of the network, and the difficulty in implementing the circuit of large-scale cluster neural networks, the present invention aims to design an MCU circuit implementation method for synchronizing and controlling large-scale discrete neural networks. The invention uses chemical synapses as a medium and connects discrete neurons in a nearest-neighbor coupling manner to form a high-dimensional neural network to simulate the information transmission of the human brain. Through synchronization analysis, the interval in which neurons reach complete synchronization is obtained, and an MCU digital hardware platform is used to implement a neural network circuit with up to 200 dimensions. Summary of the Invention

[0008] Aiming at the problems of existing neural networks, such as too many nodes, the need to detect the synchronization state of the network, and the difficulty in implementing the circuit of large-scale cluster neural networks, the present invention aims to design an MCU circuit implementation method for synchronizing and controlling large-scale discrete neural networks. First, a large-scale discrete neural network model is constructed, and the master stability function method is used for analysis to find the complete synchronization range of the large-scale neural network, determine the synchronization interval of the cluster network, and obtain richer spatio-temporal patterns of the cluster network; based on the MCU digital hardware platform with strong programmability, a large-scale neural network hardware circuit is implemented to apply the neural network to engineering practice.

[0009] The present invention provides an MCU circuit implementation method for synchronizing and controlling large-scale discrete neural networks, including the following steps: S1 Use chemical synapses to connect in a nearest-neighbor coupling manner to construct a discrete neural network model, realize a neural network with brain-like functions, and simulate the activities of brain neurons; According to the analysis of the master stability function method, through numerical theoretical derivation, synaptic snapshot graphs of complete synchronization are obtained by selecting different chemical coupling strengths, and synaptic snapshot graphs of chimera states are obtained by taking values within the asynchronous range; S3 Design a hardware circuit based on the AT32 series microcontroller, and implement a discrete neural network circuit according to the software design.

[0010] As a further improvement of the present invention, in the process of constructing the discrete neural network model in step S1, a discrete chaotic Aihara neuron model is selected, and its mathematical expression is: Select discrete chaotic Aihara neurons to construct a large-scale discrete neural network model as follows: ; Where is the neuron iteration number, represents the membrane potential of the neuron, represents the cell membrane ion level, is the state decay factor, is the delayed feedback strength, is the nonlinear gain, is the external input, where and are positive values, is a logistic function, where the steepness parameter is the connectivity matrix, and the network is made into a nearest-neighbor coupled connection by constructing an adjacency matrix, is the chemical coupling strength, is the synaptic reversal potential, is the chemical synaptic coupling function, where is the neuron membrane potential, where , determines the slope of the chemical synaptic coupling function, is the synaptic firing threshold.

[0011] As a further improvement of the present invention, the master stability function analysis method in step S2 is as follows: Step 1) First, assume that all neurons are in a synchronous state, that is , since represents the membrane potential of the neuron, represents the cell membrane ion level, then is the two states of the th neuron. When taking any respectively represents the synchronous state of the neurons, that is, all neurons are in the same state, and the equation in the synchronous state is obtained; Step 2) Use the master stability function analysis. By perturbing the synchronous state of neurons, obtain the perturbation equation of the discrete neural network; Step 3) Use the Laplacian matrix L of eigenvalues to convert the variational equation into a decoupled mapping, and apply diagonalization transformation , where the matrix Q is constructed by the eigenvectors of the matrix L , is the linear equation obtained after diagonalization after decoupling, is the variational equation of the network, so as to obtain a decoupled linear system; Step 4) Solve the maximum Lyapunov exponent of the perturbation equation and the synchronization error of the chemical coupling network equation when the coupling strength changes, and verify the results bidirectionally. Finally, obtain the interval where the discrete neural network reaches complete synchronization, and select different coupling strengths to obtain different spatio-temporal patterns.

[0012] As a further improvement of the present invention, the hardware circuit is implemented based on the AT32 series microcontroller in step S3, and the processing steps are as follows: Step 1) In the generate_system function, generate system membrane potential data through the neuron network and store the data; at the same time, encode all neuron signals and store them in an array; Step 2) Configure the target address and source address of the register, enable the DMA circular mode, and the nested vector interrupt controller NVIC configures the DMA channel interrupt priority to ensure that the transmission restarts automatically after the cycle ends. The DMA circular mode ensures continuous waveform output without additional code intervention; Step 3) Initialize the DAC and timer, let the TMR trigger the DMA request at a fixed period, and expand the dual-channel DAC data. Among them, the high 12 bits store the system membrane potential data, and the low 12 bits store the corresponding numbers of neuron signals. The right alignment mode is adopted, and the remaining positions are filled with zeros. Each trigger transfers the data content of one word to the DAC, and the dual channels are updated synchronously; Step 4) Configure the output pins of the development board through the gpio_config function. In the gpio_config design, there are two channels, namely channel DAC1 and channel DAC2. Configure PA4 of channel DAC1 and PA5 of channel DAC2 as analog modes and directly connect them to the DAC output pins; Step 5) Observe the PA4 and PA5 pins through an oscilloscope. The dual-channel pins and the pins of the development board should share the same ground, and then use the oscilloscope to display the synaptic snapshot diagram and capture various states of the neurons in the neural network.

[0013] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: For the first time, the present invention connects Aihara neurons and chemical synapses in the nearest neighbor coupling to construct a large-scale Aihara neural network. Compared with a single Aihara neuron, the large-scale neural network has stronger randomness. Further analysis using the master stability function method can completely synchronize and control the neural network. At the same time, the MCU digital platform is used to overcome the problems that it is difficult to implement the large-scale neural network circuit and it is difficult to display with an oscilloscope. The implementation of the digital platform successfully proves that it has broad application prospects in engineering fields such as the Internet of Things, signal detection, and secure communication. The present invention not only provides a brand-new idea for the synchronous detection and hardware implementation of large-scale discrete Aihara neural networks, but also can be applied to other neural networks, which is of great significance to disciplines such as non-linear neurons and intelligent control. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a specific implementation block diagram; Figure 2 It is the hardware part of the large-scale neural network circuit implementation; Figure 3 It is the software part of the large-scale neural network circuit implementation; Figure 4 It is a schematic diagram of the Aihara neural network under chemical connection; Figure 5 It is a block diagram of the DMA controller; Figure 6 It is a block diagram of the DAC module; Figure 7 It is the implementation result of the synaptic snapshot based on the MCU; Wherein Figure 7 (a) is the implementation result of the synaptic snapshot based on the MCU in the complete synchronization state, Figure 7 (b) is the implementation result of the synaptic snapshot based on the MCU in the chimera state. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings.

[0016] The present invention relates to a method for implementing an MCU circuit for synchronously controlling a large-scale discrete neural network. Using the master stability function analysis method, through theoretical derivation, the complete synchronization range of the large-scale Aihara neural network can be obtained, and the complete synchronization phenomenon of the corresponding neural network can be obtained under a certain coupling strength. The high-dimensional Aihara neural network circuit is implemented according to the c++ language programming, and the synaptic snapshot diagram can be captured using an oscilloscope.

[0017] Circuit implementation of large-scale neural networks based on an MCU digital hardware platform, which is specifically divided into two parts: hardware and software. The processing steps are as follows: Step 1) Hardware part; The hardware platform is shown in Figure 2 and mainly includes the following aspects: a 32-bit AT32F403AVGT7 microcontroller with a main frequency of 240 MHz, 1024 kB of flash memory, and 224 kB of RAM. The microcontroller is used to generate an iterative sequence and convert digital signals into analog signals using the digital-to-analog converter (DAC) module on the main board. The DAC module uses 12-bit digital inputs to generate a reference voltage between . Neuron membrane potential data values are generated through iteration using the input neuron equation. The direct memory access (DMA) module transfers the data values to the address mapped by the DAC. After D / A conversion, the PA4 and PA5 ports of the single-chip microcomputer AT32 have the functions of controlling the I / O direction and input / output, output the analog signal after DAC conversion, and display it using an oscilloscope.

[0018] Step 2) Software part; Due to the limited channels of the oscilloscope, it is impossible to output the membrane potentials of neurons in a large-scale network in parallel. To solve the above problem, an interrupt program is first used to generate output signals. When entering the interrupt program from the main program, the final state values of 100 neurons are saved in an array. Since the function of the DMA is to quickly move memory data and copy the content of a specified storage area to another storage area space. Therefore, the timer is used to control the DMA to transport data, so that the data can be transported to the DAC; on the other hand, when the data is output through a timed loop, the values will also be cyclically displayed on the oscilloscope, and the specific positions of each neuron cannot be determined. To better display the spatio-temporal pattern of the large-scale neural network, numbers are defined for each neuron, which are 1, 2,..100 in sequence, and the numbers are saved in another array, and finally displayed using the two channels of the oscilloscope. Figure 3 It is the flowchart for program implementation.

[0019] The specific steps of the algorithm of the present invention are as follows, and the specific implementation block diagram of the present invention is as Figure 1 shown: 1. First, construct a large-scale discrete neural network model: Step 1) Select the Aihara neuron model and use chemical synapses to connect with nearest-neighbor coupling to construct a large-scale discrete Aihara neural network model. The system equation is as follows. Where Figure 4 is the schematic diagram of the connection of the Aihara neural network.

[0020] ; 2. Based on the analysis of the master stability function method, through numerical theoretical derivation, the complete synchronization of the neural network is regulated as follows: Step 1) First, assume that all neurons are in a synchronous state , and obtain the equation in the synchronous state; ; Step 2) Using the master stability function analysis method, by perturbing the synchronous state of the neurons, analyze the perturbation equation of the neurons and the perturbation equation of the coupling term respectively as follows: ; Finally, according to the above analysis results, the perturbation equation of the Aihara neural network is: ; Step 3) Using the eigenvalues L of the Laplacian matrix , the variational equation can be transformed into a decoupled mapping, where L = D - G ( D is the degree matrix); ; Apply the diagonalization transformation , where the matrix Q is constructed by the eigenvectors of the matrix L , thus obtaining a new linear system of variables .

[0021] ; Substitute into the Aihara neuron to obtain the variational equation of this neural network, and obtain the synchronization range by solving the maximum Lyapunov exponent of this variational equation.

[0022] ; Step 4) Define the number of neurons in the network as 100, and set the connection matrix as the nearest neighbor coupling matrix. Calculate all the eigenvalues of the Laplacian matrix. The network is connected, so the eigenvalues can be sorted as . The maximum Lyapunov exponent of the perturbation equation and the synchronization error of the chemical coupling network equation can be solved when the coupling strength changes, and a two-way verification experiment result can be carried out. The specific values are as follows: , the initial values of all neurons are randomly selected near , and finally it is obtained that the discrete neural network can achieve complete synchronization at and .

[0023] Step 6) Select the chemical synaptic coupling strength within the synchronization interval , the network can exhibit a completely synchronous state. Near the synchronization interval, take , the network can exhibit a chimera state.

[0024] 3. Based on the numerical analysis results, design the hardware implementation of the Aihara neural network based on the MCU.

[0025] Step 1) In the generate_system function, generate the system membrane potential data through the neural network, store the data, allocate it to the global array system16bit, and save it in the data format with 16-bit precision; at the same time, encode all neuron signals and store them in another one-dimensional array neuron_16bit. Similarly, save it in the data format with 16-bit precision.

[0026] Step 2) DMA can implement three modes of data transfer between peripheral registers and memory or between memory and memory. This is mainly due to the fact that the DMA controller samples the AHB master bus and can control the AHB bus matrix to initiate AHB transactions. DMA transfer is to copy the content of a specified storage area to another storage area. Using DMA transfer can achieve higher transfer efficiency. In particular, DMA transfer does not occupy the CPU and can save a lot of CPU resources.

[0027] Figure 5 As shown in the block diagram of the DMA controller, configure the target address and source address of the register, and enable the DMA circular mode. The nested vector interrupt controller (NVIC) configures the interrupt priority of DMA1 channel 1 to ensure that the transfer restarts automatically after the cycle ends. The DMA circular mode ensures continuous waveform output. Set the amount of data to be transferred as SYSTEM_POINTS (100 points), and enable the transfer complete interrupt.

[0028] Step 3) In the dma_config design, splice the data of system16bit stored in the high 16 bits and neuron_16bit stored in the low 16 bits into dualsystem32bit in a loop. The high 16 bits and low 16 bits of each 32-bit data in dualsystem32bit respectively correspond to the 12-bit right-aligned values of DAC2 and DAC1. The target address of DMA channel 1 is set to DAC_HDR12RD_ADDR (dual-channel 12-bit right-aligned data register), the source address is the dualsystem12bit array, and the data width is a word (32 bits).

[0029] Step 4) The function of the DAC is to convert the input digital code into a corresponding analog voltage output. The block diagram of the DAC module of AT32 is shown in Figure 6. The entire DAC module is centered around the "digital-to-analog converter" at the bottom of the block diagram. On its left are the pins of the reference power supply: , and . Initialize the DAC and the timer, select the trigger source as the TMR2 timing cycle trigger, and turn off the output buffer and waveform generation functions. The TMR function configures TMR2 in the up-counting mode, sets the overflow frequency to 3.2 kHz as the DAC trigger signal source. And expand the dual-channel DAC data, where the high 12 bits store the system membrane potential data, and the low 12 bits store the corresponding numbers of neuron signals. Use the right-aligned mode, fill the remaining positions with zeros, and transfer the data content of one word to the DAC each time it is triggered, and the dual channels are updated synchronously.

[0030] Step 5) Configure the output pins of the development board through the gpio_config function. In the gpio_config design, configure PA4 (DAC1) and PA5 (DAC2) as analog modes and directly connect them to the DAC output pins.

[0031] Step 6) Connect the PA4 and PA5 pins through an oscilloscope. The dual-channel pins and the pins of the development board should be grounded. Then use the oscilloscope to display the synaptic snapshot diagram, which can capture various states of the neurons in the neural network. Run the above operation results according to the MCU digital platform, and then capture the experimental results through a digital oscilloscope.

[0032] Step 7) Based on the MCU digital hardware platform, the synaptic snapshots captured by the digital oscilloscope are as shown in Figure 7 . The implementation results of the synaptic snapshots based on the MCU are in a fully synchronous state as shown in Figure 7 (a), and the implementation results of the synaptic snapshots based on the MCU are in a chimera state as shown in Figure 7 (b). The experimental results fully verify the numerical results, indicating the feasibility of implementing a high-dimensional neural network on the MCU hardware platform, providing a practical basis for practical applications.

[0033] In summary, the present invention overcomes the problem that the prior art cannot meet the circuit implementation of the high-dimensional Aihara neural network, obtains the synchronization range of the Aihara neural network according to numerical analysis, and uses the MCU digital platform to implement the circuit of the neural network. The synchronization state of a large-scale neural network can be accurately obtained through detailed theoretical derivation and successfully implemented on the hardware platform, which demonstrates the feasibility of applying the simulation of the characteristics of a large-scale neural network to reality.

[0034] The above are only the preferred embodiments of the present invention, and are not any other form of limitation to the present invention. Any modification or equivalent change made according to the technical essence of the present invention still belongs to the scope of protection required by the present invention.

Claims

1. An MCU circuit implementation method for large-scale discrete neural network synchronous control, characterized in that: The following steps are involved: S1 uses chemical synapses to connect with nearest neighbor coupling to construct a discrete neural network model, realize a neural network with brain-like functions, and simulate brain neuron activities; S2 is analyzed based on the master stability function method. After numerical theoretical derivation, different chemical coupling strengths are selected to obtain fully synchronized synaptic snapshots, and chimera state synaptic snapshots are obtained by taking values ​​within the asynchronous range. S3 designs hardware circuits based on the AT32 series microcontrollers and implements discrete neural network circuits based on software design.

2. The MCU circuit implementation method for large-scale discrete neural network synchronous control according to claim 1 is characterized in that: In the process of constructing the discrete neural network model in step S1, a discrete chaotic Aihara neuron model is selected, and its mathematical expression is: The discrete chaotic Aihara neuron is selected to construct a large-scale discrete neural network model as follows: ； in, is the number of neuron iterations, represents the membrane potential of the neuron, Represents the cell membrane ion level, is the state attenuation factor, is the delayed feedback strength, is the nonlinear gain, is the external input, where and is a positive value, is a logistic function, where the steepness parameter is the connectivity matrix, and the network is made into nearest neighbor coupling connection by constructing the adjacency matrix. is the chemical coupling strength, is the synaptic reversal potential, is the chemical synapse coupling function, where is the neuronal membrane potential, where , determines the slope of the chemical synapse coupling function, is the synaptic firing threshold.

3. The MCU circuit implementation method for large-scale discrete neural network synchronization control according to claim 1 is characterized in that: The main stability function analysis method in step S2 is specifically as follows: Step 1) First, assume that all neurons are in a synchronized state, that is, ,because represents the membrane potential of the neuron, Represents the cell membrane ion level, The first The two states of a neuron, when taking any Respectively represent the synchronization state of neurons, that is, all neurons are in the same state, and obtain the equations in the synchronization state; Step 2) Using the master stability function analysis, the perturbation equation of the discrete neural network is obtained by perturbing the synchronization state of the neurons; Step 3) Using the Laplacian matrix L The eigenvalue of Convert the variational equations into decoupled maps and apply diagonalization transformation , where the matrix Q is the matrix L The eigenvector of is the linear equation obtained by diagonalization after decoupling, is the variational equation of the network, thus obtaining a decoupled linear system; Step 4) Solve the maximum Lyapunov exponent of the perturbation equation and the synchronization error of the chemical coupling network equation when the coupling strength changes, perform bidirectional verification on the results, and finally obtain the interval where the discrete neural network reaches complete synchronization. Select different coupling strengths to obtain different spatiotemporal patterns.

4. The MCU circuit implementation method for large-scale discrete neural network synchronization control according to claim 1 is characterized in that: In step S3, the hardware circuit is designed based on the AT32 series microcontroller, and the processing steps are as follows: Step 1) In the generate_system function, the system membrane potential data is generated through the neural network and stored; at the same time, all neuronal signals are encoded and stored in an array; Step 2) Configure the target address and source address of the register, enable DMA loop mode, and configure the DMA channel interrupt priority of the nested vector interrupt controller NVIC to ensure automatic restart of transmission after the cycle ends. The DMA loop mode ensures continuous waveform output without additional code intervention; Step 3) Initialize DAC and timer, let TMR timing cycle trigger DMA request, and expand dual-channel DAC data, where the upper 12 bits store system membrane potential data, and the lower 12 bits store the corresponding number of neuron signals. The right-aligned mode is used, and the remaining position data is padded with zeros. Each time the trigger is triggered, the data content of one word is transferred to DAC, and the dual channels are updated and output synchronously; Step 4) Configure the output pins of the development board through the gpio_config function. There are two channels in the gpio_config design, namely channel DAC1 and channel DAC2. Configure PA4 of channel DAC1 and PA5 of channel DAC2 to analog mode and connect them directly to the DAC output pins. Step 5) Observe the PA4 and PA5 pins through an oscilloscope. The dual-channel pins and the pins of the development board should share the same ground. Then use the oscilloscope to display the synaptic snapshot diagram to capture the various states of neurons in the neural network.

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