A discrete quantity fast configuration method and control system supporting hardware verification

Abstract

The present invention discloses a method and control system for fast discrete quantity configuration that supports hardware verification. The FPGA searches for corresponding discrete quantity configuration values ​​in a preset discrete quantity lookup table based on a configuration start signal and a desired discrete quantity operating mode. After configuring the discrete state of each discrete quantity group, a logic level signal is written to the configuration completion flag. When the configuration completion signal is high, the FPGA is triggered to obtain the actual discrete quantity state of each discrete quantity group on the current hardware. The current actual discrete quantity state and the discrete quantity configuration value when the hardware is configured according to the discrete quantity lookup table are input into a verification algorithm for verification. After obtaining the verification result, a logic level signal is written to the verification completion flag. The host computer determines whether the discrete quantity operating mode of the hardware is correctly configured based on the read verification result. By reducing the number of register interfaces, the FPGA assumes most of the work, thereby improving the control and debugging efficiency of discrete quantities.

Description

Technical Field

[0001] The present invention relates to the field of electronic communication and control technology, and in particular to a discrete quantity rapid configuration method and control system supporting hardware verification. Background Art

[0002] Discrete quantities include switch signals, enable signals, etc. Their most important feature is that they have a certain level state (high level or low level) at a certain moment. With the increasing complexity of modern electronic systems, there are usually a lot of discrete quantities in a system (for example, a spectrum analyzer may have dozens of electronic switches). Using FPGAs with rich I / O resources to control these discrete quantities has become a common solution in the industry. Its specific implementation usually involves first storing these discrete quantities in several registers on the internal bus defined by the logic in the FPGA, and then allowing the host computer (such as CPU, DSP, etc.) to read and write these registers to achieve the purpose of controlling the corresponding discrete quantities. The general block diagram of this solution is as follows Figure 1 .

[0003] As can be seen from the block diagram, the biggest feature of this solution is that each set of discrete quantities needs to correspond to a register. This will cause the number of register interfaces between the FPGA and the host computer to increase with the number of discrete quantities, and the host computer can only configure one register at a certain moment, that is, it can only control one set of discrete quantities at a certain moment. Figure 1 The discrete quantity control shown has the following drawbacks:

[0004] 1. There are many register interfaces, and only one set of discrete quantities can be controlled at a certain moment, resulting in low control efficiency;

[0005] 2. FPGA actually only provides a forwarding function, and is only responsible for sending the configuration values ​​sent by the host computer to the logic to the corresponding discrete quantities. The specific configuration values ​​are still determined by the host computer. This means that the software in the host computer must know the required state of the discrete quantity at the current moment, which increases the workload of the host computer software engineer and reduces the debugging efficiency of the test engineer.

[0006] 3. There is a lack of substantial verification at the hardware level. It is impossible to determine from the software level whether the discrete quantities on the hardware are controlled correctly. The only way to determine this is to use instruments such as a multimeter to measure the level status of each group of discrete quantities on the hardware, which is very inconvenient.

[0007] Therefore, there is still much room for improvement in the control of discrete quantities, and the configuration and debugging efficiency needs to be further improved. Summary of the Invention

[0008] The present invention aims to provide a method for fast discrete quantity configuration that supports hardware verification and an FPGA implementation. By migrating the configuration and verification execution process to the FPGA, the number of register interfaces between the FPGA and a host computer is greatly reduced. The host computer only needs to provide a startup configuration signal, the current operating mode of each discrete quantity, and a startup verification signal. When a configuration completion signal is received, the host computer can quickly control each group of discrete quantities on the hardware. At the same time, the host computer only needs to read the verification result when a verification completion signal is received. It can then determine whether each discrete quantity on the hardware is correctly controlled at the software level, thereby achieving substantive verification of each discrete quantity.

[0009] To achieve the above objectives, this application provides the following solutions:

[0010] On the one hand, the present application provides a method for fast configuration of discrete quantities that supports hardware verification, wherein the host computer performs the following steps:

[0011] S1. Send the discrete quantity working mode and configuration start signal required by each discrete quantity group on the current hardware to the FPGA;

[0012] S2. Polling the configuration completion signal given by the FPGA. The configuration completion signal is a logic level signal written to the configuration completion flag bit after the FPGA searches for the corresponding discrete quantity configuration value in a preset discrete quantity lookup table based on the configuration start signal and the currently required discrete quantity working mode, and configures the discrete state of each discrete quantity group on the hardware.

[0013] S3. When the configuration completion signal of the FPGA is high, a verification start signal is sent to the FPGA.

[0014] S4. Polling the FPGA for a verification completion signal, wherein the verification completion signal is a logic level signal written to the verification completion flag after the FPGA is triggered by the verification start signal to obtain the actual discrete quantity status of each discrete quantity group on the current hardware, and the current actual discrete quantity status and the discrete quantity configuration value found in step S2 are input into the verification algorithm for verification to obtain the verification result;

[0015] S5. When the check completion signal is high level after being polled, it is determined whether each discrete quantity group on the hardware is in the configured working mode according to the read check result.

[0016] In some specific implementation schemes, in step S2, the specific process of obtaining the configuration completion signal in the FPGA is:

[0017] S21, writing the discrete quantity working mode into the working mode register defined in the FPGA logic, and writing a logic high level into the configuration start register defined in the FPGA logic according to the configuration start signal to start the configuration;

[0018] S22, when the FPGA reads a logic high level from the configuration start register, clearing the configuration completion signal of the last configuration cached in the configuration completion register defined in the FPGA logic;

[0019] S23, the FPGA searches for the corresponding discrete quantity configuration value in a preset discrete quantity lookup table according to the discrete quantity working mode, and configures the discrete quantity state of each discrete quantity group on the hardware according to the discrete quantity configuration value;

[0020] S24. When the discrete quantity state configuration of each discrete quantity group on the hardware is completed, a configuration completion signal of this configuration is written into the configuration completion register.

[0021] In some specific implementation schemes, the specific process of obtaining the verification completion signal in the FPGA is:

[0022] S41, write a logic high level to the verification start register defined in the FPGA logic to start this verification;

[0023] S42, when the FPGA reads the logic high level in the verification start register, it clears the verification completion signal of the previous verification cached in the verification completion register defined in the FPGA logic;

[0024] S43. Obtain the actual discrete quantity status of each discrete quantity group on the current hardware, call the verification algorithm implemented in the FPGA logic to verify the actual discrete quantity status with the discrete quantity configuration value when the hardware is configured according to the discrete quantity lookup table, and write the obtained verification result into the verification result register defined in the FPGA logic;

[0025] S44. After the verification is completed, a verification completion signal of this verification is written into the verification completion register.

[0026] In some specific implementation schemes, the check algorithm in step S43 adopts bitwise XOR check, parity check or CRC check, and the bitwise XOR check is: performing bitwise XOR operation on the actual discrete quantity state on the hardware and the discrete quantity configuration value configured by the host computer in parallel.

[0027] In some specific implementation schemes, the preset discrete quantity lookup table is a truth table, and the discrete quantity lookup table solidifies the configuration values ​​required for each group of discrete quantities on the hardware in various working modes.

[0028] In some specific implementations, when polling the check completion register, if a check completion signal is read, the check result is read from the check result register;

[0029] Based on the verification results, determine whether the actual discrete quantity state on the hardware is consistent with the discrete quantity configuration value configured by the host computer. If they are consistent, determine that each discrete quantity group on the current hardware is working in the discrete quantity working mode specified by the host computer; if they are inconsistent, determine that there is a discrete quantity group on the current hardware that is not working in the discrete quantity working mode specified by the host computer, and find out the discrete quantity group that is not working in the discrete quantity working mode specified by the host computer based on the verification results.

[0030] In a second aspect, the present application provides a control system for fast configuration of discrete quantities supporting hardware verification, including an FPGA and a host computer, wherein the FPGA communicates with the host computer through its internal logic bus, wherein:

[0031] The host computer is used to send the discrete quantity working mode and configuration start signal required by each discrete quantity group to the FPGA.

[0032] It is also used to poll the configuration completion signal given by the FPGA. When the configuration completion signal of the FPGA is high, a verification start signal is sent to the FPGA.

[0033] It is also used to poll the verification completion signal given by FPGA. When the verification completion signal is high, it is judged whether each discrete quantity group on the hardware is in the configured working mode according to the read verification result.

[0034] FPGA, used to look up the corresponding discrete quantity configuration value in the preset discrete quantity lookup table according to the configuration start signal and the currently required discrete quantity working mode, and after configuring the discrete state of each discrete quantity group on the hardware, write the logic level signal to the configuration completion flag bit;

[0035] It is also used to trigger the FPGA to obtain the actual discrete quantity status of each discrete quantity group on the current hardware according to the verification start signal, input the current actual discrete quantity status and the discrete quantity configuration value when the hardware is configured according to the discrete quantity lookup table into the verification algorithm for verification, and then write the logic level signal to the verification completion flag after obtaining the verification result.

[0036] In some specific implementations, the FPGA includes a configuration module, a configuration start register, an operating mode register, and a configuration completion register, wherein:

[0037] A configuration module is used to write the discrete quantity working mode into the working mode register defined in the FPGA logic, and write a logic high level into the configuration start register defined in the FPGA logic to start the configuration according to the configuration start signal;

[0038] When a logic high level is read from the configuration start register, the configuration completion signal of the last configuration cached in the configuration completion register defined in the FPGA logic is cleared;

[0039] According to the discrete quantity working mode, the corresponding discrete quantity configuration value is searched in the preset discrete quantity lookup table, and the discrete quantity status of each discrete quantity group on the hardware is configured according to the discrete quantity configuration value;

[0040] When the discrete quantity state configuration of each discrete quantity group on the hardware is completed, the configuration completion signal of this configuration is written into the configuration completion register.

[0041] In some specific implementations, the FPGA further includes a verification module, a verification start register, a verification completion register, and a verification result register, wherein:

[0042] The verification module is used to write a logic high level to the verification start register defined in the FPGA logic to start this verification;

[0043] When a logic high level is read in the verification start register, the verification completion signal of the previous verification cached in the verification completion register defined in the FPGA logic is cleared;

[0044] Obtain the actual discrete quantity status of each discrete quantity group on the current hardware, call the verification algorithm implemented in the FPGA logic to verify the actual discrete quantity status with the discrete quantity configuration value when the hardware is configured according to the discrete quantity lookup table, and write the verification result into the verification result register defined in the FPGA logic;

[0045] When the verification is completed, the verification completion signal of this verification is written into the verification completion register.

[0046] In some specific implementation schemes, the check algorithm uses a bitwise XOR check, a parity check, or a CRC check. The bitwise XOR check is: performing a bitwise XOR operation on the actual discrete quantity state on the hardware and the discrete quantity configuration value configured by the host computer in parallel.

[0047] The present invention has the beneficial effects:

[0048] 1. The configuration operation proposed in this application is convenient and fast, thanks to the small number of interfaces between the FPGA and the host computer during configuration. Unlike the current common solutions in the industry, in this application, the number of register interfaces within the FPGA logic does not increase as the number of discrete quantities to be controlled increases. The host computer only needs to access a total of three registers for a single configuration or verification. Both configuration and verification require only three steps, namely, providing a configuration or verification start signal, providing a discrete quantity operating mode or reading the substantive verification results at the hardware level, and polling the configuration or verification completion flag, making the operation very simple.

[0049] 2. This application is highly encapsulated, transferring the actual control execution authority of discrete quantities from the host computer to the FPGA. During a configuration process, the host computer software engineer only needs to know the current discrete quantity operating mode and does not need to know the specific configuration value corresponding to that operating mode, because the specific configuration value is automatically derived from the discrete quantity lookup table within this method. For the host computer software engineer, controlling the discrete quantity becomes a "black box"; they only need to provide input and wait for the output result, greatly improving the work and debugging efficiency of the host computer software engineer and test engineer.

[0050] 3. This application implements true hardware verification. By enabling the verification function, the host computer can monitor the actual level status of each discrete quantity on the hardware at any time, thereby determining whether there is a discrete quantity error at the hardware level and further determining which discrete quantity has an error. When an error occurs, there is no need to use instruments such as multimeters to determine the error, greatly improving troubleshooting efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 System block diagram for existing technology implementation;

[0052] Figure 2 A system block diagram for implementing a method for rapidly configuring discrete quantities supporting hardware verification provided by an embodiment of the present invention;

[0053] Figure 3 A schematic diagram of state transitions of a configuration state machine provided in an embodiment of the present invention;

[0054] Figure 4 A schematic diagram of state transitions of a verification state machine provided in an embodiment of the present invention;

[0055] Figure 5 This is a flow chart of a method for rapid discrete quantity configuration supporting hardware verification provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0056] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is in no way intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0057] Unless otherwise specifically stated, the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention.

[0058] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0059] Additionally, descriptions of well-known structures, functions, and configurations may be omitted for clarity and conciseness. Those skilled in the art will recognize that various changes and modifications can be made to the examples described herein without departing from the spirit and scope of the present disclosure.

[0060] Technologies, methods and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods and equipment should be considered part of the authorization specification.

[0061] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0062] like Figure 1 As shown in the figure, in general, for the control of discrete quantities in a control system, each group of discrete quantities requires a corresponding register. This results in the number of register interfaces between the FPGA and the host computer increasing with the number of discrete quantities. Moreover, at a certain moment, the host computer can only configure one register, that is, at a certain moment, only one group of discrete quantities can be controlled. This undoubtedly leads to very low control efficiency in today's control systems with many discrete quantities.

[0063] Furthermore, it can be seen that in this control mode, the FPGA effectively only provides a forwarding function, responsible for transmitting the configuration values ​​issued by the host computer to the corresponding discrete variables via the corresponding registers in the internal logic bus. The specific configuration is still determined by the host computer. This means that the host computer software must know the desired state of the discrete variable at the current moment. As mentioned earlier, the state value of a discrete variable at a given moment is simply "0" or "1" and does not involve any complex software calculations. Therefore, letting the host computer determine the configuration increases the workload of the host computer software engineer and reduces the debugging efficiency of the test engineer. For example, if a discrete variable needs to be configured to mode A at a certain moment, and the corresponding configuration value for mode A is "0x3c", the host computer software engineer and test engineer must not only know that the discrete variable should operate in mode A at this time, but also send "0x3c" to the FPGA to complete the control.

[0064] After the control is completed, the existing solution lacks substantive verification at the hardware level. That is, the host computer can only confirm whether the configuration value has been correctly sent to the FPGA by reading back the value of the corresponding register. It cannot determine whether the actual discrete quantity in the hardware is controlled correctly. If a hardware error occurs (for example, a discrete quantity is forced high or low in hardware), it is impossible to locate the problem at the software level. The only way to locate it is to use instruments such as multimeters to measure the level status of the discrete quantity, which is very inconvenient.

[0065] To this end, this application proposes the following solutions:

[0066] Example 1

[0067] like Figure 2 As shown, this embodiment provides a control system that supports fast configuration of discrete quantities with hardware verification, which is implemented by FPGA and includes FPGA and a host computer. The FPGA communicates with the host computer through its internal logic bus, wherein:

[0068] The host computer is used to send the discrete quantity working mode and configuration start signal required by each discrete quantity group to the FPGA.

[0069] It is also used to poll the configuration completion signal given by the FPGA. When the configuration completion signal of the FPGA is high, a verification start signal is sent to the FPGA.

[0070] It is also used to poll the verification completion signal given by FPGA. When the verification completion signal is high, it is judged whether each discrete quantity group on the hardware is in the configured working mode according to the read verification result.

[0071] FPGA, used to look up the corresponding discrete quantity configuration value in the preset discrete quantity lookup table according to the configuration start signal and the currently required discrete quantity working mode, and after configuring the discrete state of each discrete quantity group on the hardware, write the logic level signal to the configuration completion flag bit;

[0072] It is also used to trigger the FPGA to obtain the actual discrete quantity status of each discrete quantity group on the current hardware according to the verification start signal, input the current actual discrete quantity status and the discrete quantity configuration value when the hardware is configured according to the discrete quantity lookup table into the verification algorithm for verification, and then write the logic level signal to the verification completion flag after obtaining the verification result.

[0073] Specifically, the FPGA includes a configuration module, a configuration start register, an operating mode register, and a configuration completion register, wherein:

[0074] A configuration module is used to write the discrete quantity working mode into the working mode register defined in the FPGA logic, and write a logic high level into the configuration start register defined in the FPGA logic to start the configuration according to the configuration start signal;

[0075] When a logic high level is read from the configuration start register, the configuration completion signal of the last configuration cached in the configuration completion register defined in the FPGA logic is cleared;

[0076] According to the discrete quantity working mode, the corresponding discrete quantity configuration value is searched in the preset discrete quantity lookup table, and the discrete quantity status of each discrete quantity group on the hardware is configured according to the discrete quantity configuration value;

[0077] When the discrete quantity state configuration of each discrete quantity group on the hardware is completed, the configuration completion signal of this configuration is written into the configuration completion register.

[0078] Specifically, the FPGA also includes a verification module, a verification start register, a verification completion register, and a verification result register, wherein:

[0079] The verification module is used to write a logic high level to the verification start register defined in the FPGA logic to start this verification;

[0080] When a logic high level is read in the verification start register, the verification completion signal of the previous verification cached in the verification completion register defined in the FPGA logic is cleared;

[0081] Obtain the actual discrete quantity status of each discrete quantity group on the current hardware, call the verification algorithm implemented in the FPGA logic to verify the actual discrete quantity status with the discrete quantity configuration value when the hardware is configured according to the discrete quantity lookup table, and write the verification result into the verification result register defined in the FPGA logic;

[0082] The check algorithm adopts bitwise XOR check, parity check or CRC check. The bitwise XOR check is: performing bitwise XOR operation on the actual discrete quantity state on the hardware and the discrete quantity configuration value configured by the host computer in parallel.

[0083] When the verification is completed, the verification completion signal of this verification is written into the verification completion register.

[0084] from Figure 2 、 Figure 3 and Figure 4As can be seen, the FPGA control logic primarily consists of a configuration module and a verification module. The configuration module is responsible for achieving rapid control of discrete quantities, while the verification module is responsible for implementing substantive hardware-level verification of the controlled state of discrete quantities. The configuration module internally consists of two parts: a discrete quantity lookup table and a configuration state machine. The discrete quantity lookup table is essentially a truth table, implemented in the FPGA using combinational logic resources such as LUTs. It contains the configuration values ​​for each group of discrete quantities within the entire electronic system under various operating modes. These configuration values ​​are directly transmitted to the discrete quantities by the FPGA, and the transmission process is managed by the logic control flow formed by the configuration state machine. The verification module internally consists of two parts: a verification algorithm core and a verification state machine. The verification algorithm core implements a specific verification algorithm. In this article, the verification algorithm used is XOR. Other verification algorithms (such as parity check, CRC check, etc.) can also be integrated into the verification algorithm core as needed. The calculation process of the algorithm core is managed by the logic control flow formed by the verification state machine.

[0085] In order to reduce the register connection interface with the host computer and the configuration and verification calculation amount of the host computer, the FPGA in this application undertakes most of the work, and there are only 6 register interfaces between the host computer, which are defined on the logical internal bus.

[0086] When it is necessary to control each group of discrete quantities at a certain moment, the host computer first needs to write the working mode of each group of discrete quantities at this time into the working mode register. At this time, the FPGA logic will input the value in the working mode register into the discrete quantity lookup table. The discrete quantity lookup table will obtain the corresponding discrete quantity configuration value according to the working mode. Then the host computer needs to write "1" to the configuration start register to indicate the configuration trigger. At this time, the FPGA logic will generate a configuration trigger signal to the configuration state machine, and then start the configuration of each group of discrete quantities. According to the discrete quantity configuration value obtained from the discrete quantity lookup table, each group of discrete quantities will be controlled in parallel. After the control is completed, the FPGA logic will write "1" to the configuration completion register to indicate that the configuration is complete as a configuration completion flag. The configuration completion flag will be cleared at the start of the next configuration. When the host computer polls and the flag is set, the configuration ends. The configuration state machine is divided into 4 states, namely IDLE state, CLR state, PROGRAM state and DONE state. The state transition diagram is shown as follows. Figure 3As shown in the figure, the IDLE state is responsible for waiting for the configuration trigger signal, that is, waiting for the host computer to start the configuration process. When the configuration state machine reads "1" from the configuration start register, it changes from the IDLE state to the CLR state. The CLR state is responsible for clearing the configuration completion flag generated by the last configuration. When the IDLE state changes to the CLR state, the value of the configuration completion flag in the configuration completion register is cleared. After the clearing is completed, it changes to the PROGRAM state. The PROGRAM state is responsible for configuring each group of discrete quantities. When the configuration is completed, it jumps to the DONE state. The DONE state is responsible for setting the configuration completion flag and ending the current configuration process.

[0087] In this application, the verification module can perform immediate verification of the configuration results after each configuration is completed, or the verification module can be started separately when you want to start the verification.

[0088] When hardware verification of each group of discrete quantities is required, the host computer first needs to write "1" to the verification start register to indicate the verification trigger. At this time, the FPGA logic will generate a verification trigger signal to the verification state machine. At this time, the protocol starts to start the verification. The FPGA logic will input the current status of each group of discrete quantities into the verification algorithm core in parallel. The verification algorithm core will perform bit-wise XOR operations on the status of each group of discrete quantities and the discrete quantity configuration value maintained in the current discrete quantity lookup table in parallel, and obtain the verification result and store it in the verification result register (if a group of discrete quantities is wrong, the corresponding position in the verification result register will be set to "1"). After the verification is completed, the FPGA logic will write "1" to the verification completion register as the verification completion flag. The flag will be cleared at the beginning of the next verification. When the host computer polls and the flag is set, the protocol ends. The verification state machine is also divided into 4 states, namely IDLE state, CLR state, CHECK state and DONE state. The state transition diagram is shown as follows. Figure 4 As shown in the figure, the IDLE state is responsible for waiting for the verification trigger signal, that is, waiting for the host computer to start the verification. When the verification state machine reads "1" from the verification start register, it changes from the IDLE state to the CLR state; the CLR state is responsible for clearing the verification completion flag generated by the previous verification; when changing from the IDLE state to the CLR state, the value of the verification completion flag in the verification completion register is cleared, and after the clearing is completed, it changes to the CHECK state. The CHECK state is responsible for hardware verification of the current state of each group of discrete quantities; when the verification is completed, it jumps to the DONE state. The DONE state is responsible for setting the verification completion flag and ending this verification.

[0089] Example 2

[0090] like Figure 5As shown, this embodiment provides a method for fast configuration of discrete quantities that supports hardware verification. For the above control system, the host computer performs the following steps:

[0091] S1. Send the discrete quantity working mode and configuration start signal required by each discrete quantity group on the current hardware to the FPGA;

[0092] S2. Polling the configuration completion signal given by the FPGA. The configuration completion signal is a logic level signal written to the configuration completion flag bit after the FPGA searches for the corresponding discrete quantity configuration value in a preset discrete quantity lookup table based on the configuration start signal and the currently required discrete quantity working mode, and configures the discrete state of each discrete quantity group on the hardware (the signal is high when the configuration is complete);

[0093] At this point, the following process is executed in the FPGA:

[0094] S21, writing the discrete quantity working mode into the working mode register defined in the FPGA logic, and writing a logic high level into the configuration start register defined in the FPGA logic according to the configuration start signal to start the configuration;

[0095] S22, when the FPGA reads a logic high level from the configuration start register, clearing the configuration completion signal of the last configuration cached in the configuration completion register defined in the FPGA logic;

[0096] S23, the FPGA searches for the corresponding discrete quantity configuration value in a preset discrete quantity lookup table according to the discrete quantity working mode, and configures the discrete quantity state of each discrete quantity group on the hardware according to the discrete quantity configuration value;

[0097] S24. When the discrete quantity state configuration of each discrete quantity group on the hardware is completed, a configuration completion signal of this configuration is written into the configuration completion register.

[0098] S3. When the configuration completion signal of the FPGA is high, a verification start signal is sent to the FPGA.

[0099] S4. Polling the verification completion signal provided by the FPGA. The verification completion signal is a logic level signal written to the verification completion flag after the FPGA is triggered by the verification start signal to obtain the actual discrete quantity status of each discrete quantity group on the current hardware, and the current actual discrete quantity status and the discrete quantity configuration value in step S2 are input into the verification algorithm for verification to obtain the verification result. The signal is high when the verification is completed.

[0100] At this point, the following process is executed in the FPGA:

[0101] S41, write a logic high level to the verification start register defined in the FPGA logic to start this verification;

[0102] S42, when the FPGA reads the logic high level in the verification start register, it clears the verification completion signal of the previous verification cached in the verification completion register defined in the FPGA logic;

[0103] S43. Obtain the actual discrete quantity status of each discrete quantity group on the current hardware, call the verification algorithm implemented in the FPGA logic to verify the actual discrete quantity status with the discrete quantity configuration value when the hardware is configured according to the discrete quantity lookup table, and write the obtained verification result into the verification result register defined in the FPGA logic;

[0104] S44. After the verification is completed, a verification completion signal of this verification is written into the verification completion register.

[0105] S5. When the verification completion signal is high, the hardware is judged to be in the configured working mode based on the read verification result. The read status of each discrete group on the hardware can be used to judge whether the hardware is indeed in the working mode issued by the host computer, and whether there is a situation where the configuration is successful but the discrete groups on the hardware are not working in the correct working mode.

[0106] When polling the check completion register, if the check completion signal is read, the check result is read from the check result register;

[0107] Based on the verification results, determine whether the actual discrete quantity state on the hardware is consistent with the discrete quantity configuration value configured by the host computer. If they are consistent, determine that each discrete quantity group on the current hardware is working in the discrete quantity working mode specified by the host computer; if they are inconsistent, determine that there is a discrete quantity group on the current hardware that is not working in the discrete quantity working mode specified by the host computer, and find out the discrete quantity group that is not working in the discrete quantity working mode specified by the host computer based on the verification results.

[0108] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Based on the technical essence of the present invention and within the spirit and principles of the present invention, any simple modification, equivalent replacement and improvement of the above embodiment shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for fast configuration of discrete quantities supporting hardware verification, characterized in that: The host computer performs the following steps: S1. Send the discrete quantity working mode and configuration start signal required by each discrete quantity group on the current hardware to the FPGA; S2. Polling the configuration completion signal given by the FPGA. The configuration completion signal is a logic level signal written to the configuration completion flag bit after the FPGA searches for the corresponding discrete quantity configuration value in a preset discrete quantity lookup table based on the configuration start signal and the currently required discrete quantity working mode, and configures the discrete state of each discrete quantity group on the hardware. S3. When the configuration completion signal of the FPGA is high, a verification start signal is sent to the FPGA. S4. Polling the FPGA for a verification completion signal, wherein the verification completion signal is a logic level signal written to the verification completion flag after the FPGA is triggered by the verification start signal to obtain the actual discrete quantity status of each discrete quantity group on the current hardware, and the current actual discrete quantity status and the discrete quantity configuration value found in step S2 are input into the verification algorithm for verification to obtain the verification result; S5. When the check completion signal is high level after being polled, it is determined whether each discrete quantity group on the hardware is in the configured working mode according to the read check result.

2. A method for fast discrete quantity configuration supporting hardware verification according to claim 1, characterized in that: In step S2, the specific process of obtaining the configuration completion signal in the FPGA is as follows: S21, writing the discrete quantity working mode into the working mode register defined in the FPGA logic, and writing a logic high level into the configuration start register defined in the FPGA logic according to the configuration start signal to start the configuration; S22, when the FPGA reads a logic high level from the configuration start register, clearing the configuration completion signal of the last configuration cached in the configuration completion register defined in the FPGA logic; S23, the FPGA searches for the corresponding discrete quantity configuration value in a preset discrete quantity lookup table according to the discrete quantity working mode, and configures the discrete quantity state of each discrete quantity group on the hardware according to the discrete quantity configuration value; S24. When the discrete quantity state configuration of each discrete quantity group on the hardware is completed, a configuration completion signal of this configuration is written into the configuration completion register.

3. The method for fast discrete quantity configuration supporting hardware verification according to claim 1, wherein: The specific process of obtaining the verification completion signal in FPGA is as follows: S41, write a logic high level to the verification start register defined in the FPGA logic to start this verification; S42, when the FPGA reads the logic high level in the verification start register, it clears the verification completion signal of the previous verification cached in the verification completion register defined in the FPGA logic; S43. Obtain the actual discrete quantity status of each discrete quantity group on the current hardware, call the verification algorithm implemented in the FPGA logic to verify the actual discrete quantity status with the discrete quantity configuration value when the hardware is configured according to the discrete quantity lookup table, and write the obtained verification result into the verification result register defined in the FPGA logic; S44. After the verification is completed, a verification completion signal of this verification is written into the verification completion register.

4. A method for fast discrete quantity configuration supporting hardware verification according to claim 3, characterized in that: In step S43, the check algorithm adopts bitwise XOR check, parity check or CRC check. The bitwise XOR check is: performing bitwise XOR operation on the actual discrete quantity state on the hardware and the discrete quantity configuration value configured by the host computer in parallel.

5. The method for fast discrete quantity configuration supporting hardware verification according to claim 1, characterized in that: The preset discrete quantity lookup table is a truth table, and the discrete quantity lookup table solidifies the configuration values ​​required by each group of discrete quantities on the hardware in various working modes.

6. The method for fast discrete quantity configuration supporting hardware verification according to claim 1, wherein: In step S5, when polling the verification completion register, if a verification completion signal is read, the verification result is read from the verification result register; Based on the verification results, determine whether the actual discrete quantity state on the hardware is consistent with the discrete quantity configuration value configured by the host computer. If they are consistent, determine that each discrete quantity group on the current hardware is working in the discrete quantity working mode specified by the host computer; if they are inconsistent, determine that there is a discrete quantity group on the current hardware that is not working in the discrete quantity working mode specified by the host computer, and find out the discrete quantity group that is not working in the discrete quantity working mode specified by the host computer based on the verification results.

7. A control system that supports rapid configuration of discrete quantities with hardware verification, characterized in that: Including FPGA and host computer, FPGA communicates with the host computer through its internal logic bus, where The host computer is used to send the discrete quantity working mode and configuration start signal required by each discrete quantity group to the FPGA. It is also used to poll the configuration completion signal given by the FPGA. When the configuration completion signal of the FPGA is high, a verification start signal is sent to the FPGA. It is also used to poll the verification completion signal given by FPGA. When the verification completion signal is high, it is judged whether each discrete quantity group on the hardware is in the configured working mode according to the read verification result. FPGA, used to look up the corresponding discrete quantity configuration value in the preset discrete quantity lookup table according to the configuration start signal and the currently required discrete quantity working mode, and after configuring the discrete state of each discrete quantity group on the hardware, write the logic level signal to the configuration completion flag bit; It is also used to trigger the FPGA to obtain the actual discrete quantity status of each discrete quantity group on the current hardware according to the verification start signal, input the current actual discrete quantity status and the discrete quantity configuration value when the hardware is configured according to the discrete quantity lookup table into the verification algorithm for verification, and then write the logic level signal to the verification completion flag after obtaining the verification result.

8. A control system for discrete quantity rapid configuration supporting hardware verification according to claim 7, characterized in that: FPGA includes configuration module, configuration start register, working mode register and configuration completion register, among which, A configuration module is used to write the discrete quantity working mode into the working mode register defined in the FPGA logic, and write a logic high level into the configuration start register defined in the FPGA logic to start the configuration according to the configuration start signal; When a logic high level is read from the configuration start register, the configuration completion signal of the last configuration cached in the configuration completion register defined in the FPGA logic is cleared; According to the discrete quantity working mode, the corresponding discrete quantity configuration value is searched in the preset discrete quantity lookup table, and the discrete quantity status of each discrete quantity group on the hardware is configured according to the discrete quantity configuration value; When the discrete quantity state configuration of each discrete quantity group on the hardware is completed, the configuration completion signal of this configuration is written into the configuration completion register.

9. The control system for discrete quantity rapid configuration supporting hardware verification according to claim 7, characterized in that: FPGA also includes a verification module, a verification start register, a verification completion register and a verification result register, among which, The verification module is used to write a logic high level to the verification start register defined in the FPGA logic to start this verification; When a logic high level is read in the verification start register, the verification completion signal of the previous verification cached in the verification completion register defined in the FPGA logic is cleared; Obtain the actual discrete quantity status of each discrete quantity group on the current hardware, call the verification algorithm implemented in the FPGA logic to verify the actual discrete quantity status with the discrete quantity configuration value when the hardware is configured according to the discrete quantity lookup table, and write the verification result into the verification result register defined in the FPGA logic; When the verification is completed, the verification completion signal of this verification is written into the verification completion register.

10. The control system for discrete quantity rapid configuration supporting hardware verification according to claim 7, characterized in that: The check algorithm adopts bitwise XOR check, parity check or CRC check. The bitwise XOR check is: performing bitwise XOR operation on the actual discrete quantity state on the hardware and the discrete quantity configuration value configured by the host computer in parallel.

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