Bandgap reference voltage source circuit

Abstract

The application provides a band gap reference voltage source circuit, which comprises a starting circuit, a core circuit and a current compensation circuit. The core circuit comprises a first NMOS transistor, first and second transistors, a first operational amplifier, first to third resistors and a compensation resistor. The drain of the first NMOS transistor is connected to a power supply, the source is connected to the first end of the first resistor, the base of the first transistor and the collector of the second transistor, and the gate is connected to the output end of the first operational amplifier. The second end of the first resistor is connected to the collector of the first transistor and the base of the second transistor, and the first end of the first resistor serves as the output end of the core circuit. The emitter of the first transistor is connected to the first end of the second resistor and the same input end of the first operational amplifier. The emitter of the second transistor is connected to the first end of the third resistor and the opposite input end of the first operational amplifier. The second end of the second resistor and the second end of the third resistor are respectively connected to the first end of the compensation resistor and the output end of the current compensation circuit, and the second end of the compensation resistor is grounded.

Description

Bandgap reference voltage source circuit Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a bandgap reference voltage source circuit. Background Technology

[0002] As is well known, temperature affects the performance of circuits; therefore, a circuit that outputs a reference voltage that is unaffected by temperature changes is particularly important.

[0003] The bandgap reference voltage has been extensively studied since its invention. Its principle involves weighted summation of a voltage with a negative temperature coefficient and a voltage with a positive temperature coefficient to obtain a voltage with an approximate zero temperature coefficient. A negative temperature coefficient voltage is typically achieved using the base-emitter voltage VBJT of a bipolar junction transistor (BJT) whose collector is biased with a positive temperature coefficient current. be To achieve a positive temperature coefficient voltage, the voltage difference ΔV between the base and emitter of a transistor with its collectors biased at different positive temperature coefficient current densities is typically used. be Expand the first-order temperature term of the negative temperature coefficient voltage by a certain proportion.

[0004] The early effect, also known as the base width modulation effect, refers to the change in the effective base width when the collector and emitter voltages of a transistor change, resulting in a nonlinear change in the relationship between the collector current and the collector and emitter voltages. This effect affects the transistor's current amplification factor and output characteristics, thus impacting the overall circuit performance. The nonlinear term of the base-emitter voltage difference changing with temperature is the main cause of temperature drift degradation. Summary of the Invention

[0005] The purpose of this application is to provide a bandgap reference voltage source circuit that can effectively reduce the temperature drift of the reference voltage.

[0006] One aspect of this application provides a bandgap reference voltage source circuit. The bandgap reference voltage source circuit includes a startup circuit, a bandgap reference core circuit, and a current compensation circuit. The startup circuit is used to enable the bandgap reference core circuit to escape metastability. The bandgap reference core circuit is used to generate a reference voltage. The current compensation circuit is used to compensate for the temperature drift of the reference voltage. The bandgap reference core circuit includes a first NMOS transistor, a first transistor, a second transistor, a first operational amplifier, a first resistor, a second resistor, a third resistor, and a compensation resistor. The drain of the first NMOS transistor is connected to the power supply voltage. The source of the first NMOS transistor is connected to the first terminal of the first resistor, the base of the first transistor, and the collector of the second transistor. The gate of the NMOS transistor is connected to the output of the first operational amplifier; the second end of the first resistor is connected to the collector of the first transistor and the base of the second transistor, and the first end of the first resistor serves as the output of the bandgap reference core circuit; the emitter of the first transistor is connected to the first end of the second resistor and the non-inverting input of the first operational amplifier; the emitter of the second transistor is connected to the first end of the third resistor and the inverting input of the first operational amplifier; the second ends of the second resistor and the second ends of the third resistor are connected to the first end of the compensation resistor and the output of the current compensation circuit, respectively, and the second end of the compensation resistor is grounded.

[0007] Furthermore, the voltage difference across the first resistor is equal to the difference between the base and emitter voltages of the first transistor and the base and emitter voltages of the second transistor.

[0008] Furthermore, the second resistor and the third resistor have the same resistance value.

[0009] Furthermore, the first-order temperature drift of the reference voltage generated by the bandgap reference core circuit is adjusted by adjusting the ratio of the second resistor to the first resistor; the nonlinear temperature drift of the reference voltage is adjusted by adjusting the compensation current output from the output terminal of the current compensation circuit and the resistance value of the compensation resistor.

[0010] Furthermore, the startup circuit includes a fourth resistor, a fifth resistor, a sixth resistor, a first PMOS transistor, a third transistor, and a startup transistor. The first terminal of the fourth resistor is connected to the emitter of the third transistor, and the second terminal of the fourth resistor is grounded. The first terminals of the fifth and sixth resistors, and the source of the first PMOS transistor are connected to a power supply voltage. The second terminal of the fifth resistor is connected to the collector and base of the third transistor. The gate of the startup transistor is connected to the base of the third transistor, and the drain of the startup transistor is connected to the second terminal of the sixth resistor and the gate of the first PMOS transistor. The source of the startup transistor is connected to the output terminal of the bandgap reference core circuit. The drain of the first PMOS transistor is connected to the gate of the first NMOS transistor.

[0011] Furthermore, the current compensation circuit includes a positive temperature coefficient current generation circuit, a low dropout linear regulator circuit, and a current combiner circuit. The positive temperature coefficient current generation circuit is used to generate a positive temperature coefficient current; the low dropout linear regulator circuit is used to generate a zero temperature coefficient current, a first zero temperature coefficient voltage, and a second zero temperature coefficient voltage; the current combiner circuit is used to generate a segmented compensation current based on the positive temperature coefficient voltage, the first zero temperature coefficient voltage, the second zero temperature coefficient voltage, the positive temperature coefficient current, and the zero temperature coefficient current output from the first terminal of the third resistor.

[0012] Further, the current combiner circuit includes a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first switch, a second switch, a third switch, a fourth switch, and a second compensation resistor. The sources of the second and third PMOS transistors are connected to the positive temperature coefficient current; the sources of the fourth and fifth PMOS transistors are connected to the zero temperature coefficient current; the gate of the second PMOS transistor is connected to the first zero temperature coefficient voltage; the gates of the third and fourth PMOS transistors are connected to the positive temperature coefficient voltage; and the gate of the fifth PMOS transistor is connected to the second zero temperature coefficient voltage. Currents flowing from the drains of the second, third, fourth, and fifth PMOS transistors are selected by the first, second, third, and fourth switches to flow into the output terminal of the current compensation circuit or into the first terminal of the second compensation resistor; the second terminal of the second compensation resistor is grounded.

[0013] Furthermore, the resistance value of the second compensation resistor is equal to the resistance value of the compensation resistor in the bandgap reference core circuit.

[0014] Furthermore, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor have the same dimensions.

[0015] Furthermore, the second zero temperature coefficient voltage is greater than the first zero temperature coefficient voltage.

[0016] Furthermore, when the temperature drift curve of the reference voltage is convex upward, the first switch and the third switch are connected to the first end of the second compensation resistor; the second switch and the fourth switch are connected to the first end of the compensation resistor.

[0017] Furthermore, when the temperature drift curve of the reference voltage is concave, the first switch and the third switch are connected to the first terminal of the compensation resistor; the second switch and the fourth switch are connected to the first terminal of the second compensation resistor.

[0018] Furthermore, when the reference voltage does not require compensation, the first switch, the second switch, the third switch, and the fourth switch are all connected to the first end of the second compensation resistor.

[0019] Furthermore, the low-dropout linear regulator circuit includes a second operational amplifier, a second NMOS transistor, and a resistor divider branch. The non-inverting input of the second operational amplifier is connected to the output of the bandgap reference core circuit. The inverting input of the second operational amplifier is connected to one end of the resistor divider branch and the source of the second NMOS transistor. The output of the second operational amplifier is connected to the gate of the second NMOS transistor. The other end of the resistor divider branch is grounded. The resistor divider branch has a first voltage divider output and a second voltage divider output. The first voltage divider output is used to output the first zero-temperature coefficient voltage, and the second voltage divider output is used to output the second zero-temperature coefficient voltage. The drain of the second NMOS transistor serves as the output of the zero-temperature coefficient current.

[0020] Furthermore, the low-dropout linear regulator circuit also includes a sixth PMOS transistor, a seventh PMOS transistor, and an eleventh resistor. The second terminal of the eleventh resistor is connected to the drain of the second NMOS transistor, and the first terminal of the eleventh resistor is connected to the drain of the sixth PMOS transistor and the gate of the seventh PMOS transistor. The gate of the sixth PMOS transistor is connected to the second terminal of the eleventh resistor, and the source of the sixth PMOS transistor is connected to the drain of the seventh PMOS transistor. The source of the seventh PMOS transistor is connected to the power supply voltage.

[0021] Furthermore, the positive temperature coefficient current generating circuit includes a fourth transistor and a twelfth resistor, wherein the base of the fourth transistor is connected to the output terminal of the bandgap reference core circuit, the emitter of the fourth transistor is connected to the first terminal of the twelfth resistor, the collector of the fourth transistor serves as the output terminal of the positive temperature coefficient current generating circuit, and the second terminal of the twelfth resistor is grounded.

[0022] Furthermore, the positive temperature coefficient current generation circuit also includes an eighth PMOS transistor, a ninth PMOS transistor, and a thirteenth resistor. The first end of the thirteenth resistor is connected to the drain of the eighth PMOS transistor and the gate of the ninth PMOS transistor; the second end of the thirteenth resistor is connected to the collector of the fourth transistor and the gate of the eighth PMOS transistor; the source of the eighth PMOS transistor and the drain of the ninth PMOS transistor are connected, and the source of the ninth PMOS transistor is connected to the power supply voltage.

[0023] Furthermore, the current combiner circuit also includes a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, and a thirteenth PMOS transistor. The gates of the tenth and eleventh PMOS transistors are respectively connected to the gates of the ninth and eighth PMOS transistors. The drain of the tenth PMOS transistor is connected to the source of the eleventh PMOS transistor. The source of the tenth PMOS transistor is connected to a power supply voltage. The drain of the eleventh PMOS transistor outputs the positive temperature coefficient current. The gates of the twelfth and thirteenth PMOS transistors are respectively connected to the gates of the seventh and sixth PMOS transistors. The drain of the twelfth PMOS transistor is connected to the source of the thirteenth PMOS transistor. The source of the twelfth PMOS transistor is connected to a power supply voltage. The drain of the thirteenth PMOS transistor outputs the zero temperature coefficient current.

[0024] The bandgap reference voltage source circuit of one or more embodiments of this application can achieve at least the following beneficial technical effects:

[0025] (1) In the bandgap reference core circuit of this application, the base current of the first transistor and the second transistor does not affect the collector current flowing through them. The current required by the base can be extracted separately from the path of the first NMOS transistor and the power supply voltage, without the need to set up an additional base current compensation circuit.

[0026] (2) In the bandgap reference core circuit of this application, the collector and base voltages of the first transistor and the second transistor maintain a fixed voltage difference over a wide temperature range, which reduces the impact of Earlly effect (base width modulation effect) on the accuracy of the positive temperature coefficient current.

[0027] (3) In the core circuit of the bandgap reference in this application, by adjusting the ratio of the first resistor and the second resistor, as well as the compensation current output by the current compensation circuit and the resistance value of the compensation resistor, the output reference voltage can have an extremely low temperature coefficient.

[0028] (4) In the bandgap reference core circuit of this application, the first operational amplifier, the first NMOS transistor, the first resistor and the second transistor form a negative feedback loop, which effectively suppresses the influence of other interference sources on the output reference voltage, so that the bandgap reference voltage source circuit has good stability.

[0029] (5) The current combiner circuit of this application can realize three functions—compensation for reference voltage with an upward convex shape, compensation for reference voltage with a downward concave shape, and no compensation for reference voltage—through different closing combinations of the first switch, the second switch, the third switch and the fourth switch. Attached Figure Description

[0030] Figure 1 is a schematic diagram of the structure of a bandgap reference voltage source circuit according to an embodiment of this application. Detailed Implementation

[0031] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.

[0032] The bandgap reference voltage source circuits of various embodiments of this application will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementations can be combined with each other.

[0033] Figure 1 illustrates a schematic diagram of a bandgap reference voltage source circuit 100 according to an embodiment of this application. As shown in Figure 1, the bandgap reference voltage source circuit 100 according to an embodiment of this application includes a bandgap reference core circuit 110, a startup circuit 120, and a current compensation circuit. The startup circuit 120 is used to enable the bandgap reference core circuit 110 to escape metastability; the bandgap reference core circuit 110 is used to generate a reference voltage Vref; the current compensation circuit is used to compensate for the temperature drift of the reference voltage Vref, thereby reducing the temperature drift of the reference voltage Vref output by the bandgap reference core circuit 110.

[0034] In some embodiments, the bandgap reference core circuit 110 of this application includes a first NMOS transistor MN1, a first transistor Q1, a second transistor Q2, a first operational amplifier Opma1, a first resistor R1, a second resistor R2, a third resistor R3, and a compensation resistor R. comp .

[0035] The drain of the first NMOS transistor MN1 is connected to the power supply voltage. The source of the first NMOS transistor MN1 is connected to the first terminal of the first resistor R1, the base of the first transistor Q1, and the collector of the second transistor Q2. The gate of the first NMOS transistor MN1 is connected to the output terminal of the first operational amplifier Opma1. The second terminal of the first resistor R1 is connected to the collector of the first transistor Q1 and the base of the second transistor Q2, and the first terminal of the first resistor R1 serves as the output terminal of the bandgap reference core circuit 110. The emitter of the first transistor Q1 is connected to the first terminal of the second resistor R2 and the non-inverting input terminal of the first operational amplifier Opma1. The emitter of the second transistor Q2 is connected to the first terminal of the third resistor R3 and the inverting input terminal of the first operational amplifier Opma1. The second terminals of the second resistor R2 and the second terminals of the third resistor R3 are connected to the compensation resistor R1, respectively. comp The first terminal is connected to the output terminal of the current compensation circuit, and the compensation resistor R comp The second terminal is grounded.

[0036] Optionally, the resistance values ​​of the second resistor R2 and the third resistor R3 are the same.

[0037] In the bandgap reference core circuit 110, the first operational amplifier Opma1, the first NMOS transistor MN1, and the first transistor Q1 form a positive feedback loop; the first operational amplifier Opma1, the first NMOS transistor MN1, the first resistor R1, and the second transistor Q2 form a negative feedback loop. By appropriately setting the value of the first resistor R1 to ensure that the gain of the negative feedback loop is greater than the gain of the positive feedback loop, the overall circuit achieves negative feedback, thereby enabling the bandgap reference core circuit 110 to maintain a stable static operating point.

[0038] The voltage difference across the first resistor R1 is equal to the difference ΔV between the base and emitter voltages of the first transistor Q1 and the base and emitter voltages of the second transistor Q2. be .

[0039] The difference ΔV between the base and emitter voltages of transistor Q1 and transistor Q2 be for:

[0040]

[0041] Among them, V be1 V be2These are the base-emitter voltages of transistors Q1 and Q2, respectively; k is the Boltzmann constant; T is the absolute temperature; q is the charge of a single electron; and I... C1 I C2 A1 and A2 are the collector currents of the first transistor Q1 and the second transistor Q2, respectively, and the emitter cross-sectional areas of the first transistor Q1 and the second transistor Q2, respectively.

[0042] Under the gain effect of the first operational amplifier Opma1, the voltages at the first terminals of the second resistor R2 and the third resistor R3 are approximately equal. Therefore, the current I flowing through the first resistor R1 is... R1 equal:

[0043]

[0044] Ignoring the base currents of the first transistor Q1 and the second transistor Q2, the emitter currents flowing through the first transistor Q1 and the second transistor Q2 are approximately equal to the current flowing through the first resistor R1. The voltage across the second resistor R2 generated by this current is calculated as follows:

[0045] V R2 =I R1 *R2

[0046] The current flows through the compensation resistor R. comp The voltage V1 on it is calculated as follows:

[0047] V1 = 2 * I R1 *R comp

[0048] Furthermore, the compensation current I generated by the current compensation circuit comp Flow through compensation resistor R comp Generate compensation voltage V comp The compensation voltage V comp The calculation is as follows:

[0049] V comp =I comp *R comp

[0050] Furthermore, the formula for obtaining the reference voltage Vref generated by the bandgap reference core circuit 110 is as follows:

[0051]

[0052] Among them, V be1 These are the base and emitter voltages of the first transistor Q1, and their variation with temperature T is expressed by the following formula:

[0053]

[0054] Among them, V G0 This is the bandgap voltage of silicon, T0 is the reference temperature point for the fitted curve, and V... be0 It is the base-emitter voltage of the first transistor Q1 at temperature T0, and η is a process-related parameter, which is generally between 3 and 4.

[0055] Furthermore, the detailed calculation formula for the reference voltage Vref is shown below:

[0056]

[0057] As can be seen from the formula above, the first-order temperature drift of the reference voltage Vref generated by the bandgap reference core circuit 110 can be adjusted by adjusting the ratio of the second resistor R2 to the first resistor R1, that is, by using the positive first-order term that causes the temperature drift. To offset the negative first-order term that causes temperature drift

[0058] In addition, the compensation current I output by introducing a current compensation circuit comp The compensation current I output by the current compensation circuit can be adjusted. comp and properly set the compensation resistor R comp The nonlinear temperature drift of the reference voltage Vref is adjusted by the resistance value of I. comp *R comp This term is used to reduce the temperature nonlinearity of the first transistor Q1 at full temperature. The resulting error.

[0059] The bandgap reference core circuit 110 of this application can have the following advantages:

[0060] (1) The base current of the first transistor Q1 and the second transistor Q2 does not affect the collector current flowing through them. The current required by the base can be extracted separately from the path of the first NMOS transistor MN1 and the power supply voltage, without the need to set up an additional base current compensation circuit.

[0061] (2) The collector and base voltages of the first transistor Q1 and the second transistor Q2 maintain a fixed voltage difference over a wide temperature range, reducing the Earlly effect (base width modulation effect) on the positive temperature coefficient current I. ptat The impact on accuracy;

[0062] (3) By adjusting the ratio of the first resistor R1 and the second resistor R2, and the compensation current I output by the current compensation circuit... comp and compensation resistor R compThe resistance value can ensure that the output reference voltage Vref has an extremely low temperature coefficient;

[0063] (4) The first operational amplifier Opma1, together with the first NMOS transistor MN1, the first resistor R1 and the second transistor Q2, form a negative feedback loop, which effectively suppresses the influence of other interference sources on the output reference voltage Vref, so that the bandgap reference voltage source circuit 100 has good stability.

[0064] Referring again to Figure 1, the startup circuit 120 includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first PMOS transistor MP1, a third transistor Q3, and a startup transistor Mstart. The startup transistor Mstart is an NMOS transistor.

[0065] The first end of the fourth resistor R4 is connected to the emitter of the third transistor Q3, and the second end of the fourth resistor R4 is grounded; the first end of the fifth resistor R5, the first end of the sixth resistor R6, and the source of the first PMOS transistor MP1 are connected to the power supply voltage, and the second end of the fifth resistor R5 is connected to the collector and base of the third transistor Q3; the gate of the startup transistor Mstart is connected to the base of the third transistor Q3, the drain of the startup transistor Mstart is connected to the second end of the sixth resistor R6 and the gate of the first PMOS transistor MP1, and the source of the startup transistor Mstart is connected to the output of the bandgap reference core circuit 110; the drain of the first PMOS transistor MP1 is connected to the gate of the first NMOS transistor MN1.

[0066] The startup circuit 120 of this application is a dual startup circuit. The dual startup circuit can ensure that the core circuit works in a normal state rather than a metastable state. At the same time, after the bandgap reference core circuit 110 of this application is working normally, the startup transistor Mstart and the first PMOS transistor MP1 in the startup circuit 120 will be turned off.

[0067] In operation, after the circuit is powered on, the branch containing the fifth resistor R5, the third transistor Q3, and the fourth resistor R4 is connected in series to divide the power supply voltage, for example, 1.8V, generating approximately 1.25V at the base of the third transistor Q3. The source of the startup transistor Mstart is connected to the reference voltage Vref. When the reference voltage Vref is 0 or the gate-source voltage of the startup transistor Mstart is greater than the threshold voltage of the startup transistor Mstart, the startup transistor Mstart is turned on. At this time, current is injected into the base and collector of the first transistor Q1 and the second transistor Q2 that generate the reference voltage Vref. Simultaneously, by appropriately setting the resistance value of the sixth resistor R6, the gate voltage of the first PMOS transistor MP1 is pulled low, and the first PMOS transistor MP1 is turned on, causing its source voltage to be pulled high, thereby turning on the first NMOS transistor MN1. At the same time, current is injected into the base and collector of the first transistor Q1 and the second transistor Q2 that generate the reference voltage Vref. The bandgap reference core circuit 110 establishes a static operating point, achieving the startup effect of dual-path current injection. When the reference voltage Vref output by the bandgap reference core circuit 110 reaches 1.25V, the startup transistor Mstart is turned off, reducing the current injected into the base and collector of the first transistor Q1 and the second transistor Q2. Simultaneously, the gate voltage of the first PMOS transistor MP1 is pulled high, turning off MP1 and no longer affecting the gate voltage of the first NMOS transistor MN1, thus ensuring the normal operation of the bandgap reference core circuit 110. Therefore, the startup circuit 120 of this application ensures that the bandgap reference core circuit 110 operates in a normal state rather than a metastable state. Furthermore, after the bandgap reference core circuit 110 is operating normally, the startup circuit 120 will turn off to prevent it from increasing the circuit's power consumption.

[0068] Referring again to Figure 1, in some embodiments, the current compensation circuit of this application includes a positive temperature coefficient current generation circuit 130, a low-dropout linear regulator circuit 140, and a current combiner circuit 150. The positive temperature coefficient current generation circuit 130 is used to generate a positive temperature coefficient current I. ptat The low-dropout linear regulator circuit 140 is used to generate a zero-temperature coefficient current I. ztat First zero temperature coefficient voltage V ztat1 Second zero temperature coefficient voltage V ztat2 The current combiner circuit 150 is used to output the positive temperature coefficient voltage V based on the first terminal of the third resistor R3. ptat First zero temperature coefficient voltage V ztat1 Second zero temperature coefficient voltage V ztat2 Positive temperature coefficient current I ptat and zero temperature coefficient current I ztat To generate segmented compensation current I comp .

[0069] In some embodiments, the low dropout linear regulator circuit 140 of this application includes a second operational amplifier Opma2, a second NMOS transistor MN2, and a resistor divider branch 142.

[0070] The non-inverting input of the second operational amplifier Opma2 is connected to the output of the bandgap reference core circuit 110. The inverting input of the second operational amplifier Opma2 is connected to one end of the resistor divider branch 142 and the source of the second NMOS transistor MN2. The output of the second operational amplifier Opma2 is connected to the gate of the second NMOS transistor MN2. The other end of the resistor divider branch 142 is grounded. The resistor divider branch 142 has a first voltage divider output terminal and a second voltage divider output terminal. The first voltage divider output terminal is used to output the first zero temperature coefficient voltage V. ztat1 The second voltage divider output terminal is used to output the second zero temperature coefficient voltage V. ztat2 The drain of the second NMOS transistor MN2 serves as the output terminal of the low-dropout linear regulator circuit 140. Optionally, the second zero-temperature coefficient voltage V... ztat2 Voltage V greater than the first zero temperature coefficient ztat1 .

[0071] In one embodiment of this application, the resistor divider branch 142 may include a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10. The first terminal of the seventh resistor R7 is connected to the second terminal of the eighth resistor R8, and the second terminal of the seventh resistor R7 is grounded. The first terminal of the eighth resistor R8 is connected to the second terminal of the ninth resistor R9. The first terminal of the ninth resistor R9 is connected to the second terminal of the tenth resistor R10. The first terminal of the tenth resistor R10 is connected to the inverting input of the second operational amplifier Opma2 and the source of the second NMOS transistor MN2. The first terminal of the seventh resistor R7 serves as the first voltage divider output terminal, used to output a first zero-temperature coefficient voltage V. ztat1 The first terminal of the eighth resistor R8 serves as the second voltage divider output terminal, used to output the second zero-temperature coefficient voltage V. ztat2 .

[0072] It is understood that the resistor divider branch 142 shown in Figure 1, including the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, and the tenth resistor R10, is only a schematic example of the resistor divider branch 142 of this application. However, the resistor divider branch 142 of this application is not limited to that shown in Figure 1, and may include other numbers of voltage divider resistors as needed. In addition, the inverting input terminal of the second operational amplifier Opma2 is not limited to being connected to the first terminal of the tenth resistor R10, but may also be connected to the first terminal of the ninth resistor R9, etc., and this application does not impose any restrictions on this.

[0073] A reference voltage Vref of 1.25V is input to the non-inverting input of the second operational amplifier Opma2. The negative feedback loop formed by the second NMOS transistor MN2 makes the voltage at the non-inverting input of the second operational amplifier Opma2 approximately equal to the 1.25V reference voltage Vref. Therefore, the current flowing through the second NMOS transistor MN2 is a zero-temperature coefficient current I. ztat With the resistor divider branch 142 including the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, and the tenth resistor R10, the zero temperature coefficient current I... ztat The calculation is as follows:

[0074]

[0075] Furthermore, the 1.25V reference voltage Vref is divided by resistors R7 (seventh resistor), R8 (eighth resistor), R9 (ninth resistor), and R10 (tenth resistor) to generate the first zero-temperature coefficient voltage V. ztat1 and the second zero temperature coefficient voltage V ztat2 .

[0076] In some embodiments, the low dropout linear regulator circuit 140 of this application may further include a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, and an eleventh resistor R11.

[0077] The second end of the eleventh resistor R11 is connected to the drain of the second NMOS transistor MN2, and the first end of the eleventh resistor R11 is connected to the drain of the sixth PMOS transistor MP6 and the gate of the seventh PMOS transistor MP7. The gate of the sixth PMOS transistor MP6 is connected to the second end of the eleventh resistor R11, and the source of the sixth PMOS transistor MP6 is connected to the drain of the seventh PMOS transistor MP7. The source of the seventh PMOS transistor MP7 is connected to the power supply voltage.

[0078] In some embodiments, the positive temperature coefficient current generation circuit 130 of this application includes a fourth transistor Q4 and a twelfth resistor R12.

[0079] The base of the fourth transistor Q4 is connected to the output terminal of the bandgap reference core circuit 110, the emitter of the fourth transistor Q4 is connected to the first terminal of the twelfth resistor R12, the collector of the fourth transistor Q4 serves as the output terminal of the positive temperature coefficient current generation circuit 130, and the second terminal of the twelfth resistor R12 is grounded.

[0080] The 1.25V reference voltage Vref is used as the base voltage of the fourth transistor Q4, and the positive temperature coefficient current I flows through the twelfth resistor R12. ptat The calculation is as follows:

[0081]

[0082] Among them, V be4 It is the base-emitter voltage of the fourth transistor Q4.

[0083] In some embodiments, the positive temperature coefficient current generation circuit 130 of this application may further include an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, and a thirteenth resistor R13.

[0084] The first end of the thirteenth resistor R13 is connected to the drain of the eighth PMOS transistor MP8 and the gate of the ninth PMOS transistor MP9; the second end of the thirteenth resistor R13 is connected to the collector of the fourth transistor Q4 and the gate of the eighth PMOS transistor MP8; the source of the eighth PMOS transistor MP8 and the drain of the ninth PMOS transistor MP9 are connected, and the source of the ninth PMOS transistor MP9 is connected to the power supply voltage.

[0085] Referring again to Figure 1, in some embodiments, the current combiner circuit 150 of this application includes a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, and a second compensation resistor R. comp2 .

[0086] The source of the second PMOS transistor MP2 and the source of the third PMOS transistor MP3 are connected to a positive temperature coefficient current I. ptat The source of the fourth PMOS transistor MP4 and the source of the fifth PMOS transistor MP5 are connected to a zero-temperature coefficient current I. ztat The gate of the second PMOS transistor MP2 is connected to a first zero temperature coefficient voltage V. ztat1 The gates of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to a positive temperature coefficient voltage V. ptat The gate of the fifth PMOS transistor MP5 is connected to the second zero temperature coefficient voltage V. ztat2 The currents flowing from the drains of the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 are respectively selected by the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 to flow into the output terminal of the current compensation circuit or into the second compensation resistor R. comp2 The first terminal; the second compensation resistor R comp2 The second terminal is grounded.

[0087] Optionally, the second compensation resistor R comp2 The resistance value and the compensation resistor R in the bandgap reference core circuit 110 comp The resistance values ​​are equal.

[0088] The current combiner circuit 150 of this application can achieve three functions—compensation for reference voltage Vref with an upwardly convex temperature drift curve, compensation for reference voltage Vref with a downwardly concave temperature drift curve, and no compensation for reference voltage Vref—through different combinations of closing the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4.

[0089] In some embodiments, the current combiner circuit 150 of this application may further include a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, and a thirteenth PMOS transistor MP13.

[0090] The tenth PMOS transistor MP10 and the eleventh PMOS transistor MP11, together with the ninth PMOS transistor MP9 and the eighth PMOS transistor MP8, form the first current mirror. Specifically, the gates of the tenth PMOS transistor MP10 and the eleventh PMOS transistor MP11 are connected to the gates of the ninth PMOS transistor MP9 and the eighth PMOS transistor MP8, respectively; the drain of the tenth PMOS transistor MP10 is connected to the source of the eleventh PMOS transistor MP11; the source of the tenth PMOS transistor MP10 is connected to the power supply voltage; and the drain of the eleventh PMOS transistor MP11 outputs a positive temperature coefficient current I. ptat Therefore, through the first current mirror, the positive temperature coefficient current I flowing through the ninth PMOS transistor MP9 and the eighth PMOS transistor MP8 is... ptat The current combiner circuit is given 150.

[0091] The twelfth PMOS transistor MP12 and the thirteenth PMOS transistor MP13, together with the seventh PMOS transistor MP7 and the sixth PMOS transistor MP6, form the second current mirror. The gates of the twelfth PMOS transistor MP12 and the thirteenth PMOS transistor MP13 are connected to the gates of the seventh PMOS transistor MP7 and the sixth PMOS transistor MP6, respectively; the drain of the twelfth PMOS transistor MP12 is connected to the source of the thirteenth PMOS transistor MP13; the source of the twelfth PMOS transistor MP12 is connected to the power supply voltage; and the drain of the thirteenth PMOS transistor MP13 outputs a zero-temperature coefficient current I. ztat Therefore, through the second current mirror, the zero-temperature coefficient current I flowing through the seventh PMOS transistor MP7 and the sixth PMOS transistor MP6 is... ztat The current combiner circuit is given 150.

[0092] The uncompensated reference voltage Vref, although its first temperature coefficient can be compensated by a positive temperature coefficient voltage V. ptat Precise cancellation, but due to the base and emitter voltage V of the first transistor Q1 be1The presence of a negative temperature coefficient voltage's temperature nonlinearity can cause the voltage temperature drift to exhibit either an upward convexity or a downward convexity. The current compensation circuit provided in this application can generate a compensation current I... comp and properly setting the compensation resistor R comp By adjusting the resistance value, piecewise current compensation can be performed on the temperature nonlinearity term. This can transform the temperature drift curve of the reference voltage Vref from an upwardly convex voltage to a voltage similar to an M-shape, or from a downwardly concave voltage to a voltage similar to a W-shape.

[0093] In one embodiment, the following description will take the compensation of the convex reference voltage Vref as an example.

[0094] Optionally, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 have the same dimensions. Each of the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 has a width-to-length ratio (W / L) characteristic of MOS transistors.

[0095] The positive temperature coefficient voltage V at the first terminal of the third resistor R3 ptat The voltage V from the bandgap reference core circuit 110 increases with increasing temperature; the first zero temperature coefficient voltage V at the first terminal of the seventh resistor R7. ztat1 The second zero temperature coefficient voltage V at the first terminal of the eighth resistor R8 ztat2 It is approximately unchanging with temperature within the range of -40℃ to 125℃; the first zero temperature coefficient voltage V is appropriately set. ztat1 Second zero temperature coefficient voltage V ztat2 The voltage value changes with the positive temperature coefficient voltage V ptat As the voltage gradually increases, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 transition from being on to being off, and the source voltages of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 gradually increase. Therefore, the gate-source voltage V of the second PMOS transistor MP2 and the fifth PMOS transistor MP5... sg,MP2 and V sg,MP5 Gradually increasing.

[0096] Assuming the reference voltage Vref is convex upwards before compensation, a concave nonlinear compensation voltage needs to be generated. By connecting the two voltages in series, the reference voltage Vref after the first compensation will be convex upwards from -40℃ to 80℃ and from 80℃ to 125℃. This compensation, through a single temperature halving, halves the fluctuation voltage range across the entire temperature range, thus halving the temperature drift coefficient.

[0097] In one embodiment, an example is given using the industry-standard temperature range of -40℃ ≤ T ≤ 125℃. This is achieved by rationally designing the resistance value of the twelfth resistor R12 in the circuit and its relationship to the first zero-temperature coefficient voltage V. ztat1 Second zero temperature coefficient voltage V ztat2 The value of this value allows the fifth PMOS transistor MP5 to flow with an exponentially shaped subthreshold on-state current when the temperature is above 80℃, and to turn off when the temperature is below 80℃, resulting in a zero source-drain current for MP5. The source-drain current I of the fifth PMOS transistor MP5 is... sd5 The expression is:

[0098]

[0099] Where I0 is proportional to the width-to-length ratio W / L of the MOSFET, V sg5 It is the source-gate voltage of the fifth PMOS transistor MP5, ξ>1, which is a non-ideal factor, V T It is thermal voltage.

[0100] Therefore, the first segmented current can be obtained, and the corresponding source-drain current of the fourth PMOS transistor MP4 is the zero-temperature coefficient current I. ztat Subtract the temperature-dependent current flowing through the fifth PMOS transistor MP5.

[0101] Similarly, when the temperature is below 80℃, with the positive temperature coefficient voltage V ptat As the temperature rises, the on-state current of the third PMOS transistor MP3 gradually decreases; when the temperature exceeds 80℃, the third PMOS transistor MP3 turns off, and its source-drain current becomes zero. The source-drain current I of the third PMOS transistor MP3... sd3 The expression is:

[0102]

[0103] Where I0 is proportional to the width-to-length ratio W / L of the MOSFET, V sg3 It is the source-gate voltage of the third PMOS transistor MP3, ξ>1, which is a non-ideal factor, V T It is thermal voltage.

[0104] Therefore, the second segmented current can be obtained, and the corresponding source-drain current of the second PMOS transistor MP2 is the positive temperature coefficient current I. ptat Subtract the temperature-dependent current flowing through the third PMOS transistor MP3.

[0105] This allows the current flowing through the second PMOS transistor MP2 and the fifth PMOS transistor MP5 to be turned on or off at a temperature of 80°C, thus obtaining segmented current that is turned on or off at 80°C.

[0106] The two currents are connected in parallel and superimposed to obtain the nonlinear compensation current I. comp The expression is as follows:

[0107]

[0108] The current flows through the compensation resistor R comp The voltage V with nonlinear compensation is obtained. comp The expression is as follows:

[0109]

[0110] This voltage is superimposed in series onto the uncompensated 1.25V reference voltage Vref, and the exponential temperature nonlinear voltage is superimposed on the logarithmic temperature nonlinear voltage to cancel it out, thereby achieving segmented current compensation and halving the temperature drift.

[0111] It is understood that this application can also compensate for the concave reference voltage Vref. The compensation principle of segmented current generation is similar to that of compensating for the convex reference voltage Vref, so it will not be described in detail here.

[0112] In one embodiment, when the temperature drift curve of the reference voltage Vref is convex upward, the current combiner circuit 150 can, for example, assign values ​​0101 to the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4, then the first switch S1 is connected to the second compensation resistor R. comp2 The first terminal; the second switch S2 is connected to the compensation resistor R. comp The first terminal; the third switch S3 is connected to the second compensation resistor R. comp2 The first terminal; the fourth switch S4 is connected to the compensation resistor R. comp The first terminal enables segmented current compensation for the convex reference voltage Vref.

[0113] In another embodiment, when the temperature drift curve of the reference voltage Vref is concave, the current combiner circuit 150 can, for example, assign a value of 1010 to the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4, then the first switch S1 is connected to the compensation resistor R. comp The first terminal; the second switch S2 is connected to the second compensation resistor R. comp2 The first terminal; the third switch S3 is connected to the compensation resistor R. comp The first terminal; the fourth switch S4 is connected to the second compensation resistor R.comp2 The first terminal enables segmented current compensation for the concave reference voltage Vref.

[0114] In yet another embodiment, when the reference voltage Vref does not require compensation, the current combiner circuit 150 can, for example, assign a value of 1111 to switches S1_S2_S3_S4, then the first switch S1 is connected to the second compensation resistor R. comp2 The first terminal; the second switch S2 is connected to the second compensation resistor R. comp2 The first terminal; the third switch S3 is connected to the second compensation resistor R. comp2 The first terminal; the fourth switch S4 is connected to the second compensation resistor R. comp2 The first end isolates the bandgap reference core circuit 110 and the current compensation circuit, and compensates the current I in segments. comp The value is zero, thus achieving the function of no compensation.

[0115] The bandgap reference voltage source circuit 100 of this application can achieve an extremely low temperature drift coefficient over a wide temperature range.

[0116] The bandgap reference voltage source circuit provided in the embodiments of this application has been described in detail above. Specific examples have been used to illustrate the bandgap reference voltage source circuit of the embodiments of this application. The description of the above embodiments is only for the purpose of helping to understand the core idea of ​​this application and is not intended to limit this application. It should be noted that for those skilled in the art, several improvements and modifications can be made to this application without departing from the spirit and principles of this application, and these improvements and modifications should all fall within the protection scope of the appended claims.

Claims

1. A bandgap reference voltage source circuit, characterized in that: The system includes a startup circuit, a bandgap reference core circuit, and a current compensation circuit. The startup circuit is used to free the bandgap reference core circuit from metastability. The bandgap reference core circuit generates a reference voltage. The current compensation circuit compensates for the temperature drift of the reference voltage. The bandgap reference core circuit includes a first NMOS transistor, a first transistor, a second transistor, a first operational amplifier, a first resistor, a second resistor, a third resistor, and a compensation resistor. The drain of the first NMOS transistor is connected to the power supply voltage. The source of the first NMOS transistor is connected to the first terminal of the first resistor, the base of the first transistor, and the collector of the second transistor. The gate of the first NMOS transistor is connected to the output terminal of the first operational amplifier. The second terminal of the first resistor is connected to the collector of the first transistor and the base of the second transistor, and the first terminal of the first resistor serves as the output terminal of the bandgap reference core circuit. The emitter of the first transistor is connected to the... The first terminal of the second resistor is connected to the non-inverting input terminal of the first operational amplifier; the emitter of the second transistor is connected to the first terminal of the third resistor and the inverting input terminal of the first operational amplifier; the second terminals of the second and third resistors are respectively connected to the first terminal of the compensation resistor and the output terminal of the current compensation circuit, the second terminal of the compensation resistor is grounded, and the current compensation circuit includes a positive temperature coefficient current generation circuit, a low dropout linear regulator circuit, and a current combiner circuit, wherein the positive temperature coefficient current generation circuit is used to generate a positive temperature coefficient current; the low dropout linear regulator circuit is used to generate a zero temperature coefficient current, a first zero temperature coefficient voltage, and a second zero temperature coefficient voltage; the current combiner circuit is used to generate a segmented compensation current based on the positive temperature coefficient voltage, the first zero temperature coefficient voltage, the second zero temperature coefficient voltage, the positive temperature coefficient current, and the zero temperature coefficient current output from the first terminal of the third resistor.

2. The bandgap reference voltage source circuit as described in claim 1, characterized in that: The voltage difference across the first resistor is equal to the difference between the base and emitter voltages of the first transistor and the base and emitter voltages of the second transistor.

3. The bandgap reference voltage source circuit as described in claim 1, characterized in that: The second resistor and the third resistor have the same resistance value.

4. The bandgap reference voltage source circuit as described in claim 3, characterized in that: The first-order temperature drift of the reference voltage generated by the bandgap reference core circuit is adjusted by adjusting the ratio of the second resistor to the first resistor; the nonlinear temperature drift of the reference voltage is adjusted by adjusting the compensation current output by the current compensation circuit and the resistance value of the compensation resistor.

5. The bandgap reference voltage source circuit as described in claim 1, characterized in that: The startup circuit includes a fourth resistor, a fifth resistor, a sixth resistor, a first PMOS transistor, a third transistor, and a startup transistor. The first terminal of the fourth resistor is connected to the emitter of the third transistor, and the second terminal of the fourth resistor is grounded. The first terminals of the fifth and sixth resistors, and the source of the first PMOS transistor are connected to a power supply voltage. The second terminal of the fifth resistor is connected to the collector and base of the third transistor. The gate of the startup transistor is connected to the base of the third transistor, and the drain of the startup transistor is connected to the second terminal of the sixth resistor and the gate of the first PMOS transistor. The source of the startup transistor is connected to the output terminal of the bandgap reference core circuit. The drain of the first PMOS transistor is connected to the gate of the first NMOS transistor.

6. The bandgap reference voltage source circuit as described in claim 1, characterized in that: The current combiner circuit includes a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first switch, a second switch, a third switch, a fourth switch, and a second compensation resistor. The sources of the second and third PMOS transistors are connected to the positive temperature coefficient current; the sources of the fourth and fifth PMOS transistors are connected to the zero temperature coefficient current; the gate of the second PMOS transistor is connected to the first zero temperature coefficient voltage; the gates of the third and fourth PMOS transistors are connected to the positive temperature coefficient voltage; and the gate of the fifth PMOS transistor is connected to the second zero temperature coefficient voltage. Currents flowing from the drains of the second, third, fourth, and fifth PMOS transistors are selectively fed into the output terminal of the current compensation circuit or into the first terminal of the second compensation resistor via the first, second, third, and fourth switches, respectively. The second terminal of the second compensation resistor is grounded.

7. The bandgap reference voltage source circuit as described in claim 6, characterized in that: The resistance value of the second compensation resistor is equal to the resistance value of the compensation resistor in the bandgap reference core circuit.

8. The bandgap reference voltage source circuit as described in claim 6, characterized in that: The second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor have the same dimensions.

9. The bandgap reference voltage source circuit as described in claim 6, characterized in that: The second zero temperature coefficient voltage is greater than the first zero temperature coefficient voltage.

10. The bandgap reference voltage source circuit as described in claim 9, characterized in that: When the temperature drift curve of the reference voltage is convex upward, the first switch and the third switch are connected to the first terminal of the second compensation resistor; the second switch and the fourth switch are connected to the first terminal of the compensation resistor.

11. The bandgap reference voltage source circuit as described in claim 9, characterized in that: When the temperature drift curve of the reference voltage is concave, the first switch and the third switch are connected to the first terminal of the compensation resistor; the second switch and the fourth switch are connected to the first terminal of the second compensation resistor.

12. The bandgap reference voltage source circuit as described in claim 9, characterized in that: When the reference voltage does not require compensation, the first switch, the second switch, the third switch, and the fourth switch are all connected to the first terminal of the second compensation resistor.

13. The bandgap reference voltage source circuit as described in claim 6, characterized in that: The low-dropout linear regulator circuit includes a second operational amplifier, a second NMOS transistor, and a resistor divider branch. The non-inverting input of the second operational amplifier is connected to the output of the bandgap reference core circuit. The inverting input of the second operational amplifier is connected to one end of the resistor divider branch and the source of the second NMOS transistor. The output of the second operational amplifier is connected to the gate of the second NMOS transistor. The other end of the resistor divider branch is grounded. The resistor divider branch has a first voltage divider output and a second voltage divider output. The first voltage divider output is used to output the first zero-temperature coefficient voltage, and the second voltage divider output is used to output the second zero-temperature coefficient voltage. The drain of the second NMOS transistor serves as the output of the zero-temperature coefficient current.

14. The bandgap reference voltage source circuit as described in claim 13, characterized in that: The low-dropout linear regulator circuit further includes a sixth PMOS transistor, a seventh PMOS transistor, and an eleventh resistor. The second terminal of the eleventh resistor is connected to the drain of the second NMOS transistor, and the first terminal of the eleventh resistor is connected to the drain of the sixth PMOS transistor and the gate of the seventh PMOS transistor. The gate of the sixth PMOS transistor is connected to the second terminal of the eleventh resistor, and the source of the sixth PMOS transistor is connected to the drain of the seventh PMOS transistor. The source of the seventh PMOS transistor is connected to the power supply voltage.

15. The bandgap reference voltage source circuit as described in claim 14, characterized in that: The positive temperature coefficient current generating circuit includes a fourth transistor and a twelfth resistor. The base of the fourth transistor is connected to the output terminal of the bandgap reference core circuit, the emitter of the fourth transistor is connected to the first terminal of the twelfth resistor, and the collector of the fourth transistor serves as the output terminal of the positive temperature coefficient current generating circuit. The second terminal of the twelfth resistor is grounded.

16. The bandgap reference voltage source circuit as described in claim 15, characterized in that: The positive temperature coefficient current generation circuit further includes an eighth PMOS transistor, a ninth PMOS transistor, and a thirteenth resistor. The first end of the thirteenth resistor is connected to the drain of the eighth PMOS transistor and the gate of the ninth PMOS transistor. The second end of the thirteenth resistor is connected to the collector of the fourth transistor and the gate of the eighth PMOS transistor. The source of the eighth PMOS transistor and the drain of the ninth PMOS transistor are connected, and the source of the ninth PMOS transistor is connected to the power supply voltage.

17. The bandgap reference voltage source circuit as described in claim 16, characterized in that: The current combiner circuit further includes a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, and a thirteenth PMOS transistor. The gates of the tenth and eleventh PMOS transistors are respectively connected to the gates of the ninth and eighth PMOS transistors. The drain of the tenth PMOS transistor is connected to the source of the eleventh PMOS transistor. The source of the tenth PMOS transistor is connected to a power supply voltage. The drain of the eleventh PMOS transistor outputs the positive temperature coefficient current. The gates of the twelfth and thirteenth PMOS transistors are respectively connected to the gates of the seventh and sixth PMOS transistors. The drain of the twelfth PMOS transistor is connected to the source of the thirteenth PMOS transistor. The source of the twelfth PMOS transistor is connected to a power supply voltage. The drain of the thirteenth PMOS transistor outputs the zero temperature coefficient current.

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