System time delay simulation method and device, computer equipment and storage medium

Abstract

The invention discloses a system time delay simulation method and device, computer equipment and a storage medium, and the method comprises the steps: maintaining a control chain table, adding each processing unit into the control chain table, and carrying out the ascending sorting according to the age of each processing unit; scheduling the control chain table, and judging the operation condition of the scheduled processing unit; if the processing unit meets the operation condition, taking out the IO packet to be processed from the input queue of the processing unit, executing the processing logic, and updating the timestamp of the IO packet; and if the processing unit does not meet the operation condition, increasing a first age of the processing unit at the moment to a second age of the next moment meeting the operation condition, arranging the second age to a corresponding position of the control chain table, and updating an index of the processing unit in the registry. According to the method, the problems that the delay index of the system is difficult to accurately evaluate and the performance bottleneck cannot be accurately positioned are effectively solved through the technical means of maintaining and scheduling the control linked list and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of system simulation modeling, and particularly to a system delay simulation method, apparatus, computer device, and storage medium. Background Art

[0002] In the prior art, the following problems exist in simulation simulators in terms of performance evaluation:

[0003] On the one hand, many simulation simulators strive to comprehensively consider multiple performance metrics in order to provide users with comprehensive analysis results. However, this strategy of broad attention often leads to insufficient detailed analysis of a specific performance metric (such as delay, throughput, etc.). Due to the complexity of the simulation model itself and the influence of multiple variables involved, this insufficiency may result in large evaluation errors in specific performance metrics. These errors will not only cause a significant gap between the simulation results and the actual system performance, but may also further affect the effectiveness and accuracy of the design decisions made based on the simulation results.

[0004] On the other hand, although some simulation simulators specifically focus on the delay metric and attempt to evaluate it, due to insufficient simulation granularity, it is often difficult to accurately measure and locate the delay. This lack of fineness makes it difficult for the simulation simulator to accurately capture the performance bottleneck, thus limiting its application effect in performance optimization and bottleneck analysis.

[0005] In summary, the simulation simulators in the prior art have both the problem of insufficient detailed analysis of the delay metric in performance evaluation and the problem of inaccurate delay evaluation due to insufficient simulation granularity. Summary of the Invention

[0006] The purpose of the present invention is to provide a system delay simulation method, apparatus, computer device, and storage medium, aiming to solve the problems in the prior art that the simulation simulator has difficulty in accurately evaluating the delay metric and cannot accurately locate the performance bottleneck.

[0007] In a first aspect, an embodiment of the present invention provides a system delay simulation method based on discrete events, including:

[0008] Maintain a control linked list, add each processing unit to the control linked list, and sort them in ascending order according to the age of each processing unit;

[0009] Schedule the control linked list and judge the running conditions of the scheduled processing unit;

[0010] If the processing unit meets the running conditions, take out the to-be-processed IO packet from the input queue of the processing unit, execute the processing logic, and update the timestamp of the IO packet;

[0011] If the processing unit does not meet the operating conditions, increase the first age of the processing unit at this moment to the second age at the next moment when the operating conditions are met, arrange the second age at the corresponding position in the control linked list, and update the index of the processing unit in the registry.

[0012] In a second aspect, an embodiment of the present invention further provides a discrete-event-based system delay simulation device, which includes:

[0013] A maintenance unit, configured to maintain a control linked list, add each processing unit to the control linked list, and sort them in ascending order according to the age of each processing unit;

[0014] A scheduling unit, configured to schedule the control linked list and judge the operating conditions of the scheduled processing unit;

[0015] A processing unit, configured to, if the processing unit meets the operating conditions, take out the to-be-processed IO packet from the input queue of the processing unit, execute the processing logic, and update the time stamp of the IO packet;

[0016] An updating unit, configured to, if the processing unit does not meet the operating conditions, increase the first age of the processing unit at this moment to the second age at the next moment when the operating conditions are met, arrange the second age at the corresponding position in the control linked list, and update the index of the processing unit in the registry.

[0017] In a third aspect, an embodiment of the present invention further provides a computer device, which includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the discrete-event-based system delay simulation method described in the first aspect above is implemented.

[0018] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor is caused to execute the discrete-event-based system delay simulation method described in the first aspect above.

[0019] An embodiment of the present invention provides a system delay simulation method, apparatus, computer device, and storage medium. The method maintains a control linked list, adds each processing unit to the control linked list, and sorts them in ascending order according to the age of each processing unit; schedules the control linked list and judges the operating conditions of the scheduled processing unit; if the processing unit meets the operating conditions, take out the to-be-processed IO packet from the input queue of the processing unit, execute the processing logic, and update the time stamp of the IO packet; if the processing unit does not meet the operating conditions, increase the first age of the processing unit at this moment to the second age at the next moment when it meets the operating conditions, arrange the second age at the corresponding position in the control linked list, and update the index of the processing unit in the registry. It effectively solves the problem that it is difficult to accurately evaluate the delay index of the system and it is impossible to accurately locate the performance bottleneck, and further optimizes the system architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0021] Figure 1 It is a schematic flowchart of the system delay simulation method based on discrete events provided by the embodiment of the present invention;

[0022] Figure 2 It is a schematic sub-flowchart of the system delay simulation method based on discrete events provided by the embodiment of the present invention;

[0023] Figure 3 It is another schematic sub-flowchart of the system delay simulation method based on discrete events provided by the embodiment of the present invention;

[0024] Figure 4 It is another schematic sub-flowchart of the system delay simulation method based on discrete events provided by the embodiment of the present invention;

[0025] Figure 5 It is another schematic sub-flowchart of the system delay simulation method based on discrete events provided by the embodiment of the present invention;

[0026] Figure 6 It is a schematic structural diagram of the registry provided by the embodiment of the present invention;

[0027] Figure 7 It is a schematic structural diagram of the resource block diagram provided by the embodiment of the present invention;

[0028] Figure 8 It is a schematic structural diagram of the module block diagram provided by the embodiment of the present invention;

[0029] Figure 9 A structural schematic diagram of the control block diagram provided by an embodiment of the present invention;

[0030] Figure 10 A schematic diagram of a system delay simulation device based on discrete events provided by an embodiment of the present invention;

[0031] Figure 11 A schematic diagram of a computer device provided by an embodiment of the present invention. Detailed implementation manners

[0032] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0033] It should be understood that when used in this specification and the appended claims, the terms "comprises" and "comprising" indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0034] It should also be understood that the terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms.

[0035] It should be further understood that the term " / and / " used in the specification of the present invention and the appended claims refers to any combination and all possible combinations of one or more of the related listed items, and includes these combinations.

[0036] The present invention proposes a simulation system framework, which decomposes each processing unit in the system and models the system from the module dimension, resource dimension, and control dimension. In the module dimension, the processing flow of each processing unit in the system is defined, and an age attribute is maintained for each processing unit; in the resource dimension, the resource allocation and recycling of the processing units in the system are managed, and a time stamp attribute is maintained for each resource; in the control dimension, the running order of each processing unit in the system is scheduled by maintaining a control linked list.

[0037] Please refer to Figure 1 , Figure 1It is a schematic flowchart of a system delay simulation method based on discrete events provided by an embodiment of the present invention. The method includes steps S101 to S104:

[0038] S101. Maintain a control linked list, add each processing unit to the control linked list, and sort them in ascending order according to the age of each processing unit;

[0039] In this embodiment, it is necessary to define a control linked list structure for storing processing units. Each processing unit should include its age, input queue (storing IO packets to be processed), and other necessary attributes. When new processing units are created or introduced into the system, they are added to the control linked list. When adding, it is necessary to ensure that the linked list is sorted in ascending order according to the age of the processing units for subsequent scheduling.

[0040] In one embodiment, as Figure 2 shown, the step S101 includes S201 to S203:

[0041] S201. Maintain an available resource list for each resource;

[0042] S202. When a processing unit applies for a resource, allocate the resource from the available resource list;

[0043] S203. When a processing unit releases a resource, recycle the resource to the available resource list.

[0044] In this embodiment, maintaining an available resource list for each resource is to establish a global or local available resource pool so that resources can be quickly allocated when needed. Specifically, a data structure (such as an array, linked list, hash table, etc.) can be defined to store the list of available resources. The representation of resources can be a simple identifier (such as ID), pointer, or reference, depending on the type of resource and the requirements of the system. When initializing, all available resources are added to this list.

[0045] Furthermore, when a processing unit needs resources to perform its work, it applies for resources to the system. Specifically, the processing unit sends a resource application request to the system. The system checks the available resource list to see if there are enough resources to meet the request. If there are enough resources, one or more resources are removed from the list and allocated to the processing unit. Update the status of the processing unit to reflect which resources it now has. If there are insufficient resources, it may be necessary to wait, queue, or return an error to the processing unit.

[0046] Further, when the processing unit has completed its work and no longer needs the resources, it releases these resources back to the system so that other processing units can use them. Specifically, the processing unit sends a resource release request to the system. The system verifies that the processing unit actually owns these resources (to prevent illegal release). These resources are removed from the state of the processing unit and added back to the list of available resources. The state of the available resource list is updated to reflect the new resource availability.

[0047] S102, scheduling the control linked list, and determining the operating conditions of the scheduled processing units;

[0048] In this embodiment, the simulation clock advances according to the minimum time step (usually the age of the youngest processing unit in the control list). Starting from the head of the control list (the youngest processing unit), the processing unit that needs to be scheduled is selected. For the selected processing unit, it is checked whether it meets the running conditions.

[0049] Specifically, Figure 3 As shown, the step S102 includes S301 to S304:

[0050] S301, determining whether the queue depth between the current processing unit and the downstream processing unit has reached the maximum depth;

[0051] S302: if the queue depth between the current processing unit and the downstream processing unit reaches the maximum depth, back pressure is applied to the current processing unit;

[0052] S303: if the queue depth between the current processing unit and the downstream processing unit is lower than a preset depth, the back pressure signal is released, and the time of releasing the back pressure is recorded;

[0053] S304: If the age of the current processing unit increases to the time for releasing the back pressure, the operating condition of the processing unit is determined.

[0054] In this embodiment, the purpose of step 301 is to monitor the data transmission queue between the processing units to ensure that there is no data backlog or delay due to the queue being too long. Specifically, a queue can be defined to store data sent from the current processing unit to the downstream processing unit. The length (i.e., depth) of the queue is checked in real time or periodically. The actual depth of the queue is compared with the preset maximum depth threshold.

[0055] Furthermore, when the queue reaches the maximum depth, the back pressure mechanism is used to slow down the production rate of the current processing unit to prevent the queue from overflowing. When the queue depth is reduced to a safe level, the back pressure is released, allowing the current processing unit to resume normal operation. Finally, within a period of time after the back pressure is released, the operating status of the current processing unit is evaluated to ensure that it can process data stably and efficiently.

[0056] In one embodiment, as Figure 4 shown, step S304 includes steps S401 to S404:

[0057] S401. In the current processing unit, if the queue pointed to by the pointer is not empty and the timestamp of the IO packet in the queue is less than the age of the current processing unit, then take out the IO packet and run it; otherwise, it cannot be run.

[0058] S402. If it is runnable and there are multiple producers in the current processing unit, then first run the IO packet with the smallest timestamp, take out the IO packet with the smallest timestamp, and determine whether the IO packet with the smallest timestamp meets the running conditions.

[0059] S403. If the IO packet with the smallest timestamp meets the running conditions, then increase the age of the current processing unit to the moment corresponding to the next pipeline interval.

[0060] S404. If the IO packet with the smallest timestamp does not meet the running conditions, then continue to determine whether the queue pointed to by the pointer is empty.

[0061] In this embodiment, it is ensured that only IO packets that meet the time requirements can be executed by the current processing unit. In the case of multiple producers, it is ensured that the IO packets are processed in chronological order while verifying their running conditions. Then, the age of the processing unit is updated to reflect the IO packets that have been successfully run. If the current IO packet cannot be run, it is necessary to check whether there are other runnable IO packets in the queue. That is to say, if the IO packet with the smallest timestamp does not meet the running conditions (for example, due to lack of dependencies, insufficient resources, etc.), then this IO packet is not executed. Go back to the head of the queue and re-check whether the queue is empty. If the queue is not empty, it may be necessary to continue taking out the next IO packet (possibly the IO packet with the second smallest timestamp) for the same judgment process. If the queue is empty, the current processing unit may enter a waiting state or execute other tasks.

[0062] In one embodiment, as Figure 5 shown, step S404 includes steps S501 to S502:

[0063] S501. If the queue pointed to by the pointer is empty, then take the age of the producer plus the processing delay as the characteristic time.

[0064] S502. If the queue pointed to by the pointer is not empty, then take the timestamp of the first IO packet in the queue pointed to by the pointer as the characteristic time, and count the minimum value of all characteristic times as the minimum characteristic time, and increase the age of the processing unit to the minimum characteristic time.

[0065] In this embodiment, when the queue is empty, a method is needed to estimate the time when the next IO packet may arrive so that the processing unit can make a decision based on this. When the queue is not empty, the timestamp of the first IO packet in the queue is used as the characteristic time, and the minimum characteristic time among all processing units is found to synchronize the ages of the processing units. Specifically, check whether the queue pointed to by the pointer is not empty. If the queue is not empty, take out the timestamp of the first IO packet in the queue as the characteristic time of the current processing unit. In a larger system scope (which may include multiple processing units), collect the characteristic times of all processing units and find the minimum value among them, that is, the minimum characteristic time. Increase the age of the current processing unit to the minimum characteristic time. This usually means that all processing units will be synchronized to the same time point to ensure data consistency and system stability.

[0066] S103. If the processing unit meets the operating conditions, take out the IO packet to be processed from the input queue of the processing unit, execute the processing logic, and update the timestamp of the IO packet.

[0067] In this embodiment, if the processing unit meets the operating conditions, take out the IO packet to be processed from its input queue and execute the corresponding processing logic (such as data calculation, status update, etc.). After the processing is completed, update the timestamp of the IO packet to reflect the time required for the processing. If the processing unit does not meet the operating conditions, calculate the next time point that meets the conditions (i.e., the second age), and update the age of the processing unit. Then, re-insert the processing unit into the correct position in the control linked list (sorted according to the new age).

[0068] In one embodiment, in step S103, if the processing unit meets the operating conditions, take out the IO packet to be processed from the input queue of the processing unit and execute the processing logic, including step S601:

[0069] S601. Send the processed IO packet to the downstream processing unit, and update the control linked list and the age of the processing unit according to the receiving status of the downstream processing unit.

[0070] In this embodiment, this step aims to ensure that the processed IO packet can be smoothly transmitted to the downstream processing unit, and update the relevant control structure and the status information of the processing unit according to the receiving situation of the downstream processing unit.

[0071] Specifically, after the current processing unit finishes processing an IO packet, it needs to send it to the downstream processing unit. After sending the IO packet, the current processing unit needs to update the control linked list to reflect the status that the IO packet has been sent, and according to the receiving status of the downstream processing unit (for example, whether it is successfully received, whether there is feedback, etc.), the current processing unit may need to update its age. If the downstream processing unit successfully receives and processes the IO packet and sends an acknowledgment feedback, then the age of the current processing unit may increase to reflect the completion of this processing cycle. If the downstream processing unit fails to successfully receive or process the IO packet, then the age of the current processing unit may not increase, or other measures need to be taken (such as re-sending the IO packet, recording errors, etc.).

[0072] S104. If the processing unit does not meet the operating conditions, increase the first age of the processing unit at this moment to the second age at the next moment when it meets the operating conditions, arrange the second age at the corresponding position in the control linked list, and update the index of the processing unit in the registry.

[0073] In this embodiment, for a processing unit that does not meet the operating conditions and has its age updated, it is also necessary to update its index in the registry. The registry is used to quickly search for information associated with the processing unit, such as status, location, etc. Updating the index can ensure that these units can be correctly accessed and processed during subsequent scheduling.

[0074] In another embodiment, the discrete event-based system delay simulation further includes steps S701 to S702:

[0075] S701. Add the number, processing delay list, and pipeline interval of each processing unit to the registry, and record the index of each processing unit in the registry;

[0076] S702. Maintain a consumer list and record the index of the consumers of the current processing unit in the registry.

[0077] In this embodiment, first, a structured registry is created to store information related to the processing unit. For each processing unit in the system, its number, processing delay list (including multiple processing delay values, each value corresponding to different processing conditions or priorities), and pipeline interval are sequentially added to the registry. While the processing unit information is added to the registry, record the index position of each processing unit in the registry. After adding the information, perform necessary verification to ensure that all information is accurate and up-to-date the registry in a timely manner to reflect the latest state of the system.

[0078] In step S702, it aims to establish a consumer list for tracking and recording the indexes of all consumers (i.e., downstream processing units) of the current processing unit in the registry. This helps the system understand the data flow and dependencies between processing units, thereby optimizing data processing and resource allocation.

[0079] In a specific embodiment, as Figure 6 shown is the RegistryTable. The registry is a common resource of the simulation system. Before the system runs, relevant information of all processing units will be added to the registry in the form of a ControlUnit. Δ is the processing pipeline interval of each processing unit, and Index_ControlList is the index of the processing unit in the control linked list ControlList.

[0080] As Figure 7 shown is the block diagram of Resource. The system is modeled from the resource dimension. The function of each processing unit is to maintain the InputQueue_Resource pointer, maintain the producer list, and maintain the available resources.

[0081] Specifically, the InputQueue_Resource pointer array consists of multiple pointers Ptr_InputQueue_Resource. The queue pointed to by each dotted-line pointer Ptr_InputQueue_Resource is composed of the payload (IO_Packet, i.e., IO packet) of the processing unit. Among them, the IO_Packet is produced by the corresponding producer (PU 10 ). Specifically, PU 10 sends the produced IO_Packet to the array pointed to by the pointer Ptr_InputQueue_Resource after the processing delay Time_Product 10 ; Similarly for PU k0 , details are not elaborated here.

[0082] The producer list consists of multiple ID_Producer. Each ID_Producer records the index of the corresponding producer in the registry. ID_Producer10 is the index of PU10 in the registry.

[0083] The available resource is AvailableResource, which takes effect when the processing unit is a resource management module. When other processing units apply for or release resources, it is responsible for resource allocation and recycling.

[0084] Furthermore, the backpressure judgment process of the lower-level processing unit is as follows: Judge whether the current processing unit PU 0 and the downstream processing unit (PU01 , PU 0i , PU 0j ) whether the queue between reaches the maximum depth. If it reaches the maximum depth, backpressure is applied to PU 0 . When the queue depth is lower than the maximum depth, the backpressure signal is released, and the moment when the backpressure ends is recorded. When the Age 0 of PU 0 (age) increases to this moment, the next operating condition judgment is performed; if it does not reach the maximum depth, the next operating condition judgment is directly performed.

[0085] Further, the judgment process of the processing unit operating conditions is as follows: Under the current processing unit PU 0 's Age 0 , if the queue pointed to by Ptr_InputQueue_Resource is not empty and the TimeStamp of the IO Packet in the queue is less than Age 0 , then the IO_Packet is taken out and run; otherwise, it cannot be run. If it can be run and there are multiple producers for PU 0 , the IO_Packet with the smallest TimeStamp needs to be run first according to the in-order logic. After taking out the IO_Packet to be run, if the operating conditions are still met, the Age 0 of PU 0 is increased to the moment corresponding to the next pipeline interval; if after taking it out, the operating conditions are not met, first judge whether the queue pointed to by each Ptr_InputQueue_Resource is empty. If it is empty, take the Age of the corresponding producer and increase the processing delay (Time_Product) as the characteristic time. If it is not empty, take the TimeStamp of the first IO_Packet in the queue pointed to by Ptr_InputQueue_Resource as the characteristic time. The minimum value of all characteristic times is counted as the minimum characteristic time, and Age is increased to the minimum characteristic time. If it cannot be run, directly increase Age to the minimum characteristic time.

[0086] As Figure 8 shown in the block diagram of the Module, the system is modeled from the module dimension. The function of each processing unit is to maintain a consumer list, which consists of multiple ID_Consumers and records the indexes of all consumers of the current processing unit PU0 in the registration table.

[0087] First, information such as the number of each processing unit, the processing delay list (a set of Time_Product), and the pipeline interval (Δ) is added to the registration table, and the index Index_RegistryTable of the processing unit in the registration table is recorded.

[0088] Next, run each processing unit, according to the judgment process of the processing unit operation conditions as described above, if PU 0 If it can run, the corresponding IO_Packet is taken out from the queue, and after processing, the Timestamp of the IO_Packet is increased to Age0+Time_Product, and sent to the downstream PU for processing.

[0089] like Figure 9 The control block diagram is shown, which models the system from the control dimension. The function of each processing unit is to maintain the control unit list and add the PUs in the registration table to the control list in ascending order of Age.

[0090] Furthermore, the steps of overall scheduling of the simulation system are as follows:

[0091] First, take out the first processing unit PU in the control list 1 According to the back pressure judgment process of the lower processing unit as described above, the PU 1 Next, the PU is judged according to the judgment process of the operating conditions of the processing unit as described above. 1 Perform the operation condition judgment. If the operation condition is met, run PU 1 If not satisfied, PU 1 Age 1 Growth for Age 1' , sort the processing unit to the corresponding position in the control unit list according to the ascending bubble sort, and change the index Index_ControlList of the corresponding processing unit in the registration table. Repeat the above steps until all IO_Packets are processed.

[0092] like Figure 10 As shown, the embodiment of the present invention further provides a discrete event-based system delay simulation device 800 , including: a maintenance unit 801 , a scheduling unit 802 , a processing unit 803 , and an updating unit 804 .

[0093] The maintenance unit 801 is used to maintain the control linked list, add each processing unit to the control linked list, and sort the processing units in ascending order according to their age;

[0094] A scheduling unit 802, used to schedule the control linked list and determine the operating conditions of the scheduled processing units;

[0095] The processing unit 803 is configured to take out the IO packet to be processed from the input queue of the processing unit, execute the processing logic, and update the timestamp of the IO packet if the processing unit meets the operating conditions;

[0096] An update unit 804, configured to, if the processing unit does not meet the operating conditions, increase the first age of the processing unit at this moment to the second age at the next moment when the operating conditions are met, arrange the second age at the corresponding position in the control linked list, and update the index of the processing unit in the registry.

[0097] The device maintains a control linked list, adds each processing unit to the control linked list, and sorts them in ascending order according to the age of each processing unit; schedules the control linked list and judges the operating conditions of the scheduled processing unit; if the processing unit meets the operating conditions, takes the to-be-processed IO packet from the input queue of the processing unit, executes the processing logic, and updates the timestamp of the IO packet; if the processing unit does not meet the operating conditions, increases the first age of the processing unit at this moment to the second age at the next moment when the operating conditions are met, arranges the second age at the corresponding position in the control linked list, and updates the index of the processing unit in the registry. It effectively solves the problem that it is difficult to accurately evaluate the delay index of the system and it is impossible to accurately locate the performance bottleneck, and further optimizes the system architecture.

[0098] It should be noted that those skilled in the art can clearly understand that the specific implementation processes of the above device and each unit can refer to the corresponding descriptions in the foregoing method embodiments. For the sake of convenience and brevity of description, they will not be elaborated here.

[0099] The above device for predicting the optimal read voltage can be implemented in the form of a computer program, and the computer program can run on a computer device as Figure 11 shown.

[0100] Please refer to Figure 11 , Figure 11 which is a schematic block diagram of the computer device provided by the embodiment of the present invention. The computer device 900 is a server, and the server can be an independent server or a server cluster composed of multiple servers.

[0101] Referring to Figure 11 , the computer device 900 includes a processor 902, a memory, and a network interface 905 connected through a system bus 901. Among them, the memory can include a non-volatile storage medium 903 and an internal memory 904.

[0102] The non-volatile storage medium 903 can store an operating system 9031 and a computer program 9032. When the computer program 9032 is executed, the processor 902 can be made to execute the system delay simulation method based on discrete events.

[0103] The processor 902 is used to provide computing and control capabilities to support the operation of the entire computer device 900.

[0104] The internal memory 904 provides an environment for the operation of the computer program 9032 in the non-volatile storage medium 903. When the computer program 9032 is executed by the processor 902, the processor 902 can be caused to execute the discrete event-based system delay simulation method.

[0105] The network interface 905 is used for network communication, such as providing the transmission of data information, etc. Those skilled in the art can understand that Figure 11 the structure shown in is only a block diagram of some structures related to the solution of the present invention, and does not constitute a limitation on the computer device 900 to which the solution of the present invention is applied. The specific computer device 900 may include more or fewer processing units than those shown in the figure, or combine some processing units, or have a different arrangement of processing units.

[0106] Those skilled in the art can understand that Figure 11 the embodiments of the computer device shown in do not constitute a limitation on the specific composition of the computer device. In other embodiments, the computer device may include more or fewer processing units than those shown in the figure, or combine some processing units, or have a different arrangement of processing units. For example, in some embodiments, the computer device may only include a memory and a processor. In such an embodiment, the structure and function of the memory and the processor are the same as those in Figure 1 the embodiment shown, and will not be described in detail here.

[0107] It should be understood that in the embodiment of the present invention, the processor 902 may be a central processing unit (CPU), and the processor 902 may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), off-the-shelf programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0108] In another embodiment of the present invention, a computer-readable storage medium is provided. The computer-readable storage medium may be a non-volatile computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the discrete event-based system delay simulation method of the embodiment of the present invention is implemented.

[0109] The storage medium is a physical, non-transitory storage medium, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a magnetic disk, or an optical disc, etc., which are all physical storage media that can store program codes.

[0110] Those skilled in the art can clearly understand that, for the convenience and conciseness of description, the specific working processes of the above-described devices, apparatuses, and units can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein.

[0111] As described above, the above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or substitutions within the technical scope disclosed by the present invention, and these modifications or substitutions should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A system delay simulation method based on discrete events, characterized in that: include: Maintaining a control linked list, and adding each processing unit to the control linked list, and sorting in ascending order according to the age of each of the processing units; Scheduling the control linked list and determining the operating conditions of the scheduled processing units; If the processing unit meets the operating conditions, the IO packet to be processed is taken out from the input queue of the processing unit, the processing logic is executed, and the timestamp of the IO packet is updated; If the processing unit does not meet the operating conditions, the first age of the processing unit at this moment is increased to the second age at the next moment when the operating conditions are met, and the second age is arranged to the corresponding position of the control linked list, and the index of the processing unit in the registration table is updated.

2. The discrete event-based system delay simulation method according to claim 1, characterized in that: The step of scheduling the control linked list and judging the operating conditions of the scheduled processing units includes: Determine whether the queue depth between the current processing unit and the downstream processing unit has reached the maximum depth; If the queue depth between the current processing unit and the downstream processing unit reaches the maximum depth, back pressure is applied to the current processing unit; If the queue depth between the current processing unit and the downstream processing unit is lower than a preset depth, the back pressure signal is released, and the time of releasing the back pressure is recorded; If the age of the current processing unit increases to the time of releasing the back pressure, the operating condition of the processing unit is judged.

3. The discrete event-based system delay simulation method according to claim 2, characterized in that: If the age of the current processing unit increases to the time of releasing the back pressure, the operating condition of the processing unit is judged, including: In the current processing unit, if the queue pointed to by the pointer is not empty and the timestamp of the IO packet in the queue is less than the age of the current processing unit, then the IO packet is taken out and run, otherwise it cannot be run; If it is executable and the current processing unit has multiple producers, the IO packet with the smallest timestamp is executed first, and the IO packet with the smallest timestamp is taken out, and it is determined whether the IO packet with the smallest timestamp meets the running conditions; If the IO packet with the smallest timestamp meets the running condition, the age of the current processing unit is increased to the time corresponding to the next flow interval; If the IO packet with the smallest timestamp does not meet the running condition, it is further determined whether the queue pointed to by the pointer is empty.

4. The discrete event-based system delay simulation method according to claim 3, characterized in that: If the IO packet with the smallest timestamp does not meet the running condition, then continue to determine whether the queue pointed to by the pointer is empty, including: If the queue pointed to by the pointer is empty, the age of the producer plus the processing delay is taken as the characteristic time; If the queue pointed to by the pointer is not empty, the timestamp of the first IO packet in the queue pointed to by the pointer is taken as the characteristic time, and the minimum value of all characteristic times is counted as the minimum characteristic time, and the age of the processing unit is increased to the minimum characteristic time.

5. The discrete event-based system delay simulation method according to claim 1, characterized in that: The maintaining control linked list, adding each processing unit to the control linked list, and sorting the processing units in ascending order according to the age of each processing unit, comprises: Maintain a list of available resources for each resource; When a processing unit requests a resource, the resource is allocated from the available resource list; When the processing unit releases a resource, the resource is recycled to the available resource list.

6. The discrete event-based system delay simulation method according to claim 1, characterized in that: If the processing unit meets the operating conditions, the IO packet to be processed is taken out from the input queue of the processing unit, and the processing logic is executed, including: The processed IO packet is sent to the downstream processing unit, and the control linked list and the age of the processing unit are updated according to the receiving status of the downstream processing unit.

7. The discrete event-based system delay simulation method according to claim 1, characterized in that: Also includes: Add the number, processing delay list, and pipeline interval of each processing unit to a registration table, and record the index of each processing unit in the registration table; Maintain the consumer list and record the index of the consumer of the current processing unit in the registry.

8. A system delay simulation device based on discrete events, characterized in that: include: A maintenance unit, used for maintaining the control linked list, adding each processing unit to the control linked list, and sorting the processing units in ascending order according to the age of each processing unit; A scheduling unit, used to schedule the control linked list and determine the operating conditions of the scheduled processing units; A processing unit, configured to take out the IO packet to be processed from the input queue of the processing unit, execute the processing logic, and update the timestamp of the IO packet if the processing unit meets the operating conditions; An updating unit is used to increase the first age of the processing unit at this moment to the second age at the next moment when the operating condition is met if the processing unit does not meet the operating condition, arrange the second age to the corresponding position of the control linked list, and update the index of the processing unit in the registration table.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the discrete event-based system delay simulation method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor executes the discrete event-based system delay simulation method according to any one of claims 1 to 7.

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