Data decoding method and device, electronic equipment and computer readable storage medium

Abstract

The invention provides a data decoding method and device, electronic equipment and a computer readable storage medium, and relates to the technical field of equipment charging. The method comprises the following steps: splitting a decoding process of target data in a channel into a first processing process and a second processing process; wherein the target data comprises current data and / or to-be-processed data; the first processing process comprises a processing process of converting binary bits into byte data, and the second processing process comprises a processing process of converting a plurality of byte data into data packets and submitting the data packets to a task layer; configuring a first-class interrupt mechanism of the first processing process as a highest priority, and configuring a second-class interrupt mechanism of the second processing process as a secondary priority; and interrupting the second type of interrupt mechanism based on the first type of interrupt mechanism, so that the first processing process of the to-be-processed data is executed prior to the second processing process of the current data. According to the invention, the decoding process of data can be split, and the process with high real-time performance is processed preferentially.

Description

Technical Field

[0001] This application relates to the technical field of device charging. Specifically, it relates to a data decoding method, apparatus, electronic device, and computer-readable storage medium. Background Art

[0002] To meet the multi-device charging needs of users, currently, a one-chip dual-charging solution is usually adopted. That is, a chip with a dual-channel protocol can be used to support dual-port power supply output, so as to realize power supply to two devices in one charger, solving the problem that the charging protocols and interfaces of the two devices in a dual-device are different and they cannot charge each other or charge slowly.

[0003] In the one-chip dual-charging solution, two channels of data need to be processed. For example, two channels of ASK (Amplitude Shift Keying) decoding are required. Due to the increase in functions, the requirements for code and data space increase, and at the same time, higher requirements for computing power are also put forward. However, actually affected by the chip architecture design, the main frequency of the MCU cannot be doubled. At the current conventional main frequency, the two channels of ASK data cannot be processed and decoded in real time within the same time, resulting in adverse situations such as slower charging speed, lower charging efficiency, degraded device performance, and poor stability, thus leading to a poor charging effect of the current one-chip dual-charging solution. Summary of the Invention

[0004] In view of this, the purpose of the embodiments of this application is to provide a data decoding method, apparatus, electronic device, and computer-readable storage medium to improve the problem of poor charging effect of one-chip dual-charging in the existing technology.

[0005] To solve the above problems, the embodiments of this application provide a data decoding method, and the method includes:

[0006] Split the decoding process of the target data in the channel into a first processing process and a second processing process; wherein, the target data includes current data and / or data to be processed; the first processing process includes the process of converting binary bits into byte data, and the second processing process includes the process of converting multiple byte data into data packets and submitting the data packets to the task layer.

[0007] Configure the first type of interrupt mechanism of the first processing process as the highest priority, and configure the second type of interrupt mechanism of the second processing process as the secondary priority.

[0008] Interrupt the second type of interrupt mechanism based on the first type of interrupt mechanism, so that the first processing process of the data to be processed is executed prior to the second processing process of the current data.

[0009] In the above implementation process, in order to implement the decoding process of dual-channel data, the decoding process of each path of target data in the channel can be split into a first processing process with a relatively high real-time requirement and a second processing process with a relatively low real-time requirement, and different-priority interrupt mechanisms are set for the two processing processes respectively, so that the second interrupt mechanism with a lower priority can be interrupted by the first interrupt mechanism with the highest priority, so that the first processing process of the data to be processed can be preferentially executed over the second processing process of the current data, that is, the first processing process with a relatively high real-time requirement in the two-channel data is preferentially processed, so as to realize the real-time decoding process of the two-channel data. By splitting the high-load operation unit in the high-frequency interrupt, the real-time performance of the system's interrupt response is guaranteed. The soft interrupt mechanism of the chip is used to guarantee the load operation part of the split processing, and the priority response mechanism of the soft interrupt is used to ensure that the load operation is processed in time, so as to realize the demodulation of the dual-channel data of one-chip dual-charge without increasing the working frequency, effectively optimizing the charging effect of one-chip dual-charge.

[0010] Optionally, interrupting the second interrupt mechanism based on the first interrupt mechanism includes:

[0011] If the first processing process of the current data is completed, determine whether there is the data to be processed in the channel;

[0012] If it is determined that there is the data to be processed in the channel, then interrupt the second interrupt mechanism of the second processing process of the current data based on the first interrupt mechanism of the first processing process of the data to be processed, so that the first processing process of the data to be processed is preferentially executed over the second processing process of the current data.

[0013] In the above implementation process, when the first processing process of the current data being processed currently is completed, it can first be determined whether there is another path of data to be processed in the channel. If there is data to be processed, then based on the first interrupt mechanism with the highest priority set in the first processing process of the data to be processed, interrupt the second interrupt mechanism with a lower priority of the second processing process of the current data, so that the first processing process of the data to be processed can be preferentially executed over the second processing process of the current data. It can be adjusted and interrupted according to the actual situation of the data in the channel, so that the first processing process of any path of data can be preferentially executed over the second processing process, thereby improving the processing timeliness of the first processing process.

[0014] Optionally, interrupting the second interrupt mechanism based on the first interrupt mechanism further includes:

[0015] Write the first path of byte data obtained by the current data through the first processing process into the first buffer;

[0016] Write the second - path byte data obtained by processing the to - be - processed data through the first processing process into the second buffer.

[0017] In the above implementation process, since the data decoding process is split into two parts, and due to the interrupt mechanism with different priorities, there is a situation where the two processing processes of one - path data are not processed coherently. To enable the two processing processes to be processed normally, after the first processing process of each - path data is completed, the corresponding obtained byte data can be written into the buffer corresponding to that - path data. By storing the byte data obtained after the first processing process is completed, adverse situations such as data loss and errors can be reduced.

[0018] Optionally, interrupting the second - type interrupt mechanism based on the first - type interrupt mechanism further includes:

[0019] Based on the second - type interrupt mechanism of the second processing process of the current data, read the first - path byte data stored in the first buffer;

[0020] Execute the second processing process of the current data based on the first - path byte data;

[0021] If it is determined that the second processing process of the current data is completed, then based on the second - type interrupt mechanism of the second processing process of the to - be - processed data, read the second - path byte data stored in the second buffer;

[0022] Execute the second processing process of the to - be - processed data based on the second - path byte data.

[0023] In the above implementation process, after all the first processing processes are completed, to improve the overall data decoding efficiency, according to the second - type interrupt mechanism in the second processing process of the current data, read the first - path byte data stored in the first buffer, so as to execute the second processing process of the current data based on the first - path byte data. After the second processing process of the current data is executed, continue to read the second - path byte data stored in the second buffer according to the second - type interrupt mechanism of the second processing process of the to - be - processed data, so as to execute the second processing process of the to - be - processed data based on the second - path byte data. It can immediately execute the subsequent second processing process according to the set second - type interrupt mechanism after all the first processing processes are completed, thereby improving the processing efficiency of the overall data demodulation process.

[0024] Optionally, the first processing time of the first processing process of the current data includes: the first conversion time for converting the first binary bit into the first - path byte data, and the first buffering time for writing the first - path byte data into the first buffer;

[0025] The second processing time of the first processing process of the data to be processed includes: the second conversion time for converting the second binary digit into the second-channel byte data, and the second buffering time for writing the second-channel byte data into the second buffer;

[0026] Wherein, the sum of the first processing time and the second processing time is less than or equal to the average edge-triggered interruption time of the decoding mode corresponding to the channel.

[0027] In the above implementation process, due to different decoding modes, the corresponding average edge-triggered interruption times are also different. In the processing case of any decoding mode, the time of the first processing process includes the conversion time for converting binary digits into byte data and the buffering time for writing byte data into the buffer, and the sum of the times of the two first processing processes of the two-channel data is less than the corresponding average edge-triggered interruption time, so that the first processing process with higher real-time requirements in the two-channel data can be completed within the average edge-triggered interruption time to realize the real-time decoding of the two-channel data.

[0028] Optionally, the decoding mode includes: a double-edge decoding mode or a single-edge decoding mode.

[0029] In the above implementation process, different decoding modes can be selected for processing according to different charging requirements and application scenarios.

[0030] Optionally, the current data and the data to be processed are determined in the following manner:

[0031] If the two-channel target data are not sent down simultaneously, the target data with the earlier sending time is used as the current data to be currently processed, and the target data with the later sending time is used as the data to be processed, the data to be processed;

[0032] If the two-channel target data are sent down simultaneously, any one of the two-channel target data is arbitrarily selected as the current data to be currently processed, and the other one of the two-channel target data is used as the data to be processed, the data to be processed.

[0033] In the above implementation process, if the multiple-channel data in the channel are not sent down simultaneously, the corresponding current data and data to be processed can be determined according to the sending time; if the multiple-channel data in the channel are sent down simultaneously, any one of them can be selected as the current data and the other one as the data to be processed. The current data and the data to be processed can be determined according to the actual sending situation of the data to demodulate the two-channel data.

[0034] In a second aspect, the embodiments of the present application further provide a data decoding device, and the device includes: a splitting module, a configuration module, and a processing module;

[0035] The splitting module is used to split the decoding process of the target data in the channel into a first processing process and a second processing process; wherein, the target data includes current data and / or data to be processed; the first processing process includes a process of converting binary bits into byte data, and the second processing process includes a process of converting a plurality of the byte data into data packets and submitting the data packets to the task layer;

[0036] The configuration module is used to configure the first type of interrupt mechanism of the first processing process to have the highest priority and configure the second type of interrupt mechanism of the second processing process to have the second highest priority;

[0037] The processing module is used to interrupt the second type of interrupt mechanism based on the first type of interrupt mechanism, so that the first processing process of the data to be processed is executed prior to the second processing process of the current data.

[0038] In the above implementation process, the decoding process of each path of target data in the channel is split by the splitting module into a first processing process with a relatively high real-time requirement and a second processing process with a relatively low real-time requirement. The configuration module sets different priority interrupt mechanisms for the two processing processes respectively. The processing module interrupts the second type of interrupt mechanism with a lower priority through the first type of interrupt mechanism with the highest priority, so that the first processing process of the data to be processed can be preferentially executed prior to the second processing process of the current data, that is, the first processing process with a relatively high real-time requirement in the two paths of data is preferentially processed, thereby enabling real-time decoding processing of the two paths of data.

[0039] In a third aspect, an embodiment of the present application further provides an electronic device, which includes a memory and a processor. When the processor reads and runs program instructions stored in the memory, the steps in any one of the above data decoding methods are executed.

[0040] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, in which computer program instructions are stored. When the computer program instructions are read and run by a processor, the steps in any one of the above data decoding methods are executed.

[0041] In summary, an embodiment of the present application provides a data decoding method, device, electronic device and computer-readable storage medium. By splitting high-load operation units in high-frequency interrupts, the real-time performance of the system's interrupt response is guaranteed. Utilizing the soft interrupt mechanism of the chip, the load operation part of the splitting process is guaranteed. Using the priority response mechanism of the soft interrupt, it is ensured that the load operation is processed in a timely manner, thereby realizing demodulation of dual-channel data for dual charging with one chip without increasing the working frequency, and effectively optimizing the charging effect of dual charging with one chip. Brief Description of the Drawings

[0042] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other relevant drawings can also be obtained based on these drawings.

[0043] Figure 1 It is a block diagram of an electronic device provided by an embodiment of the present application;

[0044] Figure 2 It is a flowchart of a data decoding method provided by an embodiment of the present application;

[0045] Figure 3 It is a detailed flowchart of step S400 provided by an embodiment of the present application;

[0046] Figure 4 It is another detailed flowchart of step S400 provided by an embodiment of the present application;

[0047] Figure 5 It is a waveform diagram of ASK data provided by an embodiment of the present application;

[0048] Figure 6 It is yet another detailed flowchart of step S400 provided by an embodiment of the present application;

[0049] Figure 7 It is a structural diagram of a data decoding device provided by an embodiment of the present application.

[0050] Reference Signs: 100 - Electronic device; 111 - Memory; 112 - Storage controller; 113 - Processor; 114 - Peripheral interface; 115 - Input / output unit; 116 - Display unit; 500 - Data decoding device; 510 - Splitting module; 520 - Configuration module; 530 - Processing module. Detailed Description of the Embodiments

[0051] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts belong to the scope protected by the embodiments of the present application.

[0052] In a one-chip dual-charging solution, two-way data needs to be processed. For example, two-way ASK decoding, two-way FSK encoding and modulation, two sets of PWM power control, two sets of Qi state machines, etc. need to be processed. Due to the increase in functions, the code and data space requirements increase, and at the same time, higher computing power requirements are also put forward. For example, 2KHz ASK data needs to complete real-time decoding of two-way data within the same time. However, actually affected by the chip architecture design, the main frequency of the MCU cannot be doubled. At the current conventional main frequency of 12MHz, the current solution cannot complete real-time decoding of two-way data during the ASK interruption time, resulting in adverse situations such as slower charging speed, lower charging efficiency, degraded device performance, and poor stability, thus resulting in a poor charging effect of the current one-chip dual-charging solution.

[0053] To solve this problem, the embodiment of the present application provides a data decoding method, which is applied to an electronic device. The electronic device can be a charger or a device with a charging function, and can realize real-time decoding processing of two-way data for one-chip dual charging, effectively optimizing the charging effect of one-chip dual charging.

[0054] Optionally, please refer to Figure 1 , Figure 1 which is a block diagram of an electronic device provided by the embodiment of the present application. The electronic device 100 may include a memory 111, a storage controller 112, a processor 113, a peripheral interface 114, an input / output unit 115, and a display unit 116. Those of ordinary skill in the art can understand that Figure 1 the structure shown is only schematic and does not limit the structure of the electronic device 100. For example, the electronic device 100 may further include more or fewer components than those shown in Figure 1 , or have a different configuration from that shown in Figure 1 .

[0055] The above-mentioned memory 111, storage controller 112, processor 113, peripheral interface 114, input / output unit 115, and display unit 116 are directly or indirectly electrically connected to each other to realize data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines. The above-mentioned processor 113 is used to execute the executable module stored in the memory.

[0056] Among them, the memory 111 can be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. Among them, the memory 111 is used to store programs. After receiving an execution instruction, the processor 113 executes the program. The method executed by the electronic device 100 defined by the process disclosed in any embodiment of the embodiments of the present application can be applied to the processor 113 or implemented by the processor 113.

[0057] The above-mentioned processor 113 may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor 113 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0058] The above-mentioned peripheral interface 114 can be connected to various devices that need to be charged, such as a personal computer (PC), a tablet computer, a smart phone, a personal digital assistant (PDA), etc., to couple various devices to be charged to the processor 113 and the memory 111. In some embodiments, the peripheral interface 114, the processor 113, and the memory controller 112 can be implemented on a single chip. In some other instances, they can be implemented by separate chips.

[0059] The above-mentioned input / output unit 115 is used to provide input data to the user. The input / output unit 115 can be, but is not limited to, a mouse and a keyboard, etc.

[0060] The above-mentioned display unit 116 provides an interactive interface (such as a user operation interface) between the electronic device 100 and the user or is used to display image data for the user's reference. In the present embodiment, the display unit may be a liquid crystal display or a touch display. If it is a touch display, it may be a capacitive touch screen or a resistive touch screen that supports single-point and multi-point touch operations. Supporting single-point and multi-point touch operations means that the touch display can sense touch operations generated simultaneously from one or more positions on the touch display, and the sensed touch operations are handed over to the processor for calculation and processing. In an embodiment of the present application, the display unit 116 can display a variety of data such as charging progress, charging time, remaining time, and charging status.

[0061] The electronic device in this embodiment can be used to execute each step in each data decoding method provided in the embodiment of the present application. The implementation process of the data decoding method is described in detail below through several embodiments.

[0062] See also Figure 2 , Figure 2 A flowchart of a data decoding method provided in an embodiment of the present application, the method may include steps S200-S400.

[0063] Step S200, splitting the decoding process of the target data in the channel into a first processing process and a second processing process.

[0064] The channel may include two channels of target data, and the target data may include current data being processed and / or another channel of pending data waiting to be processed. In order to realize the decoding processing of dual-channel data, the decoding process of each channel of target data in the channel may be divided into a first processing process with a higher real-time requirement and a second processing process with a lower real-time requirement.

[0065] It should be noted that the current data and the data to be processed can be determined in the following way: if the two target data are not sent at the same time, the target data with an earlier sending time is used as the current data currently being processed, and the target data with a later sending time is used as the processed data to be processed; if the two target data are sent at the same time, one target data is arbitrarily selected as the current data currently being processed, and the other target data is used as the processed data to be processed.

[0066] Among them, if the multiple paths of data in the channel are not sent simultaneously, the sending time of the target data of each path can be obtained, so as to determine the corresponding current data and data to be processed according to the sending time. For example, the data with the earlier sending time among the two paths of target data is used as the current data, and the data with the later sending time is used as the data to be processed, so that the decoding process can start immediately when the target data is sent, effectively improving the overall decoding efficiency of the target data. If the multiple paths of data in the channel are sent simultaneously, any one of them can be selected as the current data for direct processing, and the other one is used as the data to be processed. It is possible to determine the current data and the data to be processed according to the actual sending situation of the data, so as to demodulate the two paths of data.

[0067] Optionally, the first processing process may include the process of converting binary bits into byte data, that is, the process of bitinfo->bit, bit->byte, which can convert binary bits into bytes. In a computer, each byte is composed of 8 binary bits. Therefore, the first processing process can be a process of combining each binary bit to form a byte. Specifically, the first processing process can be completed through the following steps: 1. Obtain binary bits: Obtain binary bits from the input data, and these binary bits may be converted through an encoding method (such as ASCII encoding). 2. Combine binary bits: Combine the obtained binary bits and form a byte in groups of 8. 3. Convert characters: Since the binary bits represent the characters in the character set, the combined byte needs to be converted into the corresponding character. 4. Output the result: Output the converted character as text or display it on the screen for the user to view. It should be noted that during the decoding process of the first processing process, it is necessary to determine whether the length of the input data is correct to reduce the occurrence of errors or data loss. At the same time, it is also necessary to decode according to different encoding methods to avoid garbled characters or incorrect characters.

[0068] Optionally, the second processing process may include converting multiple bytes of data into data packets, i.e., bytes->packet, and submitting the data packets to the task layer, i.e., packet->protocol, and submitting the Packet to the Event task layer for complete protocol processing. Among them, the decoding process from bytes to packet refers to the process of converting byte data into data packets. A data packet is a data unit transmitted in a network, which contains the data to be sent and related control information, such as source IP address, destination IP address, port number, etc. Specifically, the decoding process from bytes to packet can be completed through the following steps: 1. Obtain byte data: Obtain byte data from the input data, and these byte data may be converted through an encoding method (such as the encoding method in the TCP / IP protocol stack). 2. Parse control information: Parse the control information from the byte data, such as source IP address, destination IP address, port number, etc. This information will be used to determine the source and destination of the data packet. 3. Recombine data packets: Recombine the byte data into complete data packets according to the control information. In this process, it may be necessary to segment or recombine the byte data into different data packets. 4. Process data packets: Process the recombined data packets, such as verifying the checksum, confirming the order, etc. If there are errors or losses in the data packets, corresponding measures need to be taken for processing. 5. Output results: Output the processed data packets to the network or pass them to the application for processing. It should be noted that during the decoding process from bytes to packet, it is necessary to ensure that the length of the input data is the length of a complete data packet or a multiple thereof to reduce the occurrence of errors or data loss. At the same time, decoding needs to be performed according to different protocols to avoid incorrect data packets or situations where they cannot be processed.

[0069] Step S300, configure the first type of interrupt mechanism of the first processing process as the highest priority, and configure the second type of interrupt mechanism of the second processing process as the second highest priority.

[0070] Among them, in order to enable the first processing process with higher real-time requirements to be executed preferentially, a first type of interrupt mechanism can be configured for the first processing process, a second type of interrupt mechanism can be configured for the second processing process, and the first type of interrupt mechanism of the first processing process can be configured as the highest priority, and the second type of interrupt mechanism of the second processing process can be configured as the second highest priority only lower than the highest priority.

[0071] Optionally, two types of interruption mechanisms can be selected and configured according to the actual situation and requirements. For example, the first type of interruption mechanism can be an ASK interruption, and the second type of interruption mechanism can be a software-triggered interruption mechanism, such as a PendSV interruption, an interruption supported by the ARM M0 kernel, such as an SVCall interruption; or user-defined IRQ0-IRQ31 interruptions that can be software-triggered, etc. Using the interruption mechanisms built into the hardware or software for processing can effectively reduce the hardware cost required for interruptions, thereby reducing the cost of the electronic device.

[0072] It should be noted that the interruption priority is to distinguish the levels of the response urgency of interruptions that need to be processed. For example, the priority level 0 is the highest, and the priority level 3 is the lowest. An interruption with a higher priority can interrupt the processing of a lower priority. After the processing of the interruption with a higher priority is completed, the interruption with a lower priority is processed, so as to achieve interruption nesting.

[0073] Optionally, the priority of a task is also a similar software processing method, which is a distinction of the task urgency at the software level. The priority of a task is lower than the priority of all interruption mechanisms. For example, it can be considered that the task-level priority starts from level 4.

[0074] Step S400: Interrupt the second type of interruption mechanism based on the first type of interruption mechanism, so that the first processing process of the data to be processed is executed prior to the second processing process of the current data.

[0075] Among them, the first type of interruption mechanism with the highest priority can interrupt the second type of interruption mechanism with a lower priority, so that the first processing process of the data to be processed can be preferentially executed prior to the second processing process of the current data, that is, the first processing process with a higher real-time requirement in the two-way data is preferentially processed, so as to achieve the real-time decoding processing of the two-way data.

[0076] In Figure 2 In the shown implementation process, by splitting the high-load operation unit in the high-frequency interruption, the real-time performance of the system's interruption response is guaranteed. Using the chip's soft interruption mechanism to guarantee the load operation part of the split processing, and using the priority response mechanism of the soft interruption to ensure that the load operation is processed in a timely manner, so as to achieve the demodulation of two-way data for dual charging with one chip without increasing the working frequency, effectively optimizing the charging effect of dual charging with one chip.

[0077] Optionally, please refer to Figure 3 , Figure 3 which is a detailed process schematic diagram of step S400 provided by an embodiment of this application. Step S400 may include steps S411-S412.

[0078] Step S411: If the first processing process of the current data is completed, determine whether there is data to be processed in the channel.

[0079] Among them, when the first processing process of the current data being processed is completed, it is possible to first determine whether there is another piece of data to be processed in the channel, so as to determine which data processing process to execute next.

[0080] Optionally, when there is only the current data in the channel, the second processing process can be directly executed based on the second interrupt mechanism of the current data.

[0081] Step S412, if it is determined that there is data to be processed in the channel, then interrupt the second interrupt mechanism of the second processing process of the current data based on the first interrupt mechanism of the first processing process of the data to be processed, so that the first processing process of the data to be processed is executed prior to the second processing process of the current data.

[0082] Among them, if there is data to be processed, then interrupt the second interrupt mechanism with a lower priority of the second processing process of the current data based on the first interrupt mechanism with the highest priority set in the first processing process of the data to be processed, so that the first processing process of the data to be processed can be executed prior to the second processing process of the current data.

[0083] In Figure 3 the illustrated embodiment, it is possible to adjust and interrupt according to the actual situation of the data in the channel, so that the first processing process of any piece of data can be executed prior to the second processing process, thereby improving the processing timeliness of the first processing process.

[0084] Optionally, please refer to Figure 4 , Figure 4 which is a detailed flowchart of another step S400 provided by the embodiment of the present application. Step S400 may further include steps S421-S422.

[0085] Step S421, write the first path of byte data obtained by the first processing process of the current data into the first buffer.

[0086] Among them, since the decoding process of the data is split into two parts, and due to the interrupt mechanisms with different priorities, there is a situation where the two processing processes of one piece of data are processed discontinuously. In order to enable the two processing processes to be processed normally, two buffers can be set according to the two pieces of data respectively, and the first path of byte data obtained by the first processing process of the current data is written into its corresponding first buffer.

[0087] Step S422, write the second path of byte data obtained by the first processing process of the data to be processed into the second buffer.

[0088] Among them, the second-way byte data obtained by the first processing process from the data to be processed can also be written into its corresponding second buffer.

[0089] Optionally, the first-way byte data and the second-way byte data can be multiple byte data of multiple types.

[0090] Optionally, the first buffer and the second buffer can be set as Ring Buffer (circular buffer or circular queue), which is a data structure of a buffer with a fixed size and connected head to tail. Ring Buffer can be used for caching data streams, asynchronous communication, and embedded devices. For example, it is used for caching network data packets and storing system logs, etc., and can provide efficient data caching read and write operations. The data operations of Ring Buffer satisfy the FIFO (First In First Out) principle. The first buffer can be set as Ring0 Buffer, which can include multiple sub-buffers such as Ring0 Buffer0, Ring0 Buffer1, Ring0 Buffer2, Ring0 Buffer3, etc.; the second buffer can be set as Ring1 Buffer, which can include multiple sub-buffers such as Ring1 Buffer0, Ring1 Buffer1, Ring1 Buffer2, Ring1 Buffer3, etc.

[0091] It should be noted that due to different decoding modes, the corresponding average time of edge-triggered interrupts is also different. Optionally, please refer to Figure 5 , Figure 5A waveform schematic diagram of ASK data provided by an embodiment of the present application. Herein, the cycle time of each ONE and ZERO is 500 us. The decoding mode of the data may include: a double-edge decoding mode or a single-edge decoding mode. The double-edge decoding mode monitors both the rising edge and the falling edge of the waveform, and the single-edge decoding mode monitors only the rising edge or the falling edge of the waveform. During the processing, the first processing time of the first processing process of the current data may include: the first conversion time for converting the first binary bit into the first path of byte data, and the first buffering time for writing the first path of byte data into the first buffer; the second processing time of the first processing process of the data to be processed may include: the second conversion time for converting the second binary bit into the second path of byte data, and the second buffering time for writing the second path of byte data into the second buffer. The first processing time and the second processing time will also change accordingly according to the decoding mode. That is, in any case of the decoding mode, the time of the first processing process includes the conversion time for converting the binary bit into byte data and the buffering time for writing the byte data into the buffer, and the sum of the times of the two first processing processes of the two paths of data is less than the corresponding average edge-triggered interrupt time, so that the first processing process with higher real-time requirements in the two paths of data can be completed within the average edge-triggered interrupt time, so as to realize the real-time decoding of the two paths of data.

[0092] Exemplarily, when decoding based on Figure 5 the embodiment of, in the case where the main frequency of the MCU is 12 MHz and the frequency of the ASK data is 2 KHz, in the double-edge decoding mode, the corresponding average edge-triggered interrupt time is about 250 us, the first conversion time and the second conversion time are about 100 us, and the first buffering time and the second buffering time are about 10 us. Therefore, the first processing time of the current data is about 100 us + 10 us = 110 us, and the first processing time of the data to be processed is about 100 us + 10 us = 110 us. The sum of the two is 220 us < the average edge-triggered interrupt time of 250 us, that is, the sum of the times of the two first processing processes of the two paths of data is less than the corresponding average edge-triggered interrupt time, so that the first processing process with higher real-time requirements in the two paths of data can be completed within the average edge-triggered interrupt time, so as to realize the real-time decoding of the two paths of data.

[0093] Exemplarily, when decoding based on Figure 5When decoding the embodiments, when the main frequency of the MCU is 12 MHz and the frequency of the ASK data is 2 KHz, in the single-edge decoding mode, the average time of the corresponding edge-triggered interrupt is about 500 us, the first conversion time and the second conversion time are about 220 us, and the first buffer time and the second buffer time are about 10 us. Therefore, the first processing time of the current data is about 220 us + 10 us = 230 us, and the first processing time of the data to be processed is about 220 us + 10 us = 230 us. The sum of the two is 460 us < the average time of the edge-triggered interrupt 500 us, that is, the sum of the times of the two first processing processes of the two-channel data is less than the average time of the corresponding edge-triggered interrupt, so that the first processing process with higher real-time requirements in the two-channel data can be completed within the average time of the edge-triggered interrupt to achieve real-time decoding of the two-channel data.

[0094] In Figure 4 In the embodiment shown, by storing the byte data obtained after the first processing process is completed, adverse situations such as data loss and errors are reduced.

[0095] Optionally, please refer to Figure 6 , Figure 6 FIG. is a detailed flowchart of another step S400 provided by the embodiment of the present application. Step S400 may further include steps S431-S434.

[0096] Step S431, based on the second type of interrupt mechanism of the second processing process of the current data, read the first-channel byte data stored in the first buffer.

[0097] Step S432, execute the second processing process of the current data based on the first-channel byte data.

[0098] Among them, after all the first processing processes are completed, in order to improve the overall decoding efficiency of the data, according to the second type of interrupt mechanism in the second processing process of the current data, the first-channel byte data stored in the first buffer can be read, so that the second processing process of the current data can be immediately executed according to the first-channel byte data.

[0099] Step S433, if it is determined that the second processing process of the current data is completed, based on the second type of interrupt mechanism of the second processing process of the data to be processed, read the second-channel byte data stored in the second buffer.

[0100] Step S434, execute the second processing process of the data to be processed based on the second-channel byte data.

[0101] Among them, after the second processing process of the current data is completed, continue to read the second-channel byte data stored in the second buffer according to the second type of interruption mechanism of the second processing process of the data to be processed, so as to immediately execute the second processing process of the data to be processed according to the second-channel byte data.

[0102] Optionally, the third processing time of the second processing process of the current data may include: the first reading time for reading the first-channel byte data from the first buffer, and the first sorting time for processing based on the first-channel byte data; the fourth processing time of the second processing process of the data to be processed may include: the second reading time for reading the second-channel byte data from the second buffer, and the second sorting time for processing based on the second-channel byte data. The third processing time and the fourth processing time will also change according to the change of the decoding mode.

[0103] Exemplarily, when decoding based on the Figure 5 embodiment, when the main frequency of the MCU is 12 MHz and the frequency of the ASK data is 2 KHz, in the double-edge decoding mode, the average time of the corresponding edge-triggered interruption is about 250 us, the first conversion time and the second conversion time are about 100 us, the first buffer time, the second buffer time, the first reading time, and the second reading time are about 10 us, and the first sorting time and the second sorting time are about 80 us. Therefore, two complete processing processes of 100 us + 80 us cannot be completed within 250 us. In the single-edge decoding mode, the average time of the corresponding edge-triggered interruption is about 500 us, the first conversion time and the second conversion time are about 220 us, the first buffer time, the second buffer time, the first reading time, and the second reading time are about 10 us, and the first sorting time and the second sorting time are about 80 us. Therefore, two complete processing processes of 220 us + 80 us cannot be completed within 500 us. This application preferentially processes the first processing process, and can preferentially complete two first processing processes with higher real-time renewal within the average time of the edge-triggered interruption. After the first processing process is completed, immediately execute the corresponding second processing process with lower real-time requirements, so that the second processing process can be completed in time, thereby completing the overall decoding process of the data, and can realize the decoding of two channels of data while meeting the real-time performance.

[0104] Optionally, using the data decoding method provided by this application to demodulate the data does not require increasing the working frequency of the MCU and the hardware cost, and the success rate of data demodulation is relatively high.

[0105] In Figure 6 the shown embodiment, after all the first processing processes are completed, the subsequent second processing process can be immediately executed according to the set second type of interruption mechanism, thereby improving the processing efficiency of the overall data demodulation process.

[0106] Please refer to Figure 7 , Figure 7 which is a schematic structural diagram of a data decoding device provided by an embodiment of the present application. The data decoding device 500 may include: a splitting module 510, a configuration module 520, and a processing module 530;

[0107] The splitting module 510 is configured to split the decoding process of the target data in the channel into a first processing process and a second processing process; wherein, the target data includes current data and / or data to be processed; the first processing process includes a process of converting binary bits into byte data, and the second processing process includes a process of converting multiple byte data into data packets and submitting the data packets to the task layer;

[0108] The configuration module 520 is configured to configure the first type of interrupt mechanism of the first processing process as the highest priority, and configure the second type of interrupt mechanism of the second processing process as the second highest priority;

[0109] The processing module 530 is configured to interrupt the second type of interrupt mechanism based on the first type of interrupt mechanism, so that the first processing process of the data to be processed is executed prior to the second processing process of the current data.

[0110] In an alternative embodiment, the processing module 530 is specifically configured to: if the first processing process of the current data is completed, determine whether there is data to be processed in the channel; if it is determined that there is data to be processed in the channel, then interrupt the second type of interrupt mechanism of the second processing process of the current data based on the first type of interrupt mechanism of the first processing process of the data to be processed, so that the first processing process of the data to be processed is executed prior to the second processing process of the current data.

[0111] In an alternative embodiment, the processing module 530 is specifically configured to: write the first path of byte data obtained by the first processing process of the current data into the first buffer; write the second path of byte data obtained by the first processing process of the data to be processed into the second buffer.

[0112] In an alternative embodiment, the processing module 530 is specifically configured to: read the first path of byte data stored in the first buffer based on the second type of interrupt mechanism of the second processing process of the current data; execute the second processing process of the current data based on the first path of byte data; if it is determined that the second processing process of the current data is completed, then read the second path of byte data stored in the second buffer based on the second type of interrupt mechanism of the second processing process of the data to be processed; execute the second processing process of the data to be processed based on the second path of byte data.

[0113] In an optional embodiment, the first processing time of the first processing process of the current data includes: the first conversion time for converting the first binary bit into the first path of byte data, and the first buffering time for writing the first path of byte data into the first buffer; the second processing time of the first processing process of the data to be processed includes: the second conversion time for converting the second binary bit into the second path of byte data, and the second buffering time for writing the second path of byte data into the second buffer; wherein, the sum of the first processing time and the second processing time is less than or equal to the average edge-triggered interruption time of the decoding mode corresponding to the channel.

[0114] In an optional embodiment, the decoding mode includes: a double-edge decoding mode or a single-edge decoding mode.

[0115] In an optional embodiment, the data decoding device 500 may further include a determination module, and the determination module is specifically configured to: if the two paths of target data are not issued simultaneously, use the target data with the earlier issuing time as the current data to be currently processed, and use the target data with the later issuing time as the data to be processed; if the two paths of target data are issued simultaneously, arbitrarily select one path of target data as the current data to be currently processed, and use the other path of target data as the data to be processed.

[0116] Since the principle of the data decoding device 500 in the embodiments of the present application for solving problems is similar to that of the embodiments of the foregoing data decoding method, the implementation of the data decoding device 500 in this embodiment can refer to the description in the embodiments of the above data decoding method, and repeated parts will not be elaborated.

[0117] The embodiments of the present application further provide a computer-readable storage medium, in which computer program instructions are stored. When the computer program instructions are read and run by a processor, the steps in any one of the data decoding methods provided in this embodiment are executed.

[0118] In several embodiments provided in this application, it should be understood that the disclosed device can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the block diagrams in the drawings show the possible architectures, functions, and operations of the devices according to multiple embodiments of this application. In this regard, each block in the block diagram can represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram, as well as combinations of the block diagrams, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0119] In addition, in each embodiment of this application, the various functional modules can be integrated together to form an independent part, or each module can exist separately, or two or more modules can be integrated to form an independent part.

[0120] If the above functions are implemented in the form of software functional modules and sold or used as an independent product, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of this application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0121] The above are only the embodiments of this application and are not used to limit the protection scope of this application. For those skilled in the art, this application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included in the protection scope of this application. It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0122] The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application.

[0123] It should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, the elements defined by the statement "comprising..." do not exclude the existence of additional identical elements in the process, method, article or device comprising the said elements.

Claims

1. A data decoding method, characterized in that, the method includes: splitting the decoding process of target data in a channel into a first processing process and a second processing process; wherein, the target data includes current data and / or data to be processed; the first processing process includes a process of converting binary bits into byte data, and the second processing process includes a process of converting multiple byte data into data packets and submitting the data packets to a task layer; configuring a first type of interrupt mechanism of the first processing process as the highest priority, and configuring a second type of interrupt mechanism of the second processing process as the second highest priority; interrupting the second type of interrupt mechanism based on the first type of interrupt mechanism, so that the first processing process of the data to be processed is executed prior to the second processing process of the current data.

2. The method according to claim 1, characterized in that, the interrupting the second type of interrupt mechanism based on the first type of interrupt mechanism includes: if the first processing process of the current data is completed, determining whether there is data to be processed in the channel; if it is determined that there is data to be processed in the channel, then interrupting the second type of interrupt mechanism of the second processing process of the current data based on the first type of interrupt mechanism of the first processing process of the data to be processed, so that the first processing process of the data to be processed is executed prior to the second processing process of the current data.

3. The method according to claim 2, characterized in that, the interrupting the second type of interrupt mechanism based on the first type of interrupt mechanism further includes: writing first-way byte data obtained by the first processing process of the current data into a first buffer; writing second-way byte data obtained by the first processing process of the data to be processed into a second buffer.

4. The method according to claim 3, characterized in that, the interrupting the second type of interrupt mechanism based on the first type of interrupt mechanism further includes: reading the first-way byte data stored in the first buffer based on the second type of interrupt mechanism of the second processing process of the current data; executing the second processing process of the current data based on the first-way byte data; if it is determined that the second processing process of the current data is completed, then reading the second-way byte data stored in the second buffer based on the second type of interrupt mechanism of the second processing process of the data to be processed; executing the second processing process of the data to be processed based on the second-way byte data.

5. The method according to claim 3, characterized in that, wherein, the first processing time of the first processing process of the current data includes: a first conversion time of converting first binary bits into the first-way byte data, and a first buffering time of writing the first-way byte data into the first buffer; The second processing time of the first processing process of the data to be processed includes: the second conversion time for converting the second binary bit into the second path of byte data, and the second buffering time for writing the second path of byte data into the second buffer; Wherein, the sum of the first processing time and the second processing time is less than or equal to the edge-triggered interrupt average time of the decoding mode corresponding to the channel.

6. The method according to claim 5, characterized in that, wherein, the decoding mode includes: a double-edge decoding mode or a single-edge decoding mode.

7. The method according to any one of claims 1-6, characterized in that, the current data and the data to be processed are determined in the following manner: If the two paths of target data are not issued simultaneously, the target data with the earlier issuing time is used as the current data to be currently processed, and the target data with the later issuing time is used as the data to be processed. If the two paths of target data are issued simultaneously, any one of the target data is randomly selected as the current data to be currently processed, and the other path of target data is used as the data to be processed.

8. A data decoding device, characterized in that, the device includes: a splitting module, a configuration module, and a processing module; The splitting module is used to split the decoding process of the target data in the channel into a first processing process and a second processing process; wherein, the target data includes current data and / or data to be processed; the first processing process includes a processing process of converting binary bits into byte data, and the second processing process includes a processing process of converting multiple paths of byte data into data packets and submitting the data packets to the task layer; The configuration module is used to configure the first type of interrupt mechanism of the first processing process as the highest priority, and configure the second type of interrupt mechanism of the second processing process as the secondary priority; The processing module is used to interrupt the second type of interrupt mechanism based on the first type of interrupt mechanism, so that the first processing process of the data to be processed is executed prior to the second processing process of the current data.

9. An electronic device, characterized in that, the electronic device includes a memory and a processor, and program instructions are stored in the memory. When the processor runs the program instructions, the steps in the method according to any one of claims 1-7 are executed.

10. A computer-readable storage medium, characterized in that, computer program instructions are stored in the readable storage medium. When the computer program instructions are run by a processor, the steps in the method according to any one of claims 1-7 are executed.

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