Application method and device of compatible interconnected switch, storage medium and electronic device

Abstract

The present application discloses an application method and device of a compatible interconnected switch, a storage medium and an electronic device, and relates to the field of server technology. The method comprises the following steps: detecting the connection status of a target port and determining the input signal level of the target port; then, when the input signal level is a first level value, determining that the input and output components in the switch control board are in device connection mode, and being able to configure a semi-interconnected architecture mode for the mounted device for the switch; and when the input signal level is a second level value, determining that the input and output components in the switch control board are in switch connection mode, and being able to configure a fully interconnected architecture mode for the switch, thereby solving the technical problem of insufficient compatibility between high-speed interconnection and flexible configuration of mounted devices between switches, and achieving the technical effect of being able to adaptively switch port configuration according to the input signal level, and being compatible with the semi-interconnected architecture of the mounted device and the fully interconnected architecture between switches.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to an application method and device for a compatible interconnected switch, a storage medium, and an electronic device. Background Art

[0002] With the surge in demand for AI computing, interconnection technology between GPUs (graphics processing units) and NICs (network interface controllers) in high-performance computing servers has become crucial for improving overall system efficiency. Traditional interconnect architectures connect GPUs and NICs to the CPU (central processing unit) via the PCIe bus (a high-speed serial computer interconnect express standard). However, this architecture suffers from communication bottlenecks and latency issues when processing large-scale parallel tasks. The fully interconnected architecture, by directly connecting SWs (switches) to form a PCIe fabric network, significantly improves inter-device communication efficiency and data processing speed.

[0003] However, in a standard fully interconnected architecture, to ensure high-speed communication between any two devices, a large number of downstream ports originally used to connect devices are converted into fabric ports for inter-SW interconnection, limiting the number of GPUs and NICs that can be mounted. Furthermore, different customers have varying requirements for GPU and NIC configurations, requiring the ability to maintain interconnection between some SWs while allowing other SW ports to mount more NICs to meet their specific network communication needs. This means that existing technologies lack compatibility between high-speed inter-SW interconnection and the flexible configuration of mounted devices (such as GPUs and NICs). Summary of the Invention

[0004] The present application provides an application method and device for a compatible interconnected switch, a storage medium, and an electronic device to at least solve the technical problem in the related art of insufficient compatibility between high-speed interconnection between SWs and flexible configuration of mounted devices (such as GPUs and NICs) in a fully interconnected architecture AI server.

[0005] The present application provides an application method of a compatible interconnected switch, comprising: detecting the connection status of a target port on a switch control board; determining an input signal level of the target port based on the detected connection status of the target port; when the input signal level is a first level value, determining that an input / output component in the switch control board is in a device connection mode, and managing and configuring a target device connected to the target port, wherein the target device is connected to the switch control board via a target connection device; when the input signal level is a second level value, determining that the input / output component in the switch control board is in a switch connection mode, and the switch control board and a reference switch control board communicate through their respective target ports.

[0006] The present application also provides an application device of a compatible interconnected switch, including: a detection module, used to detect the connection status of a target port on a switch control board; a first determination module, based on the detected connection status of the target port, determining the input signal level of the target port; a second determination module, used to determine that the input and output components in the switch control board are in a device connection mode when the input signal level is a first level value, and manage and configure the target device connected to the target port, wherein the target device is connected to the switch control board through a target connection device; a third determination module, used to determine that the input and output components in the switch control board are in a switch connection mode when the input signal level is a second level value, and the switch control board and the reference switch control board communicate through their respective target ports.

[0007] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned application methods of the compatible interconnected switch when executing the computer program.

[0008] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of the application method of any of the above-mentioned compatible interconnected switches are implemented.

[0009] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned application methods of the compatible interconnected switch when executed by a processor.

[0010] Through the present application, since the connection status of the target port is detected, the input signal level of the target port is determined; then, when the input signal level is a first level value, the input and output components in the switch control board are determined to be in device connection mode, and the switch can be configured with a semi-interconnected architecture mode for the mounted device; when the input signal level is a second level value, the input and output components in the switch control board are determined to be in switch connection mode, and the switch can be configured with a fully interconnected architecture mode, which solves the technical problem of insufficient compatibility between high-speed interconnection and flexible configuration of mounted devices between switches, and achieves the technical effect of being able to adaptively switch port configuration according to the input signal level, and being compatible with the semi-interconnected architecture of the mounted device and the fully interconnected architecture between switches. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0012] Figure 1 A schematic diagram of switch chip connections for an application method of a compatible interconnected switch provided in an embodiment of the present application;

[0013] Figure 2 A flowchart of an application method of a compatible interconnected switch provided in an embodiment of the present application;

[0014] Figure 3 A schematic diagram of a semi-interconnected architecture for an application method of a compatible interconnected switch provided in an embodiment of the present application;

[0015] Figure 4 A schematic diagram of a fully interconnected architecture for an application method of a compatible interconnected switch provided in an embodiment of the present application;

[0016] Figure 5 A circuit diagram of a switch and a device connected in a semi-interconnected architecture according to an application method of a compatible interconnected switch provided in an embodiment of the present application;

[0017] Figure 6 A circuit diagram of interconnection between switches in a fully interconnected architecture according to an application method of a compatible interconnected switch provided in an embodiment of the present application;

[0018] Figure 7 A flowchart of another method for applying a compatible interconnected switch provided in an embodiment of the present application;

[0019] Figure 8 A logical relationship diagram of an application method of a compatible interconnected switch provided in an embodiment of the present application;

[0020] Figure 9 A logical relationship diagram of another application method of a compatible interconnected switch provided in an embodiment of the present application;

[0021] Figure 10 A schematic diagram of a hardware interconnection topology provided in an embodiment of the present application;

[0022] Figure 11 is a structural diagram of an application device of a compatible interconnected switch according to an embodiment of the present application;

[0023] Figure 12 This is a structural diagram of an application electronic device of a compatible interconnected switch according to an embodiment of the present application. DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0025] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0026] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0027] like Figure 1 As shown, a PCIe switch chip connection diagram includes access device 130, which represents an external device connected to the PCIe switch system. This device can be a graphics card, network interface card, storage device, etc. Connector 160 is the physical connection point between the access device and the switch chip 110 and is responsible for transmitting data from the access device to the switch chip. Figure 1 The diagram includes two connectors 160, one located on the connection line between access device 130 and processor 120, indicating that both components are connected to the switch chip via their respective connectors. The switch chip 110 is the central component of the entire system, responsible for managing and controlling the flow of data between different devices. It can forward data from input devices to output devices, such as processors or memory, as needed. The switch chip 110 connects to various components, including connectors 160, memory 140, and controller 150, through multiple ports.

[0028] The memory 140 is a component in the system used to store data. It connects to the rest of the system through the switch chip 110, allowing data to be read and written. The processor 120 is a component that performs computing tasks. It connects to the rest of the system through the switch chip 110, allowing it to access data in the memory and perform processing operations. The controller 150 is the component responsible for management and control operations in the system. It communicates with the switch chip 110 and access devices through port information to coordinate data transmission and processing.

[0029] An embodiment of the present application provides an application method of a compatible interconnected switch, and the method is described in detail in conjunction with the execution flow of the application method of the compatible interconnected switch.

[0030] In order to more clearly understand the technical solutions provided by the embodiments of the present application, the key terms involved in the embodiments of the present application are first introduced here:

[0031] Switch: In this application, it can be expressed as a switch or a switch.

[0032] MCIO: Multi-Channel Input / Output, a high-speed signal connector used for PCIe signal transmission inside the chassis.

[0033] PCIe: Peripheral Component Interconnect Express, a high-speed signal used for high-speed transmission of I0 data within a computer system.

[0034] PCIe Switch: An I / O chip used to expand one set of PCIe signals into multiple sets of PCIe signals, used to expand CPU I / O resources.

[0035] PCIe Fabric interconnection: A technical means to realize the flow of PCIe data between SWs.

[0036] SW: In this application, it refers to PCIe Switch.

[0037] PCBA: Printed Circuit Board Assembly, circuit board.

[0038] CXL Switch: Compute Express Link Switch, a SW chip based on the CXL protocol.

[0039] FRU: Field Replaceable Unit, field replaceable unit.

[0040] Riser Card: expansion card.

[0041] CPLD (Complex Programmable Logic Device) is a complex digital integrated circuit and a type of programmable logic device (PLD).

[0042] BMC (Baseboard Management Controller) is a microcontroller that is usually integrated on the server motherboard.

[0043] A MUX (Multiplexer) is an electronic component or integrated circuit that can selectively switch multiple input signals to a single output channel.

[0044] CEM (Common Expansion Module) is a standard module interface design that is particularly suitable for expansion modules in high-performance computing and data center environments.

[0045] In this application, CEM SLOT refers to the slot on the riser card, which is used to install or connect external devices (such as GPU, NIC) to the PCIe bus of the server.

[0046] PERST (Peripheral Reset): Peripheral reset signal.

[0047] CLK BUFFER, clock buffer. CLK OE_N: Clock output enable signal. The Output Enable (OE) signal is a control signal used to turn on or off the signal output. O1 (Output 1) is an output signal or pin of CLKBUFFER, which represents the first output signal channel.

[0048] 100M Clock: 100 MHz clock signal, DP (Data Positive): represents the positive phase signal line in the differential pair, which carries the positive phase information of the 100 MHz clock signal, DN (Data Negative): represents the negative phase signal line in the differential pair, which carries the inverted phase signal of the clock signal.

[0049] I2C (Inter-Integrated Circuit): A serial bus protocol for simple bidirectional communication between microcontrollers and microprocessors. In this application, I2C is used to transmit control information, status information, or perform device management, such as transferring device configuration information between a riser card and a switch board.

[0050] BMC_I2C_FRU_SCL: The clock signal line used by the BMC to communicate with the FRU device through the I2C bus.

[0051] BMC_I2C_FRU_SDA: This is the data signal line used by the BMC to communicate with the FRU device through the I2C bus.

[0052] I2C_FRU_SCL / SDA is a set of I2C signal lines used to communicate with the Field Replaceable Unit (FRU).

[0053] The I2C_SLOT_SCL / SDA signals are associated with the I2C communication interface on the PCIe slot in server hardware and are used for communication between the server system (such as the BMC or CPLD) and devices installed in the PCIe slot (such as GPUs and NIC cards).

[0054] Slot Presence Signal (SLOT_PRSNT): A signal that detects whether a PCIe device (such as a GPU or NIC) is correctly inserted into a slot on the motherboard.

[0055] Riser in-position signal (RISER_PRSNT): used to detect whether the riser card is inserted into the specific position on the SW board.

[0056] THROTTLE: Throttling signal. Used to control the data transmission rate of the device.

[0057] Bandwidth ID (BW_ID): Bandwidth identification signal, a signal used to identify the PCIe bandwidth level supported by the device.

[0058] SW_MODE: The switch mode signal, used to indicate whether the SW port should be configured in fabric mode or downlink port mode.

[0059] MUX_SEL: Multiplexer select signal. Used to control the signal selection of the MUX (multiplexer). Based on the MUX_SEL signal, the MUX can switch different signal paths to ensure that the correct signal reaches the target port and avoid signal shorts or conflicts.

[0060] BW_MODE: Bandwidth mode signal. Used to inform SW how to configure its port bandwidth, such as x8 or x16.

[0061] Surelink Cable is a connection cable specially designed for high reliability and high performance computing environments. It is mainly used for high-speed signal transmission within or between servers.

[0062] As an optional implementation, Figure 2 As shown, the application method of the above-mentioned compatible interconnect switch includes:

[0063] S202, detecting the connection status of the target port on the switch control board;

[0064] Optionally, the switch control board may specifically be a PCIe Switch, and the connection status of the target port includes idle (unconnected) or non-idle (connected), which may be a detection of a device connected to the switch.

[0065] S204, determining an input signal level of the target port based on the detected connection status of the target port;

[0066] Optionally, once a physical connection is detected at the target port, the system will further check the level status of the input signal. By judging the level of the input signal, the system can distinguish whether the device is a riser card, a NIC, a GPU, or another switch control board.

[0067] S206, when the input signal level is the first level value, determining that the input / output component in the switch control board is in device connection mode, and managing and configuring the target device connected to the target port, wherein the target device is connected to the switch control board via the target connection component;

[0068] Alternatively, if the input signal indicates a first level (e.g., a low level L), the system determines that the target port is in a device-mounted state, such as a GPU or NIC. Furthermore, the MUX is configured in A=C mode (signal conduction), allowing the device and its functional signals (e.g., PERST, 100M CLOCK, etc.) to interact with the switch control board.

[0069] like Figure 3 As shown in the "semi-interconnected" topology diagram with GPU:NIC=2:1, each switch SW consumes 2 x16 ports for interconnection between SWs (as shown by port F in the figure), and then removes one uplink port (as shown by port H in the figure) for connection with the CPU. There are 6 x16 ports in a 144-lane SW chip that can be used to mount GPUs / NICs (as shown by port D in the figure), realizing 2 ports for mounting NICs and 4 ports for mounting GPUs.

[0070] S208 , when the input signal level is the second level value, determining that the input and output components in the switch control board are in switch connection mode, and the switch control board and the reference switch control board communicate through their respective target ports.

[0071] Alternatively, if the input signal is at the second level (e.g., high), the system determines that the target port is in the SW interconnect state (Fabric mode). Furthermore, the MUX configuration is set to B=C mode (signal blocking), ensuring that only PCIe high-speed signals are transmitted through the interconnect cable, avoiding interference from other auxiliary signals.

[0072] like Figure 4The topology shown builds a data bridge between any two SWs, avoiding the P2P performance loss caused by data bypassing the CPU. Specifically, three x16 ports are consumed for interconnection between SWs (as shown in port F in the figure), and one uplink port (as shown in port H in the figure) is removed for connection to the CPU. Five x16 ports in a 144-lane SW chip can be used to mount GPUs / NICs (as shown in port D in the figure).

[0073] Through the above-mentioned implementation mode recorded in the present application, the input signal level of the target port is determined by detecting the connection status of the target port; then, when the input signal level is a first level value, the input and output components in the switch control board are determined to be in device connection mode, and the switch can be configured with a semi-interconnected architecture mode for the mounted device; when the input signal level is a second level value, the input and output components in the switch control board are determined to be in switch connection mode, and the switch can be configured with a fully interconnected architecture mode, which solves the technical problem of insufficient compatibility between high-speed interconnection and flexible configuration of mounted devices between switches, and achieves the technical effect of being able to adaptively switch port configuration according to the input signal level, and being compatible with the semi-interconnected architecture of the mounted device and the fully interconnected architecture between switches.

[0074] In an optional implementation, determining the input signal level of the target port based on the detected connection status of the target port includes:

[0075] S1, determining that the input signal level of the target port is a first level value when the level signal detection pin detects that the presence detection circuit is turned on, wherein the level signal detection pin is inside the target port, and the presence detection circuit is used to detect the presence state of the target connection device;

[0076] S2: When the level signal detection pin detects that the presence detection circuit is disconnected, determining that the input signal level of the target port is a second level value.

[0077] In the above step S1, Figure 5 As shown, MCIO defines signals based on the requirements of the downstream riser. These signals primarily include PCIe x16 high-speed signals, PERST, 100M CLOCK, two I2C channels, slot in place, riser in place, bandwidth ID, and throttle. Each signal is defined on the corresponding connector pin (as shown on the MCIO pin in the figure). It should be noted that the riser card is a solderable board, and the signal mapping between the board-side MCIO and the line-side MCIO is A to A and B to B.

[0078] The aforementioned level signal detection pin is the MCIO A9 pin, which is used to monitor whether a riser card or device (such as a GPU or NIC) is actually inserted into the target port (such as PE2 of SW0).

[0079] The above-mentioned presence detection circuit is used to identify the physical presence status of the target connection device (Riser card or Device). When the connection device is inserted, the circuit will be turned on and the level of the level signal detection pin will be pulled down to a first level value (such as low level L). For example Figure 5 After the in-position detection circuit is turned on, the riser card sends a RISER_PRSNT signal to the CPLD of the SW board through the A9 pin. That is, when the riser card is inserted, the above input signal level is a low-level signal.

[0080] Further in the above step S2, as Figure 6 As shown, the internal MCIO signal definition is the same as Figure 5 The same definition is in Figure 6 In this configuration, both SW0 PE2 and SW1 PE1 are fabric ports. SW0 PE2 must connect to SW3 PE1 on another SW board, and SW1 PE1 must connect to SW2 PE2 on another SW board, thus achieving a fully interconnected topology. When the MCIO ports on the two boards are interconnected via cable, the signal mapping is A to B and B to A.

[0081] The level signal detection pin A9 is connected to the suspended B9, and detects that the presence detection circuit is disconnected, and thus the input signal level is a high level signal.

[0082] Through the above-mentioned implementation method described in the present application, when the level signal detection pin detects that the in-position detection circuit is turned on, the input signal level of the target port is determined to be a first level value; when the level signal detection pin detects that the in-position detection circuit is turned off, the input signal level of the target port is determined to be a second level value. That is, by obtaining the riser in-position signal from the MCIOA9 pin to perform configuration judgment and then execute control of CLK and MUX, the signal output of CPDL under different configurations is determined, and the on-off of the circuit that transmits related signals under different configurations is controlled, thereby ensuring the normal operation of the system without adding special cables and achieving the technical effect of compatibility with different configurations.

[0083] In an optional implementation, when the level signal detection pin detects that the presence detection circuit is turned on, determining that the input signal level of the target port is a first level value includes:

[0084] S1, determining that the presence detection circuit is turned on when it is detected that the pin connected to the level signal detection pin is the first pin, wherein one end of the first pin is grounded;

[0085] S2: The level of the input signal received by the target port is a first level value.

[0086] In the above step S1, Figure 5 The pin connected to the level signal detection pin is A9 in the riser card, ie, the first pin mentioned above, and one end of A9 is grounded.

[0087] Furthermore, in the above step S2, when the presence detection circuit is turned on due to the insertion of a device, the level signal detection pin will change from a high level to a low level, that is, the above first level value may be a low level.

[0088] Through the above-described implementation described in this application, upon detecting that the first pin (i.e., MCIO A9) connected to the level signal detection pin is conducting (i.e., the riser card is in place, with one end of the pin grounded through the riser card), the system can immediately identify that the riser card has been correctly inserted, thereby determining that the presence detection circuit is in the on state and further entering device connection mode. In this mode, the CPLD automatically executes control logic and configures components such as the MUX and CLK to ensure correct signal conduction and normal operation of the device. This avoids the need for additional hardware adjustments or special cables when switching between different configurations, simplifies system design, and improves mode switching flexibility.

[0089] In an optional implementation, when the level signal detection pin detects that the presence detection circuit is disconnected, determining that the input signal level of the target port is a second level value includes:

[0090] S1, determining that the presence detection circuit is disconnected when it is detected that the pin connected to the level signal detection pin is the second pin, wherein one end of the second pin is left floating;

[0091] S2: The level of the input signal received by the target port is a second level value.

[0092] In the above step S1, Figure 6 The pin connected to the level signal detection pin in the SW board 1 is B9 in the SW board 2, that is, the second pin mentioned above, and one end of B9 is set to be suspended.

[0093] Furthermore, in the above step S2, the pull-up resistor inside the SW board will stabilize the level of the level signal detection pin at a high level, that is, the above second level value may be a high level.

[0094] Through the above implementation described in this application, it is immediately recognized that the riser card is not inserted or has been removed, thereby determining that the in-place detection circuit is in a disconnected state and entering the switch full interconnection mode, which simplifies the system design and improves the flexibility of mode switching.

[0095] In an optional implementation manner, after determining that the input signal level of the target port is a first level value, the method includes:

[0096] S1, the controller in the switch control board outputs a first selection signal, wherein the first selection signal is used to indicate the connection strategy of the pins in the input and output components;

[0097] S2, determining that the input and output components in the switch control board are in device connection mode according to the first selection signal;

[0098] S3: Configure the target port to a downlink port mode based on the device connection mode, wherein the target port in the downlink port mode is used to connect to the target device.

[0099] In the above step S1, the above controller may be as follows Figure 5 The CPLD (Complex Programmable Logic Device) in the SW board has a default pull-up process on the CPLD input signal board. The first selection signal can be an indication of Figure 5 The selection of the signal path in the MUX1 in the SW board, the above-mentioned input and output components can be MUX1. By outputting the first selection signal, the system can enable a specific signal path to ensure that only signals related to device interaction can be correctly transmitted.

[0100] Further in the above step S2, for example, in the above device connection mode, Figure 5 Connecting the A-type pin and the C-type pin in MUX1 turns on the internal MUX1, and the same applies to MUX2. This ensures that after the device (such as GPU, NIC) is connected to the target port, it can receive all necessary control and clock signals, realizing plug-and-play of the device, improving the flexibility of system configuration and the efficiency of device use.

[0101] Optionally, in step S3, the target port is configured as the aforementioned downlink port mode, i.e., the mode for mounting a device, to ensure that the SW chip can correctly identify the function of the target port and execute corresponding firmware configuration to support normal communication and data exchange of the device.

[0102] In an optional implementation manner, after determining that the input signal level of the target port is the second level value, the method includes:

[0103] S1, the controller in the switch control board outputs a second selection signal, wherein the second selection signal is used to indicate the connection strategy of the pins in the input and output components;

[0104] S2, determining that the input and output components in the switch control board are in switch connection mode according to the second selection signal;

[0105] S3: configuring the target port to an interconnection port mode based on the switch connection mode, wherein the target port in the interconnection port mode is used to connect to the reference switch control board.

[0106] In the above step S1, the above controller may be as follows Figure 6 In the CPLD (Complex Programmable Logic Device) of the SW board, the second selection signal can be an indication such as Figure 6 Selection of the signal path in MUX1 in the SW board, the above-mentioned input and output components can be MUX1.

[0107] In the above step S2, for example, in the above switch connection mode, Figure 6 Connecting the C-type pin and the B-type pin in MUX1 disconnects the inside of MUX1, and the same applies to MUX2. That is, except for the necessary high-speed data signals, the connection of other signals will be isolated or blocked to adapt to the characteristics of the interconnection between SWs and to isolate related possible short-circuited signals.

[0108] Optionally, in step S3, the controller (CPLD) can notify the SW0 chip via the SW_MODE signal to configure the target port to interconnect port mode. This means that the target port will be used exclusively for point-to-point communication with other switch control boards (such as SW3), achieving smooth data flow in a fully interconnected architecture.

[0109] Through the above-mentioned implementation method recorded in this application, when it is detected that the target port will be used for interconnection between SWs, the CPLD will output a second selection signal to instruct the MUX to switch to the corresponding signal isolation mode. In this mode, the MUX only allows PCIe high-speed signals to pass through, and cuts off other control signals that may cause short circuits (such as PERST, 100M CLOCK, I2C, etc.), avoiding the risk of short circuits caused by different types of signals being connected via cable when interconnecting between SWs. This dynamic signal isolation and management mechanism effectively ensures the stable operation and efficient communication of the fully interconnected architecture AI server under different configurations, avoids signal conflicts at the hardware level, and improves the compatibility and flexibility of the system.

[0110] In an optional implementation, after configuring the target port to the downstream port mode based on the device connection mode, the method includes:

[0111] S1, a controller on a switch control board detects an online status of a target device through a first conducting circuit, wherein the target connecting device on the first conducting circuit is connected to the controller through an input / output component;

[0112] S2, when the controller receives a device online signal, it outputs a clock enable signal, wherein the clock enable signal is used to provide a data transmission synchronization signal for the target device.

[0113] The above steps S1-S2 are described in an optional embodiment. Figure 5 As shown in the figure, SLOT_PRSNT is in place and BW_ID (bandwidth ID) is sent by the Riser Card, which is then led to the SW board through the B11 and B8 pins, and further input to the CPLD after passing through MUX1, that is, the controller receives the device online signal.

[0114] Once the CPLD detects the device online signal, that is, the device is in place and active, it sends a clock enable signal to the CLK buffer. Figure 5 The CLK BUFFER shown is sent out and connected to the A11 / A12 pins. The port enable state of the CLK BUFFER is controlled by the CPLD.

[0115] Through the above-mentioned implementation method described in this application, the CPLD uses the first conduction circuit to detect the presence of the device, and then outputs a clock enable signal based on the detection result, thereby achieving precise signal control and synchronous activation of the device.

[0116] In an optional implementation, after the controller receives a device online signal and outputs a clock enable signal, the method includes:

[0117] S1, a reset signal output by the controller is transmitted to the third pin on the switch control board through the first conduction circuit, and is transmitted to the target device through a reference third pin of the same type as the third pin on the target connection device, wherein the target device performs a reset operation according to the reset signal;

[0118] S2, a function signal output by the controller is transmitted to the fourth pin on the switch control board through the first conduction circuit, and is transmitted to the target device through a reference fourth pin of the same type as the fourth pin on the target connection device, wherein the function signal is used to reduce power consumption of the target device;

[0119] S3, the reference controller on the switch control board transmits the target connection device communication signal to the fifth pin of the switch control board through the second conduction circuit, and transmits the target connection device communication signal to the target connection device through the reference fifth pin of the same type as the fifth pin on the target connection device, wherein the target connection device on the second conduction circuit is connected to the reference controller through the reference input and output component, and the target connection device communication signal is used to read the target connection device information of the target connection device;

[0120] S4, the reference controller on the switch control board transmits the device communication signal to the sixth pin of the switch control board through the second conduction circuit, and transmits it to the target device through the reference sixth pin of the same type as the sixth pin on the target connecting device, wherein the device communication signal is used to read the device information of the target device.

[0121] The above steps S1-S4 are described in an optional embodiment, as follows: Figure 5 The PERST signal shown is sent by the CPLD and sent to the MCIO A8 pin after MUX1, and finally to the CEM SLOT in the Riser Card, which is used to reset the target device connected to the slot. The THROTTLE signal is sent by the CPLD and sent to the MCIO B12 pin after MUX1, and finally to the CEM SLOT in the Riser Card, which is used to reduce the frequency and power consumption of the target device. Two I2C channels are connected to the FRU in the Riser Card for reading on-board FRU information and the CEM SLOT for reading device information. They are sent by the BMC, meaning that the reference controller mentioned above can be a BMC. After MUX2, they are connected to the MCIO A29 / A30 and B29 / B30 pins, and finally to the Riser Card.

[0122] Through this implementation, the device enters a stable state after reset, allowing further adjustments to its power consumption settings without causing system instability. After reading the target connected device information, the system can more accurately manage device communication signals, ensuring the accuracy and integrity of the information, thereby optimizing device configuration and resource allocation.

[0123] In an optional embodiment, the switch control board and the reference switch control board communicate via their respective target ports, including:

[0124] S1, sends a target data packet to a target port matching a reference switch control board through a target port matching a switch control board;

[0125] S2, determining a target receiving device based on a result of parsing the address identification information in the target data packet by the reference switch control board;

[0126] S3, forwards the target data packet to the target receiving device by referring to the receiving port on the switch control board that matches the target receiving device.

[0127] The following is a complete implementation of the above steps S1-S3. The above data packet contains the destination address, control information and actual data. Figure 4As shown, GPU0 on SW-0 needs to send data to GPU4 on SW-3. The target data packet will be sent through the downstream port of SW-0 connected to GPU0 to the fabric port on the SW board, and then transmitted to the fabric port of SW-3 through the Surelink cable.

[0128] When the target data packet arrives at SW-3, SW-3 will parse the address identification information (such as MAC address, IP address or device ID) in the data packet, and then determine which device is the final destination of the data packet based on the parsing result. For example, it is parsed that the above-mentioned target receiving device is GPU4; the target data packet is transmitted to GPU4 through the downstream port corresponding to GPU4.

[0129] In an optional embodiment, after determining that the input and output components in the switch control board are in device connection mode, the method includes:

[0130] S1, when it is detected that the bandwidth identifier of the target device corresponds to the first configuration condition, determining that the target device and the switch control board perform signal transmission through the first signal link;

[0131] S2. When it is detected that the bandwidth identifier of the target device corresponds to the second configuration condition, it is determined that the target device and the switch control board transmit signals through a second signal link, wherein the number of data channels in the second signal link is greater than the number of data channels in the first signal link.

[0132] Optionally, in step S1, the first configuration condition may be that the target device requires x8 bandwidth. When the CPLD detects that the bandwidth identifier (e.g., BW ID) signal meets the first configuration condition, it can configure the SW (switch) port to a x8 signal link via control signals such as MUX_SEL and OE_N to accommodate the device's lower bandwidth requirements. This allows the system to automatically adjust the signal link width to match the electrical characteristics of the x8 bandwidth, for example, by reducing the frequency of the clock signal and isolating unnecessary signal lines.

[0133] Optionally, in step S2, the second configuration condition can be that the target device requires x16 bandwidth. When the CPLD detects the bandwidth identifier (e.g., BW ID) indicating that the device requires x16 bandwidth, it configures the SW port as a x16 signal link. This activates all 16 data channels of the SW, providing a higher data transfer rate. Simultaneously, the SW's CLKBUFFER outputs a clock signal that matches the x16 bandwidth requirement, ensuring data transmission integrity and synchronization.

[0134] Through the implementation described in this application, triggered by the target device's BW ID signal, the CPLD automatically selects configuration steps to adapt to the device's bandwidth requirements based on the signal's high or low level. This dynamic configuration capability enables the system to intelligently adapt to the performance requirements of different devices without requiring human intervention or physical layer changes, greatly improving system flexibility and configuration compatibility.

[0135] The following describes this application in a complete implementation manner:

[0136] As the flow chart Figure 7 As shown: S702 is executed first, is RISER_PRSNT low?

[0137] When RISER_PRSNT is low, RISER_PRSNT = L indicates that the riser is in place. S704 is executed, SW_MODE output is low, and MUX_SEL output is low. S706 configures SW0_PE2 as a downstream port, and MUX: A = C (signal on).

[0138] The process then proceeds to S708 : Is SLOT_PRSNT low? If SLOT_PRSNT is high, it indicates that the device is not mounted, and the process ends.

[0139] If SLOT_PRSNT is low, it indicates that the device has been mounted and continues to execute S710. CLK_OE_N output is low, specifically 100M CLK Enable. Determine S712, is BW_ID low? If BW_ID is low, execute S714-1, BW_MODE output is low, and SW0_PE2 is configured to x16. Otherwise, execute S714-2, BW_MODE output is high, and SW0_PE2 is configured to x8x8. The corresponding logical relationship is as follows: Figure 8 shown.

[0140] When RISER_PRSNT is high, S716 is executed, SW_MODE output is high; MUX_SEL output is high. S718, SW0_PE2 is configured as Fabric; MUX: B=C (signal truncation). It should also be noted that CLK_OE_N output is high, specifically 100M CLK Disable. The corresponding logical relationship is as follows: Figure 9 shown.

[0141] A schematic diagram of a hardware interconnection topology corresponding to the embodiment of this application is as follows Figure 10As shown in the figure, there are two PCIe switches (SW0 and SW1). Each is connected to a CPU and multiple MCIO modules for signal transmission. It can be connected to a slot for mounting devices, and can also be used to connect the motherboard to the PCIe switch (SW) board, and between SW boards through Surelink cables for high-speed, low-latency PCIe fabric interconnection.

[0142] Each CPU is connected to a SW, forming an uplink port. For example, CPU0 is connected to PE0 on SW0, while CPU1 is connected to PE3 on SW1. This ensures that the CPU can interact directly with the SW, controlling the global resource allocation of the AI ​​server.

[0143] Fabric ports interconnect SW0 and SW1, as well as SWs on another layer (SW2 and SW3). SW0's PE1, PE2, and PE3 ports connect to SW2's PE1, SW3's PE1, and SW1's PE0, respectively. SW1's PE0, PE1, and PE2 ports connect to SW0's PE3, SW2's PE2, and SW3's PE2, respectively. This cross-connection creates an efficient, fully interconnected network, allowing direct communication between any two GPUs or NICs, significantly reducing data transmission latency and improving P2P communication performance.

[0144] The downstream ports of the switch (such as PE4 to PE8 on SW0 and PE4 to PE8 on SW1) are used to mount GPUs and NICs. Each port can carry a x16 device, such as a GPU or NIC, and connects to the corresponding riser board through the MCIO module, enabling flexible device expansion and signal adaptation.

[0145] The riser board acts as a bridge between the SW and the device, receiving signals from the SW through the MCIO module and forwarding them to the GPU or NIC. The MCIO port inside the riser board matches the MCIO port signal on the device, ensuring correct signal transmission.

[0146] Fabric ports only transmit PCIe high-speed signals, while upstream and downstream ports contain more functional signals, such as PERST, 100M CLOCK, I2C, in-position signals, etc. Through the signal processing of MCIO module and Riser board, it ensures the smooth operation of different configurations (such as Figure 3 The semi-interconnected architecture shown, Figure 4Furthermore, this application uses slot presence and BW ID signals to enable SW to simultaneously support x8x8 devices (network cards / GPUs), further expanding configuration compatibility.

[0147] Through the above-described implementation of the present application, the MCIO signals are arranged. The CPLD determines configuration based on the high and low level status of the Riser in-position signal, and controls the MUX and buffer via the MUX_SEL and OE_N signals, thereby physically isolating the MCIO-related signals. Furthermore, the CPLD uses the SW_MODE signal to notify the SW to synchronously execute the FW switch (switching SW port attributes such as fabric or downlink requires the use of the corresponding FW file). This achieves switching and compatibility of the PE2 port configuration, allowing the PE2 port to be selected for connection to devices or interconnection with switches. It should be noted that the same configuration can be applied to multiple ports in the same manner, increasing the flexibility and diversity of the topology.

[0148] According to another aspect of an embodiment of the present application, a switch compatible with interconnection is provided, including:

[0149] The switch control board includes a connector, a controller, a reference controller, an input / output component, a reference input / output component, a clock buffer, and at least one port. The connector is used to transmit signals to devices connected to the switch control board. The controller is used to output corresponding control signals based on the received signal level. The input / output component, the reference input / output component, and the clock buffer respectively determine their respective output signals based on the control signal.

[0150] Alternatively, as Figure 5 The switch control board (SW board) shown in the figure has the connector as MCIO, the controller as CPLD, the reference controller as BMC, the input and output component as MUX1, the reference input and output component as MUX2, the clock buffer as CLK BUFFER, and at least one port. Figure 5 The following example uses the PE2 port on SW0 as an example.

[0151] The connector is connected to the controller through input and output components, target ports and clock buffers respectively;

[0152] Alternatively, as Figure 5 In the SW board shown, the pins on MCIO are connected to the pins on one side of MUX1, and the pins on the other side of MUX1 are connected to the pins on the CPLD. Similarly, MCIO can also be connected to the CPLD through PE2, and MCIO can also be connected to the CPLD through CLK BUFFER.

[0153] The reference controller is connected to the connector via the reference input and output components.

[0154] Alternatively, as Figure 5 In the SW board shown, the BMC pins are connected to the pins on one side of MUX2, and the pins on the other side of MUX2 are connected to the pins on MCIO.

[0155] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0156] According to another aspect of the embodiment of the present application, there is also provided a device for applying a compatible interconnected switch for implementing the above-mentioned method for applying a compatible interconnected switch. Figure 11 As shown, the device includes:

[0157] Detection module 1102, used to detect the connection status of the target port on the switch control board;

[0158] A first determining module 1104 determines an input signal level of the target port based on the detected connection status of the target port;

[0159] a second determining module 1106 configured to, when the input signal level is a first level value, determine that the input / output component in the switch control board is in a device connection mode, and manage and configure a target device connected to the target port, wherein the target device is connected to the switch control board via a target connection component;

[0160] The third determining module 1108 is configured to determine that the input and output components in the switch control board are in switch connection mode when the input signal level is a second level value, and the switch control board and the reference switch control board communicate through their respective target ports.

[0161] Optionally, the above-mentioned first determination module includes: a fourth determination unit, used to determine that the input signal level of the target port is a first level value when the level signal detection pin detects that the in-place detection circuit is turned on, wherein the level signal detection pin is inside the target port, and the in-place detection circuit is used to detect the in-place state of the target connection device; when the level signal detection pin detects that the in-place detection circuit is disconnected, determine that the input signal level of the target port is a second level value.

[0162] Optionally, the above-mentioned fourth determination unit includes: a first detection unit, used to determine that the in-place detection circuit is turned on when it is detected that the pin connected to the level signal detection pin is the first pin, wherein one end of the first pin is grounded; the input signal level received by the target port is the first level value.

[0163] Optionally, the above-mentioned fourth determination module also includes: a second detection unit, used to determine that the in-place detection circuit is disconnected when it is detected that the pin connected to the level signal detection pin is the second pin, wherein one end of the second pin is left floating; and the input signal level received by the target port is the second level value.

[0164] Optionally, the above-mentioned first detection unit includes: a first output unit, used for the controller in the switch control board to output a first selection signal, wherein the first selection signal is used to indicate the connection strategy of the pins in the input and output components; determining that the input and output components in the switch control board are in device connection mode according to the first selection signal; and configuring the target port to a downstream port mode based on the device connection mode, wherein the target port in the downstream port mode is used to connect to the target device.

[0165] Optionally, the above-mentioned second detection unit includes: a second output unit, used for the controller in the switch control board to output a second selection signal, wherein the second selection signal is used to indicate the connection strategy of the pins in the input and output components; determining that the input and output components in the switch control board are in switch connection mode based on the second selection signal; configuring the target port to the interconnection port mode based on the switch connection mode, wherein the target port in the interconnection port mode is used to connect to the reference switch control board.

[0166] Optionally, the above-mentioned first output unit is also used to detect the online status of the target device through the first conductive circuit in the controller on the switch control board, wherein the target connecting device on the first conductive circuit is conductively connected to the controller through the input and output components; when the controller receives the device online signal, it outputs a clock enable signal, wherein the clock enable signal is used to provide a data transmission synchronization signal for the target device.

[0167] Optionally, the above-mentioned first output unit is also used to transmit the reset signal output by the controller to the third pin on the switch control board through the first conduction circuit, and transmit it to the target device through the reference third pin of the same type as the third pin on the target connection device, wherein the target device performs a reset operation according to the reset signal; the function signal output by the controller is transmitted to the fourth pin on the switch control board through the first conduction circuit, and transmitted to the target device through the reference fourth pin of the same type as the fourth pin on the target connection device, wherein the function signal is used to reduce power consumption for the target device; the reference controller on the switch control board transmits the target connection device through the second conduction circuit The communication signal is transmitted to the fifth pin of the switch control board, and is transmitted to the target connection device through the reference fifth pin of the same type as the fifth pin on the target connection device, wherein the target connection device on the second conduction circuit is connected to the reference controller through the reference input and output component, and the target connection device communication signal is used to read the target connection device information of the target connection device; the reference controller on the switch control board transmits the device communication signal to the sixth pin of the switch control board through the second conduction circuit, and is transmitted to the target device through the reference sixth pin of the same type as the sixth pin on the target connection device, wherein the device communication signal is used to read the device information of the target device.

[0168] Optionally, the above-mentioned third determination module includes a communication unit, which is used to send a target data packet to a target port matching a reference switch control board through a target port matching the switch control board; determine a target receiving device based on the parsing result of the address identification information in the target data packet by the reference switch control board; and forward the target data packet to the target receiving device through a receiving port on the reference switch control board that matches the target receiving device.

[0169] Optionally, the above-mentioned second determination module is also used to determine that the target device and the switch control board perform signal transmission through the first signal link when it is detected that the bandwidth identifier of the target device corresponds to the first configuration condition; and to determine that the target device and the switch control board perform signal transmission through the second signal link when it is detected that the bandwidth identifier of the target device corresponds to the second configuration condition, wherein the number of data channels in the second signal link is greater than the number of data channels in the first signal link.

[0170] For descriptions of features in the embodiments corresponding to the application device of the compatible interconnected switch, reference may be made to the relevant descriptions of the embodiments corresponding to the application method of the compatible interconnected switch, which will not be described in detail here.

[0171] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned application method embodiments of the compatible interconnected switch.

[0172] The electronic device used in this application can be a terminal device or a server. This embodiment takes the electronic device as a mobile phone or a computer as an example. Figure 12 As shown, the electronic device includes a memory 1202 and a processor 1204. The memory 1202 stores a computer program, and the processor 1204 is configured to execute the steps in any of the above method embodiments through the computer program.

[0173] Optionally, in this embodiment, the electronic device may be located in at least one network device among a plurality of network devices of a computer network.

[0174] Alternatively, those skilled in the art will appreciate that Figure 12 The structure shown is for illustration only, and the electronic device may also be a smart phone (such as an Android phone, an iOS phone, etc.), a tablet computer, a PDA, a mobile Internet device (MID), a PAD, or other terminal devices. Figure 12 It does not limit the structure of the above electronic device. For example, the electronic device may also include Figure 12 More or fewer components (such as network interfaces, etc.) as shown in, or with Figure 12 Different configurations shown.

[0175] Among them, the memory 1202 can be used to store software programs and modules, such as the program instructions / modules corresponding to the application method and device of the compatible interconnected switch in the embodiment of the present application. The processor 1204 executes various functional applications by running the software programs and modules stored in the memory 1202, that is, realizes the application method of the compatible interconnected switch mentioned above. The memory 1202 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 1202 may further include a memory remotely located relative to the processor 1204, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned networks include but are not limited to the Internet, corporate intranets, local area networks, mobile communication networks and combinations thereof. Among them, the memory 1202 can be used for storing signals, data and other information, but is not limited to it. As an example, if Figure 12 As shown, the memory 1202 may include, but is not limited to, the detection module 1102, the first determination module 1104, the second determination module 1106, and the third determination module 1108 in the application device of the compatible interconnected switch. Furthermore, the memory 1202 may also include, but is not limited to, other module units in the application device of the compatible interconnected switch, which will not be described in detail in this example.

[0176] Optionally, the transmission device 1206 is configured to receive or transmit data via a network. Specific examples of the aforementioned network may include wired networks and wireless networks. In one embodiment, the transmission device 1206 includes a network interface controller (NIC), which can be connected to other network devices and a router via a network cable to enable communication with the Internet or a local area network. In one embodiment, the transmission device 1206 is a radio frequency (RF) module configured to communicate with the Internet wirelessly.

[0177] In addition, the electronic device further includes: a display 1208; and a connection bus 1210 for connecting various module components in the electronic device.

[0178] In other embodiments, the terminal device or server may be a node in a distributed system, wherein the distributed system may be a blockchain system, and the blockchain system may be a distributed system formed by connecting multiple nodes via network communication. The nodes may form a point-to-point network, and any computing device, such as a server, terminal, or other electronic device, may become a node in the blockchain system by joining the point-to-point network.

[0179] An embodiment of the present application further provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned embodiments of the application method of the compatible interconnected switch when running.

[0180] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0181] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned application method embodiments of the compatible interconnected switch are implemented.

[0182] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps in any of the above-mentioned application method embodiments of the compatible interconnected switch.

[0183] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0184] The above describes in detail the application method and device, storage medium, and electronic device of a compatible interconnected switch provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core concept of the present application. It should be noted that, for those skilled in the art, several improvements and modifications can be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A method for applying a compatible interconnected switch, characterized in that: include: Check the connection status of the target port on the switch control board; Determining the input signal level of the target port based on the detected connection state of the target port, including: determining that a presence detection circuit is turned on when detecting that the pin connected to the level signal detection pin is a first pin, wherein one end of the first pin is grounded, the level signal detection pin is inside the target port, and the presence detection circuit is used to detect the presence state of the target connection device; and the input signal level received by the target port is a first level value; The controller in the switch control board outputs a first selection signal, wherein the first selection signal is used to indicate a connection strategy of pins in an input / output component; determining that the input / output component in the switch control board is in a device connection mode according to the first selection signal; and configuring the target port to a downstream port mode based on the device connection mode, wherein the target port in the downstream port mode is used to connect to a target device; When the input signal level is a first level value, determining that the input and output components in the switch control board are in a device connection mode, and managing and configuring a target device connected to the target port, wherein the target device is connected to the switch control board via a target connection device; When the input signal level is a second level value, the input and output components in the switch control board are determined to be in switch connection mode, and the switch control board and the reference switch control board communicate through their respective target ports.

2. The application method of the compatible interconnected switch according to claim 1, characterized in that: The step of determining the input signal level of the target port based on the detected connection status of the target port further includes: In a case where the level signal detection pin detects that the presence detection circuit is disconnected, it is determined that the input signal level of the target port is a second level value.

3. The application method of the compatible interconnected switch according to claim 2, characterized in that: The step of determining that the input signal level of the target port is a second level value when the level signal detection pin detects that the presence detection circuit is disconnected includes: determining that the presence detection circuit is disconnected when it is detected that the pin connected to the level signal detection pin is the second pin, wherein one end of the second pin is left floating; The level of the input signal received by the target port is the second level value.

4. The application method of the compatible interconnected switch according to claim 3, characterized in that: After determining that the input signal level of the target port is a second level value, the method further includes: The controller in the switch control board outputs a second selection signal, wherein the second selection signal is used to indicate a connection strategy of the pins in the input and output components; determining, according to the second selection signal, that the input and output components in the switch control board are in the switch connection mode; The target port is configured as an interconnect port mode based on the switch connection mode, wherein the target port in the interconnect port mode is used to connect to the reference switch control board.

5. The application method of the compatible interconnected switch according to claim 1, characterized in that: After configuring the target port to the downlink port mode based on the device connection mode, the method includes: The controller on the switch control board detects the online status of the target device through a first conductive circuit, wherein the target connection device on the first conductive circuit is conductively connected to the controller through the input and output component; When the controller receives a device online signal, it outputs a clock enable signal, wherein the clock enable signal is used to provide a data transmission synchronization signal for the target device.

6. The application method of the compatible interconnected switch according to claim 5, characterized in that: After the controller receives the device online signal and outputs the clock enable signal, the method includes: The reset signal output by the controller is transmitted to the third pin on the switch control board through the first conduction circuit, and is transmitted to the target device through a reference third pin of the same type as the third pin on the target connection device, wherein the target device performs a reset operation according to the reset signal; The function signal output by the controller is transmitted to the fourth pin on the switch control board through the first conduction circuit, and is transmitted to the target device through a reference fourth pin of the same type as the fourth pin on the target connection device, wherein the function signal is used to reduce power consumption of the target device; The reference controller on the switch control board transmits the target connection device communication signal to the fifth pin of the switch control board through the second conduction circuit, and transmits the target connection device communication signal to the target connection device through the reference fifth pin of the same type as the fifth pin on the target connection device, wherein the target connection device on the second conduction circuit is connected to the reference controller through the reference input and output component, and the target connection device communication signal is used to read the target connection device information of the target connection device; The reference controller on the switch control board transmits the device communication signal to the sixth pin of the switch control board through the second conduction circuit, and transmits it to the target device through a reference sixth pin of the same type as the sixth pin on the target connection device, wherein the device communication signal is used to read the device information of the target device.

7. The application method of the compatible interconnected switch according to claim 1, characterized in that: The switch control board and the reference switch control board communicate with each other through their respective target ports, including: Sending a target data packet to the target port matching the reference switch control board via the target port matching the switch control board; Determining a target receiving device based on a result of parsing the address identification information in the target data packet by the reference switch control board; The target data packet is forwarded to the target receiving device through a receiving port on the reference switch control board that matches the target receiving device.

8. The application method of the compatible interconnected switch according to claim 1, characterized in that: After determining that the input and output components in the switch control board are in device connection mode, the method includes: When it is detected that the bandwidth identifier of the target device corresponds to the first configuration condition, determining that the target device and the switch control board perform signal transmission through the first signal link; When it is detected that the bandwidth identifier of the target device corresponds to the second configuration condition, it is determined that the target device and the switch control board transmit signals through a second signal link, wherein the number of data channels in the second signal link is greater than the number of data channels in the first signal link.

9. A switch compatible with interconnection, characterized in that: include: The switch control board includes a connector, a controller, a reference controller, an input / output component, a reference input / output component, a clock buffer, and at least one port. The connector is used to transmit signals to devices connected to the switch control board. The controller is used to output corresponding control signals according to the received signal level. The input / output component, the reference input / output component, and the clock buffer respectively determine their respective output signals according to the control signal. The connector is connected to the controller through the input and output components, the target port and the clock buffer respectively; The reference controller is connected to the connector via the reference input and output component; When the pin connected to the level signal detection pin inside the target port is the first pin, it is determined that the in-position detection circuit is turned on; the input signal level received by the target port is a first level value; the controller outputs a first selection signal, wherein the first selection signal is used to indicate the connection strategy of the pins in the input-output component; the input-output component is determined to be in device connection mode according to the first selection signal; based on the device connection mode, the target port is configured to be in downstream port mode, wherein the target port in the downstream port mode is used to connect to a target device.

10. An application device for a compatible interconnected switch, characterized in that: include: A detection module, used to detect the connection status of the target port on the switch control board; A first determining module determines, based on the detected connection status of the target port, an input signal level of the target port, including: determining that a presence detection circuit is turned on when it is detected that the pin connected to the level signal detection pin is a first pin, wherein one end of the first pin is grounded, the level signal detection pin is inside the target port, and the presence detection circuit is used to detect the presence status of the target connection device; and the input signal level received by the target port is a first level value; The controller in the switch control board outputs a first selection signal, wherein the first selection signal is used to indicate a connection strategy of pins in an input / output component; determining that the input / output component in the switch control board is in a device connection mode according to the first selection signal; and configuring the target port to a downstream port mode based on the device connection mode, wherein the target port in the downstream port mode is used to connect to a target device; a second determining module, configured to, when the input signal level is a first level value, determine that the input / output component in the switch control board is in a device connection mode, and manage and configure a target device connected to the target port, wherein the target device is connected to the switch control board via a target connection device; The third determination module is used to determine that the input and output components in the switch control board are in switch connection mode when the input signal level is a second level value, and the switch control board and the reference switch control board communicate through their respective target ports.

11. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the method for applying the compatible interconnected switch according to any one of claims 1 to 8 when executing the computer program.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the application method of the compatible interconnection switch according to any one of claims 1 to 8 are implemented.

13. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the application method of the compatible interconnection switch according to any one of claims 1 to 8 are implemented.

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