Communication interface reading control method, device, chip and system

Abstract

The present application relates to a method, device, chip, and system for controlling the reading of a communication interface. The method obtains channel configuration parameters sent by a host computer, performs initialization according to the channel configuration parameters, and communicates with the target channel based on a read trigger mode when it is determined that the read trigger condition of the target channel has been met. The method also cyclically reads the data returned by the target channel based on a cyclic read count threshold, records the number of reads, and then returns a first response message to the host computer when it is determined that the number of reads has reached the cyclic read count threshold. By configuring the cyclic read count threshold for each channel, the method can continuously read data from the channel based on the cyclic read count threshold, thereby avoiding the frequent sending of instructions, saving master control resources, and reducing the number of master control interrupts.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a reading control method, device, chip and system for a communication interface. Background Art

[0002] Communication interfaces are essential in chip design. Common communication interfaces include the Serial Peripheral Interface (SPI), a synchronous peripheral interface, and the Inter-Integrated Circuit (IIC) bus interface, which are often used for communication between a single host and multiple slaves.

[0003] In traditional technology, a master and multiple slaves are connected to a communication interface bus (such as SPI or IIC). The master accesses the slave registers through a single read or write operation. During the communication process between the master and each slave, the master must issue bus control to the corresponding slave for each read or write operation.

[0004] However, for scenarios that require continuous parameter reading, the host needs to frequently send instructions through the bus, which occupies a large amount of master control resources and has low reading efficiency. Summary of the Invention

[0005] Based on this, it is necessary to provide a reading control method, device, chip and system for a communication interface that can improve reading efficiency in order to address the above technical problems.

[0006] In a first aspect, the present application provides a method for controlling reading of a communication interface, the method comprising:

[0007] Obtain channel configuration parameters sent by the host computer and initialize according to the channel configuration parameters; the channel configuration parameters include read trigger modes and cycle read count thresholds of at least two target channels, the read trigger modes of different target channels being the same or different, and the read trigger modes having corresponding read trigger conditions;

[0008] When it is determined that the read trigger condition of the target channel is met, communicating with the target channel based on the read trigger mode, cyclically reading data returned by the target channel based on the communication and the cyclic read count threshold, and recording the read count;

[0009] When it is determined that the number of reads reaches the cyclic read number threshold, a first response message is returned to the host computer.

[0010] In one embodiment, after cyclically reading the data returned by the target channel based on the communication and the cyclic read number threshold, the method further includes: storing the data read each time in a cache space corresponding to the target channel, the cache space being a storage space pre-allocated for each channel, and the cache spaces of different channels are independent of each other.

[0011] In one embodiment, the channel configuration parameters also include data transfer conditions for each target channel; after storing the data read each time in the cache space corresponding to the target channel, the method further includes: when it is determined that the data transfer conditions for the target channel are met, transferring the data in the cache space of the target channel to an external memory.

[0012] In one embodiment, when the read trigger mode is a timed trigger mode, the read trigger condition includes a corresponding trigger interval duration; the method further includes: when it is determined that the number of reads has not reached the cyclic read number threshold, starting timing; when the timing reaches the trigger interval duration, returning to execute the step of communicating with the target channel.

[0013] In one embodiment, when the read trigger mode is an interrupt trigger mode, the read trigger condition includes a condition of an external trigger interrupt signal; the method further includes: when it is determined that the number of reads has not reached the cyclic read number threshold, detecting whether an external interrupt signal is received; when it is determined that the external interrupt signal is received, returning to execute the step of communicating with the target channel.

[0014] In one embodiment, the read trigger condition also includes a first waiting time, and the method further includes: when it is determined that the external interrupt signal is not received, detecting whether the external interrupt signal is received based on the first waiting time; if the external interrupt signal is received within the first waiting time, returning to execute the step of communicating with the target channel; if the external interrupt signal is not received within the first waiting time, returning a second response message to the host computer.

[0015] In one embodiment, when the read trigger mode is a status polling trigger mode, the read trigger condition includes a condition for an externally triggered readable state; the method further includes: when it is determined that the number of reads does not reach the cyclic read number threshold, obtaining the state of the external register corresponding to the target channel; when it is determined that the state is a readable state, returning to execute the step of communicating with the target channel.

[0016] In one embodiment, the read trigger condition also includes a second waiting time and a retry number threshold, and the method also includes: when it is determined that the state is an unreadable state, retrying to obtain the state of the external register corresponding to the target channel based on the second waiting time, and recording the number of retries; if the state obtained by retry is a readable state, returning to the step of communicating with the target channel and clearing the number of retries; if the number of retries reaches the retry number threshold, and the state obtained by each retry is an unreadable state, returning a third response message to the host computer.

[0017] In a second aspect, the present application provides a reading control device for a communication interface, the device comprising:

[0018] A configuration parameter acquisition module is used to obtain channel configuration parameters sent by the host computer and initialize according to the channel configuration parameters; the channel configuration parameters include read trigger modes and cycle read count thresholds for at least two target channels, the read trigger modes of different target channels being the same or different, and the read trigger modes having corresponding read trigger conditions;

[0019] a communication control module, configured to, upon determining that a read trigger condition of the target channel is met, communicate with the target channel based on the read trigger mode, cyclically read data returned by the target channel based on the communication and the cyclic read count threshold, and record the number of reads;

[0020] The response module is used to return a first response message to the host computer when it is determined that the number of reads reaches the cyclic read number threshold.

[0021] In a third aspect, the present application provides a read control chip for a communication interface, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0022] In a fourth aspect, the present application provides a communication interface reading control chip, comprising a register control module, a trigger mode module and a main control module;

[0023] The register control module is used to obtain channel configuration parameters sent by the host computer and send the channel configuration parameters to the main control module and the trigger mode module; the channel configuration parameters include read trigger modes and cycle read count thresholds of at least two target channels, the read trigger modes of different target channels are the same or different, and the read trigger modes have corresponding read trigger conditions;

[0024] a trigger mode module, configured to configure parameters according to the read trigger modes of at least two target channels in the channel configuration parameters, and to feed back mode configuration information to the main control module;

[0025] The main control module is used to initialize according to the channel configuration parameters and the mode configuration information; and when it is determined that the read trigger condition of the target channel is met, communicate with the target channel based on the read trigger mode, cyclically read the data returned by the target channel based on the communication and the cyclic read count threshold, and record the number of reads; when it is determined that the number of reads reaches the cyclic read count threshold, return a first response message to the host computer.

[0026] In one embodiment, a storage management module is further included, which is used to allocate storage space to each channel, and the cache space of different channels is independent of each other; the main control module is also used to send the data read each time to the storage management module; the storage management module is also used to store the data in the cache space corresponding to the target channel.

[0027] In one embodiment, the channel configuration parameters also include data transfer conditions for each target channel; the register control module is further used to send the data transfer conditions for each target channel to the storage management module; the storage management module is further used to transfer the data in the cache space of the target channel to the external memory when it is determined that the data transfer conditions for the target channel are met.

[0028] In the fifth aspect, the present application provides a reading control system of a communication interface, comprising: a reading control chip of the communication interface as described in the third aspect, a host computer and at least two slaves, wherein the host computer and at least two slaves are respectively connected to the reading control chip of the communication interface.

[0029] In a sixth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when executed by a processor.

[0030] In a seventh aspect, the present application provides a computer program product, comprising a computer program, which implements the steps of the above method when executed by a processor.

[0031] The above-mentioned communication interface read control method, device, chip, readable storage medium, and program product obtain channel configuration parameters sent by the host computer, initialize according to the channel configuration parameters, and when it is determined that the read trigger condition of the target channel has been met, communicate with the target channel based on the read trigger mode, read the data returned by the target channel, and record the number of reads with the target channel. After that, when it is determined that the number of reads has reached the cyclic read count threshold, it returns a first response message to the host computer. By configuring the cyclic read count threshold for each channel, it can achieve continuous data reading from the channel based on the cyclic read count threshold, thereby avoiding frequent instruction sending, saving master control resources, and reducing the number of master control interrupts. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments of the present application or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 FIG. 1 is an application environment diagram of a reading control method of a communication interface in one embodiment;

[0034] Figure 2 1 is a flow chart of a method for controlling reading of a communication interface in one embodiment;

[0035] Figure 3 A schematic diagram of a control flow in a timing trigger mode in one embodiment;

[0036] Figure 4 A schematic diagram of a control flow in an interrupt trigger mode in another embodiment;

[0037] Figure 5 A schematic diagram of a control flow in a status polling trigger mode in one embodiment;

[0038] Figure 6 is a structural block diagram of a reading control device of a communication interface in one embodiment;

[0039] Figure 7 This is a diagram showing the internal structure of a read control chip of a communication interface in one embodiment;

[0040] Figure 8 A schematic diagram of the structure of a reading control system of a communication interface in one embodiment;

[0041] Figure 9 A schematic diagram of a DDR multi-channel storage structure in one embodiment;

[0042] Figure 10 A schematic diagram of a BRAM multi-channel storage structure in one embodiment;

[0043] Figure 11 A schematic diagram of a chip testing scenario in an embodiment. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0045] In traditional communication technology, the master must grant bus control to the corresponding slave for each read or write operation. For scenarios requiring continuous parameter reading, frequent bus commands must be sent, consuming significant master resources and resulting in low reading efficiency. Furthermore, each read data must be processed immediately, significantly increasing CPU load and making it difficult to apply to scenarios requiring continuous monitoring of data changes.

[0046] Furthermore, traditional solutions struggle to support large-scale parallel operation of channels (e.g., 64 slaves). Frequent switching between multiple channels competing for the bus results in wasted bandwidth (e.g., switching delays can reach tens of microseconds). Furthermore, each channel shares memory, and mixed data storage complicates analysis.

[0047] Based on this, an embodiment of the present application provides a read control method for a communication interface. By obtaining the channel configuration parameters sent by the host computer, initialization is performed according to the channel configuration parameters. When it is determined that the read trigger condition of the target channel is met, communication is performed with the target channel based on the read trigger mode. The data returned by the target channel is cyclically read based on the cyclic read count threshold, and the number of reads is recorded. Afterwards, when it is determined that the number of reads reaches the cyclic read count threshold, a first response message is returned to the host computer. By configuring the cyclic read count threshold for each channel, it is possible to achieve continuous data reading from the channel cyclically based on the cyclic read count threshold. This method is particularly suitable for scenarios where continuous parameter reading is required to avoid frequent instruction sending, save master control resources, and reduce the number of master control interrupts.

[0048] The communication interface reading control method provided in the embodiment of the present application can be applied to Figure 1In the application environment shown, a host computer 100 and multiple slave devices 200 are each connected to an FPGA (Field Programmable Gate Array) chip 300. The host computer 100 is responsible for data analysis and human-computer interaction. It connects to external memory to obtain processed data, applies software algorithms to analyze and present the results, and receives user instructions to adjust system operating parameters and working modes. The FPGA chip 300 is responsible for data processing (such as reading data from the slave devices 200 and transferring it to external memory) and operation flow scheduling, effectively handling complex computing and control tasks. The slave devices 200 return data to the FPGA chip 300 based on instructions from the FPGA chip 300, enabling real-time, periodic, and polled data returns. Specifically, the external memory can be integrated into the host computer 100 or placed in the cloud or other network servers. The host computer 100 can be a standalone physical server, a server cluster or distributed system consisting of multiple physical servers, or a cloud server providing cloud computing services. The slave device 200 may be, but is not limited to, various personal computers, laptops, smartphones, tablet computers, IoT devices, and portable wearable devices. The IoT devices may be smart speakers, smart TVs, smart air conditioners, smart car devices, projectors, etc. For example, the slave device 200 may be connected to the FPGA chip 300 via an SPI interface, an IIC interface, or other communication interfaces, which are not limited in this embodiment.

[0049] In one embodiment, a communication interface reading control method is provided. This embodiment uses the method applied to an FPGA chip and the slave connected to the FPGA chip based on an IIC interface as an example (the slave is described as an IIC slave). In this embodiment, Figure 2 As shown, the method may include the following steps:

[0050] Step 202: Obtain channel configuration parameters sent by the host computer and perform initialization according to the channel configuration parameters.

[0051] Among them, the channel configuration parameters are used to determine the operating mechanism of the FPGA chip and the interaction logic with the IIC slave. The channel configuration parameters can include the read trigger mode and loop read count threshold of at least two target channels, and the target channel refers to the communication channel between the FPGA chip and the target IIC slave. The read trigger mode has a corresponding read trigger condition, that is, the condition that triggers the reading of the corresponding target channel data. The loop read count threshold is the number of times the corresponding target channel data is read. The loop read count threshold can be an integer greater than or equal to 2. Based on the loop read count threshold, cyclic continuous data reading can be achieved, thereby avoiding frequent instruction sending to save master control resources.

[0052] For example, the read trigger modes of different target channels can be the same or different, and can be determined based on the mode of the IIC slave of the corresponding channel. For each target channel, its corresponding read trigger mode can include any one of a timing trigger mode, an interrupt trigger mode, and a status polling trigger mode.

[0053] For example, the cycle read count thresholds of different target channels may be the same or different, and may be configured based on actual needs, which is not limited in this embodiment.

[0054] In this embodiment, the FPGA chip obtains channel configuration parameters sent by the host computer and initializes according to these parameters. For example, based on user instructions, the host computer can write the channel configuration parameters for each IIC slave channel to the FPGA chip's register control module via a master control interface (such as an AXI (Advanced Xtensible Interface) bus). After obtaining the channel configuration parameters, the FPGA chip can enable the corresponding target channel to achieve initialization. The FPGA chip can also send a response message back to the host computer via the Respond bus.

[0055] Step 204 : When it is determined that the read trigger condition of the target channel is met, communicate with the target channel based on the read trigger mode, read the data returned by the target channel, and record the number of reads.

[0056] Communication is a protocol used for inter-device interaction. For example, if the slave device is an IIC slave, the communication is IIC communication, a short-distance serial synchronous half-duplex bus protocol that uses two signal lines (SCL, or serial clock line, and SDA, or serial data line) to transmit data between the master and slave devices. In this embodiment, the FPGA chip can trigger IIC communication with each target channel based on the channel configuration parameters obtained above to read the data returned by each target channel.

[0057] For example, the FPGA chip can monitor whether each target channel meets the corresponding read trigger condition based on the channel configuration parameters. If it is determined that a target channel meets the corresponding read trigger condition, the FPGA chip performs IIC communication with the corresponding target channel based on the read trigger mode, and cyclically reads the data returned by the target channel based on the cyclic read count threshold, while recording the read count. It is understood that the read count is used to represent the number of times data is read from the corresponding target channel.

[0058] Step 206: When it is determined that the number of reads reaches the cyclic read count threshold, a first response message is returned to the host computer.

[0059] The first response message indicates that the data reading task for the corresponding target channel has been completed. In this embodiment, when the FPGA chip determines that the number of reads from a target channel has reached the corresponding cyclic read count threshold, it indicates that the data reading task for that target channel has been completed. The FPGA chip then returns the first response message to the host computer, indicating that the data reading task for the corresponding target channel has been completed.

[0060] In the above-mentioned communication interface reading control method, the channel configuration parameters sent by the host computer are obtained, and initialization is performed according to the channel configuration parameters. When it is determined that the read trigger condition of the target channel has been met, the read trigger mode is used to communicate with the target channel, read the data returned by the target channel, and record the number of reads with the target channel. After that, when it is determined that the number of reads has reached the cyclic read count threshold, the first response message is returned to the host computer. By configuring the cyclic read count threshold for each channel, it is possible to achieve continuous data reading from the channel based on the cyclic read count threshold, thereby avoiding frequent instruction transmission, saving master control resources, and reducing the number of master control interrupts.

[0061] In an exemplary embodiment, in step 204, after reading the data returned by the target channel, the method may further include storing the data read each time in a cache space corresponding to the target channel. The cache space is pre-allocated by the FPGA chip for each channel, and the cache spaces for different channels are independent of each other. Each cache space also has a corresponding capacity, such as a 2MB DDR (Double Data Rate) or 2KB BRAM (Block Random Access Memory) buffer. DDR and BRAM are both random access memory resources in the FPGA chip.

[0062] In this embodiment, independent data storage can be achieved by allocating independent cache space to each channel. This not only avoids the problem of high parsing complexity caused by mixed storage of data from each channel, but also enables parallel reading and writing of each channel to improve reading and writing efficiency without causing multi-channel conflicts.

[0063] In an exemplary embodiment, the channel configuration parameters may further include data transfer conditions for each target channel. After storing the read data in the cache space corresponding to the target channel, the method may further include: transferring the data in the cache space of the target channel to an external memory if it is determined that the data transfer conditions for the target channel are met.

[0064] The data transfer condition may be a condition for clearing data stored in the cache space of each channel. Exemplarily, the data transfer condition may be a condition regarding the amount of data stored in the cache space, such as a cache space capacity threshold (e.g., 80%). The data transfer condition may also be a condition regarding the number of times data is stored in the cache space, such as 10 times. The data transfer condition may also be a time interval for clearing data stored in the cache space, such as 240 microseconds. It is understood that the data transfer conditions for different target channels may be the same or different, and this is not a limitation in this embodiment.

[0065] In this embodiment, by pre-configuring the data transfer conditions of each channel, when it is determined that the data transfer conditions of the target channel are met, the data in the cache space of the target channel is automatically transferred to the external memory, thereby avoiding the risk of data overflow. Compared with the method of real-time processing of data each time it is read, the number of interruptions can be reduced, the resource consumption of the FPGA chip is reduced, and it can be applied to scenarios where continuous observation of data changes is required.

[0066] In an exemplary embodiment, the channel configuration parameters may further include a data reading range of the corresponding channel. Then, in step 204, reading the data returned by the target channel may specifically include: reading the data returned by the target channel based on the data reading range.

[0067] The data read range can include the start address and read length configured for each channel. For example, if the start address configured for a channel is 0x00 and the read length is 8 bytes, the FPGA chip can read the data returned by the target channel based on the corresponding start address and read length. This not only improves throughput but also ensures the accuracy of subsequent data reads.

[0068] In an exemplary embodiment, the read trigger mode is taken as an example to further illustrate the read control method of the communication interface. Figure 3 As shown, the following steps may be specifically included:

[0069] Step 302: Obtain channel configuration parameters sent by the host computer.

[0070] Channel configuration parameters may include the read trigger mode, cyclic read count threshold, and data transfer conditions for the target channel. The read trigger mode has corresponding read trigger conditions. If the read trigger mode is a timed trigger mode, the read trigger conditions include the trigger interval duration for each channel, i.e., the timed trigger interval duration, for example, 30µs. This can be achieved using a timer.

[0071] Specifically, the host computer is responsible for configuring the parameters related to the timing trigger mode and transmitting them to the corresponding registers of the FPGA chip.

[0072] Step 304: Initialize according to the channel configuration parameters.

[0073] Initialization is the process of setting and configuring various FPGA chip parameters based on channel configuration parameters to ensure proper operation. Specifically, the FPGA chip selects channels based on these channel configuration parameters, determining which channels to activate. It then starts counters based on the trigger intervals for each channel, enables the corresponding channels, and then performs parallel processing, completing the initialization process.

[0074] Step 306: monitor whether each target channel meets the corresponding read trigger condition.

[0075] If it is monitored that the target channel meets the corresponding read trigger condition, for example, when the timer of the target channel is reached, step 308 is executed; otherwise, step 306 is executed to continue monitoring.

[0076] Step 308: Perform IIC communication to read data and record the number of reads.

[0077] If a target channel is detected to have reached the corresponding read trigger condition, IIC communication is performed with the target channel to read the data and the number of reads is recorded.

[0078] Step 310: Read data based on IIC communication and store it in the corresponding cache space.

[0079] The data returned by the target channel is read based on IIC communication and stored in the cache space corresponding to the target channel.

[0080] Step 312: When the data transfer conditions are met, data transfer is performed.

[0081] When it is detected that the cache space corresponding to a target channel meets the data transfer condition, the data in the cache space is transferred to the external memory.

[0082] Step 314: determine whether the number of reads reaches a cyclic read threshold.

[0083] After recording the number of reads in step 308, it is further determined whether the number of reads for the target channel reaches the cycle read number threshold. If not, step 316 is executed; if so, step 318 is executed.

[0084] Step 316: Count and wait for the trigger interval.

[0085] If the number of reads with a target channel does not reach the cyclic read number threshold, the timing starts and waits for the trigger interval length before returning to step 308, that is, after waiting for the trigger interval length, IIC communication is performed with the target channel again, thereby realizing cyclic reading of data.

[0086] Step 318: Return a first response message to the host computer.

[0087] If the number of reads for a target channel reaches the cyclic read count threshold, it means that the data reading task for the target channel is completed, so that the first response message can be returned to the host computer to instruct the host computer to complete the data reading task for the corresponding target channel.

[0088] For example, if the trigger interval for a certain channel is 30us, the loop read threshold is 20 times, the length of each read is 8 bytes, and the data transfer condition is to transfer data after every 10 reads, then a read operation is triggered for that channel every 30us, and 8 bytes of data are continuously read each time and stored in the cache space of the corresponding channel. After every 10 reads, the data in the cache space is transferred to the external memory, and the loop read stops after 20 times. This enables continuous data reading from the channel loop, avoiding frequent instruction transmission and saving master control resources. The independent data storage of each channel can avoid multi-channel conflicts and improve parallel reading and writing efficiency. By triggering automatic transfer, the risk of data overflow can also be avoided, the number of master control interrupts can be reduced, the resource consumption of the FPGA chip can be reduced, and overall performance can be improved.

[0089] In an exemplary embodiment, the read trigger mode is an interrupt trigger mode as an example to further illustrate the read control method of the communication interface. Figure 4 As shown, the following steps may be specifically included:

[0090] Step 402: Obtain channel configuration parameters sent by the host computer.

[0091] The channel configuration parameters may include the read trigger mode, cyclic read count threshold, and data transfer conditions for the target channel. The read trigger mode has corresponding read trigger conditions. If the read trigger mode is an interrupt trigger mode, the read trigger conditions include the conditions for the external trigger interrupt signal corresponding to each channel, i.e., the start condition of the interrupt mode, such as a low level on the INT pin.

[0092] Specifically, the host computer is responsible for configuring the interrupt trigger mode related parameters and transmitting them to the corresponding registers of the FPGA chip.

[0093] Step 404: Initialize according to the channel configuration parameters.

[0094] Initialization is the process of setting and configuring various FPGA chip parameters based on channel configuration parameters to ensure proper operation. Specifically, the FPGA chip completes the initialization process by enabling the corresponding channels and performing parallel processing based on the acquired channel configuration parameters, such as channel selection and the conditions for enabling each channel's interrupt mode.

[0095] Step 406: monitor each target channel to see if an interrupt signal is triggered.

[0096] If the target channel trigger interrupt signal is detected, it means that the corresponding target channel meets the corresponding read trigger condition, and step 408 is executed; otherwise, step 414 is executed.

[0097] Step 408: Perform IIC communication to read data and record the number of reads.

[0098] If a target channel is detected to have reached the corresponding read trigger condition, IIC communication is performed with the target channel to read the data and the number of reads is recorded.

[0099] Step 410: Store the read data in the corresponding cache space.

[0100] The data returned by the target channel is stored in the cache space corresponding to the target channel.

[0101] Step 412: When the data transfer conditions are met, data transfer is performed.

[0102] When it is detected that the cache space corresponding to a target channel meets the data transfer condition, the data in the cache space is transferred to the external memory.

[0103] Step 414: Detect whether an external interrupt signal is received based on the first waiting time.

[0104] Among them, the first waiting time can be a related parameter configured in the read trigger condition, which is used to characterize the maximum waiting time of the corresponding channel in the interrupt trigger mode. If the external interrupt signal of the target channel is received within the first waiting time, return to step 408 and perform IIC communication with the target channel. If the external interrupt signal of the target channel is not received within the first waiting time, execute step 418 and return a response message to the host computer. It can be understood that in order to distinguish the response messages returned in different scenarios, the response message returned in this scenario can be referred to as a second response message, and the second response message is used to characterize that the corresponding target channel waits for the interrupt timeout.

[0105] Step 416: Determine whether the number of reads reaches a cyclic read threshold.

[0106] After recording the number of reads in step 408, it is further determined whether the number of reads reaches the cycle read threshold. If not, the process returns to step 406 and continues to monitor whether each target channel triggers an interrupt signal. If so, the process proceeds to step 418.

[0107] Step 418: Return a response message to the host computer.

[0108] In one scenario, if the number of reads for a target channel reaches the cyclic read count threshold, it means that the data reading task for the target channel is completed, and thus a first response message can be returned to the host computer to instruct the host computer to complete the data reading task for the corresponding target channel.

[0109] In one scenario, if no external interrupt signal of a target channel is received within the first waiting period, it means that the corresponding target channel has timed out waiting for interruption, and a second response message can be returned to the host computer to indicate that the corresponding target channel has timed out waiting for interruption.

[0110] For example, if the condition for the external trigger interrupt signal for a certain channel is a low level on the INT pin, the first wait time is 100us, the cyclic read count threshold is 20 times, the length of each read is 8 bytes, and the data transfer condition is to transfer data at 240us intervals. If the INT pin of the IIC slave corresponding to a target channel is detected to be low, it means that the read trigger condition of the corresponding target channel has been met, that is, the interrupt mode of the corresponding target channel can be activated, triggering IIC communication to read data, and continuously reading 8 bytes of data each time and storing it in the buffer space of the corresponding channel. After completion, wait for the next interrupt (the maximum wait time is 100us, that is, it ends if no interrupt is detected within 100us). Data transfer is performed at 240us intervals, that is, data transfer is performed every 240us, and the cyclic reading stops after 20 times. This enables continuous reading of data from the channel to avoid frequent instruction sending and save master control resources. The independent data storage of each channel can avoid multi-channel conflicts and improve parallel reading and writing efficiency. By triggering automatic transfer, the risk of data overflow can be avoided, the number of master control interrupts can be reduced, the resource consumption of the FPGA chip can be reduced, and the overall performance can be improved.

[0111] In an exemplary embodiment, the read trigger mode is taken as a status polling trigger mode as an example to further illustrate the read control method of the communication interface. Figure 5 As shown, the following steps may be specifically included:

[0112] Step 502: Obtain channel configuration parameters sent by the host computer.

[0113] The channel configuration parameters may include the read trigger mode, cyclic read count threshold, and data transfer conditions for the target channel, and the read trigger mode has corresponding read trigger conditions. If the read trigger mode is the status polling trigger mode, the read trigger conditions include the conditions for the external trigger read status corresponding to each channel, that is, the start conditions of the status polling mode, such as the status register address and judgment conditions.

[0114] Specifically, the host computer is responsible for configuring the relevant parameters of the status polling trigger mode and transmitting them to the corresponding registers of the FPGA chip.

[0115] Step 504: Initialize according to the channel configuration parameters.

[0116] Initialization is the process of setting and configuring various FPGA chip parameters based on channel configuration parameters to ensure proper operation. Specifically, the FPGA chip can complete the initialization process by enabling the corresponding channels and performing parallel processing based on the acquired channel configuration parameters, such as channel selection and the conditions for starting the status polling mode for each channel.

[0117] Step 506: Obtain the status of the external register corresponding to the target channel.

[0118] The status is used to indicate whether the IIC slave corresponding to the target channel has readable data. In this embodiment, the state in which readable data exists is defined as a readable state, and the state in which readable data does not exist is defined as an unreadable state. The specific determination can be based on the status bit flag of the external register. For example, if the status bit flag of the external register is 1, it indicates a readable state, and if it is 0, it indicates an unreadable state.

[0119] Step 508: Determine whether the status is readable.

[0120] If it is determined that the state of the external register corresponding to the target channel is in a readable state, step 510 is executed; if it is determined that the state of the external register corresponding to the target channel is in an unreadable state, step 516 is executed.

[0121] Step 510: Perform IIC communication to read data and record the number of reads.

[0122] If the state of the external register corresponding to a target channel is monitored to be readable, it means that the corresponding read trigger condition is met, so IIC communication is performed with the target channel to read data and the number of reads is recorded.

[0123] Step 512: Store the read data in the corresponding cache space.

[0124] The data returned by the target channel read by IIC communication is stored in the cache space corresponding to the target channel.

[0125] Step 514: When the data transfer conditions are met, data transfer is performed.

[0126] When it is detected that the cache space corresponding to a target channel meets the data transfer condition, the data in the cache space is transferred to the external memory.

[0127] Step 516: Count down and wait for a second waiting time.

[0128] The second waiting time may be a pre-configured interval for reading the state of the external register corresponding to the target channel, for example, 10 us, which means that the state of the external register corresponding to the target channel is read once every 10 us.

[0129] If in step 508, the state of the external register corresponding to a target channel is monitored to be unreadable, it means that the corresponding read trigger condition has not been met. Therefore, the timing is started and after waiting for the second waiting time, the process returns to step 506 and tries to read the state of the external register corresponding to the target channel again.

[0130] Step 518: Determine whether the number of reads reaches a cyclic read count threshold.

[0131] After recording the number of reads in step 510, it is further determined whether the number of reads for the target channel has reached the cycle read threshold. If not, the process returns to step 506 and continues to read the status of the external register corresponding to the target channel. If so, the process proceeds to step 520.

[0132] Step 520: Return a response message to the host computer.

[0133] In one scenario, if the number of reads for a target channel reaches the cyclic read count threshold, it means that the data reading task for the target channel is completed, and thus a first response message can be returned to the host computer to instruct the host computer to complete the data reading task for the corresponding target channel.

[0134] In one scenario, to avoid deadlock caused by the target channel's corresponding external register being in an unreadable state, a maximum number of retries (i.e., a retry threshold) can be set for each channel. Specifically, if the target channel's corresponding external register is determined to be unreadable, the second wait duration can be used to retry obtaining the target channel's corresponding external register state, and the number of retries can be recorded. If the retried state is readable, the process returns to the step of communicating with the target channel and clears the number of retries. If the number of retries reaches the retry threshold, and the state obtained on each retry is unreadable, a third response message is returned to the host computer. This third response message indicates that the corresponding target channel's retry timeout has occurred, thereby avoiding deadlock.

[0135] For example, if the status register address for a channel's external trigger is 0x10, the second wait duration is 10us, the maximum number of retries is 10, the loop read threshold is 20, each read length is 8 bytes, and the data transfer condition is to transfer data at 240us intervals. If the status bit of the external status register corresponding to a target channel (register at address 0x10) is detected as readable, it indicates that the read trigger condition for the corresponding target channel has been met. This means that polling mode for the corresponding target channel can be initiated, triggering communication to read data. Each 8-byte data is continuously read and stored in the corresponding channel's buffer space. After completion, the next status read is performed (i.e., the status bits of the corresponding channel's external register are read again after a 10us interval). Data transfer is performed at 240us intervals, with data transfer occurring every 240us, and the loop stops after 20 reads. If the status bits of the external status register corresponding to a target channel are unreadable after 10 consecutive reads, the loop is exited to avoid deadlock. This enables continuous reading of data from the channel to avoid frequent instruction sending and save master control resources. The independent data storage of each channel can avoid multi-channel conflicts and improve parallel reading and writing efficiency. By triggering automatic transfer, the risk of data overflow can be avoided, the number of master control interrupts can be reduced, the resource consumption of the FPGA chip can be reduced, and the overall performance can be improved.

[0136] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0137] Based on the same inventive concept, embodiments of the present application also provide a communication interface read control device for implementing the aforementioned communication interface read control method. The solution provided by this device is similar to the solution described in the aforementioned method. Therefore, the specific limitations of the embodiments of the communication interface read control device provided below can be found in the aforementioned limitations of the communication interface read control method, and will not be further elaborated here.

[0138] In an exemplary embodiment, Figure 6As shown, a reading control device for a communication interface is provided, comprising: a configuration parameter acquisition module 602, a communication control module 604 and a response module 606, wherein:

[0139] Configuration parameter acquisition module 602, used to obtain channel configuration parameters sent by the host computer and initialize according to the channel configuration parameters; the channel configuration parameters include read trigger modes and cycle read count thresholds for at least two target channels, the read trigger modes of different target channels being the same or different, and the read trigger modes having corresponding read trigger conditions;

[0140] a communication control module 604 configured to, upon determining that a read trigger condition of the target channel is met, communicate with the target channel based on the read trigger mode, cyclically read data returned by the target channel based on the communication and the cyclic read count threshold, and record the read count;

[0141] The response module 606 is configured to return a first response message to the host computer when it is determined that the number of reads reaches the cyclic read count threshold.

[0142] In an exemplary embodiment, the device further includes a storage module for storing the data read each time in a cache space corresponding to the target channel. The cache space is a storage space pre-allocated for each channel, and the cache spaces of different channels are independent of each other.

[0143] In an exemplary embodiment, the channel configuration parameters also include data transfer conditions for each target channel; the device also includes a data transfer module, which is used to store the data read each time in the cache space corresponding to the target channel, and then transfer the data in the cache space of the target channel to the external memory when it is determined that the data transfer conditions of the target channel are met.

[0144] In an exemplary embodiment, when the read trigger mode is a timed trigger mode, the read trigger condition includes a corresponding trigger interval duration; the communication control module is further used to: start timing when it is determined that the number of reads has not reached the cyclic read number threshold; and return to executing the step of communicating with the target channel when the timing reaches the trigger interval duration.

[0145] In an exemplary embodiment, when the read trigger mode is an interrupt trigger mode, the read trigger condition includes a condition of an external trigger interrupt signal; the communication control module is further used to: when it is determined that the number of reads has not reached the cyclic read number threshold, detect whether an external interrupt signal is received; when it is determined that the external interrupt signal is received, return to execute the step of communicating with the target channel.

[0146] In an exemplary embodiment, the read trigger condition also includes a first waiting period, and the communication control module is also used to: when it is determined that the external interrupt signal is not received, detect whether the external interrupt signal is received based on the first waiting period; if the external interrupt signal is received within the first waiting period, return to execute the step of communicating with the target channel; if the external interrupt signal is not received within the first waiting period, return a second response message to the host computer.

[0147] In an exemplary embodiment, when the read trigger mode is a status polling trigger mode, the read trigger condition includes a condition of an externally triggered readable state; the communication control module is further used to: when it is determined that the number of reads does not reach the cyclic read number threshold, obtain the state of the external register corresponding to the target channel; when it is determined that the state is a readable state, return to execute the step of communicating with the target channel.

[0148] In an exemplary embodiment, the read trigger condition also includes a second waiting time and a number threshold, and the communication control module is also used to: when it is determined that the state is an unreadable state, retry to obtain the state of the external register corresponding to the target channel based on the second waiting time, and record the number of retries; if the state obtained by retry is a readable state, return to the step of communicating with the target channel and clear the number of retries; if the number of retries reaches the retry number threshold, and the state obtained by each retry is an unreadable state, return a third response message to the host computer.

[0149] Each module in the aforementioned communication interface reading control device may be implemented in whole or in part through software, hardware, or a combination thereof. Each module may be embedded in or independent of a processor in a computer device in the form of hardware, or may be stored in a memory in the computer device in the form of software, so that the processor can call and execute the corresponding operations of each module.

[0150] In an exemplary embodiment, a communication interface read control chip is provided, and the communication interface read control chip can be an FPGA chip. Its internal structure diagram can be as follows: Figure 7As shown. The read control chip of the communication interface includes a processor, a memory, an input / output interface (I / O) and a communication interface. The processor, the memory and the input / output interface are connected via a system bus, and the communication interface is connected to the system bus via the input / output interface. The processor of the read control chip of the communication interface is used to provide computing and control capabilities. The memory of the read control chip of the communication interface includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the read control chip of the communication interface is used to store configuration parameter data of each channel. The input / output interface of the read control chip of the communication interface is used to exchange information between the processor and an external device. The communication interface of the read control chip of the communication interface is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a read control method of the communication interface is implemented.

[0151] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the reading control chip of the communication interface to which the solution of the present application is applied. The reading control chip of the specific communication interface may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0152] In an exemplary embodiment, a reading control system of a communication interface is also provided, and its internal structure diagram can be shown as follows: Figure 8 As shown. The connection relationship between the internal modules of the FPGA chip (including the master control module, register control module, trigger mode module, storage management module, parallel processing module, etc.) and the external slave (the IIC slave is used as an example in this embodiment) and the host computer is shown. It can be understood that there can be multiple IIC slaves. Among them, 116 is the host computer, which is responsible for assigning parameters to the register control module of the FPGA chip. The host computer 116 communicates with the register control module of the FPGA chip through the AXI bus and the Respond bus. 117 is a slave, which can be an IIC slave. It interacts with the master control module of the FPGA chip through the SDA and SCL signal lines to realize the read and write functions.

[0153] The register control module in the FPGA chip 101 is used to obtain the channel configuration parameters sent by the host computer and send the channel configuration parameters to the main control module, the trigger mode module, and the parallel processing module; the channel configuration parameters include the read trigger mode and the loop read count threshold of at least two target channels. The read trigger modes of different target channels are the same or different, and the read trigger modes have corresponding read trigger conditions;

[0154] A trigger mode module is used to configure parameters according to the read trigger modes of at least two target channels in the channel configuration parameters, and to feed back the mode configuration information to the main control module;

[0155] A parallel processing module, configured to perform parallel configuration according to the read trigger modes of at least two target channels in the channel configuration parameters, and to feed back the parallel configuration information to the main control module;

[0156] The main control module is used to initialize according to the channel configuration parameters, mode configuration information and parallel configuration information; and when it is determined that the read trigger condition of the target channel is met, communicate with the target channel based on the read trigger mode, cyclically read the data returned by the target channel based on the communication and the cyclic read number threshold, and record the number of reads; when it is determined that the number of reads reaches the cyclic read number threshold, return a first response message to the host computer.

[0157] Exemplarily, the storage management module is used to allocate storage space to each channel, and the cache space of different channels is independent of each other; the main control module is also used to send the data read each time to the storage management module; the storage management module is also used to store the data in the cache space corresponding to the target channel.

[0158] Exemplarily, the channel configuration parameters also include data transfer conditions for each target channel; the register control module is further configured to send the data transfer conditions for each target channel to the storage management module; the storage management module is further configured to transfer the data in the cache space of the target channel to the external memory when it is determined that the data transfer conditions for the target channel are met.

[0159] Specifically, 101 is the clock divider in the master control module of the FPGA chip, providing clock frequencies of 100kHz, 200kHz, 400kHz, 1MHz, and 3.4MHz, and outputting them to the IIC timing control module 102. 102 is the IIC timing control module in the master control module, responsible for receiving data to be transmitted, performing timing processing, and sending the data to the slave according to the IIC data structure. It also receives data returned by the slave, parses and frames it, and temporarily stores the parsed data in the read / write data transfer module 103. 103 is the read / write data transfer module in the master control module, responsible for interacting with the IIC timing control module 102 and forwarding the data to be stored to the storage management module. 104 is the channel mode parameter register group in the register control module, responsible for receiving channel-related parameters configured by the host computer and forwarding them to the master control module, trigger mode module, and parallel processing module. 105 is the transport control parameter register group in the register control module, responsible for receiving trigger transport control parameters configured by the host computer and forwarding them to the storage management module. 106 is the read operation parameter register group in the register control module, responsible for receiving the read operation parameters configured by the host computer and forwarding them to the main control module. 107, 108, and 109 are the timing trigger unit, interrupt trigger unit, and status polling trigger unit, respectively, in the trigger mode module. They are responsible for receiving the mode selection parameters from the register control module and forwarding the processed parameters to the main control module. 110 and 111 are the BRAM storage unit and DDR storage unit in the storage management module, responsible for receiving and storing data transmitted from the main control module. 112 is the transport controller in the storage management module, responsible for receiving the transport control parameters from the register control module and generating a transport signal when the specified parameters are met. 113 is the DMA (Direct Memory Access, also known as burst data transfer mode or sometimes direct memory operation) transfer module. After receiving the transport signal generated by the transport controller, it transfers data from the BRAM or DDR to external memory 114. 114 is an external memory module connected to the FPGA and is responsible for receiving data transmitted by DMA. 115 is the parallel processing module, responsible for multi-channel parallel communication.

[0160] In an exemplary embodiment, a DDR multi-channel memory structure such as Figure 9 Figure 901 shows the memory space allocated to each channel in DDR. For example, each channel is allocated 2MB of memory, for a total of 64 channels (e.g., CH0, CH1, ..., CH63). Figure 902 shows the specific space allocation for continuous read operations in timed trigger mode. After data is stored at a specified address, the address is automatically cleared and storage restarts at address 0. A certain amount of memory space is also reserved for other functions, and this reserved space can be adjusted in real time based on usage.

[0161] In an exemplary embodiment, a BRAM multi-channel memory structure such as Figure 10 1001 shows the storage space allocated to each channel in the BRAM. For example, each channel is allocated 2KB of storage space, for a total of 64 channels (e.g., CH0, CH1, ..., CH63). 1002 shows the specific space allocation for continuous read operations in timed trigger mode. After storing data at a specified address, the address is automatically cleared and storage restarts at address 0. A certain amount of storage space is also reserved for other functions, and the reserved storage space can be adjusted in real time based on usage.

[0162] Based on the above multi-channel storage structure, each channel can operate independently without interfering with each other, and each channel can be executed simultaneously using different read modes (such as channels 1-32 in timed trigger mode and channels 33-64 in interrupt trigger mode), thereby maximizing throughput, reducing the risk of master interruption, and avoiding data overflow.

[0163] In an exemplary embodiment, taking the above-mentioned communication interface reading control system applied to a chip test scenario as an example, the corresponding system architecture can be as follows: Figure 11 The form shown includes an FPGA communication board (that is, the above-mentioned FPGA chip), a cable connection line, a circuit board of the chip under test (where the chip under test is equivalent to an IIC slave), and a host computer.

[0164] Specifically, the FPGA communication board, as the core of the system, is responsible for large-scale data processing and operational process scheduling. Different models can be selected as needed for different application scenarios. Its parallel processing capabilities and flexible logic configuration can effectively handle complex computing and control tasks.

[0165] Cables are responsible for data transmission and communication connections between hardware devices, ensuring smooth information exchange between components and significantly affecting the stability and speed of data transmission.

[0166] The chip circuit board under test is one of the data sources. It carries the chip that needs to be tested and analyzed. Its data characteristics and interface specifications determine the system data acquisition method and scope.

[0167] The host computer is responsible for data analysis and human-computer interaction. It obtains processed data by connecting to external storage, uses software algorithms to analyze and present the results, and receives user instructions to adjust system operating parameters and working modes. Its parameterized configuration supports dynamic adjustment of channel number and mode.

[0168] The workflow in different modes can refer to the above Figure 3 、 Figure 4 as well as Figure 5 The embodiment shown is not described in detail in this embodiment.

[0169] In an exemplary embodiment, a read control chip of a communication interface is provided, comprising a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0170] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0171] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0172] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0173] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. In particular, any reference to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), quantum computing-based data processing logic devices, artificial intelligence (AI) processors, and the like.

[0174] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0175] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A communication interface reading control method, characterized in that: The method is applied to an FPGA chip, and the method includes: Obtain channel configuration parameters sent by the host computer and initialize according to the channel configuration parameters; the channel configuration parameters include read trigger modes and cycle read count thresholds for at least two target channels, the read trigger modes of different target channels being the same or different, and the read trigger modes having corresponding read trigger conditions; for each target channel, the read trigger mode includes any one of a timing trigger mode, an interrupt trigger mode, and a status polling trigger mode; When it is determined that the read trigger condition of the target channel is met, communicating with the target channel based on the read trigger mode, cyclically reading data returned by the target channel based on the communication and the cyclic read count threshold, and recording the read count; When it is determined that the number of reads reaches the cyclic read count threshold, returning a first response message to the host computer; The channel configuration parameters also include data handling conditions for each target channel; after cyclically reading the data returned by the target channel based on the communication and the cyclic read count threshold, the method further includes: The data read each time is stored in the cache space corresponding to the target channel. The cache space is a storage space pre-allocated for each channel, and the cache spaces of different channels are independent of each other. When it is determined that the data transfer conditions of the target channel are met, the data in the cache space of the target channel is transferred to the external memory.

2. The method according to claim 1, characterized in that In the case where the read trigger mode is a timed trigger mode, the read trigger condition includes a corresponding trigger interval duration; The method further comprises: When it is determined that the number of reads does not reach the cyclic read number threshold, starting timing; When the timing reaches the trigger interval, the process returns to executing the step of communicating with the target channel.

3. The method according to claim 1, characterized in that In the case where the read trigger mode is an interrupt trigger mode, the read trigger condition includes a condition of an external trigger interrupt signal; and the method further includes: If it is determined that the number of reads does not reach the cyclic read number threshold, detecting whether an external interrupt signal is received; If it is determined that the external interrupt signal is received, the process returns to the step of communicating with the target channel.

4. The method according to claim 3, characterized in that The read trigger condition further includes a first waiting time, and the method further includes: In a case where it is determined that the external interrupt signal is not received, detecting whether an external interrupt signal is received based on the first waiting time; If the external interrupt signal is received within the first waiting period, returning to the step of communicating with the target channel; If the external interrupt signal is not received within the first waiting period, a second response message is returned to the host computer.

5. The method according to claim 1, characterized in that In the case where the read trigger mode is a status polling trigger mode, the read trigger condition includes a condition of an externally triggered readable state; and the method further includes: When it is determined that the number of reads does not reach the cyclic read number threshold, obtaining a state of an external register corresponding to the target channel; If it is determined that the state is a readable state, the step of communicating with the target channel is returned to be executed.

6. The method according to claim 5, characterized in that The read trigger condition further includes a second waiting time and a retry count threshold, and the method further includes: If it is determined that the state is an unreadable state, retrying to obtain the state of the external register corresponding to the target channel based on the second waiting time, and recording the number of retries; If the state obtained by retrying is a readable state, returning to the step of communicating with the target channel and clearing the number of retries; If the number of retries reaches the retry threshold, and the status obtained in each retry is an unreadable state, a third response message is returned to the host computer.

7. A reading control device for a communication interface, characterized in that: The device is applied to an FPGA chip, and the device includes: A configuration parameter acquisition module is used to obtain channel configuration parameters sent by the host computer and initialize according to the channel configuration parameters; the channel configuration parameters include read trigger modes and cycle read count thresholds for at least two target channels, the read trigger modes of different target channels being the same or different, and the read trigger modes having corresponding read trigger conditions; for each target channel, the read trigger mode includes any one of a timing trigger mode, an interrupt trigger mode, and a status polling trigger mode; a communication control module, configured to, upon determining that a read trigger condition of the target channel is met, communicate with the target channel based on the read trigger mode, cyclically read data returned by the target channel based on the communication and the cyclic read count threshold, and record the number of reads; A response module, configured to return a first response message to the host computer when determining that the number of reads reaches the cyclic read count threshold; The channel configuration parameters also include data handling conditions for each target channel; the device also includes a storage module and a data handling module, The storage module is used to store the data read each time in a cache space corresponding to the target channel, wherein the cache space is a storage space pre-allocated for each channel, and the cache spaces of different channels are independent of each other; The data transfer module is configured to transfer the data in the cache space of the target channel to the external memory when it is determined that the data transfer condition of the target channel is met.

8. A read control chip for a communication interface, characterized in that: The chip includes a register control module, a trigger mode module and a main control module; The register control module is used to obtain channel configuration parameters sent by the host computer and send the channel configuration parameters to the main control module and the trigger mode module; the channel configuration parameters include read trigger modes and cycle read count thresholds of at least two target channels, the read trigger modes of different target channels are the same or different, and the read trigger modes have corresponding read trigger conditions; a trigger mode module, configured to configure parameters according to the read trigger modes of at least two target channels in the channel configuration parameters, and to feed back mode configuration information to the main control module; The main control module is configured to perform initialization according to the channel configuration parameters and the mode configuration information; and, if it is determined that the read trigger condition of the target channel is met, communicating with the target channel based on the read trigger mode, cyclically reading data returned by the target channel based on the communication and the cyclic read count threshold, and recording the read count; When it is determined that the number of reads reaches the cyclic read count threshold, returning a first response message to the host computer; The chip also includes a storage management module for allocating storage space to each channel, with the cache spaces of different channels being independent of each other; the main control module is further configured to send each read data to the storage management module; the storage management module is further configured to store the data in the cache space corresponding to the target channel; The channel configuration parameters also include data transfer conditions for each target channel; the register control module is further used to send the data transfer conditions for each target channel to the storage management module; the storage management module is further used to transfer the data in the cache space of the target channel to the external memory when it is determined that the data transfer conditions of the target channel are met.

9. A reading control system for a communication interface, characterized in that: include: The read control chip of the communication interface, the host computer and at least two slave computers according to claim 8, wherein the host computer and the at least two slave computers are respectively connected to the read control chip of the communication interface.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

11. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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