Method for quickly designing, updating and verifying time sequence diagram of architecture model based on time sequence block

Abstract

The invention relates to the technical field of time sequence diagram updating, in particular to an architecture model time sequence diagram rapid design updating verification method based on a time sequence block, and provides the following scheme: selecting a to-be-updated area and editing the time sequence block and time sequence attributes thereof in a pop-up edit box; the editing content comprises a time sequence block name, a triggering opportunity, a message passing interval, a triggering condition and the like. And converting the editing result into a standardized logic fragment through a logic generation frame, and fusing the standardized logic fragment with an original time sequence diagram according to a layout algorithm of the time sequence diagram. According to the method, efficient updating, verification and layout optimization of the time sequence blocks in the time sequence diagram are achieved, the correctness and consistency of the time sequence relation are ensured, and the flexibility and accuracy of the design process are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of sequence diagram update, and particularly to a method for quickly designing, updating and verifying a sequence diagram of an architecture model based on sequence blocks. Background Art

[0002] In the design and development process of modern complex systems, as an important graphical tool, sequence diagrams are widely used to describe the interaction behaviors and time sequences among different components in the system. Especially in the design of architecture models, sequence diagrams are usually used to represent message passing, event triggering and timing constraints between modules, so as to facilitate the analysis of the timing logic and performance of the system. However, with the increase in system scale and complexity, the existing sequence diagram design and update methods face many challenges.

[0003] Traditional sequence diagram design methods often rely on manual operations. In large-scale systems, designers need to separately handle the event order, time interval and message path updates of each sequence block. Such manual operations not only involve huge workloads, but also are prone to errors. Especially when system requirements change, the sequence diagram needs to be updated frequently, and some key timing relationships may be missed during the update process, resulting in inaccurate designs or verification failures.

[0004] For example, Chinese Patent with application number CN116860623A relates to a method and system for updating test cases based on an operation sequence diagram. The method includes parsing the updated user operation sequence diagram, obtaining and storing the node table of the updated user operation and the pointing relationship table between nodes; comparing the updated pointing relationship table between nodes with the existing pointing relationship table between nodes to obtain a set of different pointing relationships between nodes; and obtaining an updated test case table according to the set of different pointing relationships between nodes. By comparing the pointing relationships between nodes before and after adding or deleting nodes, the present invention respectively obtains the sets of pointing relationships between nodes to be updated and to be deleted, locates and updates the existing branch paths according to the set of pointing relationships. When updating test cases, testers do not need to reconfigure the data dictionary or only need to specifically configure or modify the data dictionary of the updated nodes, and the data dictionaries of other non-updated nodes are still valid, reducing the maintenance cost of test cases.

[0005] The above patents all have the problems raised in this background art: insufficient handling of the complexity of timing relationships and lack of an automated verification mechanism. To solve the above problems, the present application designs a method for quickly designing, updating and verifying a sequence diagram of an architecture model based on sequence blocks. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a method for quickly designing, updating and verifying the timing diagram of an architecture model based on timing blocks in view of the deficiencies of the prior art. The method includes selecting the area to be updated and editing the timing blocks and their timing attributes in a pop-up editing box. The editing content includes the name of the timing block, the triggering time, the message passing interval, the triggering condition, etc. The editing result is converted into a standardized logic segment through a logic generation box and merged with the original timing diagram according to the layout algorithm of the timing diagram. This method realizes the efficient update, verification and layout optimization of the timing blocks in the timing diagram, ensures the correctness and consistency of the timing relationship, and improves the flexibility and accuracy of the design process.

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] A method for quickly designing, updating and verifying the timing diagram of an architecture model based on timing blocks, the method comprising:

[0009] Selecting the area to be updated in the timing diagram interface through an interaction device, the area to be updated being displayed in the form of a dynamic box, the dynamic box including timing blocks, interaction relationships and timing attributes, the timing attributes including the time interval of message passing, the triggering time of events, and the transfer relationship between timing blocks;

[0010] Generating a pop-up editing box corresponding to the area to be updated according to the area to be updated, and editing the timing blocks and their timing attributes in the pop-up editing box, the editing including modifying the attributes of the timing blocks;

[0011] Converting the editing result into a standardized logic segment through a logic generation box, and merging the standardized logic segment with the original timing diagram according to the layout algorithm of the timing diagram.

[0012] The selection of the area to be updated includes:

[0013] Performing a selection operation through an interaction device in the timing diagram interface to determine the initial update range of the area to be updated, the selection operation including a box selection operation, a timing block selection operation and a message path selection operation, wherein the message path selection operation includes selecting the message passing path and the timing constraint relationship between timing blocks;

[0014] Expanding the initial update range according to the time sequence of the timing blocks, the message passing sequence and the timing block dependency relationship within the initial update range;

[0015] Highlighting the expanded area to be updated in the timing diagram interface through a dynamic box, performing a timing logic check, if the check passes, marking it as the area to be updated, if the check fails, readjusting the update range according to the timing constraint relationship.

[0016] The expansion of the initial update range includes:

[0017] Analyze the message passing and event triggering relationships between timing blocks within the initial update range to obtain timing dependencies and time constraints;

[0018] According to the timing dependencies, deduce the dynamic dependency chain between timing blocks, generate message paths, and calculate the synchronization degree and dependency degree of the message paths in the timing blocks;

[0019] According to the time constraints, analyze the timing blocks through time windows, and calculate the timing delay factor of the timing blocks, where the timing delay factor refers to the minimum delay time generated by the timing block being restricted by the time of other timing blocks during message passing or event triggering;

[0020] Aggregate the timing delay factors of all timing blocks, determine the parallel execution relationship between timing blocks according to the timing delay factors, and calculate the timing expansion factor of the timing blocks according to the parallel blocks and message paths of the current timing block;

[0021] Sort the timing expansion factors of all timing blocks, take the largest timing expansion factor as the expansion radius, and superimpose it with the radius of the initial update range to obtain the range to be updated.

[0022] The calculation formula for the timing expansion factor is:

[0023]

[0024] where A i represents the timing expansion factor of timing block i, δ i represents the timing delay factor of timing block i, n represents the number of parallel blocks of timing block i, j represents a single event of timing block i, N represents the total number of events of timing block i, E j represents the triggering timing of the jth event, T max represents the maximum time delay within timing block i, l represents a single message path of timing block i, M represents the total number of message paths of timing block i, P l represents the load of the lth message path, P max represents the maximum load within timing block i, β l represents the dependency factor of the lth message path, θ l represents the timing synchronization factor of the lth message path.

[0025] The pop-up edit box includes:

[0026] An attribute editing tool for displaying and modifying the attribute information of the selected timing block, where the attribute information includes triggering timing, execution order, time interval, and message path;

[0027] An event trigger timing adjustment tool, which is used to adjust the trigger timing of each event in a timing block and provide a graphical way to display the time relationship between event triggers;

[0028] A synchronization and dependency relationship editing tool, which is used to modify the message passing path between timing blocks and adjust the dependency relationship between timing blocks;

[0029] A structure preview tool, which is used to display a preview screen of the editing result during the editing process.

[0030] Editing the timing block and its timing attributes in the pop-up editing box includes:

[0031] Selecting the timing block to be edited through an interaction device and modifying the relevant attributes of the timing block in the pop-up editing box. The attributes include the name of the timing block, the event trigger timing, the time interval of message passing, and the trigger condition;

[0032] Dragging or selecting the trigger order between events through a graphical interface, adjusting the dependency relationship between events, and modifying the interaction relationship between timing blocks;

[0033] During the editing process, the synchronization factor and delay factor of each event in the timing block are displayed in real time, and the synchronization and delay relationship between events is changed according to the synchronization factor and delay factor;

[0034] Performing logical verification on the timing block and its timing attributes, including time dependency, the sequentiality of event trigger timing, and the time interval of message passing.

[0035] The logical generation box includes:

[0036] A standardization conversion tool, which is used to convert the modifications made to the timing block and its timing attributes during the editing process into a timing logic segment that conforms to the specification;

[0037] A timing verification tool, which is used to check the time dependency, the trigger order of events, and the message passing path within the logic segment, and perform functional verification on the generated timing logic segment;

[0038] A timing dependency relationship conversion tool, which is used to analyze and convert the dependency relationship between the edited timing logic segment and the original timing diagram;

[0039] A timing attribute synchronization tool, which is used to verify whether the timing attributes of the updated timing block in the entire timing diagram meet the overall consistency and synchronization.

[0040] The layout algorithm of the timing diagram includes:

[0041] When new timing blocks or updated content are introduced, the spatial layout is adjusted according to the timing relationships, event triggering times, message passing paths, and timing attributes among the timing blocks in the timing diagram;

[0042] By analyzing the timing dependency chains of each timing block, the relative order and connection relationships of the timing blocks are adjusted. According to the dependency degree and timing attributes among the timing blocks, new message paths are generated, and the updated timing blocks are reconnected according to the dependency relationships;

[0043] According to the time constraints of each timing block, the time overlap and parallel execution situations among the timing blocks are analyzed, and the execution order and spatial distribution among the timing blocks are adjusted.

[0044] A fast design update verification system for the timing diagram of an architecture model based on timing blocks, the system includes a selection and extension module, an editing and derivation module, a logic verification module, and a layout adjustment module;

[0045] The selection and extension module is configured with an intelligent extension strategy, and the intelligent extension strategy is used to determine the initial update range and extend the initial update range according to the time order, message passing sequentiality, and timing block dependency relationships of the timing blocks within the initial update range;

[0046] The editing and derivation module is used to edit the timing blocks and their timing attributes in a pop-up editing box, and the editing includes modifying the attributes of the timing blocks;

[0047] The logic verification module is used to convert the editing result into a standardized logic fragment through a logic generation box;

[0048] The layout adjustment module is used to fuse the standardized logic fragment with the original timing diagram according to the layout algorithm of the timing diagram.

[0049] The selection and extension module includes:

[0050] An initial delineation unit, used to perform a selection operation in the timing diagram interface through an interactive device to determine the initial update range of the area to be updated;

[0051] An intelligent update unit, used to dynamically expand the initial update range and generate a new area to be updated;

[0052] An area display unit, used to display the area to be updated in the form of a dynamic box.

[0053] Compared with the prior art, the beneficial effects of the present invention are:

[0054] 1. The present invention can quickly identify and expand the area to be updated, ensure that the dependency relationships and time constraints between timing blocks are reasonably verified, and at the same time, through the dynamic box and real-time verification functions, effectively reduce manual intervention and the occurrence of errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Other features, objects, and advantages of the present invention will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0056] Figure 1 FIG. is a schematic flowchart of a method for quickly designing, updating, and verifying a timing diagram of an architecture model based on timing blocks according to Embodiment 1 of the present invention;

[0057] Figure 2 FIG. is a module diagram of a system for quickly designing, updating, and verifying a timing diagram of an architecture model based on timing blocks according to Embodiment 2 of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0058] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments.

[0059] It should be noted that in this application, timing blocks are applicable to scenarios that focus on time interactions between components, such as real-time systems, event-driven architectures, and the modeling of communication protocols. It can effectively optimize the message passing order and verify the consistency of time constraints.

[0060] Specifically, timing blocks are applied to timing diagrams, mainly focusing on the time order and message interactions between different modules. The key points of timing blocks are time constraints, event triggering times, and the time intervals of message paths, emphasizing the rationality of time logic and execution timing.

[0061] Embodiment 1:

[0062] Please refer to Figure 1 , an embodiment provided by the present invention: a method for quickly designing, updating, and verifying a timing diagram of an architecture model based on timing blocks, and the specific steps of the method are as follows:

[0063] S1: Select the area to be updated in the timing diagram interface through an interaction device, and the area to be updated is displayed in the form of a dynamic box;

[0064] In this step, select a region to be updated in the timing diagram interface through an interaction device (such as a mouse, touch screen, or other input devices). This region is highlighted in the form of a dynamic box, visually identifying the part of the timing diagram that needs to be edited or modified. The dynamic box contains relevant timing blocks, interaction relationships, and timing attributes, and the timing attributes include key timing information such as the time interval of message passing and the triggering timing of events. The region of the timing diagram to be updated can be accurately located through operations such as box selection, node operation, or message path selection, ensuring the effectiveness and accuracy of subsequent operations.

[0065] S2: Edit the timing block and its timing attributes in the pop-up edit box;

[0066] In this step, once the region to be updated is selected and highlighted, a pop-up edit box will appear, allowing modification of the timing block and its related timing attributes. In this edit box, the attributes of the timing block can be modified, such as the event triggering timing, the time interval of message passing, the dependency relationship between timing blocks, etc. The edit box provides a variety of editing tools, supporting graphical operations (such as dragging timing blocks, adjusting message paths, etc.), as well as precise attribute input and adjustment. The modifications made will directly affect the behavior and interaction relationships of the timing diagram.

[0067] S3: Convert the editing result into a standardized logic fragment through the logic generation box;

[0068] In this step, according to the modification content input in the pop-up edit box, use the logic generation box to convert the editing result into a standardized logic fragment that conforms to the unified specification. The standardized logic fragment contains verified timing information, message passing order, and its time delay and other attributes, ensuring that the edited timing diagram is logically valid and conforms to the design specifications and constraints of the timing diagram. The generated standardized logic fragment will provide a basis for subsequent fusion of the timing diagrams.

[0069] S4: According to the layout algorithm of the timing diagram, fuse the standardized logic fragment with the original timing diagram.

[0070] In this step, the layout algorithm automatically adjusts the relative positions of the new timing blocks and the message paths based on the dependency relationships between the timing blocks in the timing diagram, the sequentiality of message passing, and the time constraints, ensuring that the layout of the elements in the diagram does not conflict and conforms to the timing constraints.

[0071] The specific steps of S1 are as follows:

[0072] S1.1: Perform a selection operation in the timing diagram interface through an interaction device to determine the initial update range of the region to be updated. The selection operation includes box selection operation, timing block selection operation, and message path selection operation. Among them, the message path selection operation includes selecting the message passing path and timing constraint relationship between timing blocks;

[0073] Box selection operation: Through a mouse or touch device, the user selects an area on the timing diagram interface to select elements such as timing blocks, events, and message paths within that area. The selection range of the boxed area can be continuous or discontinuous. The box selection operation not only provides an initial scope for subsequent updates but also helps determine the boundaries that need to be extended.

[0074] Timing block selection operation: Directly select one or more timing blocks in the diagram by clicking or dragging the mouse. This selection operation is applicable when it is already clear which timing blocks need to be modified or updated. The selection of timing blocks is usually based on the user's understanding of the existing timing diagram and the expected results of the modification target. After selection, the area where the selected timing blocks are located will be automatically used as the initial update scope.

[0075] Message path selection operation: Select the message passing paths between timing blocks. Especially when the timing diagram contains complex message passing logic, it is crucial to select the message paths. By selecting the message paths, not only the specific message passing process is selected, but also the relevant timing constraint relationships are automatically included. For example, when selecting the message passing path between two timing blocks, the relevant timing constraints, such as time intervals and the timing order of message triggers, will be automatically recognized and considered based on this path;

[0076] Through these three selection operations, the target area in the timing diagram can be accurately selected, enabling the accurate positioning of the area to be updated without having to modify the entire graph. Compared with traditional methods, the update area can be flexibly specified, avoiding unnecessary interference;

[0077] S1.2: Expand the initial update scope according to the time order of the timing blocks, the sequentiality of message passing, and the timing block dependencies within the initial update scope;

[0078] Time order analysis: Analyze the time relationship between timing blocks based on the time attributes in the timing blocks (such as event trigger time, time interval of message passing). For example, the execution of a certain timing block depends on other timing blocks to complete the triggering of an event. If these timing blocks are not selected, the system will automatically include them in the expanded area. In this way, it is ensured that all relevant timing blocks are updated, avoiding missing other timing blocks that have a dependency relationship with the target timing block.

[0079] Sequentiality of message passing: The sequentiality of message passing in the timing diagram determines how messages flow between timing blocks. The order and triggering timing of any message will affect the logic of the entire timing diagram. Analyze the message passing paths within the selected area, automatically deduce the message order, and expand the update scope according to the sequentiality of message passing between timing blocks. If the passing order of the message path is unclear or there are timing conflicts, the system will automatically adjust the update scope according to the timing constraint conditions.

[0080] Temporal block dependencies: There are often complex dependencies between temporal blocks. For example, some temporal blocks may depend on the event trigger results of other temporal blocks or need to wait until the execution of a certain temporal block is completed before starting. The system will automatically identify these dependencies and further expand the initial update scope by deriving the dynamic dependency chain between temporal blocks. This derivation ensures that the update scope can cover all dependent or affected temporal blocks, avoiding omissions.

[0081] S1.3: Highlight the expanded area to be updated in the timing diagram interface with a dynamic box for timing logic verification. If the verification passes, mark it as the area to be updated. If the verification fails, readjust the update scope according to the timing constraint relationship.

[0082] After expanding the update area, highlight the expanded area in the timing diagram interface with a dynamic box to provide a clear visual indication and confirm whether the area to be updated meets the expectations. At the same time, the system will automatically perform timing logic verification to ensure that the expanded update scope is logically consistent in terms of timing and will not cause conflicts or errors. The specific verification steps include:

[0083] S1.3.1: Analyze the time dependencies between all temporal blocks within the expanded area, the orderliness of the message passing paths, the timing of event triggers, etc., and check whether they meet the constraints of the timing diagram. Especially for cross-temporal block dependencies, ensure that these dependencies are not broken, thus guaranteeing the overall consistency of the timing diagram. For example, if the execution time of a certain temporal block depends on the completion of another temporal block, ensure that all dependencies are satisfied and there are no unreasonable parallel execution situations.

[0084] S1.3.2: If the timing logic verification fails, automatically adjust the expanded area. The adjustment can be carried out in two ways:

[0085] Narrow the expanded scope: If some temporal blocks or message paths introduce conflicts that do not meet the timing constraints, the system will automatically narrow the update scope according to the timing constraint conditions and eliminate the temporal blocks or message paths that cause problems.

[0086] Reorder: The system can also reorder the temporal blocks according to the dependencies between temporal blocks to ensure that the orderliness of the message paths and the timing of event triggers are not disrupted. For example, if the update process causes an order conflict between temporal blocks, the system will adjust the order of the temporal blocks to ensure that there is no time disorder.

[0087] Specifically, the derivation of the extended area not only depends on the user's initial selection, but also determines the precise scope of the update through the system's automatic analysis of the temporal relationships, message passing order, and dependency chains of the timing blocks. Through this intelligent derivation, the system can accurately capture and expand all temporal elements related to the update, avoiding omissions or errors that may occur during traditional manual editing. At the same time, the temporal logic verification and automatic adjustment mechanism ensure temporal consistency during the update process, avoiding error propagation during the design process.

[0088] Based on the initially determined update scope, further derive and expand the update area. The expansion process not only considers the time order of the timing blocks, but also combines factors such as message passing relationships, event triggering times, and temporal dependency relationships to ensure that the update scope can cover all relevant temporal elements. The specific steps of S1.2 are as follows:

[0089] S1.2.1: Analyze the message passing and event triggering relationships between the timing blocks within the initial update scope to obtain temporal dependencies and time constraints;

[0090] First, view the message passing paths in the timing diagram, analyze how messages are passed between timing blocks, and confirm the sequentiality and temporal dependency relationships of the messages. For example, if the message sent by one timing block is the triggering condition for another timing block, then there is a strong dependency relationship between them;

[0091] Then, analyze the triggering times and sequences of the events to confirm which events are synchronously triggered and which events need to wait for other events to complete. The system maps these triggering relationships into a temporal dependency chain and calculates time constraints based on the triggering times of the events;

[0092] Temporal dependency means that the execution of a certain timing block depends on the completion of other timing blocks. For example, the execution of timing block A may depend on timing block B triggering a certain event. This dependency relationship determines the execution order and timing of the timing blocks. In addition to the dependency relationship, time constraints also involve the time interval requirements between timing blocks. For example, there may be a time interval constraint between timing blocks A and B, requiring that after A executes, B must execute within a specified time range;

[0093] Identify which timing blocks and their events are mutually dependent and which timing blocks are independent, and then determine which timing blocks need to be considered together during the update process. The purpose of this step is to ensure that no key dependency relationships are missed in the timing diagram during the update, avoiding design errors caused by inaccurate update scopes.

[0094] Specifically, first, it is necessary to analyze the message passing paths in the timing diagram to clarify the order of message passing and the dependency relationships between timing blocks. Message path analysis can reveal which timing blocks have strong dependencies and which are independent. For example, if the output of timing block A is the trigger condition for timing block B, then there is a strong dependency between A and B, and their updates need to be considered simultaneously. The triggering timing relationships of events determine which events must wait for other events to complete before they can be triggered and which events can be triggered in parallel. These triggering relationships are ultimately mapped into timing dependency chains, which in turn form the basis for time constraint calculation.

[0095] S1.2.2: According to the timing dependencies, deduce the dynamic dependency chains between timing blocks, generate message paths, and calculate the synchronization degree and dependency degree of the message paths in the timing blocks;

[0096] The dependency chains deduced based on timing dependencies represent the execution order between timing blocks. This chain indicates that certain timing blocks must start after other timing blocks have finished executing. For complex timing diagrams, dependency chains with multiple branches may be formed, which determine the expansion direction of the update scope.

[0097] A message path refers to the path in the timing diagram through which data or control signals are passed from one timing block to another. Generating a message path is not just about identifying the existence of these paths but also analyzing the characteristics of these paths, including the message passing order, triggering timing, and passing intervals;

[0098] The synchronization degree indicates whether timing blocks need to execute simultaneously or wait at the same moment. The dependency degree indicates whether a timing block depends on the states of other timing blocks when it executes. The higher the dependency degree, the more strict the requirements for the execution order of other timing blocks by the timing block. By calculating these parameters, it can be further determined which timing blocks must be executed synchronously and which can be executed independently, thereby accurately determining the expansion scope;

[0099] Specifically, according to the timing dependencies, deduce the dynamic dependency chains between timing blocks. These dependency chains reflect the execution order and mutual influence between timing blocks, clarifying which timing blocks cannot be executed until other timing blocks are completed. For complex timing diagrams, the dependency relationships between timing blocks may exhibit a multi-level or branched structure. Therefore, it is necessary to accurately deduce the dependency chains to clarify the update scope of the timing blocks. On this basis, the generated message paths not only include the message passing order but also analyze the timing characteristics, triggering timing, and passing intervals of message passing. Calculating these parameters can help further determine which timing blocks must be executed synchronously and which can be executed independently, thereby accurately expanding the update scope.

[0100] S1.2.3: Analyze the timing blocks through a time window according to the time constraint, and calculate the timing delay factor of the timing blocks. The timing delay factor refers to the minimum delay time generated by the time limit of other timing blocks during message passing or event triggering of the timing blocks.

[0101] The time window represents the maximum time limit for the execution of timing blocks at a certain moment or time period. The size and range of the time window are obtained by analyzing the dependency relationships and constraint conditions between timing blocks. For some timing blocks, their time windows may be restricted by other timing blocks. For example, if timing block A is required to complete within a certain time after B executes, the execution time of A will be restricted by the time of B.

[0102] The timing delay factor measures the impact of the time constraints of other timing blocks on the execution of a timing block. It represents the minimum delay time when a timing block starts to execute. For example, if timing block A depends on the completion of timing block B and the execution time of B is delayed, then the start time of A will be delayed accordingly. The calculation of the timing delay factor is based on the analysis result of the time window, and it can effectively quantify the execution delay of each timing block.

[0103] S1.2.4: Aggregate the timing delay factors of all timing blocks, determine the parallel execution relationship between timing blocks according to the timing delay factor, and calculate the timing extension factor of the timing block according to the parallel blocks and message paths of the current timing block.

[0104] The aggregation of the timing delay factor is mainly used to identify the parallel execution relationship between timing blocks in the timing diagram. By comprehensively considering the delay factors of all timing blocks, it can be determined which timing blocks can be executed in parallel and which timing blocks must be executed serially. The time constraints between parallel execution timing blocks are relatively loose, while the time constraints between serial execution timing blocks are relatively tight.

[0105] In the timing diagram, different timing blocks may be independently executed within the same time period, and this relationship is called parallel execution. The parallel execution ability of timing blocks can be obtained through the aggregation calculation of the timing delay factor. If the delay factors of multiple timing blocks do not affect each other, they can be executed in parallel, thereby reducing the total execution time.

[0106] The timing extension factor is a comprehensive evaluation of the timing delay factors of each timing block in the timing diagram, representing the extension factor of the entire timing update range. It is calculated by considering the parallel blocks of all timing blocks, the order of the message paths, and the total sum of the timing delays. The larger the timing extension factor, the more complex the timing relationship within the extended range and the larger the extension radius.

[0107] Specifically, the time constraints between the concurrently executed timing blocks are relatively loose, while the constraints between the serially executed timing blocks are relatively strict. By aggregating the timing delay factors, the execution relationships of the timing blocks in the timing diagram can be deduced, thus providing a more accurate basis for expanding the update scope. By analyzing the relationships between parallel and serial executions, the execution efficiency of the timing diagram can be optimized, unnecessary execution delays can be reduced, and all relevant timing blocks can be ensured to be appropriately updated.

[0108] S1.2.5: Sort the timing extension factors of all timing blocks, take the largest timing extension factor as the extension radius, and superimpose it with the radius of the initial update scope to obtain the scope to be updated, ensuring that the update scope can comprehensively cover all timing blocks and related elements that need to be updated, and avoiding missing any timing block or event.

[0109] The calculation formula for the timing extension factor is as follows:

[0110]

[0111] where A i represents the timing extension factor of timing block i, δ i represents the timing delay factor of timing block i, n represents the number of parallel blocks of timing block i, j represents a single event of timing block i, N represents the total number of events of timing block i, E j represents the triggering timing of the jth event, T max represents the maximum time delay within timing block i, l represents a single message path of timing block i, M represents the total number of message paths of timing block i, P l represents the load of the lth message path, P max represents the maximum load within timing block i, β l represents the dependency factor of the lth message path, θ l represents the timing synchronization factor of the lth message path.

[0112] Through a comprehensive analysis of the dependency relationships, message passing orders, and time constraints between timing blocks, the initially selected update area can be effectively expanded to ensure that the update scope can cover all affected timing blocks and avoid missing any key timing blocks or events. At the same time, the calculation of the timing delay factor and the timing extension factor can accurately quantify the execution relationships and dependency degrees between timing blocks, thus ensuring that the update process of the timing diagram is more accurate and meets the design requirements.

[0113] By providing an interactive editing interface, users are allowed to make detailed modifications to the timing blocks to ensure the accuracy and rationality of the timing diagram. The pop-up editing box has multiple functional modules, and each module can make refined adjustments to different aspects of the timing block. The pop-up editing box includes:

[0114] An attribute editing tool for displaying and modifying the attribute information of the selected time sequence block, where the attribute information includes trigger timing, execution order, time interval, and message path;

[0115] The trigger timing refers to the moment when the user can adjust the trigger time of an event or time sequence block through this tool. For example, the trigger timing of a certain time sequence block can be postponed or advanced from the current moment to ensure that the time sequence block can be executed in the designed time sequence order;

[0116] The execution order means that for multiple time sequence blocks with concurrent execution or dependency relationships, the user can adjust their execution order to meet specific business requirements;

[0117] The time interval refers to the minimum time interval between two time sequence blocks, which controls the time distribution of the execution of the time sequence block. This tool allows the user to manually adjust the time interval to ensure that the time relationship between the time sequence blocks is within the specified constraints.

[0118] The message path is the communication path between time sequence blocks in the time sequence diagram. The editing tool supports the user to modify the sending order of messages or re-specify the message delivery path to ensure that the messages flow between time sequence blocks in the correct order.

[0119] An event trigger timing adjustment tool for adjusting the trigger timing of each event in the time sequence block and providing a graphical way to display the time relationship between event triggers;

[0120] The event trigger timing adjustment tool displays the trigger positions of each event on the time axis. The user can adjust the trigger order and time position of the events through operations such as dragging. When the user adjusts the trigger timing of an event, the system will automatically adjust the time interval between related events and prompt the user about the possible violated time sequence constraints. This function can help the user ensure that the time constraints in the time sequence diagram are not broken, making the event adjustment of the time sequence diagram more intuitive and accurate. The user can intuitively understand the time relationship between each event, avoid errors caused by manually inputting the time sequence trigger time, and reduce design errors caused by time sequence conflicts.

[0121] A synchronization and dependency relationship editing tool for modifying the message delivery path between time sequence blocks and adjusting the dependency relationship between time sequence blocks;

[0122] The dependency relationship between time sequence blocks determines the execution order of time sequence blocks. The synchronization and dependency relationship editing tool allows the user to redefine the dependency relationship between time sequence blocks and change the execution order of time sequence blocks. For example, some time sequence blocks may depend on the completion of other time sequence blocks to execute. The user can adjust the dependency chain through this tool to make the time sequence diagram meet the new business requirements or design requirements.

[0123] A structure preview tool for displaying a preview of the editing result during the editing process.

[0124] For the selected timing block and its related attributes, a pop-up editing box is used for detailed editing. Through the graphical operations provided by the interactive interface, the modification of the timing block, events, message passing paths, etc. is completed, so as to realize the rapid design and update of the timing diagram. The specific steps of S2 are as follows:

[0125] S2.1: Select the timing block to be edited through the interactive device, and modify the related attributes of the timing block in the pop-up editing box. The attributes include the name of the timing block, the event trigger timing, the time interval of message passing, and the trigger condition;

[0126] The timing block is the basic unit in the timing diagram, which contains information such as events, message paths, and time constraints between them. In the pop-up editing box, for the selected timing block, the related attributes are modified. The specific modification contents include:

[0127] The name of the timing block. By modifying the name of the timing block, different timing blocks can be clearly identified, which helps to better manage each element in the timing diagram. The name of the timing block is usually related to the function or module it carries. By modifying the name, the structural changes in the timing diagram design can be reflected.

[0128] The event trigger timing. The trigger timing of the event determines the execution order of each event within the timing block. Modifying the trigger timing will directly affect the time point of the event in the timing diagram and its relative order with other events. This modification operation is particularly important when dealing with complex timing dependencies.

[0129] The time interval of message passing. The time interval of message passing represents the time delay of communication between events or between timing blocks. By modifying the time interval, the efficiency and delay of message passing can be adjusted. Especially when designing the timing diagram, this parameter is crucial for the smoothness of message passing.

[0130] The trigger condition. The trigger condition of each event is usually related to the completion of other events or external signals. Modifying the trigger condition can redefine the activation condition of the event, change the dependency relationship between events, and thus affect the timing structure within the timing block.

[0131] S2.2: Drag or select the trigger order between events through the graphical interface, and adjust the dependency relationship between events to modify the interaction relationship between timing blocks;

[0132] In the design of the timing diagram, the trigger order and dependency relationship between events are important manifestations of the interaction between timing blocks. Through the graphical interface, the trigger order between events can be intuitively adjusted, and the interaction relationship between timing blocks can be modified. The specific operations include:

[0133] Drag and drop to adjust the event triggering order. In the graphical interface, users can rearrange the event triggering order by dragging and dropping. The order of events determines the order of message transmission in the timing diagram. Modifying the event triggering order will affect the subsequent message path and event synchronization, especially in complex timing diagrams triggered by multiple events. Order adjustment is crucial to the correctness and executability of the timing diagram.

[0134] Adjust the dependencies between events. Dependencies indicate that some events must be triggered after other events are completed. By adjusting the dependencies between events, the execution path of the sequence diagram can be changed, and even the parallel execution or sequential execution of some events may be changed. Changing dependencies is a key means to handle complex business logic and timing rules in sequence diagrams.

[0135] Modify the interaction between timing blocks. The interaction between timing blocks is usually reflected through message passing and event triggering. By modifying the interaction, the overall structure of the timing diagram can be affected, especially when there are complex message passing paths and multiple dependencies. Modifying the interaction can effectively optimize the execution efficiency and correctness of the timing diagram.

[0136] S2.3: During the editing process, the synchronization factor and delay factor of each event in the timing block are displayed in real time, and the synchronization and delay relationship between events are changed according to the synchronization factor and delay factor;

[0137] Specifically, a key feature of the timing diagram is the synchronization and delay of events. The synchronization factor and delay factor directly determine the execution mode and time relationship of events in the timing diagram. During the editing process of the timing block, the synchronization factor and delay factor are calculated and displayed in real time to ensure that the designed timing diagram meets the timing requirements and can provide efficient and accurate time control.

[0138] The synchronization factor indicates the degree to which multiple events occur simultaneously. In a multi-event timing block, some events may be triggered simultaneously, or need to be executed synchronously under certain conditions. The calculation of the synchronization factor helps to understand the time relationship between events and ensure that their synchronization is correctly executed. For example, if the synchronization factor of multiple events is 1, it means that these events are triggered at the same time; if the synchronization factor is less than 1, it means that these events are staggered in time.

[0139] The delay factor represents the time delay between event triggering. The calculation of the delay factor can accurately control the execution time of events and ensure that events are executed according to the predetermined timing. The delay factor is particularly important for timing diagrams under multi-event dependencies. By adjusting the delay factor, the execution efficiency of the timing diagram can be effectively optimized to avoid unnecessary waiting or delays.

[0140] S2.4: Conduct logical verification on the timing block and its timing attributes, including time dependence, the order of event triggering times, and the time interval of message passing.

[0141] The design and update of the timing diagram must follow strict timing constraints; otherwise, it may lead to timing errors or logical conflicts. After the editing of the timing block and its attributes is completed, logical verification must be performed on the timing block and its attributes to ensure that the timing diagram conforms to the timing logic and design requirements. The specific verification content includes:

[0142] Time dependence verification. Time dependence means that the execution time of a certain timing block depends on the completion time of other timing blocks. If there are time dependence relationships among multiple timing blocks, it must be ensured that these dependencies do not cause conflicts. The verification of time dependence can prevent the occurrence of timing conflicts in parallel or sequential execution, ensuring that the events in the timing diagram are executed in the correct order.

[0143] Verification of the order of event triggering times. The triggering order of events must conform to the design requirements. In a timing block with multiple event triggers, if the order of events is incorrect, it may lead to incorrect message passing or logical execution. By verifying the order of triggering times, it is ensured that each event is triggered in the correct time order, avoiding logical inconsistencies.

[0144] Verification of the time interval of message passing. The time interval of message passing is usually related to factors such as the triggering times of events and the execution order. Verifying the time interval of message passing can ensure that message passing does not cause errors due to too short or too long time intervals. By verifying the time interval, timing problems caused by time constraint errors can be effectively avoided.

[0145] The described logic generation box includes:

[0146] A standardization conversion tool for converting the modifications made to the timing block and its timing attributes during the editing process into timing logic fragments that conform to the specifications;

[0147] A timing verification tool for checking the time dependence, the triggering order of events, and the message passing path within the logic fragment, and performing functional verification on the generated timing logic fragment;

[0148] A timing dependence relationship conversion tool for analyzing and converting the dependence relationship between the edited timing logic fragment and the original timing diagram;

[0149] A timing attribute synchronization tool for verifying whether the timing attributes of the updated timing block in the entire timing diagram meet the overall consistency and synchronization.

[0150] The specific steps of the described S4 are as follows:

[0151] S4.1: When new timing blocks or updated content are introduced, adjust the spatial layout according to the timing relationships, event triggering timings, message passing paths, and timing attributes among the timing blocks in the timing diagram;

[0152] S4.2: By analyzing the timing dependency chains of each timing block, adjust the relative order and connection relationships of the timing blocks, generate new message paths according to the dependency degrees and timing attributes among the timing blocks, and reconnect the updated timing blocks according to the dependency relationships;

[0153] S4.3: According to the time constraints of each timing block, analyze the time overlaps and parallel execution situations among the timing blocks, and adjust the execution order and spatial distribution among the timing blocks.

[0154] Embodiment 2:

[0155] Please refer to Figure 2 , the present invention provides an embodiment: a fast design update verification system for a timing diagram of an architecture model based on timing blocks, the system includes a selection and extension module, an editing and derivation module, a logic verification module, and a layout adjustment module;

[0156] The selection and extension module is configured with an intelligent extension strategy, and the intelligent extension strategy is used to determine an initial update range and extend the initial update range according to the time order, message passing sequentiality, and timing block dependency relationship of the timing blocks within the initial update range;

[0157] The editing and derivation module is used to edit the timing blocks and their timing attributes in a pop-up editing box, and the editing includes modifying the attributes of the timing blocks;

[0158] The logic verification module is used to convert the editing result into a standardized logic fragment through a logic generation box;

[0159] The layout adjustment module is used to fuse the standardized logic fragment with the original timing diagram according to the layout algorithm of the timing diagram.

[0160] The selection and extension module includes:

[0161] An initial circumscribing unit, which is used to perform a selection operation in the timing diagram interface through an interaction device to determine the initial update range of the area to be updated;

[0162] An intelligent update unit, which is used to dynamically extend the initial update range and generate a new area to be updated;

[0163] An area display unit, which is used to display the area to be updated in the form of a dynamic box.

[0164] The editing and derivation module includes:

[0165] Timing Attribute Editing Unit: Used to select and edit the relevant attributes of timing blocks through an interactive device, such as event triggering timing, message passing time interval, triggering conditions, etc. This unit provides a graphical interface, and users can operate by dragging, inputting, or selecting.

[0166] Event Order Adjustment Unit: Used to adjust the triggering order and dependency relationships of events in timing blocks. Supports graphical dragging and adjustment, and automatically updates the timing synchronization factor and delay factor of events.

[0167] Synchronization Dependency Deduction Unit: Used to deduce and display the synchronization and dependency relationships between timing blocks based on editing operations, calculate and display timing attributes such as synchronization factors and delay factors between events, to help designers evaluate the feasibility and consistency of the edited timing diagram.

[0168] The logic verification module includes:

[0169] Timing Logic Generation Unit: Converts the result of modifying the timing block attributes in the editing and deduction module into timing logic fragments that conform to the design specifications, ensuring that the generated logic fragments meet the timing constraint requirements.

[0170] Timing Dependency Verification Unit: Verifies whether the dependency relationships of the generated timing logic fragments conform to the predetermined timing rules, especially the time dependencies between timing blocks, message passing order, etc.

[0171] Timing Consistency Verification Unit: Performs timing consistency verification on the generated logic fragments to ensure the coordination and consistency of all timing blocks, message paths, and event triggering conditions within the global scope.

[0172] The layout adjustment module includes:

[0173] Timing Relationship Analysis Unit: Analyzes the relative positions and execution orders of timing blocks according to the time order, event triggering timing, and message passing paths of timing blocks in the timing diagram, and generates a reasonable spatial layout plan.

[0174] Dependency Relationship Adjustment Unit: Adjusts the relative order and connection methods of timing blocks according to the dependency relationships and timing attributes between timing blocks, ensuring that the layout conforms to the actual timing flow and dependency structure.

[0175] Spatial Optimization Unit: Optimizes the spatial distribution of the timing diagram according to the layout algorithm, avoids overlap and resource conflicts between timing blocks, and improves the readability of the graphical interface and the user interaction experience.

[0176] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for rapid design update verification of timing diagram of architecture model based on timing block, characterized in that: The method comprises: Selecting a region to be updated in a timing diagram interface through an interactive device, wherein the region to be updated is displayed in the form of a dynamic frame, wherein the dynamic frame includes a timing block, an interactive relationship, and a timing attribute, wherein the timing attribute includes a time interval for message transmission, a triggering timing of an event, and a transmission relationship between timing blocks; Generate a pop-up edit box corresponding to the area to be updated, and edit the timing block and its timing attributes in the pop-up edit box, wherein the editing includes modifying the attributes of the timing block; The editing result is converted into a standardized logic fragment through a logic generation frame, and the standardized logic fragment is merged with the original timing diagram according to the layout algorithm of the timing diagram.

2. According to claim 1, a method for rapid design update verification of timing diagram of architecture model based on timing block, characterized in that: The step of selecting the area to be updated includes: Performing a selection operation in the timing diagram interface through an interactive device to determine the initial update range of the area to be updated, wherein the selection operation includes a frame selection operation, a timing block selection operation, and a message path selection operation, wherein the message path selection operation includes selecting a message transmission path and a timing constraint relationship between timing blocks; Expanding the initial update range according to the time sequence, message delivery sequence and timing block dependency of the timing blocks within the initial update range; The expanded area to be updated is highlighted in the timing diagram interface through a dynamic box, and the timing logic verification is performed. If the verification passes, it is marked as the area to be updated. If the verification fails, the update range is readjusted according to the timing constraint relationship.

3. According to claim 2, a method for rapid design update verification of timing diagram of architecture model based on timing block, characterized in that: The scope of the extended initial update includes: Analyze the message passing and event triggering relationship between the timing blocks within the initial update range to obtain timing dependencies and time constraints; According to the timing dependency, a dynamic dependency chain between timing blocks is derived, a message path is generated, and a synchronization degree and a dependency degree of the message path in the timing block are calculated; According to the time constraint, the timing block is analyzed through the time window to calculate the timing delay factor of the timing block, wherein the timing delay factor refers to the minimum delay time caused by the time constraint of other timing blocks during the message transmission or event triggering process of the timing block; Aggregate the timing delay factors of all timing blocks, determine the parallel execution relationship between the timing blocks according to the timing delay factors, and calculate the timing expansion factor of the timing block according to the parallel blocks and message paths of the current timing block; The timing expansion factors of all timing blocks are sorted, and the largest timing expansion factor is taken as the expansion radius, which is superimposed with the radius of the initial update range to obtain the range to be updated.

4. According to claim 3, a method for rapid design update verification of timing diagram of architecture model based on timing block, characterized in that: The calculation formula of the timing expansion factor is: Among them, A i represents the timing expansion factor of timing block i, δ i represents the timing delay factor of timing block i, n represents the number of parallel blocks of timing block i, j represents a single event of timing block i, N represents the total number of events of timing block i, E j Indicates the triggering time of the jth event, T max represents the maximum delay within timing block i, l represents a single message path of timing block i, M represents the total number of message paths of timing block i, and P l represents the load of the lth message path, P max represents the maximum load in timing block i, β l represents the dependency factor of the lth message path, θ l Indicates the timing synchronization factor of the lth message path.

5. According to claim 4, a method for rapid design update verification of timing diagram of architecture model based on timing block, characterized in that: The pop-up edit box includes: A property editing tool, used to display and modify the property information of the selected timing block, wherein the property information includes triggering timing, execution sequence, time interval and message path; Event trigger timing adjustment tool, used to adjust the trigger timing of each event in the timing block, and provide a graphical display of the time relationship between event triggers; Synchronization and dependency editing tools, used to modify the message passing path between timing blocks and adjust the dependencies between timing blocks; The structure preview tool is used to display the preview screen of the editing results during the editing process.

6. According to claim 5, a method for rapid design update verification of timing diagram of architecture model based on timing block, characterized in that: Edit the timing block and its timing properties in the pop-up edit box, including: Select the timing block to be edited through the interactive device, and modify the relevant properties of the timing block in the pop-up edit box, the properties including the name of the timing block, event triggering timing, message transmission time interval and triggering condition; Drag or select the triggering order between events through the graphical interface, adjust the dependencies between events, and modify the interaction between timing blocks; During the editing process, the synchronization factor and delay factor of each event in the timing block are displayed in real time, and the synchronization and delay relationship between events are changed according to the synchronization factor and delay factor; Logical verification of timing blocks and their timing properties, including time dependencies, the order of event triggering timing, and the time interval for message delivery.

7. A method for rapid design update verification of timing diagram of architecture model based on timing blocks according to claim 6, characterized in that: The logic generation box includes: Standardization conversion tool, used to convert the modifications made to timing blocks and their timing attributes during editing into timing logic fragments that meet the specifications; Timing verification tools are used to check the time dependency, event triggering sequence, and message delivery path within the logic fragment, and to perform functional verification on the generated sequential logic fragment; Timing dependency conversion tool, used to analyze and convert the dependencies between the edited timing logic fragment and the original timing diagram; The timing attribute synchronization tool is used to verify whether the timing attributes of the updated timing block in the entire timing diagram meet the overall consistency and synchronization.

8. According to claim 7, a method for rapid design update verification of timing diagram of architecture model based on timing block, characterized in that: The layout algorithm of the timing diagram includes: When new timing blocks or updated content are introduced, the spatial layout is adjusted according to the timing relationship between the timing blocks in the timing diagram, event triggering timing, message transmission path and timing attributes; By analyzing the timing dependency chain of each timing block, the relative order and connection relationship of the timing blocks are adjusted, and according to the dependency degree and timing attributes between the timing blocks, a new message path is generated, and the updated timing blocks are reconnected according to the dependency relationship; According to the time constraints of each timing block, the time overlap and parallel execution between the timing blocks are analyzed, and the execution order and spatial distribution between the timing blocks are adjusted.

9. A system for rapid design update verification of timing diagram of architecture model based on timing block, which is implemented based on a method for rapid design update verification of timing diagram of architecture model based on timing block as claimed in any one of claims 1 to 8, characterized in that: The system includes a selection and expansion module, an editing and derivation module, a logic verification module and a layout adjustment module; The selection expansion module is configured with an intelligent expansion strategy, which is used to determine the initial update range and expand the initial update range according to the time sequence of the timing blocks within the initial update range, the message transmission sequence and the timing block dependency; The editing and derivation module is used to edit the timing block and its timing attributes in a pop-up editing box, wherein the editing includes modifying the attributes of the timing block; The logic verification module is used to convert the editing result into a standardized logic fragment through a logic generation box; The layout adjustment module is used to merge the standardized logic fragment with the original timing diagram according to the layout algorithm of the timing diagram.

10. The system for rapid design and update verification of timing diagram of architecture model based on timing blocks according to claim 9, characterized in that: The selection expansion module includes: An initial delineation unit, used to perform a selection operation in the time sequence diagram interface through an interactive device to determine an initial update range of the area to be updated; An intelligent update unit, used to dynamically expand the initial update range and generate a new area to be updated; The area display unit is used to display the area to be updated in the form of a dynamic frame.

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