A chip optimization processing method, system and chip

Abstract

The application discloses a chip optimization processing method and system and a chip. The method comprises the following steps: an on-chip system located on the chip acquires rules. The rules reflect behavior prediction when the on-chip system runs target software, and the rules are obtained by analyzing running information collected when the on-chip system historically runs the target software. The running information is generated when the on-chip system runs the target software. The on-chip system takes measures in advance according to the rules when running the target software. The measures taken in advance estimate future operations of the on-chip system and make preparations for the operations. The application solves the problems of being unable to cover other software and high cost caused by using a hardware accelerator when optimizing a processor for specific software, so that the optimization of the processor performance can be realized for different target programs.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip field, in particular to a chip optimization processing method and system and chip. BACKGROUND

[0002] The traditional processor mainly faces the general computing scene, and the target is to cope with flexible programs and have a relatively balanced performance, but this will inevitably produce different performance fluctuations due to different programs. In fact, in some scenarios, the same program will run for a long time, including but not limited to cloud computing, servers running search, recommendation, advertising, EDA, and other special programs.

[0003] In order to further improve the software running efficiency, the most easily thought way is to improve the performance of the processor. However, in the actual application process, it is very high to design special hardware for programs. In another processing method, a hardware dedicated accelerator (Domain Specific Accelerator, referred to as DSA) can be used. The hardware accelerator is a hardware architecture designed for specific programs to achieve optimal performance, but the disadvantage is that it cannot cover a wide range of scenarios, and the cost is also not low. SUMMARY

[0004] The embodiments of the present application provide a chip optimization processing method, system and chip to at least solve the problem that the hardware accelerator cannot cover other software and the cost is high when the processor is optimized for specific software.

[0005] According to one aspect of the present application, a chip optimization processing method is provided, comprising: an on-chip system located on a chip acquires a rule, wherein the rule reflects the behavior prediction when the on-chip system runs a target software, and the rule is analyzed according to the running information collected when the on-chip system historically runs the target software, and the running information is generated by the on-chip system running the target software; the on-chip system takes measures in advance according to the rule when running the target software, wherein the measures are determined according to the rule, the measures taken in advance estimate the future operations of the on-chip system and prepare for the operations.

[0006] Further, the analysis software receives the running information, wherein the running information is obtained through an interface pre-configured on the chip, and the running information is saved in a storage space outside the chip after being read out from the interface; the analysis software determines the rule after analyzing the running information; the analysis software sends the rule to the system on chip; or, the system on chip obtains the rule, including that the analysis software receives the running information; the analysis software obtains parameters for generating the rule according to the running information; the system on chip receives the parameters, and uses the parameters in an algorithm running on the system on chip to generate the rule; wherein, the algorithm is used to generate the rule.

[0007] Further, the computing resource running the analysis software is different from the system on chip running the target software.

[0008] Further, in the case that the chip includes multiple cores, the cores on the chip include two parts, the first part of the two parts is used to run the analysis software, and the second part of the two parts is used to run the target software as a system on chip; or, the analysis software runs on a computing device which is different from the computing device where the chip is located; or, the analysis software runs in the system on chip, and the system on chip uses different time domain resources to run the analysis software and the target software in time division.

[0009] Further, the target software runs on multiple chips, wherein the multiple chips are respectively located on different computing devices; the analysis software receives running information generated by the system on chip running the target software on each chip of the multiple chips; the analysis software analyzes all the running information generated by the system on chip to obtain the rule; and the analysis software transmits the rule to the system on chip on each chip of the multiple chips.

[0010] According to another aspect of the present application, a chip is also provided, including a central processing unit and a cache; wherein, the system on chip on the chip is used to perform the following method steps: obtaining a rule, wherein the rule reflects a behavior prediction when the system on chip runs a target software, and the rule is obtained by analyzing running information collected when the system on chip historically runs the target software, and the running information is generated by the system on chip running the target software; and taking measures in advance according to the rule when running the target software, wherein the measures are determined according to the rule, the measures taken in advance predict future operations of the system on chip and prepare for the operations.

[0011] Further, the chip further comprises one or more interfaces, the interfaces are configured to send the running information outside the system on chip, and receive rules from the analysis software or receive parameters from the analysis software; wherein the parameters are used in an algorithm running on the system on chip, the rules are generated according to the parameters.

[0012] According to another aspect of the present application, a chip optimization processing system is further provided, comprising the chip and the analysis software, wherein the analysis software is configured to perform the following steps: receiving the running information, wherein the running information is obtained through the interface pre-configured on the chip, and the running information is saved in a storage space outside the chip after being read out from the interface; determining the rules after analyzing the running information; sending the rules to the system on chip; or obtaining the parameters for generating the rules according to the running information, and sending the parameters to the system on chip; wherein the parameters are used in an algorithm running on the system on chip, and the rules are generated according to the parameters; and the algorithm is configured to generate the rules.

[0013] Further, the computing resource running the analysis software is different from the system on chip running the target software.

[0014] Further, in the case that the chip comprises a plurality of cores, the cores on the chip comprise two parts, the first part of the two parts is configured to run the analysis software, and the second part of the two parts is configured to run the target software as a system on chip; or the analysis software runs on a computing device, and the computing device is different from the computing device where the chip is located; or the analysis software runs in the system on chip, and the system on chip uses different time domain resources to run the analysis software and the target software in time division.

[0015] In the embodiments of the present application, the system on chip on the chip is used to obtain the rules, wherein the rules reflect the behavior prediction of the system on chip running the target software, the rules are obtained by analyzing the running information collected when the system on chip runs the target software in the past, and the running information is generated when the system on chip runs the target software; the system on chip takes measures in advance according to the rules when running the target software, wherein the measures are determined according to the rules, the measures taken in advance estimate the future operations of the system on chip and prepare for the operations. The present application solves the problem that the use of hardware accelerators for processor optimization for specific software cannot cover other software and the cost is high, so that the optimization of processor performance can be realized for different target programs. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings, which are part of the specification, illustrate embodiments of the present application and, together with the general description of the application given above, and the detailed description of the embodiments given below, serve to explain the application. In the drawings:

[0017] Figure 1 is a schematic diagram of computer hardware and software architecture according to the related art;

[0018] Figure 2 is a schematic diagram of target software running optimization according to an embodiment of the present application Figure 1 ;

[0019] Figure 3 is a schematic diagram of target software running optimization according to an embodiment of the present application Figure 2 ;

[0020] Figure 4 is a schematic diagram of target software running optimization according to an embodiment of the present application Figure 3 ;

[0021] Figure 5 is a schematic diagram of interaction timing according to an embodiment of the present application Figure 1 ;

[0022] Figure 6 is a schematic diagram of interaction timing according to an embodiment of the present application Figure 2 ;

[0023] Figure 7 is a schematic diagram of interaction timing according to an embodiment of the present application Figure 3 ;

[0024] Figure 8 is a schematic diagram of interaction flow according to an embodiment of the present application;

[0025] Figure 9 is a schematic diagram of interaction flow according to an embodiment of the present application; and,

[0026] Figure 10 is a flowchart of a chip optimization processing method according to an embodiment of the present application. DETAILED DESCRIPTION

[0027] It should be noted that the embodiments and features of the present application can be combined with each other in the case of no conflict. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0028] It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described herein can be executed in an order different from that shown herein.

[0029] In the related art, in order to improve performance, a processor is usually implemented using more resources, for example, in order to improve the hit rate of cache, the traditional processor manufacturer mainly increases the area of cache and improves the amount of data in cache to improve performance. This way will increase the cost and also make the size of the processor larger. In the following embodiments, the historical running information of the target software or target program is mainly fully processed and analyzed to predict the future running track. In this way, the performance is not replaced by area, but the performance is improved by prediction, while the area is saved.

[0030] First, the technical terms involved in the following embodiments are described below.

[0031] System on chip

[0032] In the following embodiments, the system in the chip (or also called processor) is called system on chip, which can include central computing unit, cache, etc. In some documents, the central processing unit (CPU) can be understood as a system on chip, and in other documents, the central processing unit can also be understood as a central computing unit on the system on chip. In order to avoid such ambiguity, system on chip and central computing unit are used in the following embodiments.

[0033] Offline software or offline program

[0034] In the following embodiments, the online program represents real-time running, for example, the target software is an online software, which is running in real time for high performance; the analysis software is an offline program, which can be run offline separately in time sequence or on other machines, and the analysis software can also be an online program for online analysis for high performance. It should be noted that if there are multiple cores, the cores can be divided into two parts, one part running online program, and the other part running offline program. In an example, the processing running inside the chip is a hardware real-time processing, but if it is running in real time on the operating system layer on the system on chip, it is also an online program, and offline is a separation in time and space, for example, not real-time running is called offline, and running on other systems is called offline, and the scene requiring high performance execution will choose online implementation.

[0035] Figure 1 According to the computer software and hardware architecture diagram in the related art, as shown in Figure 1 , the application or program runs on the operating system, and then runs on the chip through the compiler. In Figure 1 , the application or program, operating system and compiler are all called software part, and the chip and the chip inside running system on chip are called hardware part.

[0036] i-cache and d-cache

[0037] The i-cache (instruction cache) and d-cache (data cache) play different roles to improve the execution efficiency of the system-on-chip and the overall system performance. The i-cache is a cache specifically used to store the instructions that the system-on-chip is about to execute. When the system-on-chip needs to execute an instruction, it will first check if the instruction has been cached in the i-cache. If the instruction is already cached in the i-cache (known as a cache hit), the system-on-chip can directly read the instruction from the i-cache without waiting for it to be fetched from the memory. This significantly improves the access speed of the instruction, thus speeding up the execution efficiency of the program. The d-cache is a cache specifically used to store the data that the system-on-chip has recently used, such as variables, arrays, etc. When the system-on-chip needs to access these data, it will check if the data has been cached in the d-cache. If the data is already cached in the d-cache, the system-on-chip can directly read it from the d-cache, thus avoiding the delay caused by frequently reading data from the memory. This improves the access speed of the data, thus enhancing the overall performance of the program.

[0038] In one example, the system-on-chip can also employ multi-level caching, in which case the i-cache and d-cache can be part of the multi-level cache system integrated within the system-on-chip. For example, a typical system-on-chip can contain L1, L2, and L3 three-level caches. Among them, the L1 cache is the cache closest to the core of the system-on-chip, which is usually divided into i-cache and d-cache two parts. When the system-on-chip executes a program, it will first look for the required instructions and data in the L1 cache. If the required data or instructions are not found in the L1 cache, the system-on-chip will further look for them in the L2 or L3 cache.

[0039] In the following embodiments, in order to improve the performance of the system-on-chip, the running of the system-on-chip is predicted, so that the instructions and / or data can be prefetched in advance. This prefetching can include: configuring the instructions needed in the future in the i-cache, and / or configuring the data needed in the future in the d-cache.

[0040] Overview of paging mechanism

[0041] Paging is a finer-grained memory space partitioning mechanism than segmentation. When paging is enabled, the processor must go through a page management mechanism to translate a linear address into a physical address. Paging divides both the linear address space and the physical address space into fixed-size pages (typically 4 KB) and maintains a set of page translation table structures through the memory management unit (MMU) to complete the mapping and translation of linear address space pages to physical address pages.

[0042] Replace algorithm

[0043] The replace algorithm for a central processing unit refers to an algorithm used to manage the allocation of central processing unit time slices. It is mainly used to determine which programs will be given priority for allocation to the central processing unit when multiple programs are running simultaneously. These algorithms take into account factors such as program priority, central processing unit load, I / O operation frequency, and size. Several replace algorithms in the related art are introduced below.

[0044] Optimal page replacement algorithm: This is a theoretical algorithm that can select the page that will not be accessed for the longest time in the future for replacement, thereby minimizing the page fault rate. However, due to its complexity and large amount of calculation, it is rarely used in actual systems.

[0045] First-in, first-out (FIFO) algorithm: This algorithm replaces pages in the order in which they entered the memory, with the earliest entering page being replaced first. This algorithm is simple to implement, but can lead to the "Belady phenomenon", where an increase in allocated pages leads to an increase in page fault rate.

[0046] Least recently used (LRU) algorithm: This algorithm selects the least recently used page for replacement. The LRU algorithm can better reflect the usage trend of pages, but requires more management overhead.

[0047] Clock algorithm: This is an approximate implementation of the LRU algorithm, which determines which pages should be replaced by simulating the ticking of a clock. This algorithm reduces management overhead, but in some cases does not perform as well as LRU.

[0048] The technical solutions in the following embodiments can be applied to replace algorithms.

[0049] Translation lookaside buffer

[0050] Translation Lookaside Buffer (TLB), also translated as page table cache, address bypass cache, is a cache on chip, used by memory management unit to improve the speed of virtual address to physical address translation. All desktop and server chips (such as x86) use TLB. TLB has a fixed number of space slots for storing virtual address mapping to physical address tag page table entries. It is a typical content-addressable memory (CAM). Its search key is virtual memory address, and the search result is physical address. If the requested virtual address exists in the TLB, the CAM will give a very fast matching result, and then the obtained physical address can be used to access the memory. If the requested virtual address does not exist in the TLB, the tag page table will be used for virtual to physical address translation, and the access speed of the tag page table is much slower than that of the TLB. Some systems allow the tag page table to be swapped to secondary storage, so the virtual to physical address translation may take a very long time.

[0051] The technical solutions in the following embodiments can also be applied in the TLB.

[0052] Target software

[0053] The target software is software running on the operating system. In an example, the target software is running online in real time; the analysis software can be offline, or online in a high-performance demand scenario. The target software can be software with various functions, for example, in a big data system, the target software can be software for data processing; in a video system, the target software can be software for image processing, etc. In the following embodiments, the target software can be long-term running software, for example, the license plate recognition and early warning software in a video monitoring system is long-term running software. The optimization processing measures in the following embodiments can be used for these software, so that the running of the target software is more efficient. In order to distinguish from the target software, in the following embodiments, the software (chip information offline processing program) for analyzing and processing chip information is called log analysis software (referred to as analysis software), which can also be called first software (hereinafter, offline software refers to first software), and the target software can also be called second software.

[0054] In order to solve the problems in the related art, in the following embodiments, a chip optimization processing method is provided, Figure 10 is a flowchart of the chip optimization processing method according to the embodiments of the present application, as Figure 10 shown, the steps included in the method in Figure 10 are described below.

[0055] Step S102, an on-chip system on a chip acquires a rule, wherein the rule reflects a behavior prediction of the on-chip system running a target software, and the rule is analyzed according to running information collected when the on-chip system historically runs the target software.

[0056] The rule used in this step can be analyzed in various ways. As an optional embodiment, the running information can be analyzed by analysis software. The analysis software can process the rule through a pre-step: the analysis software receives the running information, wherein the running information is acquired through an interface pre-configured on the chip, and the running information is saved in a storage space (e.g., a memory) outside the chip after being read out from the interface; the analysis software determines the rule after analyzing the running information; and the analysis software sends the rule to the on-chip system.

[0057] For the rule, it can be determined according to the running of the on-chip system whether the optimization of the rule needs to be continued. As an optional embodiment, after the rule is obtained according to the running information, the on-chip system runs the target software according to the rule, records performance data of the on-chip system running the target software according to the rule; in the case that the performance data meets the expectation, the rule is determined to be a required rule; in the case that the performance data does not meet the expectation, the on-chip system continues to run the target software to collect the running information, the analysis software generates a rule again according to all the collected running information, the on-chip system runs the target software according to the rule generated again, records the performance data again and judges whether it meets the expectation, and so on, until the performance data meets the expectation.

[0058] Step S104, the on-chip system takes a measure in advance according to the rule when running the target software, wherein the measure is determined according to the rule, and the measure taken in advance estimates future operations of the on-chip system and prepares for the operations.

[0059] Step S106, different rules are used by the on-chip system when running different target softwares.

[0060] Through the above steps, the problem that the use of a hardware accelerator for processor optimization for a specific software cannot cover other software and the cost is high is solved, so that the optimization of processor performance can be realized for different target programs.

[0061] In the above steps, there are many measures that can be taken by the on-chip system according to the rule, which will be illustrated by examples.

[0062] In an example 1, the SoC determines, according to the rule, a cache to be used in the future when running the target software, and prepares the cache to be used in the future in advance, the cache including at least one of: an instruction cache, a data cache.

[0063] In an example 2, the SoC determines, according to the rule, an instruction branch to be used in the future when running the target software, and prepares the instruction branch to be used in the future in advance.

[0064] In an example 3, the SoC determines, according to the rule, a translation lookaside buffer to be used in the future when running the target software, and prepares the translation lookaside buffer to be used in the future in advance.

[0065] It should be noted that the above three examples can be used alone or together, and of course, other measures can be taken.

[0066] For the analysis software, the computing resource running the analysis software and the SoC running the target software can be different computing resources. For example, in the case where the chip includes multiple cores, the cores on the chip include two parts, the first part of the two parts is used to run the analysis software, and the second part of the two parts is used as the SoC to run the target software. For another example, the analysis software runs on a computing device, and the computing device is different from the computing device where the chip is located. For another example, the target software runs on multiple chips, wherein the multiple chips are respectively located on different computing devices; the analysis software receives the running information generated by the SoC running the target software on each of the multiple chips; the analysis software analyzes all the running information generated by the SoCs to obtain the rule; and the analysis software transmits the rule to the SoC on each of the multiple chips.

[0067] In another example, the SoC can run an algorithm, and the algorithm can generate the rule. At this time, the SoC obtaining the rule includes: the analysis software receiving the running information; the analysis software obtaining parameters for generating the rule according to the running information; the SoC receiving the parameters, and using the parameters in the algorithm running on the SoC to generate the rule; wherein the algorithm is used to generate the rule. In this example, the algorithm can be a neural network model, and the parameters can be parameters or weights of layers of the neural network model.

[0068] The above will be described in detail below with reference to the accompanying drawings.

[0069] Figure 2 is a schematic diagram of running optimization of target software according to an embodiment of the present application,Figure 2 The software side in the above corresponds to Figure 1 The software part in the above, Figure 2 The hardware side in the above corresponds to Figure 1 The hardware part in the above, Figure 2 The chip information offline processing program in the above corresponds to the analysis software mentioned above, Figure 2 The real-time running accelerated program in the above corresponds to the target software mentioned above. The hardware side has multiple cores, which can include two-part cores: the first part of the cores includes core 10, core 11 to core 1M, and the second part of the cores includes core 20, core 21 to core 2N. The second part of the cores is used to run the accelerated program, and this part of the cores is called the program acceleration core. The first part of the cores is used to run the analysis software, and this part of the cores is called the information processing core.

[0070] An interface is configured on the hardware side, which can be configured to obtain the running information obtained by the core for running the target program during the running of the target program (i.e., the chip running information on the hardware side) from the system on a chip, and the obtained running information can be saved in the memory. Here, the memory is not the cache on the chip, and the memory has a larger storage capacity than the cache, so a large amount of running information can be saved. These running information will be used to predict the information of the target software running on the system on a chip in the future, and the result of the prediction can be used to guide the running of the system on a chip on the target program.

[0071] The prediction is analyzed by the chip information offline processing program (i.e., the analysis software) (it should be noted that, in an example, in some high-performance demand scenarios, real-time analysis of the program can also be performed in real time, and the rules are configured in real time, i.e., the analysis software can be offline or online), and the characteristics of the system on a chip running the target software are obtained through analysis. The rules (i.e., the running rules generated by the software side) are obtained through analysis of these characteristics, which predict the future behavior of the system on a chip running the target software. After obtaining the rules, the rules are sent to the program acceleration core through the memory, and the program acceleration core processes the target software according to the rules.

[0072] In Figure 2 The analysis software is run by a part of the cores, and in another embodiment, it can also be executed by an independent host or computing resource. Figure 3 is a schematic diagram of the target software running optimization according to the embodiment of the application Figure 2 As shown in Figure 3 is used instead of Figure 3 Figure 2 ​The first part of the kernel (i.e., the information processing kernel) requires clarification. It's important to note that the "separate host" here refers to a chip running the analysis software that is not the same chip running the target software. This separate host can also be understood as computing resources independent of the chip running the target software. These computing resources can be a single host, a cluster of hosts, or cloud computing resources. Figure 3 In this context, the target software (i.e., the accelerated program) runs through a chip, which may contain multiple cores. Figure 3 Kernels 0, 1, and K are used to run the target software. During execution, they collect hardware chip operation information. The software offline processing program (i.e., analysis software) generates operation rules based on the operation information (the operation rules here are related to...). Figure 2 The operating rules are the same in all cases. After generating the operating rules, they are sent to the on-chip system (OSS) on the chip. The OSS then processes the target software according to the operating rules.

[0073] The target software may also run on multiple different hosts or on different processors, which can be understood as chips. Figure 4 This is a schematic diagram of the target software operation optimization according to the embodiments of this application. Figure 3 ,like Figure 4 As shown, the processors here operate in a distributed manner, with each processor running the target software. Each processor sends runtime information to the analysis software, which then aggregates and analyzes the runtime information to derive the runtime rules (i.e., Figure 4 The system executes the rules (as specified in the instructions) and sends these rules to the processors. It should be noted that the execution rules sent to each processor can be the same, or different rules can be sent based on the processor's attributes.

[0074] As can be seen from the above implementation methods, the software program can be divided into two parts: one part is the program to be accelerated that runs in real time (i.e., the target software or target program), and the other part is the software program that performs offline processing on the information generated by the real-time operation of the on-chip system (i.e., the analysis software or analysis program).

[0075] In the above Figure 2 to Figure 4 In terms of structural division, the software side runs an offline analysis program and a real-time accelerated program. On the hardware side, the on-chip system's operational information generated by the target program is transmitted to the software-side offline analysis program. The offline analysis program can function like... Figure 2 It can run on a portion of the information processing core of the same server, or it can run on other servers or PC hosts. The memory layer is an information exchange mechanism that can, for example... Figure 2 This kind of internal interaction via memory can also be like... Figure 3 or Figure 4The information is exchanged between the other host through the network or other forms. In another example, the analysis software can also run in the system on chip, which runs the analysis software and the target software in different time domain resources. Regardless of how the analysis software and the target software use different computing resources, the analysis software obtains the running information through the storage device outside the chip, then analyzes, and finally optimizes the running of the target software in the system on chip through the rule. As an example, the external storage device can be the memory outside the chip, which is connected with the chip. The following is described by taking the memory as an example.

[0076] The memory can be a storage medium outside the CPU chip or a storage medium on the chip, which stores not only the instructions and data required by the program, but also the CPU key information generated by the acceleration core (i.e., the core running the target program). The software calculates and generates new running rules by using the key information, which are sent to the memory and configured to the program acceleration core (i.e., the core running the target program) to guide the CPU running behavior and improve the system performance.

[0077] The above Figure 2 to Figure 4 Several optional architectures are introduced, and the following describes several optional software and hardware interaction time sequences. The system on chip runs the target software in the first period of time, and sends the running information obtained by running the target software in the first period of time to the analysis software. The analysis software analyzes the running information to obtain the first rule in the second period of time, and transmits the first rule to the system on chip. The system on chip runs the target software according to the first rule in the third period of time, and sends the running information generated in the third period of time to the analysis software. The analysis software generates the second rule by analyzing all the collected running information and transmits the second rule to the system on chip, and so on. Alternatively, in the Nth period of time, the system on chip runs the target software according to the rule sent by the analysis software before, and the analysis software analyzes the running information obtained before to obtain a new rule in the Nth period of time. In the N+1th period of time, the system on chip runs the target software according to the new rule, and the analysis software analyzes the running information in the Nth period of time to obtain a new rule again in the N+1th period of time, and so on. Alternatively, after the system on chip runs the target software for a period of time, the analysis software analyzes the rule according to the running information obtained in the period of time, and sends the rule to the system on chip. In the following time, the system on chip always uses the rule.

[0078] The following describes the above several time sequences in combination with the drawings.

[0079] Figure 5 is the interaction time sequence according to the embodiment of the applicationFigure 1 In Figure 5 , the timing diagram of "interrupt processing" is shown as Figure 5 , hardware running refers to the on-chip system running target software, in the process of running, the information generated by the chip running target software is collected (hardware information or key information in Figure 5 ), after the key information is collected, the analysis software is analyzed to generate rules, and then the rules are sent to the on-chip system for hardware running. In Figure 5 , the hardware in L0-L1 runs based on the default rule, and then sends the information collected in L0-L1 to the analysis software, and the analysis software analyzes the information collected in L0-L1 to generate the first rule (L0-L1 rule). In L1-L2, the hardware still runs based on the default rule. In L2-L3, the hardware runs based on the L0-L1 rule (since the rule is optimized, the running hardware in this segment will produce an accelerated effect, which is called L0-L1 rule accelerated running). Collect the key information generated in L2-L3 and send it to the analysis software. The analysis software can analyze the key information collected in L2-L3 to generate a new rule (which can be called the second rule), or it can analyze the key information collected in L0-L3 to generate a new rule (which can be called the third rule). The hardware still runs based on the first rule in L2-L3, and runs based on the second rule or the third rule in L3-L4, and so on, until the generated rule meets the expectation.

[0080] Figure 6 is an interactive timing diagram according to an embodiment of the present application Figure 2 In Figure 6 , the timing diagram of "pipeline processing" is shown as Figure 6 , the on-chip system runs target software in L0-L1, collects information generated in L0-L1, and the analysis software analyzes the hardware information in L1-L2 to obtain rules. At the same time, the on-chip system still runs based on the default rule in L1-L2. The on-chip system runs based on the rules generated in L0-L1 in L2-L3, the analysis software processes the information in L0-L2 in L2-L3 to obtain running rules, and the on-chip system runs based on the rules generated in L0-L2 in L3-L4. The analysis software processes the information in L0-L3 in L3-L4 to obtain new running rules. The on-chip system runs based on the rules generated in L0-L3 after L4, and the analysis software processes the information generated in L0-L4 after L4 to obtain rules. In turn, until the obtained running rules meet the expectation.

[0081] Figure 7 is an interactive timing diagram according to an embodiment of the present application Figure 3 , inFigure 7 The timing diagram of "one-time processing" is shown in Figure 7 As shown, the system on chip runs the target software in L0-L1, collects information in L1, and then analyzes the software in L0-L1 to process the key information to obtain the running rules. The system on chip is accelerated based on the L0-L1 rules after L2. In Figure 7 Only one rule is generated in Figure 7 , and thus it is called one-time processing.

[0082] In summary, in Figure 5 , the hardware continuously runs, and when the key information is collected or the data request of the software is received, the key information data is generated and transmitted to the software side for processing. When the new running rules are calculated, the rules are issued to the hardware side to guide the subsequent execution and prediction of the hardware. The hardware running and software processing are asynchronous, the software processing can be executed at intervals, the results are issued to the hardware, and during this period the hardware will continuously run to accelerate the program. Essentially, as long as the new rules come, the hardware running efficiency will be higher, but if the new rules do not come, the hardware will still execute according to the previous rules, without blocking the hardware running. In Figure 6 , the hardware and software are still executed asynchronously, but at this time the system will perform extremely efficient pipeline execution interaction. The hardware continuously runs, and at the same time the software side also executes in real time according to the full bandwidth. The software side continuously requests or reads the hardware information, and updates the rules of the hardware at a high frequency. This design is suitable for the scene where the special program of the hardware side acceleration changes frequently. Figure 7 In Figure 7 , the offline processing software only needs to process the hardware information once in a long time, and can be configured to the hardware. This design is suitable for the scene where the same type of special program runs for a long time.

[0083] Figure 5 to Figure 7 In Figure 5 to Figure 7 , no matter how the timing is processed, similar interaction steps are embodied, Figure 8 is an interaction flowchart according to an embodiment of the present application, as shown in Figure 8As shown, the interaction process includes the following steps: first, the to-be-accelerated program (i.e., target software) is started, the target software is run on the chip after being started, and information (i.e., key information) generated when the chip runs the target software is collected during the running process. The collection process can also start after a request message of the analysis software is received. It should be noted that the chip has a cache for storing the key information, but the size of the cache is limited, and therefore, the key information needs to be captured and saved in the memory or other storage space in a timely manner, so that a relatively large amount of key information can be saved. Then, the collected key information is analyzed by the analysis software to generate a rule. Since the rule is used to guide the hardware of the chip to run, the rule is also referred to as a hardware guidance rule. The hardware guidance rule is sent to the chip, and the system on chip on the chip uses the hardware guidance rule when running the target software. In simple terms, Figure 8 embodies the following steps: 1. Start; 2. Start the to-be-accelerated program; 3. The chip hardware runs the to-be-accelerated program; 4. The hardware generates key information, and if the key information is generated, the key information is transmitted to the software; 5. Run the information processing software program (i.e., analysis software); 6. The analysis software generates a rule and writes the rule to the system on chip of the chip to achieve acceleration.

[0084] Figure 9 is a schematic diagram of an interaction process according to an embodiment of the present application, as Figure 9 shown, the analysis software analyzes the information from the system on chip by using a software analysis algorithm. Since the information obtained from the system on chip is obtained according to different target software, the rules generated by different target software can be different, and therefore, the information generated by the running of different target software on the system on chip can generate corresponding rules, that is, this is a kind of customized processing for the target software. The system on chip includes a central processing unit and a cache, wherein the central processing unit is used to execute the target software, and the cache is used to save the instructions and data corresponding to the target software. Then, the information generated by the system on chip when executing the target software (so-called real-time information is information that needs to be continuously captured from the cache and saved in the memory or other storage space with large capacity) is analyzed by the analysis software to obtain a rule. After the rule is obtained, the central processing unit can obtain the operation to be performed in the future according to the rule, so as to perform the advance processing (therefore, the rule can also be understood as a prediction of future behavior), so as to improve the efficiency of the system on chip. In Figure 9In this process, the central processing unit executes the program to be accelerated. The on-chip system stores key information generated in real time (i.e., real-time information) in memory. The analysis software develops customized analysis algorithms based on different dedicated programs. The input of the algorithm is the real-time information generated by the hardware. The software generates future trajectory guidance rules required for hardware execution and simultaneously issues rules that can locate execution rules. When the on-chip system executes the target software, it searches for rules at addresses in memory. The search rules have higher information density and occupy less area, which can reduce search time complexity and avoid bandwidth loss and increased search latency caused by directly reading execution rules. The on-chip system issues search requests and generates the information required for the search based on the accuracy of internal predictions. The search information and search rules are matched and searched to find the fragment address pointer of the corresponding rule. After reading the hardware execution rule, its information is extracted and the prediction information is input to the on-chip system for subsequent prediction actions.

[0085] In the above implementation, an interface can be pre-configured in the processor (or chip) to obtain information generated during the execution of the target software. That is, the hardware exposes an information interface, and the software reads the information and processes it offline. Leveraging the flexibility of the software, specific optimizations can be implemented for different programs to achieve optimal performance for each program. Traditional processors do not perform specific optimizations for each program, or rather, the processor itself cannot be specifically optimized. Software engineers can only adapt the processor by optimizing programs or compilers to achieve better performance. In the above implementation, the processor can be adapted to the program without changing the hardware, as modifying the hardware is very costly. However, by fully utilizing the flexibility of the software processing algorithm, different rules can be designed according to the running program (these rules can be understood as rules specific to the target software or program), generating program-specific rules to guide hardware operation and improve performance.

[0086] In one alternative implementation, the software-side offline algorithm analyzes and processes real-time information provided by the processor hardware. The processed rules can be time-independent discrete fragments or long historical fragments with strong temporal and spatial locality. These rules can predict future processor behavior, but to avoid consuming too much storage space, compression algorithms can be used to compress the rules, thus storing more rules in less storage space, achieving a predictive architecture design with long historical information and guidance information.

[0087] In the above-mentioned embodiments, software offline analysis and other hardware and software collaborative design are adopted, which needs to use the information generated by the target program running on the system on chip (these information are used for future prediction, thus also called historical information). Since the cache of the processor for the historical information is usually only stored in the on-chip cache (RAM or SRAM), the historical information is less, and the analysis and processing of long historical range cannot be performed. For example, the dynamic branch prediction algorithm: Branch History Table (BHT), GShare, TAggedGEometric history (TAGE) and other algorithms mainly store the historical information on the SRAM, and the size of the SRAM determines the length of the historical information that can be stored, so the traditional method generally increases the area of the processor to improve the performance. The above-mentioned embodiments use the long historical information stored in the on-chip or off-chip memory as the prediction data source, and the processor hardware exposes the information interface to the offline analysis software. The offline analysis software uses its flexibility to perform specific analysis on the special program (i.e. the target software), provides the rule guidance rule for the future running of the system on chip, and the hardware performs high-performance prediction and execution according to the rule.

[0088] Through the above-mentioned embodiments, the offline software uses the long historical information provided by the hardware for analysis and processing, ensures the prediction accuracy, and improves the processor execution performance with the prediction accuracy. The above-mentioned embodiments ensure the flexibility of the software and hardware system without changing the hardware, saving the cost.

[0089] The above-mentioned embodiments, based on the hardware information uploading and the software side offline processing to give the hardware execution rule, can have the acceleration effect on the following aspects: branch prediction; i-cache, d-cache prefetch, improving cache hit rate; TLB prefetch, improving TLB hit rate, avoiding direct page table reading. In the above-mentioned embodiments, by predicting the time node of the data update of the multi-core and the data itself, the performance and power consumption loss caused by repeated update due to the broadcast mechanism in the traditional multi-core cache consistency is solved, the future prediction trajectory can guide the prefetch behavior of the local host cache in the distributed cluster, thereby effectively reducing the system performance influence caused by the network delay and improving the performance.

[0090] The computer program corresponding to the above-mentioned analysis software can also be loaded into a computer or other programmable data processing device, so that a series of operation steps are performed on the computer or other programmable device to generate a computer implemented process, and the instructions executed on the computer or other programmable device provide a process for implementing the flow Figure 1 one flow or multiple flows and / or blocks Figure 1The steps of the functions specified in one or more blocks can be implemented with different modules. In this embodiment, such a device or system is provided. The system or device is used to implement the functions of the method in the above embodiment. Each module in the system or device corresponds to each step in the method, which has been described in the method and will not be repeated here.

[0091] In an embodiment, a chip is also provided, which includes a central processing unit and a cache; wherein a system on chip on the chip is used to perform the following method steps: obtaining a rule, wherein the rule reflects a behavior prediction when the system on chip runs a target software, the rule is obtained by analyzing running information collected when the system on chip historically runs the target software, the running information is generated by the system on chip running the target software; and taking measures in advance according to the rule when running the target software, wherein the measures are determined according to the rule, the measures taken in advance predict and prepare for future operations of the system on chip.

[0092] As an optional implementation, it further includes an interface, wherein the interface is one or more, the interface is used to send the running information outside the system on chip, and receive the rule from the analysis software or receive the parameter from the analysis software; wherein the parameter is used in an algorithm running on the system on chip, the rule is generated by the algorithm.

[0093] For the above chip, in an embodiment, a chip optimization processing system is also provided, which includes the above chip and an analysis software, wherein the analysis software is used to perform the following method steps: receiving running information, wherein the running information is obtained through an interface pre-configured on the chip, the running information is saved in a storage space outside the chip after being read out from the interface; determining the rule after analyzing the running information; sending the rule to the system on chip; or obtaining a parameter for generating the rule according to the running information, and sending the parameter to the system on chip; wherein the parameter is used in an algorithm running on the system on chip, the rule is generated by the algorithm; the algorithm is used to generate the rule. Other steps performed by the analysis software have been described in the above implementation and will not be repeated here. For example, the computing resource running the analysis software is different from the system on chip running the target software.

[0094] Optionally, in the case that the chip comprises a plurality of cores, the cores on the chip comprise two parts, a first part of the two parts is used to run the analysis software, and a second part of the two parts is used to run the target software as a system on chip; or the analysis software is run on a computing device different from the computing device where the chip is located; or the analysis software is run in the system on chip, and the system on chip uses different time domain resources to run the analysis software and the target software in time sharing mode.

[0095] Through the above embodiments, the problem that the use of a hardware accelerator for processor optimization for specific software cannot cover other software and has high cost is solved, so that the optimization of processor performance can be realized for different target programs.

[0096] The above only is the embodiment of the present application, and does not limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the scope of claims of the present application.

Claims

1. A method of chip optimization processing, the method comprising: The method comprises: a system-on-chip on the chip acquires rules, wherein the rules reflect a prediction of behavior of the system-on-chip when running target software, the rules are analyzed according to running information collected when the system-on-chip historically runs the target software, and the running information is generated by the system-on-chip when running the target software; the system-on-chip takes measures in advance according to the rules when running the target software, wherein the measures are determined according to the rules, the measures taken in advance predict and prepare for future operations of the system-on-chip; wherein predicting and preparing for the future operations include at least one of the following: the system-on-chip determines, according to the rules, a cache to be used in the future when running the target software, and prepares the cache to be used in the future in advance, the cache including at least one of the following: an instruction cache and a data cache; the system-on-chip determines, according to the rules, an instruction branch to be used in the future when running the target software, and prepares the instruction branch to be used in the future in advance; and the system-on-chip determines, according to the rules, a translation lookaside buffer to be used in the future when running the target software, and prepares the translation lookaside buffer to be used in the future in advance.

2. The method of claim 1, further comprising: an analysis software receiving the running information, wherein the running information is acquired through an interface pre-configured on the chip, and the running information is saved in a storage space outside the chip after being read out from the interface; the analysis software determines the rules after analyzing the running information; and the analysis software sends the rules to the system-on-chip; or the system-on-chip acquiring the rules comprises: the analysis software receiving the running information; the analysis software obtaining parameters for generating the rules according to the running information; and the system-on-chip receiving the parameters and using the parameters in an algorithm running on the system-on-chip to generate the rules; wherein the algorithm is used to generate the rules.

3. The method of claim 2, wherein, A computing resource running the analysis software is different from a computing resource of the system-on-chip running the target software.

4. The method of claim 3, wherein: in a case where the chip comprises a plurality of cores, the cores on the chip comprise two parts, a first part of the two parts is used to run the analysis software, and a second part of the two parts is used to run the target software as a system-on-chip; or the analysis software runs on a computing device different from a computing device where the chip is located; or the analysis software runs in the system-on-chip, and the system-on-chip uses different time domain resources to run the analysis software and the target software in different time periods.

5. The method of claim 4, wherein: The target software runs on a plurality of chips, wherein the plurality of chips are located on different computing devices respectively; the analysis software receives running information generated by a system on a chip running the target software on each of the plurality of chips; the analysis software analyzes the running information generated by all the systems on a chip to obtain the rule; and the analysis software transmits the rule to the system on a chip on each of the plurality of chips.

6. A chip comprising a central processing unit and a cache; wherein, The system on a chip on the chip is configured to perform the following method steps: obtaining a rule, wherein the rule reflects a behavior prediction of the system on a chip running a target software, and the rule is obtained by analyzing running information collected when the system on a chip historically runs the target software, and the running information is generated by the system on a chip running the target software; when running the target software, taking a measure in advance according to the rule, wherein the measure is determined according to the rule, the measure taken in advance predicts an operation to be performed by the system on a chip in the future and prepares for the operation; and wherein the predicted operation and the preparation include at least one of the following: the system on a chip determines a cache to be used in the future when running the target software according to the rule, and prepares the cache to be used in the future in advance, the cache including at least one of the following: an instruction cache, a data cache; the system on a chip determines an instruction branch to be used in the future when running the target software according to the rule, and prepares the instruction branch to be used in the future in advance; and the system on a chip determines a translation lookaside buffer to be used in the future when running the target software according to the rule, and prepares the translation lookaside buffer to be used in the future in advance.

7. The chip of claim 6, further comprising an interface, wherein the interface is one or more, and the interface is configured to transmit the running information outside the system on a chip, and receive a rule from the analysis software or receive a parameter from the analysis software; wherein the parameter is used in an algorithm running on the system on a chip, and the rule is generated by the algorithm.

8. A chip optimization processing system, characterized by comprising: The system of claim 6 or 7, wherein the analysis software is configured to perform the following method steps: receiving running information, wherein the running information is obtained through an interface pre-configured on the chip, and the running information is saved in a storage space outside the chip after being read out from the interface; analyzing the running information to determine the rule; transmitting the rule to the system on a chip; or obtaining a parameter for generating the rule according to the running information, and transmitting the parameter to the system on a chip; wherein the parameter is used in an algorithm running on the system on a chip, and the rule is generated by the algorithm.

9. The system of claim 8, wherein, The computing resource running the analysis software is different from the system on a chip running the target software.

10. The system of claim 9, wherein In the case that the chip comprises a plurality of cores, the core on the chip comprises two parts, a first part of the two parts is used for running the analysis software, and a second part of the two parts is used for running the target software as a system on chip; or, The analysis software is run on a computing device which is different from the computing device where the chip is located; or, The analysis software is run in the system on chip, and the system on chip uses different time domain resources to run the analysis software and the target software in time division mode.

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