Data processing method and device, equipment and storage medium
Through the combination method of difference processing and multiplication accumulation calculation unit, Savitzky-Golay filtering processing is simplified, the problem of FPGA resource tightness is solved, and efficient resource utilization and time constraints are achieved.
Patent Information
- Application Number
- CN202411974338.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-05-30
AI Technical Summary
When using FPGA to implement Savitzky-Golay filtering, the system resource consumption is high, especially the consumption of DSP and adders, resulting in resource tightness.
Using the combination method of the difference processing and the multiplication accumulation calculation unit, the Savitzky-Golay filtering processing is simplified and the use of DSP and adder and subtracter is reduced.
It greatly reduces the resource consumption of DSP and adders, improves timing stability, ensures time constraints, and reduces system resource usage.
Smart Images
Figure CN120070229A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data processing technologies, and in particular, to a data processing method, apparatus, device, and storage medium. Background Art
[0002] With the development of semiconductor technology and sensor technology, industrial cameras are increasingly widely used in various fields. Due to the diverse applications in the industrial field and high requirements for performance and reliability, FPGAs are often used as the main control chips in industrial cameras. The Savitzky-Golay filter is a special low-pass filter, also known as the Savitzy-Golay smoother. The obvious use of a low-pass filter is to smooth noisy data. The Savitzky-Golay filter was initially proposed by Savitzky A and Golay M in 1964 and is widely used for smoothing and denoising data streams. It has strong anti-noise ability and can robustly extract edge points.
[0003] When implementing SG filtering for every 21 rows and 2 columns using an FPGA, the conventional method requires 20 * 2 multipliers and 19 * 2 full adders and subtracters, which consumes a relatively large amount of system resources. Summary of the Invention
[0004] This section of the application is used to briefly introduce concepts, which will be described in detail in the subsequent Detailed Description section. This section of the application is not intended to identify the key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.
[0005] Some embodiments of this application propose a method, apparatus, electronic device, and computer-readable medium to solve the technical problems mentioned in the above Background Art section.
[0006] As a first aspect of this application, some embodiments of this application provide a data processing method, including: obtaining image data; performing Savitzky-Golay filtering on the image data to obtain a filtering result; outputting the filtering result; wherein, performing Savitzky-Golay filtering on the image data includes: performing difference processing on data of adjacent rows in the image data to obtain adjacent differences; performing multiplication processing on the adjacent differences and the product parameters corresponding to the row before the adjacent rows to obtain a plurality of values to be added; and accumulating the plurality of values to be added to obtain the filtering result.
[0007] Optionally, in some embodiments of this application, the bit value range of the image data is less than or equal to 7.
[0008] Optionally, in some embodiments of the present application, the absolute value of the product parameter is less than or equal to 27.
[0009] Optionally, in some embodiments of the present application, wherein, the Savitzky-Golay filtering process of the image data is processed by a plurality of multiply-accumulate calculation units.
[0010] Optionally, in some embodiments of the present application, wherein, at least one of the multiply-accumulate calculation units simultaneously calculates the Savitzky-Golay filtering of two adjacent columns in the image data.
[0011] Optionally, in some embodiments of the present application, wherein, a plurality of the multiply-accumulate calculation units are divided into multiple groups in a cascaded manner.
[0012] Optionally, in some embodiments of the present application, wherein, the Savitzky-Golay filtering process of the image data is processed by a plurality of pure addition calculation units.
[0013] As a second aspect of the present application, some embodiments of the present application provide a data processing device, including: an acquisition module, configured to acquire image data; a filtering module, configured to perform Savitzky-Golay filtering on the image data to obtain a filtering result; an output module, configured to output the filtering result; wherein, the performing Savitzky-Golay filtering on the image data includes: performing a difference process on data of adjacent rows in the image data to obtain adjacent differences; performing a multiplication process on the adjacent differences and a product parameter corresponding to the row before the adjacent rows to obtain a plurality of values to be added; and accumulating the plurality of values to be added to obtain the filtering result.
[0014] As a third aspect of the present application, some embodiments of the present application provide an electronic device, including: one or more processors; a storage device, on which one or more programs are stored, and when the one or more programs are executed by the one or more processors, the one or more processors implement the method described in any implementation manner of the first aspect above.
[0015] As a fourth aspect of the present application, some embodiments of the present application provide a computer-readable medium, on which a computer program is stored, wherein, when the program is executed by a processor, the method described in any implementation manner of the first aspect above is implemented.
[0016] The beneficial effects of the present application are as follows: to provide a data processing method, device, equipment and storage medium that reduce system resource occupation and thus implement Savitzky-Golay filtering processing.
[0017] More specifically, some embodiments of the present application may produce the following specific beneficial effects: It consumes 1 / 4 of the DSP and 0 adders of the traditional method, significantly reducing the lut resources.
[0018] Using (A - D)*B of the DSP eliminates 1 / 2 of the DSP and adders, and using the high and low bits of port A to calculate 2 columns of data simultaneously eliminates the remaining 1 / 2 of the DSP, so the DSP is only 1 / 4 of the original.
[0019] Using (A - D)*B + C of the DSP to achieve internal accumulation eliminates the adder.
[0020] Using the dedicated cascade port and cascade dedicated wiring of the DSP for multi - level cascade improves the timing stability and ensures the time constraint. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The drawings constituting a part of the present application are used to provide a further understanding of the present application, making other features, objects, and advantages of the present application more obvious. The schematic embodiments and descriptions of the drawings of the present application are used to explain the present application and do not constitute an improper limitation of the present application.
[0022] In addition, throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the elements and elements are not necessarily drawn to scale.
[0023] In the drawings: Figure 1 is a schematic diagram of the main steps of a data processing method according to an embodiment of the present application; Figure 2 is a schematic diagram of the data structure of a calculation unit according to an embodiment of the present application; Figure 3 is a schematic diagram of the structure of a data processing device according to an embodiment of the present application; Figure 4 is a schematic diagram of the structure of an electronic device according to an embodiment of the present application; Figure 5 is a schematic diagram before the DSP system cascade according to an embodiment of the present application; Figure 6 is a schematic diagram before the DSP system cascade according to an embodiment of the present application; Figure 7 is an image before filtering according to an embodiment of the present application; Figure 8 is an image after filtering according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0024] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to more thoroughly and completely understand the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not used to limit the protection scope of the present disclosure.
[0025] In addition, it should be noted that for ease of description, only parts related to the relevant invention are shown in the drawings. Without conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other.
[0026] It should be noted that concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence relationship of the functions performed by these devices, modules or units.
[0027] It should be noted that the modifications of "one" and "multiple" mentioned in the present disclosure are illustrative rather than restrictive. Those skilled in the art should understand that unless otherwise clearly stated in the context, it should be understood as "one or more".
[0028] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only for illustrative purposes and are not used to limit the scope of these messages or information.
[0029] The present disclosure will be described in detail below with reference to the drawings and in combination with embodiments.
[0030] Referring to Figure 1 As shown, as the first aspect of the present application, some embodiments of the present application provide a data processing method, which mainly includes the following steps: S101: Obtain image data.
[0031] S102: Perform Savitzky-Golay filtering on the image data to obtain a filtering result.
[0032] S103: Output the filtering result.
[0033] Among them, performing Savitzky-Golay filtering on the image data includes: performing difference processing on the data of adjacent rows in the image data to obtain adjacent differences; performing multiplication processing on the adjacent differences and the product parameters corresponding to the row before the adjacent rows to obtain a plurality of values to be added; and accumulating the plurality of values to be added to obtain a filtering result.
[0034] Optionally, in some embodiments of the present application, the bit value range of the image data is less than or equal to 7.
[0035] Optionally, in some embodiments of the present application, the absolute value of the product parameter is less than or equal to 27.
[0036] Optionally, in some embodiments of the present application, wherein, the Savitzky-Golay filtering process of the image data is processed by a plurality of multiply-accumulate calculation units.
[0037] Optionally, in some embodiments of the present application, wherein, at least one multiply-accumulate calculation unit simultaneously calculates the Savitzky-Golay filtering of two adjacent columns in the image data.
[0038] Optionally, in some embodiments of the present application, wherein, a plurality of multiply-accumulate calculation units are divided into multiple groups according to the cascade.
[0039] Optionally, in some embodiments of the present application, wherein, the Savitzky-Golay filtering process of the image data is processed by a plurality of pure addition calculation units.
[0040] Refer to Figure 2 As shown, as a specific embodiment of the present application, the present application is described in detail as follows: Taking the DSP48E1 (the calculation unit in the present application) in the 7-series FPGA chip of Xilinx as an example, it supports (A±D)*B±C, the A port is a 25-bit signed number, and the B port width is 18-bit signed number.
[0041] Since the finally calculated value is the gradient and does not replace the original image, it is sufficient to take the upper 7 bits of the image data. The absolute value of the parameter m is at most 27, and adding the sign bit of 6 bits is sufficient. The result of 7bit*6bit is 13bit, leaving 4 bits for carry and can be accumulated 15 times. Therefore, the data structure of the A port of the DSP is {the data of the second column, 10’b0, the data of the first column}.
[0042] In this way, one DSP can be used as two DSPs, and the SG filtering of two columns can be calculated simultaneously. Refer to Figure 5 And Figure 6 As shown, this undoubtedly simplifies the DSP architecture.
[0043] Then, a total of 12 DSPs are required to calculate the gradient value of one point in 21 rows, of which 10 are for multiply-accumulate and 2 are for pure addition.
[0044] 10 multiply-accumulate DSPs are cascaded and divided into 4 groups (DSP0, DSP123, DSP456, DSP789), and are divided into 3 types (2, 3, 4) according to the clock cycle delay. As shown in the following figure, the following serial numbers are all 0-based indexes.
[0045] The DSP internally has 4 - level registers and can support a maximum delay of 4 clock cycles. DSP1 / 4 / 7 calculate the subtraction of symmetric row data in the first clock cycle (for example, row 1 - row 18, i.e., data[r - 8] - data[r + 8]), multiply the result of the subtraction by parameter m in the second clock cycle, and output P1 / 4 / 7 in the third clock cycle.
[0046] DSP2 / 5 / 8 calculate the subtraction of symmetric row data in the first cycle (for example, row 2 - row 17, i.e., data[r - 7] - data[r + 7]), multiply the result of the subtraction by parameter m in the second clock cycle, add the calculation result of DSP1 / 4 / 7 in the third clock cycle (DSP2 + P1, DSP5 + P4, DSP8 + P7), and output the result P2 / 5 / 8 in the fourth cycle.
[0047] DSP0 / 3 / 6 / 9 use internal register delay for input in the first cycle, calculate the subtraction of symmetric row data in the second clock cycle (for example, row 3 - row 16, i.e., data[r - 6] - data[r + 6]), calculate the result of the subtraction multiplied by the parameter in the third clock cycle, add 0 to DSP0, and add the calculation result of DSP2 / 5 / 8 to DSP3 / 6 / 9 in the fourth clock cycle (DSP3 + P2, DSP6 + P5, DSP9 + P8), and output the calculation result P0 / 3 / 6 / 9 in the fifth clock cycle.
[0048] In the fifth clock cycle, DSP10 calculates P0 + P3, DSP11 calculates P6 + P9, DSP10 outputs the result P10 in the sixth clock cycle, DSP11 + P10, and outputs the final gradient value in the seventh clock cycle.
[0049] Specifically, the comparison between the prior art and this application is as follows: Existing calculation formula: X = datar0 + datar_1 * m0 + datar1 * (-1) * m0 + datar_2 * m1 + datar2 * (-1) * m1 + datar_3 * m2 + datar3 * (-1) * m2 + datar_4 * m3 + datar4 * (-1) * m3 + datar_5 * m4 + datar5 * (-1) * m4 + datar_6 * m5 + datar6 * (-1) * m5 + datar_7 * m6 + datar7 * (-1) * m6 + datar_8 * m7 + datar8 * (-1) * m7 + datar_9 * m8 + datar9 * (-1) * m8 + datar_10* m9 + datar10* (-1) * m9。
[0050] The optimized calculation formula of this application X = datar0 + (datar_1 - datar1 ) * m0 + (datar_2 - datar2 ) * m1 + (datar_3 - datar3 ) * m2 + (datar_4 - datar4 ) * m3 + (datar_5 - datar5 ) * m4 + (datar_6 - datar6 ) * m5 + (datar_7 - datar7 ) * m6 + (datar_8 - datar8 ) * m7 + (datar_9 - datar9 ) * m8 + (datar_10 - datar10) * m9。
[0051] The implementation method of this application can be achieved in four steps: The first step: Each formula can save 1 dsp. Direct calculation requires 2 dsps, and only 1 can be used in the following way p1 = (datar_1 - datar1 ) * m0 p4 = (datar_4 - datar4 ) * m3 p7 = (datar_7 - datar7 ) * m6 The second step: Each formula can save 2 dsps. Direct calculation requires 3 dsps, and only 1 can be used in the following way p2 = (datar_2 - datar2 ) * m1 + p1 p5 = (datar_5 - datar5 ) * m4 + p4 p8 = (datar_8 - datar8) * m7 + p7 Step 3: Each formula can save 2 DSPs. Direct calculation requires 3 DSPs. In the following way, only 1 DSP is needed. p3 = (datar_3 - datar3) * m2 + p2 p6 = (datar_6 - datar6) * m5 + p5 p9 = (datar_9 - datar9) * m8 + p8 p0 = (datar_10 - datar10) * m9 Step 4: Save 1 DSP. p10 = p0 + p3; p11 = p10 + p6 + p9.
[0052] Refer to Figure 7 and Figure 8 As can be seen from the reference shown, a clearer image can be obtained by adopting the filtering scheme of the present application.
[0053] Refer to Figure 3 As shown, as a second aspect of the present application, some embodiments of the present application provide a data processing device, including: an acquisition module for acquiring image data; a filtering module for performing Savitzky-Golay filtering processing on the image data to obtain a filtering result; an output module for outputting the filtering result; wherein, the performing Savitzky-Golay filtering processing on the image data includes: performing difference processing on the data of adjacent rows in the image data to obtain adjacent differences; performing multiplication processing on the adjacent differences and the product parameters corresponding to the row before the adjacent rows to obtain a plurality of values to be added; and accumulating the plurality of values to be added to obtain the filtering result.
[0054] As Figure 4 shown, the electronic device 800 may include a processing device (such as a central processing unit, a graphics processing unit, etc.) 801, which may perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 802 or the program loaded from the storage device 808 into the random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the electronic device 800 are also stored. The processing device 801, the ROM 802, and the RAM 803 are connected to each other through a bus 804. The input / output (I / O) interface 805 is also connected to the bus 804.
[0055] Typically, the following devices can be connected to the I / O interface 805: input devices 806 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 807 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 808 including, for example, magnetic tapes, hard disks, etc.; and a communication device 809. The communication device 809 can allow the electronic device 800 to communicate with other devices wirelessly or wiredly to exchange data. Although Figure 4 the electronic device 800 with various devices is shown, it should be understood that it is not required to implement or have all the shown devices. Instead, more or fewer devices can be implemented or had. Figure 4 Each block shown in can represent one device or, as needed, multiple devices.
[0056] Specifically, according to some embodiments of the present disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, some embodiments of the present disclosure include a computer program product that includes a computer program carried on a computer-readable medium, and the computer program contains program codes for performing the methods shown in the flowcharts. In such some embodiments, the computer program can be downloaded and installed from the network through the communication device 809, or installed from the storage device 808, or installed from the ROM 802. When the computer program is executed by the processing device 801, the above functions defined in the methods of some embodiments of the present disclosure are performed.
[0057] It should be noted that the computer-readable medium in some embodiments of the present disclosure can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.
[0058] In some embodiments of the present disclosure, a computer-readable storage medium may be any tangible medium that contains or stores a program, which can be used by or in conjunction with an instruction execution system, apparatus, or device. In some embodiments of the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.
[0059] In some embodiments, the client and the server can communicate using any currently known or future-developed network protocol such as HTTP (HyperText Transfer Protocol), and can be interconnected with digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include local area networks ("LAN"), wide area networks ("WAN"), the Internet (e.g., the Internet), and end-to-end networks (e.g., ad hoc end-to-end networks), as well as any currently known or future-developed networks.
[0060] The above computer-readable medium may be included in the above electronic device; it may also exist separately without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the one or more programs are executed by the electronic device, the electronic device is caused to: acquire image data; perform Savitzky-Golay filtering on the image data to obtain a filtering result; output the filtering result; wherein, performing Savitzky-Golay filtering on the image data includes: performing difference processing on the data of adjacent rows in the image data to obtain adjacent differences; performing multiplication processing on the adjacent differences and the multiplication parameters corresponding to the row before the adjacent rows to obtain a plurality of values to be added; and accumulating the plurality of values to be added to obtain the filtering result.
[0061] Computer program code for performing the operations of some embodiments of the present disclosure may be written in one or more programming languages or combinations thereof. The programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may execute entirely on the user's computer, partially on the user's computer, execute as a stand-alone software package, execute partially on the user's computer and partially on a remote computer, or execute entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).
[0062] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a part of code that contains one or more executable instructions for implementing a specified logical function.
[0063] It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings.
[0064] For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system that performs the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.
[0065] The units described in some embodiments of the present disclosure may be implemented in software or in hardware.
[0066] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, by way of non-limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGA), application specific integrated circuits (ASIC), application specific standard products (ASSP), system on a chip (SOC), complex programmable logic devices (CPLD), and the like.
[0067] The above description is only some preferred embodiments of the present disclosure and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present disclosure is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above inventive concept. For example, the technical solutions formed by mutually replacing the above features with the technical features (but not limited to) disclosed in the embodiments of the present disclosure that have similar functions.
Claims
1. A data processing method, characterized in that: The data processing method comprises: Get image data; The image data is subjected to Savitzky-Golay filtering to obtain a filtering result; Outputting the filtering result; The step of performing Savitzky-Golay filtering on the image data includes: Performing difference processing on data of adjacent rows in the image data to obtain adjacent differences; Performing product processing on the adjacent difference values and the product parameter corresponding to the previous row of the adjacent row to obtain a plurality of values to be added; The plurality of values to be added are accumulated to obtain the filtering result.
2. The data processing method according to claim 1, characterized in that: The bit value range of the image data is less than or equal to 7.
3. The data processing method according to claim 2, characterized in that: The absolute value of the product parameter is less than or equal to 27.
4. The data processing method according to claim 3, characterized in that: in, The Savitzky-Golay filtering process of the image data is processed by a plurality of multiplication-accumulation calculation units.
5. The data processing method according to claim 4, characterized in that: in, At least one of the multiplication-accumulation calculation units simultaneously calculates the Savitzky-Golay filtering of two adjacent columns in the image data.
6. The data processing method according to claim 5, characterized in that: in, The plurality of multiplication-accumulation computing units are divided into a plurality of groups according to cascade connection.
7. The data processing method according to claim 6, characterized in that: in, The Savitzky-Golay filtering process on the image data is processed by a plurality of pure addition calculation units.
8. A data processing device, comprising: An acquisition module, used for acquiring image data; The filtering module performs Savitzky-Golay filtering on the image data to obtain the filtering result; An output module, used for outputting the filtering result; The step of performing Savitzky-Golay filtering on the image data includes: Performing difference processing on data of adjacent rows in the image data to obtain adjacent differences; Performing product processing on the adjacent difference values and the product parameter corresponding to the previous row of the adjacent row to obtain a plurality of values to be added; The plurality of values to be added are accumulated to obtain the filtering result.
9. An electronic device, comprising: one or more processors; a storage device having one or more programs stored thereon; When the one or more programs are executed by the one or more processors, the processors implement the method according to any one of claims 1 to 7.
10. A computer readable medium having a computer program stored thereon, wherein: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.