Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel. The array substrate comprises a substrate; the first conductive layer is located on one side of the substrate, and the first conductive layer comprises a first power line; the second conducting layer is located on the side, away from the substrate, of the first conducting layer and comprises a first signal line, a second signal line and a second power line, the first signal line and the second signal line are arranged at intervals in the first direction, and the second power line is located between the first signal line and the second signal line. The first power line, the first signal line, the second signal line and the second power line extend and are formed in the second direction, and the first power line and the second power line are connected through holes. According to the display panel, the first power line and the second power line are connected through holes, the distribution area of the power lines can be increased, the resistance of the power lines is reduced, the influence of insufficient driving voltage on the display panel is improved, and the display effect of the display panel is improved.

Description

[0001] This application is a divisional application based on the invention with application number: 202211371395.7, application date: November 3, 2022, the applicants are Hefei Visionox Technology Co., Ltd. and Kunshan Govisionox Co., Ltd., and the invention name is “Array Substrate and Display Panel”. Technical Field

[0002] The present application relates to the field of display, and in particular to an array substrate and a display panel. Background Art

[0003] Organic Light-Emitting Diode (OLED) is an active light-emitting device. Compared with the traditional liquid crystal display (LCD) display method, OLED display technology does not require a backlight and has the characteristic of self-luminescence. OLED uses a thinner organic material film layer and a glass substrate. When an electric current passes through, the organic material will emit light. Therefore, OLED display panels can significantly save electricity, can be made lighter and thinner, can withstand a wider range of temperature changes than LCD display panels, and have a larger viewing angle. OLED display panels are expected to become the next generation of flat-panel display technology after LCD, and are one of the most popular technologies in flat-panel display technology.

[0004] The OLED display panel includes an array substrate and a display substrate. The array substrate includes a power line and a pixel circuit. The power line sends a driving signal to the pixel circuit, which drives the display substrate to emit light. If the power line resistance is too large, the driving voltage will be insufficient, which will affect the display effect of the display panel. Summary of the invention

[0005] The embodiments of the present application provide an array substrate and a display panel, aiming to improve the display effect of the display panel.

[0006] An embodiment of the first aspect of the present application provides an array substrate, comprising: a substrate; a first conductive layer, located on one side of the substrate, the first conductive layer comprising a first power line; a second conductive layer, located on a side of the first conductive layer away from the substrate, the second conductive layer comprising a first signal line, a second signal line and a second power line located between the first signal line and the second signal line, wherein the first power line, the first signal line, the second signal line and the second power line are all extended and formed along the second direction, and the first power line and the second power line are connected by vias.

[0007] According to an embodiment of the first aspect of the present application, the second power line includes a plurality of power blocks spaced apart in the second direction and connection lines connected between adjacent two power blocks, wherein the width of the connection line in the first direction is smaller than the width of the power block in the first direction.

[0008] According to any one of the foregoing embodiments of the first aspect of the present application, the second conductive layer further includes:

[0009] A first connection portion, connected to the first signal line and located between the first signal line and the second signal line;

[0010] A second connection portion, connected to the second signal line and located between the first signal line and the second signal line;

[0011] Among the two connection lines located on both sides of the same power block in the second direction and connected thereto, one is the first connection line and the other is the second connection line. The first connection line extends between the first connection portion and the second signal line, and the second connection line extends between the second connection portion and the first signal line.

[0012] According to any one of the foregoing embodiments of the first aspect of the present application, the first connection line is connected to the side of the power block facing the second signal line, and the second connection line is connected to the side of the power block facing the first signal line.

[0013] According to any one of the foregoing embodiments of the first aspect of the present application, a plurality of second power lines are spaced apart in the first direction. The power blocks of at least one second power line include a functional block and an auxiliary block. The connection line of the second power line further includes a third connection line. The auxiliary block and the functional block are spaced apart in the second direction and are connected to each other through the third connection line. A first via portion is provided between the auxiliary block and the functional block;

[0014] The array substrate further includes a third conductive layer and a fourth conductive layer. The third conductive layer and the fourth conductive layer are respectively disposed on both sides of the second conductive layer. The third conductive layer includes a third signal line, and the fourth conductive layer includes a pixel electrode. The pixel electrode is connected to the third signal line through the first via portion.

[0015] According to any one of the foregoing embodiments of the first aspect of the present application, among two adjacent second power lines in the first direction, one is a first sub-power line and the other is a second sub-power line. The first sub-power line includes a functional block and does not include an auxiliary block. The second sub-power line includes a functional block and an auxiliary block. A second via portion is provided between the power block of the first sub-power line and the first connection portion and / or the second connection portion. The pixel electrode is connected to the third signal line through the second via portion.

[0016] According to any one of the foregoing embodiments of the first aspect of the present application, it further includes:

[0017] The fourth conductive layer is located on a side of the second conductive layer facing away from the substrate. The fourth conductive layer includes pixel electrodes, and a positive projection of the pixel electrodes in the thickness direction of the array substrate overlaps at least partially with a positive projection of the second power line in the thickness direction.

[0018] According to any of the foregoing embodiments of the first aspect of the present application, a positive projection of each power supply block in the thickness direction overlaps at least partially with a positive projection of each pixel electrode in the thickness direction.

[0019] According to any of the foregoing embodiments of the first aspect of the present application, a positive projection of the power supply block in the thickness direction is centrosymmetrically arranged about a center of a positive projection of the pixel electrode in the thickness direction.

[0020] According to any of the foregoing embodiments of the first aspect of the present application, a positive projection of the power supply block in the thickness direction is located within a positive projection of the pixel electrode in the thickness direction.

[0021] According to any of the foregoing embodiments of the first aspect of the present application, areas of at least two pixel electrodes are different, areas of at least two power supply blocks are different, and an area of the power supply block is positively correlated with an area of its corresponding pixel electrode.

[0022] According to any of the foregoing embodiments of the first aspect of the present application, a positive projection of the first power line on the substrate overlaps at least partially with a positive projection of the second power line on the substrate.

[0023] According to any of the foregoing embodiments of the first aspect of the present application, the array substrate further includes a plurality of pixel circuits disposed on one side of the substrate, and the plurality of pixel circuits are arranged in columns along a second direction;

[0024] The first signal line is a first data line, the second signal line is a second data line, and the first data line and the second data line are configured to provide data signals to a plurality of pixel circuits in the same column arranged along the second direction.

[0025] According to any of the foregoing embodiments of the first aspect of the present application, among two adjacent pixel circuits in the second direction, a data signal of one of the pixel circuits is provided by the first data line, and a data signal of the other pixel circuit is provided by the second data line.

[0026] An embodiment of the second aspect of the present application provides a display panel, including the array substrate of any of the foregoing embodiments of the first aspect.

[0027] In the array substrate provided by the embodiment of the present application, the array substrate includes a substrate, a first conductive layer and a second conductive layer disposed on the substrate. A first power line is disposed in the first conductive layer, and a first signal line, a second signal line and a second power line located between the first signal line and the second signal line are disposed in the second conductive layer. The first power line and the second power line are connected by vias, which can increase the distribution area of the power line, thereby reducing the resistance of the power line, improving the influence on the display panel due to insufficient driving voltage, and further improving the display effect of the display panel. In addition, the second conductive layer is further provided with a first signal line and a second signal line arranged side by side with the second power line in the first direction, which can enrich the functions of the second conductive layer. Description of the Drawings

[0028] By reading the following detailed description of the non-limiting embodiments with reference to the drawings, other features, objects and advantages of the present application will become more obvious. Among them, the same or similar reference numerals represent the same or similar features, and the drawings are not drawn to actual scale.

[0029] Figure 1 is a top view of an array substrate provided by an embodiment of the present application;

[0030] Figure 2 is Figure 1 a partial cross-sectional view of;

[0031] Figure 3 is a top view of an array substrate provided by another embodiment of the present application;

[0032] Figure 4 is a schematic diagram of the pixel circuit structure of an array substrate provided by an embodiment of the present application;

[0033] Figure 5 is Figure 1 a partial enlarged structural view of.

[0034] Description of the Reference Numerals:

[0035] 01, Substrate;

[0036] 02, First Conductive Layer; 210, First Power Line;

[0037] 03, Second Conductive Layer; 310, First Signal Line; 320, Second Signal Line; 330, Second Power Line; 330a, First Sub-Power Line; 330b, Second Sub-Power Line; 331, Power Block; 331a, Function Block; 331b, Auxiliary Block; 332, Connection Line; 332a, First Connection Line; 332b, Second Connection Line; 332c, Third Connection Line; 340, First Connection Port; 350, Second Connection Port; 360, First Via Port; 370, Second Via Port;

[0038] 04. The third conductive layer; 410. The third signal line;

[0039] 05. The fourth conductive layer; 510. The pixel electrode;

[0040] X. The first direction; Y. The second direction; Z. The thickness direction. Detailed implementation manners

[0041] The features and exemplary embodiments of various aspects of the present application will be described in detail below. To make the objectives, technical solutions, and advantages of the present application clearer and more understandable, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0042] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, the elements defined by the statement "including..." do not exclude the existence of additional identical elements in the process, method, article or device including the said elements.

[0043] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "above" or "over" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the component is flipped, this layer or region will be "below" or "beneath" the other layer or another region.

[0044] Embodiments of the present application provide an array substrate and a method for manufacturing the same. The following will describe the embodiments of the array substrate and the method for manufacturing the same with reference to the accompanying drawings.

[0045] Embodiments of the present application provide an array substrate, which can be used for a display panel, and the display panel can be an Organic Light Emitting Diode (OLED) display panel.

[0046] Please refer to Figure 1 and Figure 2 , Figure 1 which shows a top view of a partial layer structure of an array substrate provided by an embodiment of the present application, Figure 2 is Figure 1 a partial cross-sectional view of

[0047] As shown in Figure 1 and Figure 2 , an embodiment of the first aspect of the present application provides an array substrate, which includes a substrate 01, a first conductive layer 02, and a second conductive layer 03; the first conductive layer 02 is located on one side of the substrate 01, and the first conductive layer 02 includes a first power line 210; the second conductive layer 03 is located on the side of the first conductive layer 02 away from the substrate 01, and the second conductive layer 03 includes a first signal line 310 and a second signal line 320 that are spaced apart along the first direction X, and a second power line 330 located between the first signal line 310 and the second signal line 320. Among them, the first power line 210, the first signal line 310, the second signal line 320, and the second power line 330 are all formed by extending along the second direction Y, and the first power line 210 and the second power line 330 are connected through vias.

[0048] In the array substrate provided by the embodiment of the present application, the array substrate includes a substrate 01 and a first conductive layer 02 and a second conductive layer 03 disposed on the substrate 01. A first power line 210 is disposed in the first conductive layer 02, and a first signal line 310, a second signal line 320, and a second power line 330 located between the first signal line 310 and the second signal line 320 are disposed in the second conductive layer 03. The first power line 210 and the second power line 330 are connected through vias, which can increase the distribution area of the power line, thereby reducing the resistance of the power line, improving the influence on the display panel due to insufficient driving voltage, and further improving the display effect of the display panel. In addition, the second conductive layer 03 is further provided with a first signal line 310 and a second signal line 320 arranged side by side with the second power line 330 along the first direction X, which can enrich the functions of the second conductive layer 03.

[0049] Please refer to Figures 1 to 3 together with Figure 3 which is an enlarged structural schematic diagram of an array substrate provided by another embodiment of the present application, Figure 3 which is different from Figure 1 in that the array substrate is increased with a conductive layer including a pixel electrode 510.

[0050] Optionally, the display panel includes an array substrate and a light-emitting layer located on the array substrate. The light-emitting layer includes a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer that are sequentially stacked. The pixel electrode 510 can be an anode or a cathode.

[0051] The second power supply line 330 is located between the first signal line 310 and the second signal line 320. The positive projection of the second power supply line 330 along the thickness direction Z of the array substrate overlaps with the positive projection of the pixel electrode 510 located thereon along the thickness direction Z of the array substrate. Thus, the flatness of the pixel electrode 510 can be improved by adjusting the shape of the second power supply line 330, and the color shift problem caused by the pixel electrode 510 reflecting the light emitted by the light-emitting layer in all directions can be improved, thereby better improving the display effect of the display panel.

[0052] Optionally, an insulating layer is provided between the first conductive layer 02 and the second conductive layer 03 to prevent the routing of the first conductive layer 02 and the second conductive layer 03 from being short-circuited. In the embodiments of the present application, an insulating layer is provided between adjacent two conductive layers to prevent short-circuit connection, which will not be elaborated here.

[0053] The substrate 01 can be a flexible substrate or a rigid substrate. For example, the material of the substrate 01 can include flexible materials such as polyimide, or the material of the substrate 01 can include rigid materials such as glass. Other film layers can also be provided between the first conductive layer 02 and the substrate 01, as long as the first conductive layer 02 is located on one side of the substrate 01. The material of the first conductive layer 02 can include a metal material, so that the first power supply line 210 has good electrical conductivity. The material of the second conductive layer 03 can include a metal material, so that the first signal line 310, the second signal line 320, and the second power supply line 330 have good electrical conductivity.

[0054] There are various ways to arrange the first signal line 310 and the second signal line 320. In some optional embodiments, the first signal line 310 is a first data line, and the second signal line 320 is a second data line. The array substrate further includes a plurality of pixel circuits provided on one side of the substrate 01. The plurality of pixel circuits are arranged in columns along the second direction Y. The first data line and the second data line are used to provide data signals to a plurality of pixel circuits in the same column arranged along the second direction Y.

[0055] As Figure 4 shown, the data line data is used to send data signals to the pixel circuits. In an optional specific embodiment, among two adjacent pixel circuits in the same column, the data signal of one pixel circuit is provided by the first data line, and the data signal of the other pixel circuit is provided by the second data line. Then, the number of pixel circuits that the same data line needs to drive is reduced, which can reduce the transmission time of the data signal on the data signal line, reduce the delay, and increase the power supply time of a single sub-pixel.

[0056] In these optional embodiments, a plurality of pixel circuits in the same column can transmit data signals through two data lines, namely the first data line and the second data line, which can extend the charging time of a single pixel circuit and improve the display effect of the display panel.

[0057] In some alternative embodiments, the array substrate further includes a fourth conductive layer 05, which is located on a side of the second conductive layer 03 facing away from the substrate 01, and the fourth conductive layer 05 includes pixel electrodes 510.

[0058] If the first data line and the second data line are provided corresponding to the same column of pixel circuits, then the first data line and the second data line can be provided corresponding to the same column of pixel electrodes 510. A positive projection of the second power line 330 located between the first data line and the second data line along the thickness direction Z at least partially overlaps with a positive projection of the pixel electrode 510 along the thickness direction Z. The distribution of the second power line 330 affects the surface shape of the insulating layer thereon, and further affects the flatness of the pixel electrode 510. Therefore, by reasonably setting the distribution of the second power line 330, the flatness of the pixel electrode 510 can be improved, which is beneficial to improving the display effect. For example, improving the flatness of the pixel electrode 510 can improve the display effect of the display panel affected by the light emitted by the light-emitting layer being too scattered due to the unevenness of the pixel electrode 510.

[0059] In these alternative embodiments, the distance between the second conductive layer 03 and the fourth conductive layer 05 is closer. For example, when the insulating layer is prepared on the second conductive layer 03 and then the pixel electrode 510 is prepared, the flatness of the surface of the second conductive layer 03 facing the insulating layer will affect the flatness of the surface of the pixel electrode 510 on the insulating layer, and the distributions of the first signal line 310, the second signal line 320, and the second power line 330 will also affect the flatness of the surface of the insulating layer, and thus the distributions of the first signal line 310, the second signal line 320, and the second power line 330 will indirectly affect the flatness of the pixel electrode 510. The positive projections of the pixel electrode 510 and the second power line 330 at least partially overlap, so that the second power line 330 can improve the problem of unevenness of the pixel electrode 510.

[0060] In addition, by disposing the first signal line 310 and the second signal line 320 in a conductive layer closer to the pixel electrode 510, the distance between the first signal line 310 and the second signal line 320 and other signal lines in the array substrate along the thickness direction Z can be increased, the parasitic circuit generated by the overlap of the first signal line 310 and the second signal line 320 with other signal lines can be reduced, and the stability of signal transmission can be ensured.

[0061] There are various ways to set the second power line 330. Optionally, the second power line 330 can extend along the second direction Y and have a uniform width.

[0062] In some other alternative embodiments, such as Figure 3As shown in the figure, the second power supply line 330 includes a plurality of power supply blocks 331 spaced apart along the second direction Y and connection lines 332 connected between two adjacent power supply blocks 331. Among them, the extension width of the connection line 332 in the first direction X is smaller than the width of the power supply block 331 in the first direction X.

[0063] In these alternative embodiments, the second power supply line 330 includes power supply blocks 331 and connection lines 332. The power supply blocks 331 have a larger width, which can increase the distribution area of the second power supply line 330, reduce the resistance of the second power supply line 330, and thus increase the driving voltage, improving the display effect of the display panel.

[0064] In addition, by reasonably setting the positions of the power supply blocks 331 and the connection lines 332, the positive projection of the power supply blocks 331 along the thickness direction Z of the array substrate can overlap with the positive projection of the pixel electrodes 510 along the thickness direction Z of the array substrate. Since the positive projection area of the power supply blocks 331 along the thickness direction Z of the array substrate is relatively large, it can increase the overlapping area between the positive projection of the power supply blocks 331 along the thickness direction Z and the positive projection of the pixel electrodes 510 along the thickness direction Z. By reasonably setting the shape of the power supply blocks 331, the flatness of the pixel electrodes 510 can be indirectly affected, and thus the problem of uneven pixel electrodes 510 can be better improved. By reasonably setting the positions of the connection lines 332, the problem of short-circuit connection between the second power supply line 330 and the first signal line 310 and the second signal line 320 can also be improved.

[0065] There are various ways to set the shape of the power supply blocks 331. The positive projection of the power supply blocks 331 on the substrate 01 can be in the shape of a circle, a semicircle, a polygon, or an irregular shape, etc. Optionally, the positive projection of the power supply blocks 331 on the substrate 01 is a quadrilateral such as a rectangle, a square, or a rhombus. Here, the shape of the positive projection of the power supply blocks 331 on the substrate 01 is not limited, and it can be specifically set according to actual needs.

[0066] When the second power supply line 330 includes connection lines 332 and power supply blocks 331, the positive projection of the connection lines 332 and / or the power supply blocks 331 along the thickness direction Z overlaps at least partially with the positive projection of the pixel electrodes 510 along the thickness direction Z.

[0067] Optionally, the positive projection of each power supply block 331 along the thickness direction Z overlaps at least partially with the positive projection of each pixel electrode 510 along the thickness direction Z. The distribution area of the power supply blocks 331 is larger, and the overlapping of the power supply blocks 331 and the pixel electrodes 510 can better improve the problem of uneven pixel electrodes 510.

[0068] Optionally, the positive projection of the power supply block 331 along the thickness direction Z is centrosymmetrically arranged about the center of the positive projection of the pixel electrode 510 along the thickness direction Z. The center of the positive projection of the pixel electrode 510 along the thickness direction Z can be the geometric center of the positive projection of the pixel electrode 510 along the thickness direction Z. The positive projection of the power supply block 331 along the thickness direction Z is centrosymmetrically arranged about the geometric center, so that the flatness at different positions around the center of the pixel electrode 510 is close, and the influence of the unevenness of the pixel electrode 510 on the display effect is better improved.

[0069] Optionally, at least a part of the power supply blocks 331 satisfy that the positive projection of the power supply block 331 along the thickness direction Z is located within the positive projection of the pixel electrode 510 along the thickness direction Z, so that the power supply block 331 can better improve the influence of the unevenness of the pixel electrode 510 on the display effect.

[0070] For example, the center of the positive projection of the power supply block 331 along the thickness direction Z coincides with the center of the positive projection of the pixel electrode 510 along the thickness direction Z, so that the power supply block 331 can better improve the influence of the unevenness of the pixel electrode 510 on the display effect.

[0071] The array substrate includes a plurality of pixel electrodes 510, and the area sizes between the pixel electrodes 510 can be the same or different. For example, when the array substrate is used for a display panel and the display panel includes a plurality of sub-pixels, the distribution areas of the plurality of sub-pixels can be the same or different. For example, in some embodiments, the sub-pixels of the display panel include red sub-pixels, blue sub-pixels, and green sub-pixels. The distribution area of the blue sub-pixels may be larger, while the distribution area of the green sub-pixels is smaller. Correspondingly, the positive projection area of the pixel electrode 510 of the blue sub-pixel along the thickness direction Z is larger than the positive projection area of the pixel electrode 510 of the green sub-pixel along the thickness direction Z.

[0072] When the positive projection areas of two pixel electrodes 510 along the thickness direction Z are inconsistent, the positive projection areas of the power supply blocks 331 corresponding to the two pixel electrodes 510 along the thickness direction Z can be the same or different.

[0073] In some alternative embodiments, the areas of at least two pixel electrodes 510 are different, the areas of at least two power supply blocks 331 are different, and the area of the power supply block 331 is positively correlated with the area of the corresponding pixel electrode 510. For example, the pixel electrode 510 includes a first pixel electrode and a second pixel electrode, the power supply block 331 includes a first power supply block and a second power supply block, the positive projection of the first power supply block along the thickness direction Z overlaps at least partially with the positive projection of the first pixel electrode along the thickness direction Z, and the positive projection of the second power supply block along the thickness direction Z overlaps at least partially with the positive projection of the second pixel electrode along the thickness direction Z, that is, the first power supply block corresponds to the first pixel electrode, and the second power supply block corresponds to the second pixel electrode. When the positive projection area of the first pixel electrode along the thickness direction Z is larger than the positive projection area of the second pixel electrode along the thickness direction Z, the positive projection area of the first power supply block along the thickness direction Z is larger than the positive projection area of the second power supply block along the thickness direction Z.

[0074] In these alternative embodiments, pixel electrodes 510 with different areas correspond to power supply blocks 331 with different areas, and the area of the power supply block 331 is positively correlated with the area of the corresponding pixel electrode 510, which can better improve the planarization degree of the pixel electrode 510 corresponding to the power supply block 331 in a targeted manner and better improve the display effect of the display panel.

[0075] Please refer to Figures 1 to 4 , Figure 5 is Figure 1 a partially enlarged structural schematic diagram of

[0076] In some alternative embodiments, as Figures 1 to 5 shown, the second conductive layer 03 further includes a first connection portion 340 and a second connection portion 350. The first connection portion 340 is connected to the first signal line 310 and is located between the first signal line 310 and the second signal line 320; the second connection portion 350 is connected to the second signal line 320 and is located between the first signal line 310 and the second signal line 320; among the two connection lines 332 located on both sides of the same power supply block 331 in the second direction Y and connected thereto, one of them is the first connection line 332a, and the other is the second connection line 332b. The first connection line 332a extends between the first connection portion 340 and the second signal line 320, and the second connection line 332b extends between the second connection portion 350 and the first signal line 310. When the first signal line 310 is a first data line and the first data line is used to transmit data signals to the pixel circuit, the first connection portion 340 is, for example, used to connect the first signal line 310 and the pixel circuit driven by the first signal line 310. Similarly, when the second signal line 320 is a second data line and the second data line is used to transmit data signals to the pixel circuit, the second connection portion 350 can be used to connect the second signal line 320 and the pixel circuit driven by the second signal line 320.

[0077] In these alternative embodiments, the second conductive layer 03 includes a first connection portion 340 and a second connection portion 350. The first connection portion 340 is connected to the first signal line 310 and is located between the first signal line 310 and the second signal line 320, that is, there is a first gap between the first connection portion 340 and the second signal line 320; the second connection portion 350 is connected to the second signal line 320 and is located between the first signal line 310 and the second signal line 320, that is, there is a second gap between the first connection portion 340 and the first signal line 310. Since the first connection portion 340 is connected to the first signal line 310, the first gap is arranged closer to the second signal line 320. Similarly, the second gap is arranged closer to the first signal line 310. On both sides of the same power supply block 331, a first connection line 332a and a second connection line 332b are provided. The first connection line 332a extends between the first connection portion 340 and the second signal line 320, that is, the first connection line 332a extends through the first gap, and the second connection line 332b is arranged between the second connection portion 350 and the second signal line 320, and the second connection line 332b extends through the second gap, which can better ensure the insulation between the second power supply line 330 and the first signal line 310 and the second signal line 320.

[0078] There are various ways to set the connection positions of the first connection line 332a and the second connection line 332b to the power supply block 331. For example, the first connection line 332a and the second connection line 332b can be connected to the same side of the power supply block 331 in the first direction X.

[0079] In some other alternative embodiments, the first connection line 332a is connected to the side of the power supply block 331 facing the second signal line 320, and the second connection line 332b is connected to the side of the power supply block 331 facing the first signal line 310.

[0080] In these alternative embodiments, on the one hand, when the first connection line 332a is located on the side of the power supply block 331 facing the second signal line 320, the first connection line 332a can pass through between the second signal line 320 and the first connection portion 340 along a relatively straight extension path, which can simplify the shape of the first connection line 332a. Similarly, the second connection line 332b is connected to the side of the power supply block 331 facing the first signal line 310, which can also simplify the shape of the second connection line 332b and facilitate the preparation of the first connection line 332a and the second connection line 332b. On the other hand, the first connection line 332a and the second connection line 332b are connected to the diagonal sides of the power supply block 331, and the first connection line 332a and the second connection line 332b are arranged relatively symmetrically with respect to the power supply block 331, which can better improve the unevenness problem of the pixel electrode 510.

[0081] In some optional embodiments, such as Figures 1 to 5 As shown, a plurality of second power lines 330 are spaced apart along the first direction X, and a power block 331 of at least one second power line 330 includes a functional block 331a and an auxiliary block 331b. Optionally, the orthographic projection of the functional block 331a along the thickness direction Z and the orthographic projection of the pixel electrode 510 along the thickness direction Z are at least partially overlapped, and the distribution area and position of the functional block 331a will indirectly affect the flatness of the pixel electrode 510, that is, the functional block 331a has the function of adjusting the flatness of the pixel electrode 510. The auxiliary block 331b is used to assist in increasing the distribution area of ​​the power block 331, so as to increase the distribution area of ​​the second power line 330 and reduce the resistance of the second power line 330. The connection line 332 of the second power line 330 also includes a third connection line 332c, and the auxiliary block 331b and the functional block 331a are spaced apart in the second direction Y and are connected to each other through the third connection line 332c. The third connection line 332 c may be located closer to the second signal line 320 of the first signal line 310 and the second signal line 320 , or the third connection line 332 c may be located closer to the first signal line 310 of the first signal line 310 and the second signal line 320 .

[0082] A power block 331 may include one or more functional blocks 331a, and / or, a power block 331 may include one or more auxiliary blocks 331b. If the auxiliary block 331b and the functional block 331a of a power block 331 need to be connected through multiple third connection lines 332c, then the multiple third connection lines 332c may be located on the same side. Specifically, compared to the second signal line 320, the multiple third connection lines 332c are all located closer to the first signal line 310; or, compared to the first signal line 310, the multiple third connection lines 332c are all located closer to the second signal line 320. In addition, the multiple third connection lines 332c may also be located on different sides, for example, a portion of the third connection lines 332c are located closer to the first signal line 310, and another portion of the third connection lines 332c are located closer to the second signal line 320.

[0083] The second conductive layer 03 may further include a first via portion 360 disposed between the auxiliary block 331b and the functional block 331a; the array substrate further includes a third conductive layer 04 and the fourth conductive layer 05 as described above, the third conductive layer 04 and the fourth conductive layer 05 are disposed on both sides of the second conductive layer 03, that is, the third conductive layer 04 is located on the side of the second conductive layer 03 facing the substrate 01, and the fourth conductive layer 05 is located on the side of the second conductive layer 03 facing away from the substrate 01. The third conductive layer 04 includes a third signal line 410, and at least one pixel electrode 510 of the fourth conductive layer 05 is connected to the third signal line 410 through the first via portion 360.

[0084] Among them, there are various ways to set the third signal line 410. For example, the transistor TFT in the pixel circuit of the array substrate includes a semiconductor part, a gate, a source, and a drain, and the third signal line 410 can be one of the source and the drain. Or the third signal line 410 is a bridge wiring for connecting the pixel electrode 510 to the source or the drain.

[0085] There are various ways to set the relative positions of the third conductive layer 04 and the first conductive layer 02. The third conductive layer 04 can be located on the side of the first conductive layer 02 facing the substrate 01, or the third conductive layer 04 can be located between the first conductive layer 02 and the second conductive layer 03, or the third conductive layer 04 and the first conductive layer 02 are multiplexed.

[0086] In these alternative embodiments, the power supply block 331 is divided into an auxiliary block 331b and a functional block 331a. The auxiliary block 331b and the functional block 331a are connected to each other through a third connection line 332c. A first via portion 360 is provided between the auxiliary block 331b and the functional block 331a, that is, the power supply block 331 is separately arranged in the functional block 331a and the auxiliary block 331b to provide a space for the first via portion 360. The pixel electrode 510 can be connected to the third signal line 410 through the first via portion 360.

[0087] There are various ways to set the second power supply line 330. For example, the shapes and setting methods of the second power supply lines 330 arranged side by side at intervals along the first direction X can be the same.

[0088] In some other alternative embodiments, as Figure 5 shown, the shapes of two adjacent second power supply lines 330 along the first direction X are different. For example, among two adjacent second power supply lines 330 along the first direction X, one is a first sub-power supply line 330a and the other is a second sub-power supply line 330b. The first sub-power supply line 330a includes the above-mentioned functional block 331a but does not include the auxiliary block 331b, and the second sub-power supply line 330b includes the above-mentioned functional block 331a and the auxiliary block 331b. That is, among two adjacent second power supply lines 330, the power supply block 331 of one is integrally arranged, and the power supply block 331 of the other is separately arranged into a functional block 331a and an auxiliary block 331b. In the first sub-power supply line 330a that does not include the auxiliary block 331b, a second via portion 370 is provided between the power supply block 331 and the first connection portion 340 and / or the second connection portion 350. The pixel electrode 510 is connected to the third signal line 410 through the second via portion 370, and the second via portion 370 is located in the second conductive layer 03.

[0089] As can be seen from the above, both the first via portion 360 and the second via portion 370 are used to connect the pixel electrode 510 to the third signal line 410. The difference between the two is that the installation positions of the first via portion 360 and the second via portion 370 are different. The first via portion 360 is arranged in the column where the second sub-power line 330b is located, and the second via portion 370 is arranged in the column where the first sub-power line 330a is located. Therefore, the first via portion 360 is used to connect the pixel electrode 510 in the column where the second sub-power line 330b is located to the third signal line 410, and the second via portion 370 is used to connect the pixel electrode 510 in the column where the first sub-power line 330a is located to the third signal line 410. In these alternative embodiments, the shapes of two adjacent second power lines 330 along the first direction X are different, and the connection positions of the corresponding pixel electrodes 510 and the third signal line 410 are different. Continuing to refer to Figure 3 and Figure 5 the example shown, the pixel electrode 510 includes a first pixel electrode 510a and a second pixel electrode 510b adjacent to each other along the first direction X. The positive projection of the first pixel electrode 510a in the thickness direction Z and the power block 331 of the first sub-power line 330a in the thickness direction Z overlap at least partially. The second pixel electrode 510b and the function block 331a of the second sub-power line 330b overlap at least partially in the thickness direction Z. The first pixel electrode 510a and the second pixel electrode 510b are connected to different third signal lines 410. The first pixel electrode 510a is connected to the third signal line 410 through the second via portion 370, and the second pixel electrode 510b is connected to the third signal line 410 through the first via portion 360. Through the reasonable arrangement of the positions of the first connecting portion 340, the second connecting portion 350, the first via portion 360, the second via portion 370, the first sub-power line 330a, and the second sub-power line 330b as described above, it is beneficial to realize each function.

[0090] In the above embodiment, the second power line 330 may include the first sub-power line 330a and the second sub-power line 330b arranged alternately. In some other embodiments, the second power line 330 may only include the first sub-power line 330a. In still some other embodiments, the second power line 330 may only include the second sub-power line 330b.

[0091] Optionally, the orthographic projection area of a power block 331 of the first sub-power line 330a in the thickness direction Z is larger than the orthographic projection area of a functional block 331a of the second sub-power line 330b in the thickness direction Z, and the orthographic projection area of a first pixel electrode 510 in the thickness direction Z is larger than the orthographic projection area of a second pixel electrode 510 in the thickness direction Z. That is, for pixel electrodes 510 of different sizes, different size designs are made for the power blocks 331 of the first sub-power line 330a and the second sub-power line 330b, which can better improve the unevenness problem of the first pixel electrode 510 and the second pixel electrode 510.

[0092] In some alternative embodiments, the orthographic projection of the first power line 210 on the substrate 01 and the orthographic projection of the second power line 330 on the substrate 01 at least partially overlap. In this way, it can be ensured that the distance between each first power line 210 and each second power line 330 is relatively close, which is convenient for the first power line 210 and the second power line 330 to be connected to each other. In any of the above embodiments, there are various setting shapes of the first connection line 332a and the second connection line 332b, as long as the first connection line 332a and the second connection line 332b can both connect adjacent power blocks 331.

[0093] For example, in the first sub-power line 330a, the first connection line 332a and the second connection line 332b can be arranged to extend along a straight path. The first connection line 332a is located on the side of the power block 331 of the first sub-power line 330a close to the second signal line 320, and the second connection line 332b is located on the side of the power block 331 of the first sub-power line 330a close to the first signal line 310. Arranging the first connection line 332a and the second connection line 332b to extend along a straight path can simplify the shapes of the first connection line 332a and the second connection line 332b, which is convenient for the preparation of the first connection line 332a and the second connection line 332b.

[0094] Optionally, there are multiple second via portions 370, and the second via portions 370 can be located between the power block 331 of the first sub-power line 330a and the first connection portion 340 and / or the second connection portion 350. Optionally, the number of the second via portions 370 is the same as the number of the power blocks 331 in the first sub-power line 330a, and a second via portion 370 is provided on one side of each power block 331 in the second direction Y to increase the connection area between the first power line 210 and the first sub-power line 330a.

[0095] Optionally, in the second sub-power line 330b, there are various setting shapes of the third connection line 332c. For example, the third connection line 332c can be arranged to extend along a straight path to simplify the shape of the third connection line 332c.

[0096] Optionally, the areas of the functional block 331a and the auxiliary block 331b may be the same or different. For example, the orthographic projection area of the functional block 331a in the thickness direction Z is greater than that of the auxiliary block 331b in the thickness direction Z. The functional block 331a is overlapped with the pixel electrode 510. The larger area of the functional block 331a can better improve the unevenness problem of the pixel electrode 510.

[0097] Optionally, the first connection line 332a and / or the second connection line 332b are used to connect the functional block 331a of one of the adjacent two power supply blocks 331 to the auxiliary block 331b of the other. There are various ways to set the shapes of the first connection line 332a and the second connection line 332b. For example, the edges of the auxiliary block 331b and the power supply block 331 facing the second signal line 320 are aligned in the second direction Y. The first connection line 332a can extend along a straight line to connect the functional block 331a of one of the adjacent two power supply blocks 331 to the auxiliary block 331b of the other, which can simplify the shape of the first connection line 332a. Or, when the edges of the auxiliary block 331b and the power supply block 331 facing the first signal line 310 are misaligned in the second direction Y, the second connection line 332b extends along a bent path to connect the functional block 331a of one of the adjacent two power supply blocks 331 to the auxiliary block 331b of the other.

[0098] Optionally, in the second sub-power supply line 330b, the first connection line 332a and the third connection line 332c are aligned in the second direction Y to simplify the shape of the connection line 332.

[0099] An embodiment of the second aspect of the present application further provides a display panel, including the array substrate of any one of the above first aspect embodiments. Since the display panel provided by the embodiment of the second aspect of the present application includes the above array substrate, the display panel provided by the embodiment of the second aspect of the present application has the beneficial effects of the above array substrate, which will not be elaborated here.

[0100] The display panel provided by the embodiment of the present application may be at least one of an organic light-emitting diode display panel, a liquid crystal display panel, and a micro light-emitting diode display panel.

[0101] An embodiment of the third aspect of the present application further provides a display device, including the display panel of any one of the above first aspect embodiments. Since the display device provided by the embodiment of the third aspect of the present application includes the display panel of any one of the above first aspect embodiments, the display device provided by the embodiment of the third aspect of the present application has the beneficial effects of the display panel of any one of the above second aspect embodiments, which will not be elaborated here.

[0102] The display devices in the embodiments of the present application include, but are not limited to, devices with display functions such as mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline telephones, consoles, etc.

[0103] In accordance with the embodiments of the present application as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. These embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. An array substrate, It is characterized in that include: substrate; A first conductive layer, located on one side of the substrate, wherein the first conductive layer comprises a first power line; a second conductive layer, located on a side of the first conductive layer away from the substrate, the second conductive layer comprising a first signal line, a second signal line and a second power line between the first signal line and the second signal line, arranged in a first direction at intervals; The first power line, the first signal line, the second signal line and the second power line are all extended along the second direction, and the first power line and the second power line are connected via holes.

2. The array substrate according to claim 1, It is characterized in that The second power line includes a plurality of power blocks spaced apart along the second direction and a connection line connected between two adjacent power blocks, wherein a width of the connection line in the first direction is smaller than a width of the power block in the first direction.

3. The array substrate according to claim 2, It is characterized in that The second conductive layer further comprises: A first connecting portion connected to the first signal line and located between the first signal line and the second signal line; a second connection portion connected to the second signal line and located between the first signal line and the second signal line; Of the two connecting wires located on both sides of the same power block in the second direction and connected thereto, one is a first connecting wire and the other is a second connecting wire, the first connecting wire is extended between the first connecting portion and the second signal wire, and the second connecting wire is extended between the second connecting portion and the first signal wire; Preferably, the first connecting line is connected to a side of the power block facing the second signal line, and the second connecting line is connected to a side of the power block facing the first signal line.

4. The array substrate according to claim 3, It is characterized in that A plurality of the second power lines are spaced apart along the first direction, the power block of at least one of the second power lines comprises a functional block and an auxiliary block, the connection line of the second power line further comprises a third connection line, the auxiliary block and the functional block are spaced apart in the second direction and are connected to each other through the third connection line, and a first via portion is provided between the auxiliary block and the functional block; The array substrate also includes a third conductive layer and a fourth conductive layer, wherein the third conductive layer and the fourth conductive layer are respectively arranged on both sides of the second conductive layer, the third conductive layer includes a third signal line, and the fourth conductive layer includes a pixel electrode, and the pixel electrode is connected to the third signal line through the first via portion.

5. The array substrate according to claim 4, It is characterized in that Among two adjacent second power supply lines along the first direction, one is a first sub-power supply line and the other is a second sub-power supply line. The first sub-power supply line includes the functional block and does not include the auxiliary block. The second sub-power supply line includes the functional block and the auxiliary block. A second via portion is provided between the power supply block of the first sub-power supply line and the first connection portion and / or the second connection portion. The pixel electrode is interconnected with the third signal line through the second via portion.

6. The array substrate according to any one of claims 2 to 5, wherein, it further comprises: a fourth conductive layer located on a side of the second conductive layer away from the substrate. The fourth conductive layer includes pixel electrodes. A positive projection of the pixel electrodes along the thickness direction of the array substrate overlaps at least partially with a positive projection of the second power supply lines along the thickness direction; Preferably, a positive projection of each power supply block along the thickness direction overlaps at least partially with a positive projection of each pixel electrode along the thickness direction; Preferably, a positive projection of the power supply block along the thickness direction is centrosymmetrically arranged about a center of a positive projection of the pixel electrode along the thickness direction; Preferably, a positive projection of the power supply block along the thickness direction is located within a positive projection of the pixel electrode along the thickness direction.

7. The array substrate according to claim 6, wherein, areas of at least two of the pixel electrodes are different, areas of at least two of the power supply blocks are different, and the area of the power supply block is positively correlated with the area of the corresponding pixel electrode.

8. The array substrate according to any one of claims 1 to 5, wherein, a positive projection of the first power supply line on the substrate overlaps at least partially with a positive projection of the second power supply line on the substrate.

9. The array substrate according to any one of claims 1 to 5, wherein, the array substrate further comprises a plurality of pixel circuits provided on one side of the substrate. The plurality of pixel circuits are arranged in columns along the second direction; the first signal line is a first data line, the second signal line is a second data line, and the first data line and the second data line are used to provide data signals to a plurality of the pixel circuits in the same column arranged along the second direction; Preferably, among two adjacent pixel circuits in the second direction, a data signal of one of the pixel circuits is provided by the first data line, and a data signal of the other pixel circuit is provided by the second data line.

10. A display panel, wherein, it includes the array substrate according to any one of claims 1 - 9.

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