Voltage and phase compensation circuit and display device including the same

Abstract

Disclosed are a voltage and phase compensation circuit and a display device including the same. The voltage and phase compensation circuit includes: a first inverting adder configured to add and invert a plurality of panel signals to output a first inverted signal; a second inversion adder configured to add and invert a feedback signal obtained from the delayed panel signal and the first inversion signal to output a second inversion signal; and a coupler configured to couple the first inversion signal and the second inversion signal.

Description

Technical Field

[0001] The present disclosure relates to a voltage and phase compensation circuit for reducing electromagnetic interference (hereinafter referred to as "EMI") signals emitted from a display panel, and a display device including the circuit. Background Art

[0002] A driving circuit of a display device writes pixel data of an input image into pixels of a display panel to reproduce the input image on a pixel array. The display device includes a display panel driving circuit, such as a data driving circuit that supplies pixel data signals to data lines, and a gate driving circuit that supplies gate signals (or scan signals) to gate lines (or scan lines), etc. A flat panel display device includes a control circuit that controls the data driving circuit and the gate driving circuit, such as a timing controller.

[0003] A touch screen may be provided on a screen of the display device. In this case, the display panel driving circuit may further include a touch sensor driving circuit for driving a touch sensor of the touch screen.

[0004] Descriptions provided in the background art section should not be assumed to be prior art merely because they are mentioned in the background art section or are associated with the descriptions in the background art section. The descriptions in the background art section may include information describing one or more aspects of the subject technology, and the descriptions in this section do not limit the present invention. Summary of the Invention

[0005] The inventors have recognized that AC signals output from a display panel driving circuit may generate EMI and adversely affect peripheral devices. Therefore, an object of the present disclosure is to solve the above necessity and / or disadvantages.

[0006] The present disclosure provides a voltage and phase compensation method for minimizing EMI and a display device using the same.

[0007] Problems of the present disclosure are not limited to the above problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following descriptions.

[0008] According to an exemplary embodiment of the present disclosure, a voltage and phase compensation circuit includes: a first inverting adder configured to add and invert a plurality of panel signals to output a first inverted signal; a second inverting adder configured to add and invert a feedback signal obtained from a delayed panel signal and the first inverted signal to output a second inverted signal; and a coupler that combines the first inverted signal and the second inverted signal.

[0009] A signal combining the first inverted signal and the second inverted signal may have an inverted phase of the delayed panel signal and a voltage equal to the voltage of the delayed panel signal.

[0010] The first inverting adder may include a first operational amplifier, which includes an inverting input terminal connected to a plurality of input resistors to which a panel signal is applied, a non-inverting input terminal to which a reference voltage is applied, and an output terminal connected to the inverting input terminal to output a first inverted signal, wherein a resistor is interposed between the inverting input terminal and the output terminal. The second inverting adder may include a second operational amplifier, which includes an inverting input terminal connected to a plurality of input resistors to which a feedback signal and a first inverted signal are applied, a non-inverting input terminal to which a reference voltage is applied, and an output terminal connected to the inverting input terminal to output a second inverted signal, wherein a resistor is interposed between the inverting input terminal and the output terminal.

[0011] The plurality of input resistors of the first operational amplifier may include a first input resistor, a second input resistor, and a third input resistor to which the panel signal is applied, and the plurality of input resistors of the second operational amplifier include a first input resistor, a second input resistor, and a third input resistor to which the feedback signal is applied, and a fourth input resistor to which the first inverted signal is applied.

[0012] The resistance values of the plurality of input resistors of the first operational amplifier and each of the input resistors of the second operational amplifier may all be the same.

[0013] The resistance value of the resistor interposed between the output terminal and the inverting input terminal may be less than the resistance value of any one of the plurality of input resistors of the first operational amplifier and the plurality of input resistors of the second operational amplifier.

[0014] The panel signal may include a first panel signal, a second panel signal, and a third panel signal having different phases. The feedback signal may include a first feedback signal obtained by delaying the first panel signal, a second feedback signal obtained by delaying the second panel signal, and a third feedback signal obtained by delaying the third panel signal. The first panel signal, the second panel signal, and the third panel signal may be input to the inverting input terminal of the first operational amplifier through the input resistors of the first operational amplifier. The first feedback signal, the second feedback signal, the third feedback signal, and the first inverted signal may be input to the inverting input terminal of the second inverting adder through the input resistors of the second operational amplifier.

[0015] The output voltage ratios of the first operational amplifier and the second operational amplifier may be the same.

[0016] The connector may include a capacitor and a diode connected in series between the output terminal of the first operational amplifier and the output terminal of the second operational amplifier.

[0017] The capacitor may allow only the AC component of the second inverted signal to pass to the diode, and the diode may block the reverse current from flowing to the second operational amplifier.

[0018] According to an exemplary embodiment of the present disclosure, a display device includes: a display panel on which wirings to which a plurality of panel signals are applied, feedback lines each connected to the wirings, a plurality of pixels, and cancellation signal lines are provided; a display panel driving circuit configured to write pixel data of an input image into the pixels; a signal generator configured to output the panel signals; and a voltage and phase compensator configured to supply a cancellation signal to the cancellation signal lines. The voltage and phase compensator includes: a first inverting adder configured to add and invert the panel signals to output a first inverted signal; a second inverting adder configured to add and invert a feedback signal received from the feedback lines and the first inverted signal to output a second inverted signal; and a coupler configured to combine the first inverted signal and the second inverted signal to output a cancellation signal.

[0019] The display panel may further include a plurality of data lines to which a data voltage is applied; and a plurality of gate lines to which a gate signal is applied. The display panel driving circuit may further include a data driver configured to output a data voltage; a demultiplexer connected between an output terminal of the data driver and the data lines; and a gate driver configured to output a gate signal. The panel signals may include at least one of a control signal for controlling a transistor of the demultiplexer and a clock input to the gate driver.

[0020] The display panel may further include a TX line connected to a plurality of touch sensors. The display panel driving circuit may further include a touch sensor driver configured to supply a driving signal to the TX line. The panel signals may include a driving signal.

[0021] According to another exemplary embodiment of the present disclosure, a display device includes: a display panel on which a TX line connected to a plurality of touch sensors, a plurality of pixels, and cancellation signal lines is provided; a touch sensor driver configured to sequentially supply a driving signal to the TX line; and a voltage and phase compensator configured to supply a cancellation signal to the cancellation signal lines. The voltage and phase compensator includes: an inverting adder circuit configured to add and invert the driving signals from the touch sensor driver; and a coupler connected between the inverting adder circuit and the cancellation signal lines.

[0022] The inverting adder circuit may include: a first inverting adder configured to add and invert two or more group signals in which a plurality of the driving signals are grouped to output a first inverted signal; and a second inverting adder configured to add and invert the group signals and the first inverted signal to output a second inverted signal.

[0023] The coupler can combine the first anti-phase signal and the second anti-phase signal to output a cancellation signal.

[0024] Each of the group of signals can include two or more drive signals grouped by a logical OR. The group of signals can be sequentially input to each of the first inverting summer and the second inverting summer. Each of the drive signals can include a plurality of pulses.

[0025] The first inverting summer can include a first operational amplifier, which includes an inverting input terminal connected to a plurality of input resistors to which the group of signals is applied, a non-inverting input terminal to which a reference voltage is applied, and an output terminal connected to the inverting input terminal to output the first anti-phase signal, wherein a resistor is interposed between the inverting input terminal and the output terminal. The second inverting summer can include a second operational amplifier, which includes an inverting input terminal connected to a plurality of input resistors to which the group of signals and the first anti-phase signal are applied, a non-inverting input terminal to which a reference voltage is applied, and an output terminal connected to the inverting input terminal to output the second anti-phase signal, wherein a resistor is interposed between the inverting input terminal and the output terminal.

[0026] The plurality of input resistors of the first operational amplifier can include a first input resistor, a second input resistor, a third input resistor, and a fourth input resistor to which the group of signals is applied and which have gradually increasing resistance values, and the plurality of input resistors of the second operational amplifier can include a first input resistor, a second input resistor, a third input resistor, and a fourth input resistor to which the group of signals is applied and which have gradually increasing resistance values.

[0027] The output voltage ratio between the first operational amplifier and the second operational amplifier can be the same.

[0028] The resistance values of at least two of the input resistors of the first operational amplifier can be different from each other. The resistance values of at least two of the input resistors of the second operational amplifier can be different from each other.

[0029] The coupler can include a capacitor and a diode connected in series between the output terminal of the first operational amplifier and the output terminal of the second operational amplifier.

[0030] The inverting summer circuit can include: an inverting summer configured to add and invert a group of signals in which the drive signals applied to the TX line are grouped and an anti-phase signal in which the group of signals is inverted; and a coupler configured to combine the output signal of the inverting summer and the anti-phase signal to output a cancellation signal.

[0031] The inverting adder may include an operational amplifier, which includes an inverting input terminal connected to a plurality of input resistors for applying a set of signals and an inverted signal, a non-inverting input terminal to which a reference voltage is applied, and an output terminal connected to the inverting input terminal, wherein a resistor is interposed between the inverting input terminal and the output terminal.

[0032] The coupler may include a capacitor and a diode connected in series between the output terminal of the operational amplifier and the node to which the inverted signal is applied.

[0033] The capacitor may only allow the AC component of the second inverted signal to pass to the diode, and the diode may block the reverse current from flowing to the second operational amplifier.

[0034] The present disclosure may implement a display device having high efficiency, high brightness, long life, and no EMI.

[0035] The present disclosure may improve the efficiency of electromagnetic wave cancellation by compensating the voltage and phase of the inverted signal to match the panel signal, regardless of whether the panel signal, which is the target signal for electromagnetic wave cancellation, overlaps.

[0036] According to the present disclosure, the EMI emitted from the display panel may be minimized by applying a cancellation signal obtained by combining the inverted signal of the panel signal and the inverted signal of the residual noise to a cancellation signal line.

[0037] According to the present disclosure, the TX lines of a touch screen having a multi-channel transmission structure may be grouped to separately control the voltage of each TX group having a large electromagnetic emission asymmetry, so as to increase the cancellation effect and freely control the amount of electromagnetic emission.

[0038] The effects of the present disclosure are not limited to the above effects, and other effects not mentioned will be clearly understood by those skilled in the art according to the description of the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] By describing the exemplary embodiments of the present disclosure in detail with reference to the accompanying drawings, the above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art, wherein:

[0040] Figure 1 is a block diagram showing a display device according to an exemplary embodiment of the present disclosure;

[0041] Figure 2 is a circuit diagram showing an example of a demultiplexer;

[0042] Figure 3 is a cross-sectional view showing an example of a display panel;

[0043] Figure 4is a diagram showing an example of a voltage and phase compensation circuit according to an example embodiment of the present disclosure;

[0044] Figure 5A and Figure 5B is a diagram showing an example of a panel signal and a first inverted signal;

[0045] Figure 6 is a waveform diagram showing an example of delaying a panel signal in a display panel;

[0046] Figure 7 is a waveform diagram showing an example of phase and voltage asymmetry between a first inverted signal and a panel signal when the first inverted signal is applied to a display panel;

[0047] Figure 8 is a waveform diagram showing an example of phase and voltage symmetry between a panel signal and a cancellation signal;

[0048] Figure 9 is a waveform diagram showing an example of residual noise and inverted residual noise;

[0049] Figure 10 is a waveform diagram showing a cancellation signal and a panel signal observed in an experiment;

[0050] Figure 11 is a circuit diagram showing in detail an example embodiment of a voltage and phase compensator;

[0051] Figure 12 and Figure 13 is a diagram showing an example of a TX line;

[0052] Figure 14 is a waveform diagram showing an example of a drive signal applied to a TX line;

[0053] Figure 15 is showing for Figure 14 is a waveform diagram showing an example of a method of grouping the drive signals shown in;

[0054] Figure 16 is showing in detail the voltage and phase compensator into which is input Figure 15 is a circuit diagram showing an example of a voltage and phase compensator for the TX group signal shown in;

[0055] Figure 17 is a waveform diagram showing an example of a cancellation signal having a voltage difference for each TX group;

[0056] Figure 18 is showing for Figure 14 is a waveform diagram showing another example of a method of grouping the drive signals shown in;

[0057] Figure 19 is showing in detail in which is input asFigure 18 Circuit diagram of an example of a voltage and phase compensator for a single set of signals and an inverted set of signals as shown;

[0058] Figure 20 is an experimental result graph showing the EMI improvement effect of a comparative example with a phase difference between a panel signal and a first inverted signal; and

[0059] Figure 21 is an experimental result graph showing the EMI improvement effect of a voltage and phase compensation circuit according to an example embodiment of the present disclosure.

[0060] Throughout the drawings and the detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and descriptions of these elements may be exaggerated. Detailed Description

[0061] According to the example embodiments described below with reference to the accompanying drawings, the advantages and features of the present disclosure and the methods for implementing the present disclosure will be more clearly understood. However, the present disclosure is not limited to the following example embodiments, but may be implemented in various different forms. On the contrary, these example embodiments will make the disclosure of the present disclosure complete and allow those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is limited only within the scope of the appended claims.

[0062] The shapes, sizes, areas, ratios, angles, quantities, etc. shown in the drawings used to describe the example embodiments of the present disclosure are only examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0063] Terms such as "comprising", "having", "including", "containing", "constituting", "made of", "formed by", "composed of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". Any reference to the singular may include the plural, unless otherwise clearly stated.

[0064] Even if not explicitly stated, components are interpreted to include a normal error range.

[0065] When describing positional or interconnecting relationships such as "on", "above", "over", "below", "under", "beside", "beneath", "near", "next to", "adjacent to", "on the side of", "close to", "connected or coupled to", "intersecting", "crossing", etc. between two components, one or more other components may be interposed therebetween, unless "exactly" or "directly" is used.

[0066] Spatially relative terms, such as "below", "beneath", "under", "lower", "above", "upper", etc., may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It should be understood that, in addition to the orientation shown in the figures, spatially relative terms may also include different orientations of an element during use or operation. For example, if an element in the figure is inverted, an element described as "below" or "beneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary term "below" may include both below and above orientations. Similarly, the exemplary terms "above" or "over" may include both "above" and "below" orientations.

[0067] When describing temporal precedence relationships such as "after", "subsequently", "next", "before", etc., they may not be continuous on a temporal basis, unless "immediately" or "directly" is used.

[0068] Terms such as "first", "second", "A", "B", "a", and "b", etc. may be used to distinguish elements from each other, but the function or structure of a component is not limited by the serial number or component name in front of the component.

[0069] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. may be used herein. Each of these terms is not used to define the essence, order, or sequence of the corresponding component, but only to distinguish the corresponding component from other components. In the case where a structural element or layer is described as "connected", "coupled", "adhered", or "joined" to another structural element or layer, it is generally interpreted that the other structural element or layer may be "connected", "coupled", "adhered", or "joined" to the structural element or layer directly or indirectly.

[0070] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of the first item, the second item, and the third item" represents all combinations of two or more of the first item, the second item, and the third item, as well as the first item, the second item, or the third item.

[0071] As used herein, the term "device" may refer to a display device including a display panel and a driver for driving the display panel. Examples of the display device may include a light-emitting device and the like. In addition, examples of the device may include a laptop computer, a television, a computer monitor, an automotive device, a wearable device, and an automotive equipment device, and a complete product or a final product set of electronic devices (or equipment) or a set of devices (or equipment) each including a light-emitting device and the like, such as a mobile electronic device such as a smartphone or a tablet computer, but the embodiments of the present disclosure are not limited thereto.

[0072] Throughout the specification, the same reference numerals generally denote the same elements.

[0073] For ease of description, the dimensions and thicknesses of each component shown in the drawings are illustrated, and the present disclosure is not limited to the dimensions and thicknesses of the components shown.

[0074] The following exemplary embodiments may be partially or completely combined or combined with each other and may be linked and operated in various ways technically. The exemplary embodiments may be executed independently or in association with each other.

[0075] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. It will be further understood that terms, such as those defined in a commonly used dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the related art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0076] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the drawings.

[0077] Referring Figure 1 and Figure 2 , a display device according to an exemplary embodiment of the present disclosure includes a display panel 100, a display panel driving circuit for writing video data into pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels 101 and the display panel driving circuit, but the components of the display device of the present disclosure are not limited thereto. In addition, all components of each display device according to all embodiments of the present disclosure are operably coupled and configured.

[0078] The substrate of the display panel 100 can be a plastic substrate, a thin glass substrate, or a metal substrate, but is not limited thereto. In some example embodiments, the substrate can be formed of a flexible plastic material. In some example embodiments, the substrate can be made of a flexible polymer film. For example, the flexible polymer film can be made of any one of polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyarylate (PAR), polysulfone (PSF), cycloolefin copolymer (COC), triacetyl cellulose (TAC), polyvinyl alcohol (PVA), and polystyrene (PS), and the present disclosure is not limited thereto. The display panel 100 can be a panel having a rectangular structure, having a length in the X-axis direction (or the first direction), a width in the Y-axis direction (or the second direction), and a thickness in the Z-axis direction (or the third direction), but is not limited thereto. For example, at least a part of the display panel 100 can have a curved exterior. For example, at least a part having a curved exterior can be provided at the center of the display panel 100, alternatively, at least a part having a curved exterior can be provided at at least one side of the display panel 100, but is not limited thereto.

[0079] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel can be applied to a transparent display device in which an image is displayed on the screen and an actual object is visible outside the display panel 100. The display panel 100 can be manufactured as a flexible display panel. The display panel 100 can be manufactured as an extendable and stretchable panel, but is not limited thereto.

[0080] In the display panel 100, a display area AA can be defined and a non-display area NA can be provided near, surrounding, or around the display area AA. The display area AA of the display panel 100 includes a pixel array for displaying an input image. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels 101 arranged in a matrix. For example, in the display area AA, a plurality of pixel regions can be arranged in a matrix form along a plurality of row lines and column lines. The plurality of pixel regions can include pixel regions displaying different colors (e.g., red (R), green (G), and blue (B) or red (R), green (G), blue (B), and white). At this time, adjacent red (R), green (G), and blue (B) pixel regions or adjacent red (R), green (G), blue (B), and white pixel regions can be used as a unit pixel for displaying a color image. The display panel 100 can also include a power supply line commonly connected to the pixels 101. The power supply line is commonly connected to the pixel circuit to supply a constant voltage required to drive the pixels 101 to the pixels. The power supply line can be implemented as a long strip wiring in a first direction or a second direction, or can be implemented as a grid wiring in which the wiring in the first direction is electrically connected to the wiring in the second direction.

[0081] The pixel 101 can include a liquid crystal cell, which includes liquid crystal molecules or a light-emitting element. A plurality of sub-pixels are the smallest units constituting the display area AA, and n sub-pixels form one pixel. Each of the plurality of sub-pixels can emit light having different wavelengths from each other. The plurality of sub-pixels can include a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors from each other, or the plurality of sub-pixels can include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel that emit light of different colors from each other. For example, each pixel 101 can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color implementation. Each pixel can also include a white sub-pixel.

[0082] For example, the plurality of sub-pixels may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, wherein the red sub-pixel, the green sub-pixel, and the blue sub-pixel may be set in a repeating manner. Alternatively, the plurality of sub-pixels may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, wherein the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be set in a repeating manner, or the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be set in a quadrilateral type. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel may be sequentially set along the row direction, or the red sub-pixel, the blue sub-pixel, the green sub-pixel, and the white sub-pixel may be sequentially set along the row direction. However, in the exemplary embodiments of the present disclosure, the color type, the arrangement type, and the arrangement order of the sub-pixels are not limited and may be configured in various forms according to the light-emitting characteristics, the device lifetime, and the device specifications.

[0083] In addition, according to the light-emitting characteristics, the sub-pixels may have different light-emitting areas. For example, the sub-pixels that emit light of a color different from that of the blue sub-pixel may have a light-emitting area different from that of the blue sub-pixel. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel or the red sub-pixel, the blue sub-pixel, the white sub-pixel, and the green sub-pixel may each have a different light-emitting area.

[0084] Each sub-pixel includes a pixel circuit for driving a light-emitting element. Each pixel circuit may be connected to a data line, a gate line, and a power supply line. Hereinafter, "pixel" may be interpreted as "sub-pixel".

[0085] The pixel array includes a plurality of pixel rows L1-Ln. Each of the pixel rows L1 to Ln includes a row of pixels arranged along the row direction (X-axis direction) in the pixel array of the display panel 100. The pixels provided in one pixel row share the gate line 103. The sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period is the time obtained by dividing one frame period by the total number of the pixel rows L1 to Ln.

[0086] The power supply 140 generates a constant voltage (or DC voltage) required to drive the pixel array of the display panel 100 and the display panel driving circuit through a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 140 may output a constant voltage required to drive the display panel driving circuit and the pixels by adjusting the level of the DC input voltage applied from the host system 200.

[0087] The display panel driving circuit writes the video data of the input image into the pixels of the display panel 100 under the control of the timing controller 130. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0088] The display panel driving circuit further includes a touch sensor driver 170 for driving the touch sensors of the touch screen 160. The touch sensors may be provided on the display panel 100 in an on-cell type or an in-cell type, or may be implemented as an in-cell type touch sensor embedded in the display panel 100. The touch sensors may be touch sensors using capacitance, such as self-capacitance type touch sensors or mutual-capacitance type touch sensors, but are not limited thereto.

[0089] The data driver 110 and the touch sensor driver 170 may be integrated in a single driving integrated circuit (IC). In a mobile terminal or a wearable terminal, the timing controller 130, the power supply 140, the level shifter 150, the data driver 110, the touch sensor driver 170, etc. may be integrated in a single driving IC, but are not limited thereto.

[0090] The output terminals of the data driver 110 may be electrically connected to the data lines 102 of the display panel 100. The data driver 110 receives video data of an input image received as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 converts the video data of the input image into a gamma compensation voltage using a digital-to-analog converter (hereinafter referred to as "DAC") to output the data voltage. The gamma reference voltage may be output from the power supply 140. The gamma reference voltage is subdivided into gamma compensation voltages for each gray level by a voltage dividing circuit of the data driver 110 and is supplied to the DAC. The DAC generates a data voltage as the gamma compensation voltage corresponding to the gray level of the video data. The data voltage output from the DAC is output to the data lines 102 from each data output channel of the data driver 110 through an output buffer. The data driver 110 may be configured with at least one data IC. In this case, as an example, the data IC of the data driver 110 may be connected to a non-display area on the corresponding side of the display panel 100, or may be directly mounted on the non-display area. As an example, the data IC of the data driver 110 may be mounted on a flexible circuit film and connected to a non-display area on the corresponding side of the display panel 100.

[0091] The display panel driving circuit may further include a plurality of demultiplexers (DEMUX) 112 provided between the data lines 102 and the output terminals of the data driver 110. The demultiplexer 112 may be a 1:N demultiplexer, where N is a natural number greater than or equal to 2. In the case of a 1:3 demultiplexer 112, as Figure 2 shown, the data voltage Vdata output from the data driver 110 is sequentially supplied to the first to third data lines 1021, 1022, and 1023 using the first to third transistors M1, M2, and M3. In Figure 2Among them, GATE is a gate signal output from the gate driver 120. The sub-pixels 1011, 1012, and 1013 are connected to the corresponding data lines 1021, 1022, and 1023 and the gate line 103. In Figure 2 Among them, the reference numerals MUX1, MUX2, and MUX3 are control signals applied to the gates of the transistors M1, M2, and M3.

[0092] When the demultiplexer 112 is connected between the output terminal of the data driver 110 and the data line 102, the number of channels of the data driver 110 can be reduced. The demultiplexer 112 can also be omitted.

[0093] The gate driver 120 can be formed on the display panel 100. The gate driver 120 can be disposed in the non-display area NA outside the display area AA in the display panel 100, or at least a part thereof can be disposed in the display area AA. Although in Figure 1 Among them, an example shows that one gate driver 120 is disposed on one side of the display panel 100, but the number and arrangement of the gate drivers 120 are not limited thereto. For example, two gate drivers 120 can be respectively disposed on both sides of the display panel 100. For example, the gate driver 120 can be mounted on the display panel 100. Thus, a structure in which the gate driver 120 is directly mounted on the display panel 100 is referred to as an in-panel gate (GIP) structure, but is not limited thereto. Alternatively, the gate driver 120 can be spaced apart from the display panel 100, but is not limited thereto.

[0094] The gate driver 120 can supply the gate signal to the gate line 103 in a single-feed manner, but the present disclosure is not limited thereto. For example, the gate driver 120 can also supply the gate signal to the gate line 103 in a dual-feed manner. In single-feed, the gate signal is applied to one end of the gate line 103. In the dual-feed manner, the gate signal is simultaneously applied to both ends of the gate line 103.

[0095] The gate driver 120 uses a shift register and / or edge trigger to sequentially output pulses of the gate signal to the gate line 103.

[0096] The touch sensor driver 170 is connected to the touch line. A plurality of touch sensors are connected to the touch line. The touch line can be divided into a TX line and an RX line. A driving signal (hereinafter referred to as a "signal") for driving the touch sensor is applied to the TX line, and the output signal of the touch sensor is transmitted to the RX line, but is not limited thereto. The touch sensor driver 170 can convert the voltage of the TX signal through a level shifter and supply the voltage to the TX line.

[0097] The touch sensor driver 170 applies a TX signal to the touch sensor via the TX line, amplifies the voltage received from the touch sensor via the RX line, converts the amplified voltage into digital data, and outputs touch raw data. The touch sensor driver 170 compares the input touch raw data with a preset reference value and outputs the touch raw data TDATA indicating each touch input. The touch raw data TDATA equal to or greater than the reference value can be output as a logical value indicating a touch input. The touch raw data TDATA can be transmitted to the host system 200.

[0098] The timing controller 130 receives video data of an input image and a timing signal synchronized with data from the host system 200. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, etc. Here, the horizontal synchronization signal is a signal indicating the time taken for one horizontal line of a display screen, and the vertical synchronization signal is a signal indicating the time taken for displaying one frame of a screen. The data enable signal may correspond to a signal indicating a period during which a data voltage is supplied to pixels. Since the vertical period and the horizontal period can be known by a method of counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of one horizontal period 1H.

[0099] The timing controller 130 controls the display panel driving circuit by generating a signal for controlling the operation timing of the display panel driving circuit based on the timing signals Vsync, Hsync, and DE received from the host system 200.

[0100] The host system 200 can scale an image signal from a video source to match the resolution of the display panel 100 and send it to the timing controller 130 together with the timing signal. The host system 200 processes a user command received through a touch input in response to the touch raw data TDATA input from the touch sensor driver 170.

[0101] When a still image or always-on display (AOD) data is input under the control of the timing controller 130 or the host system 200, the display panel driving circuit can enter a low-power mode to reduce the power consumption of the display device. In the normal mode, the scanning rate of the display panel 100 is reduced, so the refresh rate of the pixel 101 can be reduced to 60 Hz, 144 Hz, 240 Hz, etc. The refresh rate is the frequency at which video data is written to the pixel 101. In the low-power mode, the refresh rate of the pixel 101 is reduced to a frequency lower than 60 Hz. For example, the refresh rate of the pixel 101 is reduced to a frequency lower than 50 Hz, such as 1 Hz to 30 Hz. When the refresh rate is 1 Hz, the first frame out of 60 frames per second can be a refresh frame, and the subsequent 59 frames can be hold frames. During the refresh frame period, after charging the data voltage Vdata of the video data in the pixel 101, the pixel 101 can maintain the data voltage charged in the previous refresh frame during the consecutive hold frame periods without charging the data voltage Vdata to maintain the light-emitting state.

[0102] The display panel driving circuit includes a voltage and phase compensator 300 that outputs a cancellation signal CS, and the voltage and phase of the cancellation signal CS are inverted with respect to an alternating current signal (hereinafter referred to as "panel signal") applied to the display panel driving circuit. The cancellation signal CS is applied to a cancellation signal line provided on the display panel 100.

[0103] The voltage and phase compensator 300 can be provided on a printed circuit board (PCB) on which the timing controller 130, the level shifter 150, the touch sensor driver 170, etc. are mounted, but is not limited thereto. The voltage and phase compensator 300 can include at least one of a first voltage and phase compensator connected to the output terminal of the level shifter 150 and a second voltage and phase compensator connected to the output terminal of the touch sensor driver 170.

[0104] In the case of an electroluminescent display device, the display panel can have a cross-sectional structure as Figure 3 shown, but is not limited thereto.

[0105] Referring to Figure 3 , the display panel 100 can include a circuit layer 12, a light-emitting device layer 14, a packaging layer 16, and a touch sensor layer 18 laminated on a substrate 10.

[0106] The circuit layer 12 can include pixel circuits, a demultiplexer 112, a gate driver 120, etc. connected to wirings such as data lines, gate lines, and power supply lines. The wirings and circuit elements of the circuit layer 12 can include a plurality of insulating layers, two or more metal layers separated from each other with an insulating layer interposed therebetween, and an active layer including a semiconductor material.

[0107] The light-emitting device layer 14 may include a light-emitting device EL driven by a pixel circuit. The light-emitting device EL may be implemented as an organic light-emitting device (e.g., OLED) or an inorganic light-emitting device (e.g., micro-LED). The light-emitting device EL may include a red light-emitting device, a green light-emitting device, and a blue light-emitting device. In another exemplary embodiment, the light-emitting device layer 14 may include a white light-emitting device and a color filter. The light-emitting device EL of the light-emitting device layer 14 may be covered by a plurality of protective layers including an organic film and an inorganic film.

[0108] The encapsulation layer 16 covers the light-emitting device layer 14 to seal the circuit layer 12 and the light-emitting device layer 14. The encapsulation layer 16 may have a multi-insulating film structure in which an organic film and an inorganic film are alternately stacked. The inorganic film blocks the penetration of moisture or oxygen. The organic film planarizes the surface of the inorganic film. When the organic film and the inorganic film are stacked in multiple layers, the movement path of moisture or oxygen is longer than that of a single layer, so that the penetration of moisture and oxygen affecting the light-emitting device layer 14 can be effectively blocked.

[0109] The encapsulation layer 16 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer to the third encapsulation layer may be sequentially stacked on the light-emitting device layer 14. The first encapsulation layer and the third encapsulation layer may be formed of an inorganic film layer including an inorganic material, and the second encapsulation layer may be formed of an organic film layer including an organic material.

[0110] The first encapsulation layer may be formed at the lowermost end of the encapsulation layer 16. For example, it may be in contact with the upper surface of the light-emitting device layer 14. The first encapsulation layer may be formed of a material such as silicon nitride SiNx, silicon oxide SiOx, silicon oxynitride SiON, or aluminum oxide Al2O3.

[0111] The second encapsulation layer may be formed on the first encapsulation layer. The second encapsulation layer may be formed of a material such as acrylic resin, epoxy resin, polyimide, polyethylene PE, or silicon oxycarbide SiOC.

[0112] The third encapsulation layer may be formed on the second encapsulation layer. The third encapsulation layer may be formed of the same material as the first encapsulation layer, but the present disclosure is not limited thereto. The third encapsulation layer may be formed of a material different from that of the first encapsulation layer.

[0113] In addition, the encapsulation layer is not limited to three layers. For example, it may include n layers (where n is an integer greater than 3) in which an inorganic encapsulation layer and an organic encapsulation layer are alternately stacked.

[0114] The touch sensor layer 18 may be disposed on the encapsulation layer 16. The touch sensor layer 18 includes a touch sensor and touch lines 19 connected to the touch sensor. The touch lines 19 and the touch sensor electrodes may be formed of a metal pattern disposed on the encapsulation layer 16. At the intersections of the metal wiring patterns, for example, at the portions where the TX line and the RX line intersect, an insulating layer may be provided between the metal wiring patterns to insulate them from each other.

[0115] A polarizer or a color filter layer may be disposed on the touch sensor layer 18. The polarizer may improve visibility and contrast by converting the polarization of external light reflected by the metals of the touch sensor layer 18 and the circuit layer 12. The color filter layer may include red, green, and blue color filters. The color filter layer may further include a black matrix pattern. The black matrix pattern may be used to prevent light leakage of the color filter layer. Alternatively, the black matrix pattern may be used to increase the absorption rate of external light incident from the outside of the display device. Since only a very small amount of incident external light can be reflected by the black matrix pattern, visibility and clarity may be increased due to less influence of the external light. In addition, the black matrix pattern is used to reduce the contrast caused by the bottom reflection of the external light and may absorb light having wavelengths in the visible light range. The color filter layer may absorb a part of the wavelengths of the light reflected by the metals of the circuit layer 12 and the touch sensor layer 18 to substitute for the function of the polarizer and increase the color purity of the image reproduced in the pixel array.

[0116] Figure 4 FIG. is a diagram illustrating an example of a voltage and phase compensation circuit according to an exemplary embodiment of the present disclosure. In this exemplary embodiment, the voltage and phase compensation circuit receives the panel signal and a feedback signal received from the display panel before the panel signal is applied to the display panel to output a cancellation signal. The cancellation signal is applied to a cancellation signal line provided on the display panel.

[0117] Reference Figure 4 , the display panel 100 includes a feedback signal line 44 connected to signal lines to which panel signals Sin1, Sin2, and Sin3 are applied and a cancellation signal line 40 to which a cancellation signal CS is applied.

[0118] The panel signals Sin1, Sin2, and Sin3 are signals applied to the display panel 100 to induce electromagnetic emission from the display panel 100. The panel signals Sin1, Sin2, and Sin3 may be a plurality of panel signals having different phases and may overlap each other or may not overlap each other. For example, as Figure 5A shown, any two of the panel signals Sin1, Sin2, and Sin3 overlap each other. Alternatively, for example, as Figure 5BAs shown, any two of the panel signals Sin1, Sin2, and Sin3 do not overlap with each other, but are not limited thereto. The panel signals Sin1, Sin2, and Sin3 may be control signals applied to the transistor 42 of the demultiplexer 112, clocks applied to the transistor 42 of the gate driver 120, TX signals applied to the touch sensor, etc., but are not limited thereto. The signal lines to which the panel signals Sin1, Sin2, and Sin3 are applied may be metal wirings connecting to the transistors of the display panel 100.

[0119] The panel signals Sin1, Sin2, and Sin3 may include two or more of the control signal of the demultiplexer 112, the clock input to the gate driver 120, and the TX signal applied to the touch sensor. For example, the panel signals Sin1, Sin2, and Sin3 may include all of the control signal of the demultiplexer 112, the clock input to the gate driver 120, and the TX signal applied to the touch sensor, but are not limited thereto.

[0120] The cancellation signal CS is a signal whose phase is inverted (or shifted by 180 degrees) with respect to the panel signals Sin1, Sin2, and Sin3 and has the same voltage as the voltages of the panel signals Sin1, Sin2, and Sin3. The cancellation signal is applied to the cancellation signal line 40 provided on the display panel to cancel electromagnetic waves from the panel signals Sin1, Sin2, and Sin3. The cancellation signal line 40 is a metal wiring that emits an electromagnetic wave with an inverted phase, and this electromagnetic wave compensates for the electromagnetic wave generated due to the panel signals Sin1, Sin2, and Sin3 by being applied with the cancellation signal CS. The cancellation signal line 40 may be a single-loop pattern provided in the non-display area NA of the display panel 100, but is not limited thereto.

[0121] When the cancellation signal CS has the inverted phases of the panel signals Sin1, Sin2, and Sin3 that are delayed in the display panel 100 and has an amplitude equal to the amplitude of the delayed panel signals Sin1, Sin2, and Sin3, the waveforms of the delayed panel signals Sin1, Sin2, and Sin3 are symmetric with the waveform of the cancellation signal CS. The amplitude may be voltage. In this case, the electromagnetic waves caused by the panel signals Sin1, Sin2, and Sin3 can be minimized only by a single cancellation signal line 40. The cancellation signal line 40 may include a plurality of wirings.

[0122] The voltage and phase compensator 300 includes a first inverting adder 310, a second inverting adder 320, and a coupler 330.

[0123] The first inverting adder 310 adds and inverts two or more panel signals Sin1, Sin2, and Sin3 input from the signal generator 400 to output a first inverted signal PS1. The signal generator 400 can be at least one of the timing controller 130, the level shifter 150, and the touch sensor driver 170.

[0124] The second inverting adder 320 receives feedback signals FB1, FB2, and FB3 from the feedback signal lines 44 that transmit the panel signals Sin1, Sin2, and Sin3 on the display panel 100, and receives the first inverted signal PS1 from the first inverting adder 310. The panel signals Sin1, Sin2, and Sin3 are RC-delayed due to the resistance R and capacitance C present in the transmission path of the signal lines including the display panel 100 from the signal generator 400. The feedback signals FB1, FB2, and FB3 are the panel signals in which the propagation delay of the panel signals Sin1, Sin2, and Sin3 is reflected.

[0125] The second inverting adder 320 adds and inverts the feedback signals FB1, FB2, and FB3 and the first inverted signal PS1 to output a second inverted signal PS2. When the feedback signals FB1, FB2, and FB3 are added to the first inverted signal PS1, most of them can be canceled, but due to the phase difference and voltage difference between the feedback signals FB1, FB2, and FB3 and the first inverted signal PS1, residual noise that is not canceled may remain. The second inverted signal output from the second inverting adder 320 is the inverted signal of the residual noise.

[0126] The connector 330 can combine the first inverted signal PS1 and the second inverted signal PS2 to output a cancellation signal CS. When the first inverted signal PS1 and the second inverted signal PS2 are connected to each other, the connector 330 can block the DC component of the second inverted signal PS2 and block the current flowing to the second inverting adder 320.

[0127] Figure 5A and Figure 5B are diagrams showing examples of the panel signal and the first inverted signal.

[0128] The panel signals Sin1, Sin2, and Sin3 include pulses. The pulses of the panel signals Sin1, Sin2, and Sin3 can have intervals where they overlap with each other as Figure 5A shown, or can be as Figure 5BThe ones shown do not overlap with each other. The first anti-phase signal PS1 is a signal obtained by adding and inverting the panel signals Sin1, Sin2, and Sin3. The voltage and phase compensator 300 combines the second anti-phase signal PS2, which is obtained by adding and inverting the feedback signals FB1, FB2, and FB3 in which the delays of the panel signals Sin1, Sin2, and Sin3 are reflected, with the first anti-phase signal PS1 to generate a cancellation signal CS. For example, via the second anti-adder 320, the second anti-phase signal PS2 is obtained by adding and inverting the feedback signals FB1, FB2, and FB3 with the first anti-phase signal PS1, and via the connector 330, the cancellation signal CS is generated by combining the second anti-phase signal PS2 with the first anti-phase signal PS1, but the present disclosure is not limited thereto.

[0129] The voltage and phase compensator 300 can match the voltage and phase of the cancellation signal CS and the panel signals Sin1, Sin2, and Sin3 applied to the display panel 100, regardless of whether the panel signals Sin1, Sin2, and Sin3 overlap, thereby minimizing or at least reducing the electromagnetic waves generated by the panel signals Sin1, Sin2, and Sin3. When the phases of the panel signals Sin1, Sin2, Sin3, and the cancellation signal CS applied to the display panel 100 are inverted close to 180 degrees with respect to each other, the cancellation efficiency approaches 100%, and the harmonic voltages of the panel signals Sin1, Sin2, Sin3, and the cancellation signal CS are equal to each other.

[0130] Figure 6 is a waveform diagram showing an example of delaying a panel signal at a display panel. Figure 7 is a waveform diagram showing an example of the phase and voltage asymmetry between a first anti-phase signal and a panel signal when the first anti-phase signal is applied to a display panel. Figure 8 is a waveform diagram showing an example in which the phases and voltages of a panel signal and a cancellation signal are symmetric. Figure 9 is a waveform diagram illustrating examples of residual noise and anti-phase residual noise. Figure 10 is a waveform diagram showing the cancellation signal and the panel signal observed in an experiment.

[0131] When the panel signal Sin is applied to the display panel 100, its amplitude (voltage) decreases due to the RC delay, as Figure 6 shown. This is due to the RC delay caused by the wiring resistance of the display panel 100 and the channel capacitance and resistance of the transistor 42. In Figure 6 ,"Sout" represents the panel signal Sin applied to the display panel 100 and delayed due to the RC delay.

[0132] When the first anti-phase signal PS1 is applied to the display panel 100 as a cancellation signal, as Figure 7As shown, since the delay amounts of the delayed panel signal Sout and the cancellation signal are different from each other, there are a phase difference ΔP and a voltage difference ΔV between the delayed panel signal Sout and the cancellation signal. When the panel signal Sout and the cancellation signal are asymmetric, the cancellation efficiency of the electromagnetic wave is reduced. When there is a phase difference between the first inverted signal PS1 and the panel signal Sin, the cancellation efficiency may be further reduced.

[0133] Reference Figure 8 and Figure 9 , the voltage and phase compensator 300 generates a cancellation signal CS by combining the first inverted signal PS1 obtained by adding and inverting the panel signals Sin1, Sin2, and Sin3 and the second inverted signal PS2 obtained by adding and inverting the feedback signals FB1, FB2, and FB3 input from the display panel 100 to the first inverted signal PS1. For example, via the second anti-adder 320, the second inverted signal PS2 is obtained by adding and inverting the feedback signals FB1, FB2, and FB3 to the first inverted signal PS1, and via the coupler 330, the cancellation signal CS is generated by combining the second inverted signal PS2 with the first inverted signal PS1, but the present disclosure is not limited thereto. When the feedback signals FB1, FB2, and FB3 are added to the first inverted signal PS1, uncancelled residual noise Nres is generated. The second inverted signal PS2 is the inverted signal of the residual noise Nres / Nres.

[0134] Regardless of whether the panel signals overlap and even if there is a phase difference between the panel signals and the first inverted signal PS1, the cancellation signal CS output from the voltage and phase compensator 300 always has an inverted phase with respect to the panel signals Sin1, Sin2, and Sin3 applied to the display panel 100 and has the same amplitude as the amplitudes of the panel signals Sin1, Sin2, and Sin3. This can be seen in Figure 7 and Figure 10 seen. Figure 10 shows the cancellation signal CS and the panel signal Sin observed in the experiment, as Figure 10 seen, the cancellation signal CS output from the voltage and phase compensator 300 has an inverted phase with respect to the panel signal Sin applied to the display panel 100 and has the same amplitude as the amplitude of the panel signal Sin.

[0135] Figure 11 is a circuit diagram showing a detailed exemplary embodiment of the voltage and phase compensator.

[0136] Reference Figure 11, the voltage and phase compensator 300 includes a first inverting adder 310 connected to the output terminal of the signal generator 400 and a second inverting adder 320 connected to the feedback signal line 44 of the display panel 100. And the voltage and phase compensator 300 includes a coupler 330 that connects to the output terminal of the first inverting adder 310, the output terminal of the second inverting adder 320, and the cancellation signal line 40 of the display panel 100 to apply the cancellation signal CS obtained by combining the first inverted signal PS1 and the second inverted signal PS2 to the cancellation signal line 40.

[0137] The first inverting adder 310 includes a first operational amplifier OP1, resistors R1, R2, and R3 connected to the inverting input terminal "-" of the first operational amplifier OP1, and a resistor Rb connected between the output terminal and the inverting input terminal "-" of the first operational amplifier OP1.

[0138] The driving voltage Vh is applied to the VDD terminal of the first operational amplifier OP1, and the low-potential voltage Vl is applied to the VSS terminal. The reference voltage Vp is applied to the non-inverting input terminal of the first operational amplifier OP1.

[0139] The panel signals Sin1, Sin2, and Sin3 are input to the inverting input terminal "-" of the first operational amplifier OP1 through the resistors R1, R2, and R3. The first inverting adder 310 adds and inverts the panel signals Sin1, Sin2, and Sin3 to output the first inverted signal PS1, as Figure 5A and Figure 5B shown.

[0140] When the voltage of the first panel signal Sin1 is V1, the voltage of the second panel signal Sin2 is V2, and the voltage of the third panel signal Sin3 is V3, the output voltage Vo of the first inverting adder 310 is as shown in Equation 1 below:

[0141]

[0142] The second inverting adder 320 includes a second operational amplifier OP2, resistors R1, R2, R3, and Rp connected to the inverting input terminal "-" of the second operational amplifier OP2, and a resistor Rb connected between the output terminal and the inverting input terminal "-" of the second operational amplifier OP2.

[0143] The driving voltage Vh is applied to the VDD terminal of the second operational amplifier OP2, and the low-potential voltage Vl is applied to the VSS terminal. The reference voltage Vp is applied to the non-inverting input terminal of the second operational amplifier OP2.

[0144] The feedback signals FB1, FB2, and FB3 of the panel signals received from the feedback signal lines 44 of the display panel 100 are input to the inverting input terminal "-" of the second operational amplifier OP2 through resistors R1, R2, and R3. The first inverted signal PS1 output from the first inverting adder 310 is input to the inverting input terminal "-" of the second operational amplifier OP2 through a resistor Rp. The second inverting adder 320 outputs a second inverted signal PS2 generated as a result of adding and inverting the feedback signals FB1, FB2, and FB3 and the first inverted signal PS1.

[0145] The connector 330 includes a capacitor C and a diode D connected in series between the output terminal of the first operational amplifier OP1 and the output terminal of the second operational amplifier OP2. The capacitor C is connected between the output terminal of the second operational amplifier OP2 and the diode D. The diode D includes an anode connected to the capacitor C and a cathode connected to the output terminal of the first operational amplifier OP1. The capacitor C only allows the AC component of the second inverted signal to be transmitted to the diode D, and the diode D blocks the reverse current flowing to the second operational amplifier OP2.

[0146] To improve the cancellation efficiency, the voltages of the first inverted signal PS1 and the second inverted signal PS2 should be combined at the same ratio. For this purpose, the gains of the first operational amplifier OP1 and the second operational amplifier OP2 should be matched so that their output voltage ratios are the same. For example, when the output voltage of the first operational amplifier OP1 is 1, the output voltage of the second operational amplifier OP2 can be 1, but it is not limited thereto. When the gains of the first operational amplifier OP1 and the second operational amplifier OP2 are different, the first inverted signal PS1 and the second inverted signal PS2 can be combined in a state where their phases and voltages do not exactly match.

[0147] The gains of the operational amplifiers OP1 and OP2 can be determined by the resistors R1, R2, R3, Rp, and Rb. For example, the resistors can be R1 = R2 = R3 = Rp = 3KΩ and Rb = 1KΩ, but it is not limited thereto. Vh and Vl can be Vh = 16V and Vl = -9V, but it is not limited thereto. Vp can be a voltage between 3V and 7V, but it is not limited thereto.

[0148] Figure 11 The shown voltage and phase compensation circuit can combine the first inverted signal PS1 and the second inverted signal PS2 to output a cancellation signal CS, where the second inverted signal PS2 compensates the voltage and phase of the first inverted signal PS1 to one within the driving voltage requirements of the operational amplifiers OP1 and OP2 and the display panel 100 through the gain matching of the inverting adders 310 and 320.

[0149] Figure 12 and Figure 13This is a diagram showing an example of a TX line. Figure 14 This is a waveform diagram showing an example of a drive signal applied to the TX line.

[0150] Referring to Figures 12 to 14 , the touch screen includes a plurality of TX lines TX1 to TXn that supply TX signals to the touch sensors, RX lines RX1 to RXm that intersect the TX lines TX1 to TXn, and a plurality of touch sensors Cts connected to the TX lines TX1 to TXn and the RX lines RX1 to RXm. The touch sensors Cts are charged depending on the drive voltage of the TX signals applied to the TX lines TX1 to TXn. The voltage of the touch sensors Cts can be received by the touch sensor driver 170 through the RX lines RX1 to RXm.

[0151] The touch sensor driver 170 sequentially applies TX signals including a plurality of pulses to the TX lines TX1 to TXn. For example, after applying a first TX signal to the first TX line TX1, a second TX signal is applied to the second TX line TX2. After applying the (n - 1)th TX signal to the (n - 1)th TX line TX(n - 1), the nth TX signal is applied to the nth TX line TXn, where n is an integer.

[0152] Since the TX lines TX1 to TXn have different lengths and different loop sizes, the amount of electromagnetic wave emission can be different. As a result, it is difficult to generate an anti-phase signal that accurately reverses 180 degrees for each of the TX lines 191 to 19n because the deviation of the propagation delay of the TX signals applied to the TX lines TX1 to TXn is large.

[0153] The touch sensor driver 170 or the voltage and phase compensator 300 groups the TX signals applied to the TX lines TX1 to TXn and generates a plurality of TX group signals. The voltage and phase compensator 300 adds and inverts the TX group signals and appropriately adjusts the gain of the anti - adder for each group to output a cancellation signal CS in which the phase and voltage of the TX signals applied to the TX lines match. Due to the difference in the propagation delay of the TX signals applied to the TX lines, there may be a difference in the TX voltage applied to the TX lines. To improve the electromagnetic wave cancellation efficiency of the TX signals applied to the TX lines, the gain of the anti - adder can be adjusted for each group so that the voltage of the cancellation signal CS can vary discretely, linearly, and continuously for each group. For example, different cancellation signals CS are applied to different TX group signals, but it is not limited to this.

[0154] Figure 15 This is a diagram showing an example of Figure 14 a method of grouping the drive signals shown in

[0155] Referring to Figure 14 andFigure 15 The TX signals TS1 to TSn sequentially applied to the TX lines TX1 to TXn can be grouped into I TX line units (where I is a natural number greater than or equal to 2). Each of the TX signals TS1 to TSn can include a plurality of pulses.

[0156] The touch sensor driver 170 or the voltage and phase compensator 300 can group the I TX signals TS1 to TSn sequentially applied to the I TX lines TX1 to TXn using OR logic to output one TX group signal.

[0157] In an example where the number of TX lines TX1 to TXn is 24 and I = 6, the TX signals sequentially applied to the six TX lines can be grouped into one TX group signal. The touch sensor driver 170 sequentially outputs the first TX signal TS1 to the sixth TX signal TS6, and the first TX signal TS1 to the sixth TX signal TS6 are combined to output the first TX group signal TXG1. Subsequently, the touch sensor driver 170 sequentially outputs the seventh TX signal TS7 to the twelfth TX signal TS12, and the seventh TX signal TS7 to the twelfth TX signal TS12 are combined to output the second TX group signal TXG2. Subsequently, the touch sensor driver 170 sequentially outputs the thirteenth TX signal TS13 to the eighteenth TX signal TS18, and the thirteenth TX signal TS13 to the eighteenth TX signal TS18 are combined to output the third TX group signal TXG3. Subsequently, the touch sensor driver 170 sequentially outputs the nineteenth TX signal TS19 to the twenty-fourth TX signal TS24, and the nineteenth TX signal TS19 to the twenty-fourth TX signal TS24 are combined to output the fourth TX group signal TXG4. However, the embodiments of the present disclosure are not limited thereto. For example, in an example where the number of TX lines TX1 to TXn is 24 and I = 8, the TX signals sequentially applied to the eight TX lines can be grouped into one TX group signal. The touch sensor driver 170 sequentially outputs the first TX signal TS1 to the eighth TX signal TS8, and the first TX signal TS1 to the eighth TX signal TS8 are combined to output the first TX group signal TXG1. Subsequently, the touch sensor driver 170 sequentially outputs the ninth TX signal TS9 to the sixteenth TX signal TS16, and the ninth TX signal TS9 to the sixteenth TX signal TS16 are combined to output the second TX group signal TXG2. Subsequently, the touch sensor driver 170 sequentially outputs the seventeenth TX signal TS17 to the twenty-fourth TX signal TS24, and the seventeenth TX signal TS17 to the twenty-fourth TX signal TS24 are combined to output the third TX group signal TXG3, and is not limited thereto.

[0158] A voltage and phase compensator according to an exemplary embodiment of the present disclosure may include an inverting adder circuit that adds and inverts drive signals from a touch sensor driver, and a coupler connected between the inverting adder circuit and a cancellation signal line.

[0159] Figure 16 is shown in detail Figure 15 FIG. is a circuit diagram of an example of a voltage and phase compensator into which the TX group signals shown are input. In Figure 16 FIG., components substantially the same as those of the above exemplary embodiment are denoted by the same reference numerals, and their detailed descriptions are omitted. In the present exemplary embodiment, the TX lines of a touch screen having a multi-channel transmission structure may be grouped to control the voltage of each TX group having a relatively large asymmetry in electromagnetic wave emission amount, respectively, thereby increasing the cancellation effect and freely controlling the electromagnetic wave emission amount within the voltage used by the display device. Figure 17 FIG. is a waveform diagram of an example of a cancellation signal having a voltage difference for each TX group.

[0160] Referring to Figure 16 FIG., the touch sensor driver 170 outputs TX signals TS1 to TSn that are sequentially shifted and TX group signals TXG1 to TXG4 in which the TX signals TS1 to TSn are grouped.

[0161] The level shifter 172 may be connected to the output terminals of the touch sensor driver 170. The voltages of the output signals TS1 to TSn and TXG1 to TXG4 output from the touch sensor driver 170 may be converted into larger voltages by the level shifter 172.

[0162] The touch sensor driver 170 provides a first TX group signal TXG1 to the voltage and phase compensator 300, while the first TX signal TS1 to the sixth TX signal TS6 are sequentially applied to the first TX line TX1 to the sixth TX line TX6 of the display panel 100 through the level shifter 172. Subsequently, the touch sensor driver 170 provides a second TX group signal TXG2 to the voltage and phase compensator 300, while the seventh TX signal TS7 to the twelfth TX signal TS12 are sequentially applied to the seventh TX line TX7 to the twelfth TX line TX12 of the display panel 100 through the level shifter 172. Subsequently, the touch sensor driver 170 provides a third TX group signal TXG3 to the voltage and phase compensator 300, while the thirteenth TX signal TS13 to the eighteenth TX signal TS18 are sequentially applied to the thirteenth TX line TX13 to the eighteenth TX line TX18 of the display panel 100 through the level shifter 172. Subsequently, the touch sensor driver 170 provides a fourth TX group signal TXG4 to the voltage and phase compensator 300, while the nineteenth TX signal TS19 to the twenty-fourth TX signal TS24 are sequentially applied to the nineteenth TX line TX19 to the twenty-fourth TX line TX24 of the display panel 100 through the level shifter 172. However, the embodiments of the present disclosure are not limited thereto.

[0163] For example, in an example where the number of TX lines TX1 to TXn is 24 and I = 8, the touch sensor driver 170 provides a first TX group signal TXG1 to the voltage and phase compensator 300, while the first TX signal TS1 to the eighth TX signal TS8 are sequentially applied to the first TX line TX1 to the eighth TX line TX8 of the display panel 100 through the level shifter 172. Subsequently, the touch sensor driver 170 provides a second TX group signal TXG2 to the voltage and phase compensator 300, while the ninth TX signal TS9 to the sixteenth TX signal TS16 are sequentially applied to the ninth TX line TX9 to the sixteenth TX line TX16 of the display panel 100 through the level shifter 172. Subsequently, the touch sensor driver 170 provides a third TX group signal TXG3 to the voltage and phase compensator 300, while the seventeenth TX signal TS17 to the twenty-fourth TX signal TS24 are sequentially applied to the seventeenth TX line TX17 to the twenty-fourth TX line TX24 of the display panel 100 through the level shifter 172.

[0164] The voltage and phase compensator 300 may be connected between the level shifter 172 and the display panel 100. The voltage and phase compensator 300 includes a first inverting adder 310, a second inverting adder 320, and a coupler 330.

[0165] The first inverting adder 310 includes a first operational amplifier OP1, input resistors R1 to R4 connected to the inverting input terminal "-" of the first operational amplifier OP1, and a feedback resistor Rb connected between the output terminal and the inverting input terminal "-" of the first operational amplifier OP1.

[0166] The TX group signals TXG1 to TXG2 grouped by logical OR can be sequentially input to the inverting input terminals "-" of the first inverting adder 310 and the second inverting adder 320. For example, after the first TX group signal TXG1 is input to the first inverting adder 310 and the second inverting adder 320, the second TX group signal TXG2 can be input to the first inverting adder 310 and the second inverting adder 320.

[0167] The TX group signals TXG1 to TXG4 are input to the inverting input terminal "-" of the first operational amplifier OP1 through the resistors R1 to R4. The first inverting adder 310 adds and inverts the TX group signals TXG1 to TXG4 to output a first inverted signal PS1. The first inverted signal PS1 can cancel most of the electromagnetic waves emitted from the TX lines TX1 to TXn.

[0168] The second inverting adder 320 includes a second operational amplifier OP2, input resistors R1 to R4 and Rp connected to the inverting input terminal "-" of the second operational amplifier OP2, and a feedback resistor Rb connected between the output terminal and the inverting input terminal "-" of the second operational amplifier OP2. The gains of the first operational amplifier OP1 and the second operational amplifier OP2 can be matched so that the output voltage ratios are the same.

[0169] The TX group signals TXG1 to TXG4 and the first inverted signal PS1 are input to the inverting input terminal "-" of the second operational amplifier OP2 through the resistors R1, R2, R3, and R4. The second inverting adder 320 adds and inverts the TX group signals TXG1 to TXG4 and the first inverted signal PS1 to output a second inverted signal PS2. The second inverted signal PS2 can cancel the residual noise not canceled by the first inverted signal PS1.

[0170] A capacitor Cp can be connected in series between the TX group signal output terminal of the level shifter 172 and the input resistors R1, R2, R3, and R4 of the second operational amplifier OP2. The capacitor Cp prevents noise or ripple from being input to the second operational amplifier OP2. A resistor can be connected together with the capacitor Cp or, in the absence of the capacitor, the resistor can be connected between the TX group signal output terminal of the level shifter 172 and the input resistors R1, R2, R3, and R4 of the second operational amplifier OP2. The resistor and / or the capacitor Cp for suppressing noise can also be applied to other exemplary embodiments.

[0171] The connector 330 combines the first antiphase signal PS1 and the second antiphase signal PS2 to output a cancellation signal CS. The cancellation signal CS is applied to the cancellation signal line 40 of the display panel 100 to cancel the electromagnetic wave emitted from the TX line without residual noise. The connector 330 may include a capacitor C and a diode D connected in series between the output terminal of the first operational amplifier OP1 and the output terminal of the second operational amplifier OP2.

[0172] The voltage of the cancellation signal CS can be set differently for each TX group signal to match the voltages of the TX signals TS1 to TSn applied to the TX lines TX1 to TXn. By using the resistance values for setting the gains of the inverting adders 310 and 320, the voltage of the cancellation signal CS can be different for each TX group. At least two of the resistance values of the input resistors R1, R2, R3, and R4 of the first operational amplifier OP1 may be different from each other. For example, the resistance values of all the input resistors R1, R2, R3, and R4 of the first operational amplifier OP1 may be different, but not limited thereto. At least two of the resistance values of the input resistors R1, R2, R3, R4, and Rp of the second operational amplifier OP2 may be different from each other. For example, the resistance values of all the input resistors R1, R2, R3, R4, and Rp of the second operational amplifier OP2 may be different, but not limited thereto.

[0173] When the resistance values of the resistors R1, R2, R3, and R4 to which the TX group signals TXG1 to TXG4 are applied are R1 < R2 < R3 < R4, the voltage of the cancellation signal CS can be controlled to be TXG1 > TXG2 > TXG3 > TXG4, as Figure 17 shown. The voltage and phase compensator 300 can appropriately adjust the gains of the inverting adders 310 and 320 for each TX group, and output the voltage of the cancellation signal CS as a voltage having a difference in discrete, linear, and continuous voltage levels for each TX group. For example, the voltage of the cancellation signal CS can be freely controlled by voltage differences such as 0V, 0.1V…8.5V, 16.2V, 17V, 18V, etc. for each TX group.

[0174] In addition, the voltage and phase compensator 300 can group the TX signals TS1 to TSn output from the touch sensor driver 170 or the level shifter 172 by using the same method as in Figure 15 or Figure 18 . In this case, the touch sensor driver 170 does not have to generate TX group signals.

[0175] Figure 18 and Figure 19Shows an exemplary embodiment in which the voltage and phase compensator 300 uses only a single inverting adder to output a cancellation signal. This exemplary embodiment can provide a sufficient cancellation effect by compensating the phase of the inverted signal.

[0176] Figure 18 Is a waveform diagram showing another example of the method of grouping drive signals shown in Figure 14

[0177] Referring to Figure 18 , the touch sensor driver 170 or the voltage and phase compensator 300 uses OR logic to group the TX signals TS1 to TSn applied to all TX lines TX1 to TXn into one signal and outputs a single group signal TXG. Moreover, the touch sensor driver 170 or the voltage and phase compensator 300 uses NOR logic to output an inverted group signal / TXG. The phases of the single group signal TXG and the inverted group signal / TXG are in phase with each other.

[0178] Figure 19 Is a detailed circuit diagram showing an example of a voltage and phase compensator into which a single group signal and an inverted group signal are input as shown in Figure 18

[0179] Referring to Figure 19 , the touch sensor driver 170 outputs sequentially shifted TX signals TS1 to TSn, a single group signal TXG, and an inverted group signal / TXG. The voltages of the output signals TS1 to TSn, TXG, and / TXG output from the touch sensor driver 170 can be converted into larger voltages by the level shifter 172.

[0180] The voltage and phase compensator 300 includes an inverting adder 340 and a coupler 350.

[0181] The inverting adder 340 includes an operational amplifier OP, resistors R1 and Rp connected to the inverting input terminal "-" of the operational amplifier OP, and a resistor Rb connected between the output terminal and the inverting input terminal "-" of the operational amplifier OP.

[0182] The single group signal TXG and the inverted group signal / TXG are input to the inverting input terminal "-" of the operational amplifier OP through the resistors R1 and Rp. The inverting adder 340 adds and inverts the single group signal TXG and the inverted group signal / TXG and outputs them.

[0183] When the voltage of the group signal TXG is V1 and the voltage of the inverted group signal / TXG is V2, the output voltage Vo of the inverting adder 340 is as shown in Equation 2 below:

[0184]

[0185] The connector 350 combines the output signal of the inverting adder 340 with the inverted group signal / TXG to output a cancellation signal CS. The cancellation signal CS is applied to the cancellation signal line 40 of the display panel 100. The cancellation signal CS is inverted 180 degrees in phase with respect to the TX signals TS1 to TSn applied to the TX lines TX1 to TXn to cancel the electromagnetic waves emitted from the TX lines TX1 to TXn. The connector 350 may include a capacitor C and a diode D, which are connected in series between the output terminal of the operational amplifier OP and the node to which the inverted group signal / TXG is applied.

[0186] Figure 20 and Figure 21 Shows the experimental results of comparing the voltage and phase compensators according to the comparative example and the exemplary embodiments according to the present disclosure in order to verify the EMI improvement effect of the present disclosure. Figure 20 Is a diagram showing the experimental results of the EMI improvement effect of a comparative example having a phase difference between the panel signal and the first inverted signal. Figure 21 Is a diagram showing the experimental results of the EMI improvement effect of the voltage and phase compensation circuit according to the exemplary embodiments of the present disclosure.

[0187] The comparative example is a sample having a phase difference of 100 ns between the panel signal and the first inverted signal when the first inverted signal is applied to the cancellation signal line of the display panel without the second inverted signal. In the comparative example, the maximum EMI was measured to be approximately 60 [dBμV] in Figure 20 . In contrast, the maximum EMI measured in the present disclosure was measured to be approximately 50 [dBμV] in Figure 21 . Therefore, when compared with the comparative example, the present disclosure provides an EMI improvement effect of reducing by approximately 10 [dB].

[0188] According to one or more exemplary embodiments of the present disclosure, the display device may be applied to a mobile device, a video phone, a smart watch, a watch phone, a wearable device, a foldable device, a rollable device, a bendable device, a flexible device, a curved device, a sliding device, a variable device, an electronic notepad, an e-book, a portable multimedia player (PMP), a personal digital assistant (PDA), an MP3 player, a mobile medical device, a desktop PC, a laptop PC, a netbook computer, a workstation, a navigation, a vehicle navigation, a vehicle display device, a vehicle device, a theater device, a theater display device, a television, a wallpaper device, a sign device, a game device, a laptop computer, a monitor, a camera, a video camera, and household appliances, etc. Additionally, the display device according to one or more exemplary embodiments of the present disclosure may be applied to an organic light emitting display device or an inorganic light emitting display device.

[0189] The objects to be achieved by the present disclosure described above, the devices for achieving these objects, and the effects of the present disclosure do not specify the basic features of the claims. Therefore, the scope of the claims is not limited to the disclosure of the present disclosure.

[0190] Although example embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the example embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above example embodiments are illustrative in all respects and do not limit the present disclosure.

[0191] Cross - reference to related applications

[0192] This application claims the benefit of priority of Korean Patent Application No. 10 - 2023 - 0167649, filed on November 28, 2023, the entire contents of which are hereby incorporated by reference herein for all purposes.

Claims

1. A voltage and phase compensation circuit, the voltage and phase compensation circuit comprising: a first inverting adder configured to add and invert a plurality of panel signals to output a first inverted signal; a second inverting adder configured to add and invert a feedback signal obtained from the delayed panel signal to the first inverted signal to output a second inverted signal; as well as A coupler is configured to combine the first inverted signal and the second inverted signal.

2. The voltage and phase compensation circuit according to claim 1, wherein: A signal combining the first inverted signal and the second inverted signal has an inverted phase of the delayed panel signal and has a voltage equal to that of the delayed panel signal.

3. The voltage and phase compensation circuit according to claim 1, wherein: The first inverting adder comprises: A first operational amplifier, the first operational amplifier comprising: a first inverting input terminal connected to a plurality of first input resistors to which the plurality of panel signals are applied; a first non-inverting input terminal to which a reference voltage is applied; and a first output terminal connected to the first inverting input terminal, a first resistor interposed between the first output terminal and the first inverting input terminal, the first output terminal outputting the first inverting signal, and Wherein, the second inverting adder comprises: A second operational amplifier, the second operational amplifier comprising: a second inverting input terminal connected to a plurality of second input resistors to which the feedback signal and the first inverted signal are applied; a second non-inverting input terminal to which the reference voltage is applied; and A second output terminal is connected to the second inverting input terminal, a second resistor is interposed between the second output terminal and the second inverting input terminal, and the second output terminal outputs the second inverted signal.

4. The voltage and phase compensation circuit according to claim 3, wherein: The plurality of panel signals include: A first panel signal, a second panel signal and a third panel signal having different phases, Wherein, the feedback signal includes: a first feedback signal obtained from a delay of the first panel signal; a second feedback signal obtained from a delay of the second panel signal; and a third feedback signal obtained from the delay of the third panel signal, wherein the first panel signal, the second panel signal, and the third panel signal are input to the first inverting input terminal of the first operational amplifier through the plurality of first input resistors of the first operational amplifier, and The first feedback signal, the second feedback signal, the third feedback signal and the first inverted signal are input to the second inverting input terminal of the second inverting adder through the plurality of second input resistors of the second operational amplifier.

5. The voltage and phase compensation circuit according to claim 3, wherein: An output voltage ratio of the first operational amplifier is the same as an output voltage ratio of the second operational amplifier.

6. The voltage and phase compensation circuit according to claim 3, wherein: The connector comprises: A capacitor and a diode are connected in series between the first output terminal of the first operational amplifier and the second output terminal of the second operational amplifier.

7. A display device, comprising: A display panel, on which wirings to which a plurality of panel signals are applied, feedback lines respectively connected to the wirings, a plurality of pixels, and a cancellation signal line are located; a display panel driving circuit configured to write pixel data of an input image into the plurality of pixels; a signal generator configured to output the plurality of panel signals; as well as a voltage and phase compensator configured to supply a cancellation signal to the cancellation signal line, Wherein, the voltage and phase compensator comprises: a first inverting adder configured to add and invert the plurality of panel signals to output a first inverted signal; a second inverting adder configured to add and invert the feedback signal received from the feedback line to the first inverted signal to output a second inverted signal; and A coupler is configured to combine the first inverted signal and the second inverted signal to output the cancellation signal.

8. The display device according to claim 7, wherein: The display panel further includes: a plurality of data lines to which data voltages are applied; and A plurality of strobe lines to which strobe signals are applied, Wherein, the display panel driving circuit further includes: a data driver configured to output the data voltage; a demultiplexer connected between the plurality of data lines and an output terminal of the data driver; and a gate driver configured to output the gate signal, and The plurality of panel signals include at least one of a control signal configured to control a transistor of the demultiplexer or a clock input to the gate driver.

9. The display device according to claim 8, wherein: The display panel further includes a TX line connected to the plurality of touch sensors, The display panel driving circuit further includes a touch sensor driver, wherein the touch sensor driver is configured to supply a driving signal to the TX line, and Wherein, the plurality of panel signals include the driving signal.

10. A display device, comprising: A display panel, wherein a TX line connected to a plurality of touch sensors, a plurality of pixels and a cancellation signal line are located on the display panel; a touch sensor driver configured to sequentially supply a driving signal to the TX line; and a voltage and phase compensator configured to supply a cancellation signal to the cancellation signal line, Wherein, the voltage and phase compensator comprises: an inverting adder circuit configured to add and invert drive signals from the touch sensor driver; and A connector is connected between the inverting adder circuit and the cancellation signal line.

11. The display device according to claim 10, wherein: The inverting adder circuit comprises: a first inverting adder configured to add and invert two or more group signals in which a plurality of driving signals are grouped to output a first inverted signal; and A second inverting adder configured to add and invert the two or more group signals and the first inverted signal to output a second inverted signal.

12. The display device according to claim 11, wherein: The coupler is configured to combine the first inverted signal and the second inverted signal to output one of the cancellation signals.

13. The display device according to claim 11, wherein: Each of the two or more group signals includes two or more of the drive signals grouped by a logical OR, The two or more group signals are sequentially input to each of the first inverting adder and the second inverting adder, and Each of the drive signals includes a plurality of pulses.

14. The display device according to claim 11, wherein: The first inverting adder comprises: A first operational amplifier, the first operational amplifier comprising: a first inverting input terminal electrically connected to a plurality of first input resistors to which the two or more group signals are applied; a first non-inverting input terminal to which a reference voltage is applied; and a first output terminal electrically connected to the first inverting input terminal to output the first inverted signal, a first resistor being interposed between the first output terminal and the first inverting input terminal, and Wherein, the second inverting adder comprises: A second operational amplifier, the second operational amplifier comprising: a second inverting input terminal connected to a plurality of second input resistors to which the two or more group signals and the first inverted signal are applied; a second non-inverting input terminal to which the reference voltage is applied; and A second output terminal is connected to the second inverting input terminal to output the second inverted signal, and a second resistor is interposed between the second output terminal and the second inverting input terminal.

15. The display device according to claim 14, wherein: An output voltage ratio of the first operational amplifier is the same as an output voltage ratio of the second operational amplifier.

16. The display device according to claim 15, wherein: The resistance values ​​of at least two of the plurality of first input resistors of the first operational amplifier are different from each other, and Resistance values ​​of at least two of the plurality of second input resistors of the second operational amplifier are different from each other.

17. The display device according to claim 14, wherein: The connector comprises: A capacitor and a diode are connected in series between the first output terminal of the first operational amplifier and the second output terminal of the second operational amplifier.

18. The display device according to claim 10, wherein: The inverting adder circuit comprises: an inverting adder configured to add and invert a group signal in which the driving signals applied to the TX line are grouped and an inverted signal in which the group signal is inverted; and A coupler configured to combine the output signal of the inverting adder and the inverted signal to output one of the cancellation signals.

19. The display device according to claim 18, wherein: The inverting adder circuit comprises: An operational amplifier including an inverting input terminal connected to a plurality of input resistors to which the group signal and the inverted signal are applied, a non-inverting input terminal to which a reference voltage is applied, and an output terminal connected to the inverting input terminal, with a resistor interposed between the output terminal and the inverting input terminal.

20. The display device according to claim 19, wherein: The connector comprises: A capacitor and a diode are connected in series between the output terminal of the operational amplifier and a node to which the inverted signal is applied.

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