Display device

Abstract

The present application provides a display device, which may include: a display panel including a first display area and a second display area; a main panel driver configured to generate a common logic signal and drive the first display area based on the common logic signal; and a first slave panel driver configured to drive the second display area based on the common logic signal received from the master panel driver. The first slave panel driver does not generate the common logic signal.

Description

Technical Field

[0001] The inventive concept relates to a display device, and more particularly, to a display device operating at low power consumption. Background Art

[0002] Generally, a display device includes a display panel and a panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The panel driver includes a gate driver that provides a gate signal to the gate lines, a data driver that provides a data voltage to the data lines, an emission driver that provides an emission signal to the emission lines, and a driving controller that controls the gate driver, the data driver, and the emission driver.

[0003] Generally, when a display device includes a plurality of panel drivers, each of the plurality of driving controllers generates an operation signal for driving the display panel, which may increase power consumption. Summary of the Invention

[0004] Some embodiments provide a display device in which power consumption is reduced by causing one panel driver to generate a common logic signal for performing a common operation and applying the common logic signal to another panel driver when performing the common operation.

[0005] According to an embodiment, a display device may include: a display panel including a first display area and a second display area; and a main panel driver and a first slave panel driver configured to drive the first display area and the second display area respectively based on a common logic signal generated by the main panel driver. The first slave panel driver is configured to receive the common logic signal from the main panel driver without generating the common logic signal.

[0006] In an embodiment, the main panel driver may include a main driving controller. The first slave panel driver may include a first slave driving controller. The main driving controller may generate the common logic signal and output the common logic signal to the first slave driving controller.

[0007] In an embodiment, the main panel driver may include a main driving controller. The first slave panel driver may include a first slave driving controller. The main driving controller may include a first main driving circuit configured to output a signal for performing a first driving operation. The first slave driving controller may include a first-first slave driving circuit configured to output a signal for performing a first driving operation. The common logic signal may be a signal for performing the first driving operation.

[0008] In an embodiment, the first main driving circuit may include: a first-first main detailed operation logic circuit configured to output a signal for performing a first-first detailed operation; and a first-second main detailed operation logic circuit configured to output a signal for performing a first-second detailed operation. The first-first slave driving circuit may include: a first-first-first slave detailed operation logic circuit configured to output a signal for performing a first-first detailed operation; and a first-first-second slave detailed operation logic circuit configured to output a signal for performing a first-second detailed operation. The common logic signal may be generated by the first-first main detailed operation logic circuit. The first slave panel driver may perform the first-first detailed operation based on the common logic signal.

[0009] In an embodiment, the common logic signal may be applied to the first slave driving controller, and the first-first-first slave detailed operation logic circuit may remain inactive.

[0010] In an embodiment, the main driving controller may further include a second main driving circuit that causes the main panel driver to perform a second driving operation different from the first driving operation. The first slave driving controller may further include a first-second slave driving circuit that causes the first slave panel driver to perform the second driving operation. The common logic signal may include a first common logic signal and a second common logic signal. The first common logic signal may be a signal for performing the first driving operation, and the second common logic signal may be a signal for performing the second driving operation.

[0011] In an embodiment, the second main driving circuit may further include: a second-first main detailed operation logic circuit configured to output a signal for performing a second-first detailed operation; and a second-second main detailed operation logic circuit configured to output a signal for performing a second-second detailed operation. The first-second slave driving circuit may include: a first-second-first slave detailed operation logic circuit configured to output a signal for performing a second-first detailed operation; and a first-second-second slave detailed operation logic circuit configured to output a signal for performing a second-second detailed operation. The second common logic signal may be generated by the second-first main detailed operation logic circuit. The first slave panel driver may perform the second-first detailed operation based on the second common logic signal.

[0012] In an embodiment, the second common logic signal may be applied to the first slave driving controller, and the first-second-first slave detailed operation logic circuit may remain inactive.

[0013] In an embodiment, the common logic signal may be applied to the first slave panel driver during a blank period of the first slave panel driver.

[0014] In an embodiment, the first display area and the second display area may emit light at different driving frequencies.

[0015] In an embodiment, the display device may further include: a third display area in the display panel; and a second slave panel driver configured to drive the third display area based on a common logic signal. The second slave panel driver may receive the common logic signal from the main panel driver without generating the common logic signal.

[0016] In an embodiment, the common logic signal may include a first slave common logic signal and a second slave common logic signal. The first slave common logic signal may be applied to the first slave panel driver, and the second slave common logic signal may be applied to the second slave panel driver.

[0017] In an embodiment, the main panel driver may include a main drive controller. The first slave panel driver may include a first slave drive controller. The second slave panel driver may include a second slave drive controller. The main drive controller may include a first main drive circuit configured to output a signal for performing a first driving operation. The first slave drive controller may include a first-first slave drive circuit configured to output a signal for performing a first driving operation. The second slave drive controller may include a second-first slave drive circuit configured to output a signal for performing a first driving operation. The common logic signal may be a signal for performing a first driving operation.

[0018] In an embodiment, the first main drive circuit may include: a first-first main detailed arithmetic logic circuit configured to output a signal for performing a first-first detailed operation; and a first-second main detailed arithmetic logic circuit configured to output a signal for performing a first-second detailed operation. The first-first slave drive circuit may include: a first-first-first slave detailed arithmetic logic circuit configured to output a signal for performing a first-first detailed operation; and a first-first-second slave detailed arithmetic logic circuit configured to output a signal for performing a first-second detailed operation. The second-first slave drive circuit may include: a second-first-first slave detailed arithmetic logic circuit configured to output a signal for performing a first-first detailed operation; and a second-first-second slave detailed arithmetic logic circuit configured to output a signal for performing a first-second detailed operation. The common logic signal may be generated by the first-first main detailed arithmetic logic circuit. The first slave panel driver may perform a first-first detailed operation based on the common logic signal, and the second slave panel driver may perform a first-first detailed operation based on the common logic signal.

[0019] According to an embodiment, a display device may include: a display panel including a first display area and a second display area; a main panel driver including a common logic circuit configured to generate a common logic signal and a main detailed arithmetic logic circuit configured to generate a main detailed logic signal, and configured to drive the first display area based on the common logic signal and the main detailed logic signal; and a slave panel driver including a first slave detailed arithmetic logic circuit configured to generate a first slave detailed logic signal, and configured to drive the second display area based on the common logic signal and the first slave detailed logic signal.

[0020] In an embodiment, the common logic signal may control the main panel driver and the first slave panel driver to perform a common operation.

[0021] In an embodiment, the common logic signal may be applied to the first slave panel driver during a blank period of the first slave panel driver.

[0022] In an embodiment, the display device may further include a second slave panel driver configured to drive a third display area based on the common logic signal and a second slave detailed logic signal, and the second slave panel driver includes a second slave detailed arithmetic logic circuit configured to generate the second slave detailed logic signal. The display panel may further include a third display area.

[0023] In an embodiment, the common logic signal may include a first slave common logic signal and a second slave common logic signal. The first slave common logic signal may control the main panel driver and the first slave panel driver to perform a common operation. The second slave common logic signal may control the main panel driver and the second slave panel driver to perform a common operation.

[0024] In an embodiment, the second slave common logic signal may be applied to the first slave panel driver during a blank period of the first slave panel driver. The second slave common logic signal may be applied to the second slave panel driver during a blank period of the second slave panel driver.

[0025] As described above, in a display device according to an embodiment, the display device may include a main panel driver and a slave panel driver. When the main panel driver and the slave panel driver perform a common operation, the main panel driver may generate a common logic signal. The common logic signal may be applied to the slave panel driver. The slave panel driver may not generate a common logic signal for performing the common operation. Accordingly, power consumption of the display device may be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Exemplary, non-limiting embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0027] Figure 1is a block diagram showing a display device according to an embodiment of the inventive concept.

[0028] Figure 2 is a diagram showing Figure 1 the first display area and the main panel driver of the display device.

[0029] Figure 3 is a block diagram showing the second display area and the first slave panel driver.

[0030] Figure 4 is a diagram showing the main drive controller included in Figure 1 the main panel driver and the first slave drive controller included in Figure 1 the first slave panel driver.

[0031] Figure 5 is a diagram showing the drive circuit included in Figure 4 the main drive controller and the drive circuit included in Figure 4 the first slave drive controller.

[0032] Figure 6 is a diagram showing the main detailed arithmetic logic circuit included in Figure 5 the main drive circuit and the slave detailed arithmetic logic circuit included in Figure 5 the first slave drive circuit.

[0033] Figure 7 is a diagram showing a plurality of common logic circuits and a plurality of main detailed logic circuits included in Figure 6 the main drive circuit, and a plurality of common logic circuits and a plurality of slave detailed arithmetic logic circuits included in Figure 6 the first slave drive circuit.

[0034] Figure 8 is a diagram showing a plurality of common logic circuits and a plurality of main detailed logic circuits included in Figure 6 the main drive circuit, and a plurality of common logic circuits and a plurality of slave detailed arithmetic logic circuits included in Figure 6 the first slave drive circuit.

[0035] Figure 9 is a diagram showing an example of a third display area and a second slave panel driver included in Figure 1 the display device.

[0036] Figure 10 is a diagram showing an example of a third display area and a second slave panel driver included in Figure 1 the display device.

[0037] Figure 11is a block diagram showing an electronic device according to an embodiment of the inventive concept.

[0038] Figure 12 is a diagram showing an example in which Figure 11 the electronic device is implemented as a smartphone. DETAILED DESCRIPTION

[0039] Hereinafter, the inventive concept will be described in detail with reference to the accompanying drawings.

[0040] Figure 1 is a block diagram showing a display device according to an embodiment of the inventive concept.

[0041] Referring to Figure 1 , the display device includes a display panel 100 and a panel driver 110. The display panel 100 may include a first display area AA1 and a second display area AA2. The panel driver 110 may include a main panel driver 110A and a first sub-panel driver 110B. The main panel driver 110A may drive the first display area AA1. The first sub-panel driver 110B may drive the second display area AA2. However, the inventive concept is not limited to the display areas driven by the main panel driver 110A and the first sub-panel driver 110B. For example, the main panel driver 110A may drive the second display area AA2. For example, the first sub-panel driver 110B may drive the first display area AA1. For example, the display panel 100 may be a liquid crystal display (LCD), an organic light emitting diode (OLED) display panel, or a quantum dot (QD) display panel, but the inventive concept is not limited thereto.

[0042] In an embodiment, the display panel 100 may include a display area on which an image is displayed and a peripheral area adjacent to the display area. The display area may include a first display area AA1 and a second display area AA2. In an embodiment, the first display area AA1 and the second display area AA2 may emit light at different driving frequencies.

[0043] In the present embodiment, the main panel driver 110A may output a common logic signal LOGS to the first sub-panel driver 110B. The common logic signal LOGS may be a signal for driving the second display area AA2. The common logic signal LOGS may be generated by the main panel driver 110A. The first sub-panel driver 110B may not generate the common logic signal LOGS.

[0044] Figure 2 is a block diagram showing Figure 1 the first display area AA1 of the display device and the main panel driver 110A.

[0045] Referring to Figure 1 andFigure 2 In an embodiment, the main panel driver 110A may include a gate driver 300, a data driver 500, a transmit driver 600, and a main drive controller 200A. Among them, the gate driver 300 is configured to provide gate signals to the pixels PX. The data driver 500 is connected to the pixels PX through data lines DL. The transmit driver 600 is connected to the pixels PX through transmit lines EL. The main drive controller 200A is configured to control the gate driver 300, the data driver 500, and the transmit driver 600. In an embodiment, the main panel driver 110A may further include a sensing driver 700. The sensing driver 700 may be connected to the pixels PX through sensing lines SL.

[0046] The display panel 100 may include data lines DL and pixels PX connected to the data lines DL. In addition, the display panel 100 may further include gate lines GL for providing gate signals to the pixels PX.

[0047] The display device may include a first display area AA1, a main drive controller 200A, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, a transmit driver 600, and a sensing driver 700. In an embodiment, the main drive controller 200A and the data driver 500 may be implemented as a single integrated circuit.

[0048] In an embodiment, the gate driver 300 may be integrated in the peripheral area of the display panel 100. In an embodiment, the gate driver 300 may be mounted in the peripheral area of the display panel 100.

[0049] The first display area AA1 may include gate lines GL, data lines DL, transmit lines EL, and pixels PX electrically connected to the gate lines GL, data lines DL, and transmit lines EL. The gate lines GL and the data lines DL may extend in directions intersecting each other.

[0050] The main drive controller 200A may receive input image data IMG and input control signals CONT from a main processor (e.g., an application processor and / or a graphics processing unit, etc.). For example, the input image data IMG may include red image data, green image data, and blue image data. For example, the input image data IMG may include white image data. For example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signals CONT may include a main clock signal and a data enable signal. The input control signals CONT may further include a vertical synchronization signal and a horizontal synchronization signal. The main drive controller 200A may output a common logic signal LOGS to the first slave drive controller 200B (refer to Figure 3 ).

[0051] The main drive controller 200A can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT. In an embodiment, the main drive controller 200A can generate a fifth control signal CONT5 based on the input image data IMG and the input control signal CONT.

[0052] The main drive controller 200A can generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 can include a vertical start signal and a scan clock signal.

[0053] The main drive controller 200A can generate a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and output the third control signal CONT3 to the gamma reference voltage generator 400.

[0054] The main drive controller 200A generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 can include a horizontal start signal and a load signal.

[0055] The main drive controller 200A can generate a data signal DATA based on the input image data IMG and the input control signal CONT. The main drive controller 200A can output the data signal DATA to the data driver 500.

[0056] The main drive controller 200A can generate a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT. The main drive controller 200A can output the fourth control signal CONT4 to the emission driver 600.

[0057] The main drive controller 200A can generate a fifth control signal CONT5 for controlling the operation of the sensing driver 700 based on the input control signal CONT, and output the fifth control signal CONT5 to the sensing driver 700.

[0058] The gate driver 300 can generate a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the main drive controller 200A. The gate driver 300 can output the gate signal to the gate line GL of at least one of the display areas (e.g., the first display area AA1, the second display area AA2, etc.).

[0059] The gamma reference voltage generator 400 may generate a gamma reference voltage VGREF in response to a third control signal CONT3 received from the main driving controller 200A. The gamma reference voltage generator 400 may provide the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to each of the data signals DATA. For example, the gamma reference voltage generator 400 may be disposed in the main driving controller 200A or in the data driver 500.

[0060] The data driver 500 may receive a second control signal CONT2 and data signals DATA from the main driving controller 200A, and receive the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 may convert the data signals DATA into data voltages VDATA of an analog type using the gamma reference voltage VGREF. The data driver 500 may output the data voltage VDATA to the data lines DL.

[0061] In an embodiment, the data driver 500 may be implemented with one or more integrated circuits. In another embodiment, the data driver 500 and the main driving controller 200A may be implemented as a single integrated circuit, and the single integrated circuit may be referred to as a timing controller embedded data driver (TED).

[0062] The emission driver 600 may generate an emission signal for driving the emission lines EL in response to a fourth control signal CONT4 received from the main driving controller 200A. The emission driver 600 may output the emission signal to the emission lines EL of at least one of the display areas (e.g., the first display area AA1, the second display area AA2, etc.).

[0063] In an embodiment of the inventive concept, the emission driver 600 may be integrated in the peripheral area of the display panel 100. In an embodiment of the inventive concept, the emission driver 600 may be mounted in the peripheral area of the display panel 100.

[0064] Although, for ease of explanation, in Figure 2 the gate driver 300 is disposed on the first side of the display panel 100 and the emission driver 600 is disposed on the second side of the display panel 100, the inventive concept is not limited thereto. The gate driver 300 and the emission driver 600 may be disposed on the first side of the display panel 100. For example, the gate driver 300 and the emission driver 600 may be disposed in the peripheral area on the same side of the display area of the display panel 100. For example, the gate driver 300 and the emission driver 600 may be integrally formed with each other.

[0065] In an embodiment, the sensing driver 700 may receive a fifth control signal CONT5 from the main drive controller 200A. The sensing driver 700 may generate sensing data SD by sensing pixels PX via sensing lines SL. For example, the sensing driver 700 may sense the driving characteristics (e.g., mobility and / or threshold voltage) of driving transistors of pixels PX by measuring sensing currents (or sensing voltages) of the driving transistors via the sensing lines SL. For example, the operation of sensing the driving characteristics (e.g., mobility and / or threshold voltage) of the sensing driving transistors may be referred to as a sensing operation.

[0066] In an embodiment, the sensing driver 700 may be implemented with one or more integrated circuits. In another embodiment, the sensing driver 700 may be disposed in the data driver 500 or the main drive controller 200A.

[0067] In addition, in an embodiment, the main panel driver 110A may not include the sensing driver 700. The inventive concept is not limited to the types of drivers that the main panel driver 110A may include.

[0068] Figure 3 is a block diagram of Figure 1 the second display area AA2 of the display device and the first sub-panel driver 110B.

[0069] Referring to Figure 3 , except that the first sub-panel driver 110B may include a first sub-drive controller 200B, the first sub-panel driver 110B is substantially the same as Figure 2 the main panel driver 110A. The first sub-drive controller 200B does not generate a common logic signal LOGS, and the first sub-drive controller 200B receives the common logic signal LOGS from the main drive controller 200A (refer to Figure 2 ). The same reference numerals will be used to refer to the same elements, and any repeated explanations of the above elements will be omitted.

[0070] In addition, in an embodiment, the first sub-panel driver 110B may not include the sensing driver 700. Although the main panel driver 110A and the first sub-panel driver 110B are depicted as having separate embodiments, in some embodiments, some components such as the gate driver 300 and the emission driver 600 may be shared by the first display area AA1 and the second display area AA2. The inventive concept is not limited to the types of drivers that the first sub-panel driver 110B may include.

[0071] Figure 4 is a block diagram showing the main drive controller 200A included in the Figure 1 main panel driver 110A and the Figure 1Block diagram of the first slave drive controller 200B in the first slave panel driver 110B. Figure 5 It shows the drive circuit included in Figure 4 the main drive controller 200A of Figure 4 and the drive circuit included in the first slave drive controller 200B of

[0072] Refer to Figures 1 to 5 , the main drive controller 200A can output a common logic signal LOGS to the first slave drive controller 200B.

[0073] In this embodiment, the main drive controller 200A may include a first main drive circuit MIP1, a second main drive circuit MIP2, and a third main drive circuit MIP3. The first slave drive controller 200B may include a first - first slave drive circuit SIP1, a first - second slave drive circuit SIP2, and a first - third slave drive circuit SIP3.

[0074] In this embodiment, the main panel driver 110A and the first slave panel driver 110B may perform the same operations. The same operations may be referred to as "common operations". For example, the common operations may include a brightness control operation, a sensing operation, and an operation of changing the data signal DATA based on the sensed data SD (e.g., an external compensation operation). For example, the common operations may include an operation of determining a deteriorated area of the display panel 100, an operation of changing the data signal DATA, an operation of changing the driving frequency of the display panel 100, etc. However, the inventive concept is not limited to the operations included in the common operations of the panel drivers (e.g., the main panel driver 110A and the first slave panel driver 110B). In an embodiment, the input control signal CONT may include a signal for determining the common operations.

[0075] In this embodiment, the first main drive circuit MIP1 may generate a signal for performing a first driving operation. For example, the first driving operation may be a brightness control operation. However, the inventive concept is not limited to the type of the first driving operation. For example, the first driving operation may be an external compensation operation. The first driving operation may be set by the user.

[0076] In the present embodiment, when the first driving operation is performed by the main panel driver 110A and the first slave panel driver 110B, the first main driving circuit MIP1 may generate a common logic signal LOGS (e.g., the first common logic signal). The common logic signal LOGS (e.g., the first common logic signal) may be a signal for the main panel driver 110A and the first slave panel driver 110B to perform the first driving operation. In the present embodiment, the first-first slave driving circuit SIP1 may not generate the common logic signal LOGS (e.g., the first common logic signal). When the first driving operation is a common operation, the first-first slave driving circuit SIP1 may remain inactive. The first slave panel driver 110B may perform the first driving operation in response to the common logic signal LOGS.

[0077] In the present embodiment, the second main driving circuit MIP2 may generate a signal for performing a second driving operation. For example, the second driving operation may be a sensing operation. However, the inventive concept does not limit the second driving operation to any specific type of operation. For example, the second driving operation may be an operation of determining a deteriorated area of the display panel 100. For example, the second driving operation may be referred to as a brightness control operation. The second driving operation may be set by a user.

[0078] In the present embodiment, when the second driving operation is performed by the main panel driver 110A and the first slave panel driver 110B, the second main driving circuit MIP2 may generate a common logic signal LOGS (e.g., the second common logic signal). The common logic signal LOGS (e.g., the second common logic signal) may be a signal for the main panel driver 110A and the first slave panel driver 110B to perform the second driving operation. In the present embodiment, the first-second slave driving circuit SIP2 may not generate the common logic signal LOGS (e.g., the second common logic signal). When the second driving operation is a common operation, the first-second slave driving circuit SIP2 may remain inactive. The first slave panel driver 110B may perform the second driving operation in response to the common logic signal LOGS.

[0079] In the present embodiment, the third main driving circuit MIP3 may generate a signal for performing a third driving operation. For example, the third driving operation may be an external compensation operation. However, the inventive concept does not limit the third driving operation to any specific type of operation. For example, the third driving operation may be an operation of changing the data signal DATA. For example, the third driving operation may be referred to as a sensing operation. The third driving operation may be set by a user.

[0080] In the present embodiment, when the third driving operation is performed by the main panel driver 110A and the first slave panel driver 110B, the third main driving circuit MIP3 may generate a common logic signal LOGS. The common logic signal LOGS may be a signal for the main panel driver 110A and the first slave panel driver 110B to perform the third driving operation. In the present embodiment, the first - third slave driving circuits SIP3 may not generate the common logic signal LOGS. When the third driving operation is a common operation, the first - third slave driving circuits SIP3 may remain inactive. The first slave panel driver 110B may perform the third driving operation in response to the common logic signal LOGS.

[0081] In an embodiment, the third driving operation is performed by the main panel driver 110A instead of the first slave panel driver 110B, and the main panel driver 110A may not output the common logic signal LOGS. For example, when the third driving operation is not a common operation, the third main driving circuit MIP3 may not generate the common logic signal LOGS.

[0082] In the present embodiment, the main panel driver 110A and the first slave panel driver 110B may perform a common operation in response to the common logic signal LOGS. For example, when the first driving operation is a common operation, the common logic signal LOGS may be a signal for triggering the first driving operation. For example, when the first driving operation and the second driving operation are common operations, the common logic signal LOGS may include a signal for triggering the first driving operation and a signal for triggering the second driving operation. In the present embodiment, the common logic signal LOGS may be generated from the main driving controller 200A. The first slave driving controller 200B may not generate the common logic signal LOGS.

[0083] In the present embodiment, the common logic signal LOGS may be applied during a blank period of the first slave panel driver 110B.

[0084] In a conventional display device, a conventional main driving controller may generate a signal for performing a common operation. A conventional slave driving controller may also generate a signal for performing a common operation.

[0085] In contrast, in a display device according to the inventive concept, the main driving controller 200A may generate the common logic signal LOGS, but the first slave driving controller 200B may not generate the common logic signal LOGS. Accordingly, power consumption of the display device according to the inventive concept may be reduced.

[0086] In an embodiment, the main drive controller 200A may output a drive data signal different from the common logic signal LOGS to the first slave drive controller 200B. In addition, the first slave drive controller 200B may output a drive data signal to the main drive controller 200A. However, the inventive concept is not limited to the type of drive data signal.

[0087] Figure 6 is a block diagram showing the main detailed arithmetic logic circuit MLOG included in the Figure 5 main drive circuit MIP and the slave detailed arithmetic logic circuit SLOG included in the Figure 5 first slave drive circuit SIP. Figure 7 is a block diagram showing an example of a set of common logic circuits CLOG and a set of main detailed arithmetic logic circuits MLOG included in the Figure 6 main drive circuit MIP, and a set of common logic circuits CLOG and a set of slave detailed arithmetic logic circuits SLOG included in the Figure 6 first slave drive circuit SIP. Figure 8 is a block diagram showing an example of a set of common logic circuits CLOG and a set of main detailed arithmetic logic circuits MLOG included in the Figure 6 main drive circuit MIP, and a set of common logic circuits CLOG and a set of slave detailed arithmetic logic circuits SLOG included in the Figure 6 first slave drive circuit SIP. As used herein, a "set" of elements includes one or more elements.

[0088] Refer to Figures 1 to 8, the main drive circuit MIP may include a first main detailed arithmetic logic circuit MLOG1, a second main detailed arithmetic logic circuit MLOG2, a third main detailed arithmetic logic circuit MLOG3, a fourth main detailed arithmetic logic circuit MLOG4, a fifth main detailed arithmetic logic circuit MLOG5, and a sixth main detailed arithmetic logic circuit MLOG6. For simplicity, each of the main detailed arithmetic logic circuits MLOG1, MLOG2, etc. may be referred to herein as a "main detailed arithmetic logic circuit". The common logic circuit CLOG may be a circuit that generates signals for common operations to be performed. For example, the common logic circuit CLOG may be at least one of the first main detailed arithmetic logic circuit MLOG1, the second main detailed arithmetic logic circuit MLOG2, the third main detailed arithmetic logic circuit MLOG3, the fourth main detailed arithmetic logic circuit MLOG4, the fifth main detailed arithmetic logic circuit MLOG5, and the sixth main detailed arithmetic logic circuit MLOG6. For example, the main detailed arithmetic logic circuit may be a circuit that generates signals (e.g., main detailed logic signals) that cause the main panel driver 110A and the first slave panel driver 110B to perform different operations from each other. For example, the main detailed arithmetic logic circuit may generate signals that cause the first main detailed arithmetic logic circuit MLOG1, the second main detailed arithmetic logic circuit MLOG2, the third main detailed arithmetic logic circuit MLOG3, the fourth main detailed arithmetic logic circuit MLOG4, the fifth main detailed arithmetic logic circuit MLOG5, the sixth main detailed arithmetic logic circuit MLOG6, and the first slave panel driver 110B to perform different operations. For example, the different operations may be operations to change the driving frequency. For example, the first slave detailed arithmetic logic circuit may be a circuit that generates signals (e.g., first slave detailed logic signals) that cause the main panel driver 110A and the first slave panel driver 110B to perform different operations. For example, the different operations may be operations to change the driving frequency.

[0089] The first main drive circuit MIP1 may include a first-first main detailed arithmetic logic circuit, a first-second main detailed arithmetic logic circuit, a first-third main detailed arithmetic logic circuit, a first-fourth main detailed arithmetic logic circuit, a first-fifth main detailed arithmetic logic circuit, and a first-sixth main detailed arithmetic logic circuit.

[0090] In this embodiment, the first driving operation may include first-first detailed operations to first-sixth detailed operations. The first-first main detailed arithmetic logic circuit may generate a signal for executing the first-first detailed operation. The first-second main detailed arithmetic logic circuit may generate a signal for executing the first-second detailed operation. The first-third main detailed arithmetic logic circuit may generate a signal for executing the first-third detailed operation. The first-fourth main detailed arithmetic logic circuit may generate a signal for executing the first-fourth detailed operation. The first-fifth main detailed arithmetic logic circuit may generate a signal for executing the first-fifth detailed operation. The first-sixth main detailed arithmetic logic circuit may generate a signal for executing the first-sixth detailed operation.

[0091] The first slave driving circuit SIP may include a first slave detailed arithmetic logic circuit SLOG1, a second slave detailed arithmetic logic circuit SLOG2, a third slave detailed arithmetic logic circuit SLOG3, a fourth slave detailed arithmetic logic circuit SLOG4, a fifth slave detailed arithmetic logic circuit SLOG5, and a sixth slave detailed arithmetic logic circuit SLOG6. For example, the first-first slave driving circuit SIP1 may include a first-first-first slave detailed arithmetic logic circuit, a first-first-second slave detailed arithmetic logic circuit, a first-first-third slave detailed arithmetic logic circuit, a first-first-fourth slave detailed arithmetic logic circuit, a first-first-fifth slave detailed arithmetic logic circuit, and a first-first-sixth slave detailed arithmetic logic circuit.

[0092] The first-first-first slave detailed arithmetic logic circuit may generate a signal for executing the first-first detailed operation. The first-first-second slave detailed arithmetic logic circuit may generate a signal for executing the first-second detailed operation. The first-first-third slave detailed arithmetic logic circuit may generate a signal for executing the first-third detailed operation. The first-first-fourth slave detailed arithmetic logic circuit may generate a signal for executing the first-fourth detailed operation. The first-first-fifth slave detailed arithmetic logic circuit may generate a signal for executing the first-fifth detailed operation. The first-first-sixth slave detailed arithmetic logic circuit may generate a signal for executing the first-sixth detailed operation.

[0093] For example, when the first driving operation is a brightness control operation, the first-first detailed operation may be an operation of controlling a predetermined area of the first display area AA1. In addition, the first-second detailed operation is an operation of increasing or decreasing the brightness of the first display area AA1. The first-third detailed operation is an operation of increasing or decreasing the brightness of another predetermined area of the first display area AA1. For example, when the first driving operation is a brightness control operation, the first-first detailed operation may be an operation of controlling a predetermined area of the second display area AA2. In addition, the first-second detailed operation is an operation of increasing or decreasing the brightness of the second display area AA2. The first-third detailed operation is an operation of increasing or decreasing the brightness of another predetermined area of the second display area AA2. However, the inventive concept is not limited to the operations of the first-first detailed operation to the first-third detailed operation included in the first driving operation. For example, the first-first detailed operation to the first-sixth detailed operation may be set by the user.

[0094] Figure 7 An example is depicted in which the first-first detailed operation, the first-fifth detailed operation, and the first-sixth detailed operation are common operations. In this case, the first-first main detailed arithmetic logic circuit, the first-fifth main detailed arithmetic logic circuit, and the first-sixth main detailed arithmetic logic circuit may be a common logic circuit CLOG. Therefore, the first-first main detailed arithmetic logic circuit, the first-fifth main detailed arithmetic logic circuit, and the first-sixth main detailed arithmetic logic circuit may generate a common logic signal LOGS. In addition, the first-first-first sub-detailed arithmetic logic circuit, the first-first-fifth sub-detailed arithmetic logic circuit, and the first-first-sixth sub-detailed arithmetic logic circuit may be a common logic circuit CLOG. The first-first-first sub-detailed arithmetic logic circuit, the first-first-fifth sub-detailed arithmetic logic circuit, and the first-first-sixth sub-detailed arithmetic logic circuit may not generate a common logic signal LOGS. The first sub-panel driver 110B may perform the first-first detailed operation, the first-fifth detailed operation, and the first-sixth detailed operation in response to the common logic signal LOGS received from the first-first main detailed arithmetic logic circuit, the first-fifth main detailed arithmetic logic circuit, and the first-sixth main detailed arithmetic logic circuit.

[0095] Figure 8Illustrates an example where the first - second detailed operations and the first - third detailed operations are common operations. In this case, the first - second main detailed arithmetic logic circuits and the first - third main detailed arithmetic logic circuits, the first - first - second slave detailed arithmetic logic circuits and the first - first - third slave detailed arithmetic logic circuits can be the common logic circuit CLOG. The first - second main detailed arithmetic logic circuits and the first - third main detailed arithmetic logic circuits can generate a common logic signal LOGS. The first - first - second slave detailed arithmetic logic circuits and the first - first - third slave detailed arithmetic logic circuits may not generate the common logic signal LOGS.

[0096] The first slave panel driver 110B can perform the first - second detailed operation and the first - third detailed operation in response to the common logic signal LOGS received from the first - second main detailed arithmetic logic circuits and the first - third main detailed arithmetic logic circuits.

[0097] For example, although not explicitly shown, the second main drive circuit MIP2 can include a second - first main detailed arithmetic logic circuit, a second - second main detailed arithmetic logic circuit, a second - third main detailed arithmetic logic circuit, a second - fourth main detailed arithmetic logic circuit, a second - fifth main detailed arithmetic logic circuit, and a second - sixth main detailed arithmetic logic circuit.

[0098] In this embodiment, the second drive operation can include second - first detailed operations to second - sixth detailed operations. The second - first main detailed arithmetic logic circuit can generate a signal for causing the execution of the second - first detailed operation. The second - second main detailed arithmetic logic circuit can generate a signal for causing the execution of the second - second detailed operation. The second - third main detailed arithmetic logic circuit can generate a signal for causing the execution of the second - third detailed operation. The second - fourth main detailed arithmetic logic circuit can generate a signal for causing the execution of the second - fourth detailed operation. The second - fifth main detailed arithmetic logic circuit can generate a signal for causing the execution of the second - fifth detailed operation. The second - sixth main detailed arithmetic logic circuit can generate a signal for causing the execution of the second - sixth detailed operation.

[0099] The first - second slave drive circuit SIP2 can include a first slave detailed arithmetic logic circuit to a sixth slave detailed arithmetic logic circuit. For example, the first - second slave drive circuit SIP2 can include a first - second - first slave detailed arithmetic logic circuit, a first - second - second slave detailed arithmetic logic circuit, a first - second - third slave detailed arithmetic logic circuit, a first - second - fourth slave detailed arithmetic logic circuit, a first - second - fifth slave detailed arithmetic logic circuit, and a first - second - sixth slave detailed arithmetic logic circuit.

[0100] The first - second - first slave detailed operation logic circuit can generate a signal that causes the execution of the second - first detailed operation. The first - second - second slave detailed operation logic circuit can generate a signal that causes the execution of the second - second detailed operation. The first - second - third slave detailed operation logic circuit can generate a signal that causes the execution of the second - third detailed operation. The first - second - fourth slave detailed operation logic circuit can generate a signal that causes the execution of the second - fourth detailed operation. The first - second - fifth slave detailed operation logic circuit can generate a signal that causes the execution of the second - fifth detailed operation. The first - second - sixth slave detailed operation logic circuit can generate a signal that causes the execution of the second - sixth detailed operation.

[0101] For example, when the second driving operation is a sensing operation, the second - first detailed operation can be an operation of sensing a predetermined area of the display panel 100. In addition, the second - second detailed operation is an operation of sensing the display panel 100 in real time. The second - third detailed operation is an operation of changing the data voltage VDATA. However, the inventive concept is not limited to the operations of the second - first detailed operation to the second - third detailed operation included in the second driving operation. For example, the second - first detailed operation to the second - sixth detailed operation can be set by the user.

[0102] In Figure 7 the example, the second - first detailed operation, the second - fifth detailed operation, and the second - sixth detailed operation are common operations. In this case, the second - first main detailed operation logic circuit, the second - fifth main detailed operation logic circuit, and the second - sixth main detailed operation logic circuit can be a common logic circuit CLOG. Therefore, the second - first main detailed operation logic circuit, the second - fifth main detailed operation logic circuit, and the second - sixth main detailed operation logic circuit can generate a common logic signal LOGS. In addition, the first - second - first slave detailed operation logic circuit, the first - second - fifth slave detailed operation logic circuit, and the first - second - sixth slave detailed operation logic circuit can be a common logic circuit CLOG. The first - second - first slave detailed operation logic circuit, the first - second - fifth slave detailed operation logic circuit, and the first - second - sixth slave detailed operation logic circuit may not generate a common logic signal LOGS. The first panel driver 110B can execute the second - first detailed operation, the second - fifth detailed operation, and the second - sixth detailed operation in response to the common logic signal LOGS received from the second - first main detailed operation logic circuit, the second - fifth main detailed operation logic circuit, and the second - sixth main detailed operation logic circuit.

[0103] In Figure 8In the example, the second-second detailed operation and the second-third detailed operation are common operations. In this case, the second-second main detailed arithmetic logic circuit and the second-third main detailed arithmetic logic circuit, the first-second-second slave detailed arithmetic logic circuit and the first-second-third slave detailed arithmetic logic circuit can be the common logic circuit CLOG. The second-second main detailed arithmetic logic circuit and the second-third main detailed arithmetic logic circuit can generate a common logic signal LOGS. The first-second-second slave detailed arithmetic logic circuit and the first-second-third slave detailed arithmetic logic circuit may not generate the common logic signal LOGS.

[0104] The first slave panel driver 110B can perform the second-second detailed operation and the second-third detailed operation in response to the common logic signal LOGS received from the second-second main detailed arithmetic logic circuit and the second-third main detailed arithmetic logic circuit.

[0105] For example, the third main drive circuit MIP3 can include a third-first main detailed arithmetic logic circuit, a third-second main detailed arithmetic logic circuit, a third-third main detailed arithmetic logic circuit, a third-fourth main detailed arithmetic logic circuit, a third-fifth main detailed arithmetic logic circuit, and a third-sixth main detailed arithmetic logic circuit.

[0106] In the present embodiment, the third drive operation can include a third-first detailed operation to a third-sixth detailed operation. The third-first main detailed arithmetic logic circuit can generate a signal for causing the execution of the third-first detailed operation. The third-second main detailed arithmetic logic circuit can generate a signal for causing the execution of the third-second detailed operation. The third-third main detailed arithmetic logic circuit can generate a signal for causing the execution of the third-third detailed operation. The third-fourth main detailed arithmetic logic circuit can generate a signal for causing the execution of the third-fourth detailed operation. The third-fifth main detailed arithmetic logic circuit can generate a signal for causing the execution of the third-fifth detailed operation. The third-sixth main detailed arithmetic logic circuit can generate a signal for causing the execution of the third-sixth detailed operation.

[0107] The first-third slave drive circuit SIP3 can include a first slave detailed arithmetic logic circuit to a sixth slave detailed arithmetic logic circuit. For example, the first-third slave drive circuit SIP3 can include a first-third-first slave detailed arithmetic logic circuit, a first-third-second slave detailed arithmetic logic circuit, a first-third-third slave detailed arithmetic logic circuit, a first-third-fourth slave detailed arithmetic logic circuit, a first-third-fifth slave detailed arithmetic logic circuit, and a first-third-sixth slave detailed arithmetic logic circuit.

[0108] The first - third - first slave detailed arithmetic logic circuit can generate a signal that causes the execution of the third - first detailed operation. The first - third - second slave detailed arithmetic logic circuit can generate a signal that causes the execution of the third - second detailed operation. The first - third - third slave detailed arithmetic logic circuit can generate a signal that causes the execution of the third - third detailed operation. The first - third - fourth slave detailed arithmetic logic circuit can generate a signal that causes the execution of the third - fourth detailed operation. The first - third - fifth slave detailed arithmetic logic circuit can generate a signal that causes the execution of the third - fifth detailed operation. The first - third - sixth slave detailed arithmetic logic circuit can generate a signal that causes the execution of the third - sixth detailed operation.

[0109] For example, when the third driving operation is an external compensation operation, the third - first detailed operation can be an external compensation operation performed on a predetermined area of the display panel 100. In addition, the third - second detailed operation is an operation of storing the sensed data SD. The third - third detailed operation is an operation of generating the data signal DATA based on the sensed data SD. However, the inventive concept is not limited to the operations of the third - first detailed operation to the third - third detailed operation included in the third driving operation. For example, the third - first detailed operation to the third - sixth detailed operation can be set by the user.

[0110] For example, the third - first detailed operation, the third - fifth detailed operation, and the third - sixth detailed operation are common operations, and the third - first main detailed arithmetic logic circuit, the third - fifth main detailed arithmetic logic circuit, and the third - sixth main detailed arithmetic logic circuit can be a common logic circuit CLOG. Therefore, the third - first main detailed arithmetic logic circuit, the third - fifth main detailed arithmetic logic circuit, and the third - sixth main detailed arithmetic logic circuit can generate a common logic signal LOGS. In addition, the first - third - first slave detailed arithmetic logic circuit, the first - third - fifth slave detailed arithmetic logic circuit, and the first - third - sixth slave detailed arithmetic logic circuit can be a common logic circuit CLOG. The first - third - first slave detailed arithmetic logic circuit, the first - third - fifth slave detailed arithmetic logic circuit, and the first - third - sixth slave detailed arithmetic logic circuit may not generate a common logic signal LOGS. The first slave panel driver 110B can execute the third - first detailed operation, the third - fifth detailed operation, and the third - sixth detailed operation in response to the common logic signal LOGS received from the third - first main detailed arithmetic logic circuit, the third - fifth main detailed arithmetic logic circuit, and the third - sixth main detailed arithmetic logic circuit.

[0111] For example, if the third - second detailed operation and the third - third detailed operation are common operations, the third - second main detailed arithmetic logic circuit, the third - third main detailed arithmetic logic circuit, the first - third - second slave detailed arithmetic logic circuit, and the first - third - third slave detailed arithmetic logic circuit can be the common logic circuit CLOG. The third - second main detailed arithmetic logic circuit and the third - third main detailed arithmetic logic circuit can generate a common logic signal LOGS. The first - third - second slave detailed arithmetic logic circuit and the first - third - third slave detailed arithmetic logic circuit may not generate the common logic signal LOGS.

[0112] The first slave panel driver 110B can perform the third - second detailed operation and the third - third detailed operation in response to the common logic signal LOGS received from the third - second main detailed arithmetic logic circuit and the third - third main detailed arithmetic logic circuit.

[0113] In this embodiment, the common logic circuit CLOG included in the first slave driving circuit SIP may not generate the common logic signal LOGS. The first slave panel driver 110B can perform the common operation in response to the common logic signal LOGS received from the main panel driver 110A. Therefore, the power consumption of the display device can be reduced. In addition, the first slave driving circuit SIP may not generate the common logic signal LOGS, so that the first slave driving circuit SIP may not include a circuit for generating the common logic signal LOGS. Therefore, the size of the first slave driving controller 200B can be reduced. In addition, the integration of the display device can be improved.

[0114] In an embodiment, the common logic circuit CLOG can be changed. In an embodiment, the common logic circuit CLOG can be changed in real time in response to an input control signal CONT.

[0115] Figure 9 is a block diagram showing an example of the third display area AA3 and the second slave panel driver 110C included in Figure 1 the display device.

[0116] Refer to Figure 9 , the second slave panel driver 110C is substantially the same as the first slave panel driver 110B of Figure 3 . Therefore, the same reference numerals will be used to refer to the same elements, and any repeated explanations of the above elements will be omitted.

[0117] In this embodiment, the second slave panel driver 110C can receive the common logic signal LOGS. The common logic signal LOGS can be a signal that enables the main panel driver 110A, the first slave panel driver 110B, and the second slave panel driver 110C to perform a common operation.

[0118] In this embodiment, the second slave panel driver 110C may include a common logic circuit and a second slave detailed operation logic circuit. For example, the second slave detailed operation logic circuit may be a circuit that generates a signal (e.g., a second slave detailed logic signal) that causes the main panel driver 110A and the second slave panel driver 110C to perform different operations from each other. For example, the different operations may be operations of changing the driving frequency.

[0119] In this embodiment, the first slave panel driver 110B and the second slave panel driver 110C may not generate a common logic signal LOGS. Therefore, the power consumption of the display device can be further reduced.

[0120] Figure 10 is a block diagram showing an example of a third display area AA3 and a second slave panel driver 110C included in the Figure 1 display device.

[0121] Referring to Figure 9 and Figure 10 , except that the first slave panel driver 110B may receive a first slave common logic signal LOGS1, and the second slave panel driver 110C may receive a second slave common logic signal LOGS2, Figure 10 the display device of Figure 9 is substantially the same as the display device of

[0122] such that the same reference numerals will be used to refer to the same elements, and any repeated explanations of the above elements will be omitted.

[0123] In this embodiment, the first slave panel driver 110B may receive a first slave common logic signal LOGS1. The first slave common logic signal LOGS1 may be a signal that causes the main panel driver 110A and the first slave panel driver 110B to perform a common operation. The common operation of the main panel driver 110A and the first slave panel driver 110B may be referred to as a first common operation.

[0124] In this embodiment, the second slave panel driver 110C may receive a second slave common logic signal LOGS2. The second slave common logic signal LOGS2 may be a signal that causes the main panel driver 110A and the second slave panel driver 110C to perform a common operation. The common operation of the main panel driver 110A and the second slave panel driver 110C may be referred to as a second common operation.

[0125] In addition, the first common operation and the second common operation may be different, such that the number of first slave common logic signals LOGS1 and the number of second slave common logic signals LOGS2 may be different. Accordingly, the power consumption of the display device can be controlled more effectively.

[0126] In the present embodiment, the second slave panel driver 110C may include a second slave driving controller, and the second slave driving controller may include a second-first slave driving circuit configured to output a signal for performing the first driving operation described above.

[0127] In the present embodiment, the second-first slave driving circuit may include: a second-first-first slave detailed operation logic circuit configured to output a signal for performing the first-first detailed operation described above; and a second-first-second slave detailed operation logic circuit configured to output a signal for performing the first-second detailed operation described above. In the present embodiment, the second slave panel driver 110C may be configured to perform the first-first detailed operation described above based on the common logic signal generated by the first-first master detailed operation logic circuit.

[0128] Figure 11 is a block diagram showing an electronic device 1000 according to an embodiment of the inventive concept. Figure 12 is a diagram showing an example in which Figure 11 the electronic device is implemented as a smart phone.

[0129] Referring to Figure 11 and Figure 12 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be Figure 1 the display device. In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, etc.

[0130] In an embodiment, as Figure 12 shown in

[0131] The processor 1010 may perform various computing functions or various tasks. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 may be connected to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 may be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0132] The processor 1010 may output the input image data IMG and the input control signal CONT to Figure 2 the main panel driver 110A of Figure 3 and the first slave panel driver 110B of

[0133] The memory device 1020 may store data for operating the electronic device 1000. For example, the memory device 1020 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.), and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.).

[0134] The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1040 may include input devices such as a keyboard, a keypad, a mouse device, a touchpad, a touch screen, etc. and output devices such as a printer, a speaker, etc. In some embodiments, the display device 1060 may be included in the I / O device 1040. The power supply 1050 may supply power for the operation of the electronic device 1000. The display device 1060 may be connected to other components via a bus or other communication link.

[0135] The display device according to an embodiment may be applied to display devices included in a computer, a notebook, a mobile phone, a smart phone, a smart tablet, a PMP, a PDA, an MP3 player, etc.

[0136] The above is an explanation of the inventive concept of the present invention and should not be construed as a limitation of the inventive concept. Although some embodiments of the inventive concept have been described, those skilled in the art will readily understand that many modifications are possible in the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. The inventive concept is defined by the appended claims and their equivalents.

Claims

1. Display equipment, including: The display panel comprises a first display area and a second display area; as well as a master panel driver and a first slave panel driver configured to drive the first display area and the second display area, respectively, based on a common logic signal generated by the master panel driver, Wherein, the first slave panel driver is configured to receive the common logic signal from the master panel driver without generating the common logic signal.

2. The display device according to claim 1, wherein: The main panel driver includes a main drive controller, Wherein, the first slave panel driver comprises a first slave driving controller, and Wherein, the master drive controller is configured to generate the common logic signal and output the common logic signal to the first slave drive controller.

3. The display device according to claim 1, wherein: The main panel driver includes a main drive controller, Wherein, the first slave panel driver comprises a first slave driving controller, wherein the main driving controller comprises a first main driving circuit configured to output a signal for performing a first driving operation, wherein the first slave driving controller comprises a first-first slave driving circuit configured to output a signal for performing the first driving operation, and The common logic signal is a signal used to perform the first driving operation.

4. The display device according to claim 3, wherein: The first main driving circuit comprises: a first-first master detailed operation logic circuit configured to output a signal for performing a first-first detailed operation; and a first-second master detailed operation logic circuit configured to output a signal for performing a first-second detailed operation; Wherein, the first-first slave driving circuit comprises: a first-first-first slave detailed operation logic circuit configured to output a signal for performing the first-first detailed operation; and a first-first-second slave detailed operation logic circuit configured to output a signal for performing the first-second detailed operation; wherein the common logic signal is generated by the first-first master detailed operation logic circuit, and Wherein, the first slave panel driver is configured to perform the first-first detailed operation based on the common logic signal.

5. The display device according to claim 4, wherein: The common logic signal is applied to the first slave driving controller, and the first-first-first slave detailed operation logic circuit remains inactive.

6. The display device according to claim 3, wherein: The main driving controller further includes a second main driving circuit that causes the main panel driver to perform a second driving operation different from the first driving operation, Wherein, the first slave driving controller further includes a first-second slave driving circuit that enables the first slave panel driver to perform the second driving operation, The common logic signal includes a first common logic signal and a second common logic signal, and The first common logic signal is a signal for performing the first driving operation, and the second common logic signal is a signal for performing the second driving operation.

7. The display device according to claim 6, wherein: The second main driving circuit comprises: a second-first master detailed operation logic circuit configured to output a signal for performing a second-first detailed operation; and a second-second main detailed operation logic circuit configured to output a signal for performing a second-second detailed operation; Wherein, the first-second slave driving circuit comprises: a first-second-first slave detailed operation logic circuit configured to output a signal for performing the second-first detailed operation; and a first-second-second slave detailed operation logic circuit configured to output a signal for performing the second-second detailed operation; wherein the second common logic signal is generated by the second-first master detailed operation logic circuit, and Wherein, the first slave panel driver is configured to perform the second-first detailed operation based on the second common logic signal.

8. The display device according to claim 7, wherein: The second common logic signal is applied to the first slave driving controller, and the first-second-first slave detailed operation logic circuit remains inactive.

9. The display device according to claim 1, wherein: The common logic signal is applied to the first slave panel driver during a blank period of the first slave panel driver.

10. The display device according to claim 1, wherein: The first display area and the second display area emit light at different driving frequencies.

11. The display device according to claim 1, further comprising: a third display area, in the display panel; as well as a second slave panel driver configured to drive the third display area based on the common logic signal received from the master panel driver, and Wherein, the second slave panel driver does not generate a common logic signal.

12. The display device according to claim 11, wherein: The common logic signal includes a first slave common logic signal and a second slave common logic signal, and Wherein, the first slave common logic signal is applied to the first slave panel driver, and the second slave common logic signal is applied to the second slave panel driver.

13. The display device according to claim 11, wherein: The main panel driver includes a main drive controller, Wherein, the first slave panel driver comprises a first slave driving controller, Wherein, the second slave panel driver comprises a second slave driving controller, wherein the main driving controller comprises a first main driving circuit that enables the main panel driver to perform a first driving operation, wherein the first slave driving controller comprises a first-first slave driving circuit configured to output a signal for performing the first driving operation, wherein the second slave driving controller comprises a second-first slave driving circuit configured to output a signal for performing the first driving operation, and The common logic signal is a signal used to perform the first driving operation.

14. The display device according to claim 13, wherein: The first main driving circuit comprises: a first-first master detailed operation logic circuit configured to output a signal for performing a first-first detailed operation; and a first-second master detailed operation logic circuit configured to output a signal for performing a first-second detailed operation; Wherein, the first-first slave driving circuit comprises: a first-first-first slave detailed operation logic circuit configured to output a signal for performing the first-first detailed operation; and a first-first-second slave detailed operation logic circuit configured to output a signal for performing the first-second detailed operation; Wherein, the second-first slave driving circuit comprises: a second-first-first slave detailed operation logic circuit configured to output a signal for performing the first-first detailed operation; and a second-first-second slave detailed operation logic circuit configured to output a signal for performing the first-second detailed operation; wherein the common logic signal is generated by the first-first master detailed operation logic circuit, and Wherein, the first slave panel driver is configured to perform the first-first detailed operation based on the common logic signal, and the second slave panel driver is configured to perform the first-first detailed operation based on the common logic signal.

15. Display equipment, including: The display panel comprises a first display area and a second display area; a main panel driver including a common logic circuit configured to generate a common logic signal and a main detailed operation logic circuit configured to generate a main detailed logic signal, and configured to drive the first display area based on the common logic signal and the main detailed logic signal; as well as The slave panel driver includes a first slave detailed operation logic circuit configured to generate a first slave detailed logic signal, and is configured to drive the second display area based on the common logic signal and the first slave detailed logic signal.

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