Clock synchronization circuit, driving circuit and driving method

Abstract

The invention discloses a clock synchronization circuit, a driving circuit and a driving method. The clock synchronization circuit comprises a detection unit used for receiving a first initial pulse signal and generating a detection signal with a first level when the voltage value of the first initial pulse signal is in a preset range; the trigger unit is used for receiving the first clock signal and the detection signal, and the trigger unit is used for generating an effective trigger signal according to the detection signal of the first level at an effective edge of the first clock signal; the output unit is used for generating a second clock signal according to the first clock signal and the trigger signal, when the trigger signal is invalid, the second clock signal changes along with the first clock signal, and when the trigger signal is valid, the second clock signal is kept at a low level. Therefore, the clock signal can be kept at the low level when the initial pulse signal is located at the effective edge, and abnormal display of the clock signal which is not located at the low level at high temperature is avoided.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and particularly to a clock synchronization circuit, a driving circuit and a driving method. Background Art

[0002] In modern display technology, display panels, as key components, are widely used in various electronic devices such as mobile phones, computer monitors, televisions, etc. During the normal operation of the display panel, a timing controller needs to provide a clock signal CLK and a start pulse signal STV to the gate driving circuit.

[0003] When the start pulse signal STV jumps to the effective level, it usually indicates the start of a new display cycle. Thereafter, at the effective edge of each clock signal CLK, the gate driving circuit sequentially selects corresponding pixels, and the source driving circuit charges the capacitor in the pixel, thereby realizing the progressive display of the image.

[0004] In the prior art, a pre-charging technique is usually adopted to shorten the charging time of the capacitor in the pixel circuit. The charge sharing technique is a common pre-charging technique. Switching elements are configured between adjacent data channels or pixel circuits. When the switching elements are turned on, these data channels or pixel circuits can share charges, thereby improving the charging speed and optimizing the display performance.

[0005] However, charge sharing generates high temperature. Figure 1 The waveform diagrams of multiple clock signals are shown. As Figure 1 shown in region I in, usually, at the effective edge of the start pulse signal STV, the clock signal is not at the low level potential. However, at high temperature, the clock signal not at the low potential will cause display anomalies and reduce the display quality. Summary of the Invention

[0006] In view of the above problems, the purpose of the present application is to provide a clock synchronization circuit, a display driving circuit and a driving method, which maintain the low-level output of the clock signal at the effective edge of the start pulse signal.

[0007] According to one aspect of the present application, a clock synchronization circuit is provided. The clock synchronization circuit is connected between a timing control circuit and a gate driving circuit of a display panel. The timing control circuit generates a first clock signal, a first start pulse signal, and a second start pulse signal with the same timing. The clock synchronization circuit receives the first start pulse signal and the first clock signal and provides a second clock signal to the gate driving circuit. The clock synchronization circuit includes: a detection unit configured to receive the first start pulse signal and generate a detection signal with a first level when the voltage value of the first start pulse signal is within a preset range; a trigger unit configured to receive the first clock signal and the detection signal, and the trigger unit is configured to generate a valid trigger signal according to the detection signal with the first level at the active edge of the first clock signal; and an output unit configured to generate the second clock signal according to the first clock signal and the trigger signal. The second clock signal and the second start pulse signal are used to select / turn off pixels of the display panel. The output unit is configured to control the second clock signal to follow the change of the first clock signal when the trigger signal is invalid, and pull down the second clock signal to a low level when the trigger signal is valid.

[0008] Optionally, the second start pulse signal is multiplexed as the first start pulse signal.

[0009] Optionally, the detection unit includes: a first comparator, with the non-inverting input terminal receiving the first start pulse signal and the inverting input terminal receiving a first reference voltage; a second comparator, with the non-inverting input terminal receiving a second reference voltage and the inverting input terminal receiving the first start pulse signal; a first resistor, with the first end of the first resistor connected to the output terminal of the first comparator; a second resistor, with the first end of the second resistor connected to the output terminal of the second comparator; and a third resistor, with the first end of the third resistor connected to the second ends of the first resistor and the second resistor and providing the detection signal, and the second end of the third resistor is grounded.

[0010] Optionally, the detection unit further includes a delay module, and the first start pulse signal is provided to the first comparator and the second comparator through the delay module.

[0011] Optionally, the trigger unit includes a D flip-flop, with the data input terminal of the D flip-flop receiving the detection signal, the clock input terminal receiving the first clock signal, and the inverted output terminal providing the trigger signal.

[0012] Optionally, the voltage domain in which the trigger unit operates is the same as the voltage domain in which the second start pulse signal operates, and this voltage domain is greater than the voltage domain in which the first start pulse signal operates.

[0013] Optionally, the output unit includes: a switching transistor, whose control terminal receives the trigger signal, whose first terminal receives the first clock signal, and whose second terminal provides the second clock signal; and a seventh resistor connected between the second terminal of the switching transistor and the power supply terminal at a low level.

[0014] Optionally, the output unit further includes: an eighth resistor, through which the first clock signal is provided to the first terminal of the switching transistor.

[0015] According to a second aspect of the present application, there is provided a driving circuit for a display panel, which includes: a timing control circuit for generating a first clock signal, a first start pulse signal and a second start pulse signal having the same timing; a clock synchronization circuit as described in any one of the above, connected to the timing control circuit for generating a second clock signal according to the first start pulse signal and the first clock signal; and a gate driving circuit connected to the timing control circuit and the clock synchronization circuit, for providing a scan signal to the display panel according to the second start pulse signal and the second clock signal, and pixels of the display panel are selected or turned off according to the corresponding scan signal.

[0016] According to a third aspect of the present application, there is provided a driving method for a display panel, which includes: obtaining a first start pulse signal, a second start pulse signal and a first clock signal provided by a timing control circuit, where the first start pulse signal and the second start pulse signal have the same timing; detecting the start pulse signal, and generating a detection signal having a first level when the voltage value of the start pulse signal is within a preset range; at an active edge of the first clock signal, generating a valid trigger signal according to the detection signal having the first level; generating the second clock signal according to the trigger signal and the first clock signal; and selecting / turning off corresponding pixels on the display panel according to the second start pulse signal and the second clock signal, where when the trigger signal is invalid, the second clock signal changes following the first clock signal, and when the trigger signal is valid, the second clock signal is pulled down to a low level.

[0017] According to the clock synchronization circuit, driving circuit and driving method provided by the present application, the potential state of the first start pulse signal is detected, and the first clock signal is controlled according to the detection result, so as to keep the low-level output of the second clock signal at the active edge of the first start pulse signal, that is, the active edge of the second start pulse signal, avoiding display anomalies at high temperatures caused by clock signals not at a low potential, which is beneficial to improving the display effect. Description of the Drawings

[0018] Through the following description of the embodiments of the present invention with reference to the accompanying drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0019] Figure 1 A waveform diagram of multiple clock signals is shown;

[0020] Figure 2 A schematic structural diagram of a display device according to an embodiment of the present application is shown;

[0021] Figure 3 A schematic structural diagram of a clock synchronization circuit according to an embodiment of the present application is shown;

[0022] Figure 4 A schematic circuit diagram of a clock synchronization circuit according to an embodiment of the present application is shown;

[0023] Figure 5 A schematic waveform diagram of a detection unit is shown;

[0024] Figure 6 A schematic waveform diagram of a trigger unit is shown;

[0025] Figure 7 A schematic waveform diagram of a clock synchronization circuit is shown;

[0026] Figure 8 A schematic flowchart of a driving method according to an embodiment of the present application is shown. Detailed Embodiments

[0027] The various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are denoted by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0028] At the same time, certain terms are used in this specification and the claims to refer to particular components. Those of ordinary skill in the art should understand that manufacturers may use different names to refer to the same component. This specification and the claims do not use the difference in names as a way to distinguish components, but rather use the difference in the functions of components as the criterion for distinction.

[0029] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by a programmable circuit. When an element or circuit is said to be "connected to" another element or when an element or circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there may be intermediate elements, and the connection between the elements can be physical, logical, or a combination thereof. In contrast, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0030] In addition, it should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0031] It should also be noted that in the various methods and processes of this application, the magnitude of the serial numbers of the steps does not mean the order of execution, nor does it constitute any limitation on the implementation process of the embodiments of this application.

[0032] Figure 2 The schematic structural diagram of the display device according to the embodiment of the present application is shown. As Figure 2 shown, the display device according to the embodiment of the present application includes a display panel 100 and a display driving circuit 200.

[0033] The display panel 100 includes n×m pixel units in an n×m array, n gate lines GL and m source lines DL, where n and m are positive integers. In Figure 2 it, only one gate line GL and one source line DL are shown as examples. In the display panel, the pixel units in the same row are connected to the same gate line GL, and the pixel units in the same column are connected to the same source line DL. The pixel units receive scan signals via the corresponding gate lines GL to be selected or turned off, and the selected pixel units receive data signals via the corresponding source lines DL for display.

[0034] The display driving circuit 200 includes a timing control circuit 210, a gate driving circuit 220, and a source driving circuit 230.

[0035] In some embodiments, the timing control circuit 210 provides a first clock signal CLK0, a second start pulse signal STV1, and a source driving control signal Cont. The gate driving circuit 220 provides scan signals to the display panel according to the second start pulse signal STV1 and the first clock signal CLK0, and the source driving circuit 230 provides data signals to the display panel according to the source driving control signal Cont.

[0036] Under normal circumstances, when the active edge of the second start pulse signal STV1 arrives, the first clock signal CLK0 is not at a low potential. When the driving circuit 200 operates in a high-temperature environment, the first clock signal CLK0 that is not at a low potential will cause abnormal display. In the embodiments of the present application, referring to Figure 2 , the driving circuit 200 further includes a clock synchronization circuit 240 connected between the timing control circuit 210 and the gate driving circuit 220, configured to provide a second clock signal CLK1 according to the first start pulse signal STV0 and the first clock signal CLK0. Among them, the timings of the first start pulse signal STV0 and the second start pulse signal STV1 are the same, so that the second clock signal CLK1 controls the second clock signal CLK1 to maintain a low-level output at the active edge of the first start pulse signal STV0, that is, the second start pulse signal STV1, and controls the second clock signal CLK1 to change following the first clock signal CLK0 in other stages.

[0037] Figure 3 FIG. shows a schematic structural diagram of the clock synchronization circuit according to an embodiment of the present application; Figure 4 FIG. shows a schematic circuit diagram of the clock synchronization circuit according to an embodiment of the present application. The following combines Figure 3 and Figure 4 to further illustrate the clock synchronization circuit 240.

[0038] Referring to Figure 3 and Figure 4 , the clock synchronization circuit provided by the present application includes a detection unit 241, a trigger unit 242, and an output unit 243.

[0039] The detection unit 241 is configured to detect the first start pulse signal STV0 and provide a detection signal DS according to the detection result. Among them, when the first start pulse signal STV0 is within a preset range, a detection signal DS with a first level is generated.

[0040] Combined with Figure 4 , the detection unit 241 includes a first comparator U1, a second comparator U2, and resistors R1-R3.

[0041] The non-inverting input terminal of the first comparator U1 receives the first start pulse signal STV0, and the inverting input terminal receives the first reference voltage. The non-inverting input terminal of the second comparator U2 receives the second reference voltage, and the inverting input terminal receives the first start pulse signal STV0. The first end of the first resistor R1 is connected to the output terminal of the first comparator U1, the first end of the second resistor R2 is connected to the output terminal of the second comparator U2. The second end of the first resistor R1, the second end of the second resistor R2, and the first end of the third resistor R3 are connected to the illustrated node C and provide a detection signal. The second end of the third resistor R3 is grounded.

[0042] The range determined by the first reference voltage and the second reference voltage is the preset range of the first start pulse signal STV0. When the first start pulse signal STV0 is within this preset range, it indicates that the voltage value of the first start pulse signal STV0 changes, and it is determined whether the first start pulse signal STV0 is at the rising edge or the falling edge at this time. Since the timing of the first start pulse signal STV0 and the second start pulse signal STV1 is the same, the second start pulse signal STV1 is also at the rising edge or the falling edge at this time.

[0043] Figure 5 The schematic waveform diagram of the detection unit is shown. It should be understood that although in Figure 5 , the first start pulse signal STV0 takes a square wave as an example, at time t1, the first start pulse signal STV0 should gradually rise within the preset range, and at time t2, the first start pulse signal STV0 should gradually fall within the preset range.

[0044] Taking the first level of the detection signal DS as the low level and the second level as the high level as an example: when the first start pulse signal STV0 is within the preset range, both the first comparator U1 and the second comparator U2 output low-level signals, and the detection signal DS provided by the node C is also at the low level at this time, that is, the detection signal at this time has the first level; when the first pulse signal STV0 is not within the preset range, one of the first comparator U1 and the second comparator U2 outputs a high level and the other outputs a low level, and the detection signal DS provided by the node C is at the high level at this time, that is, the detection signal at this time has the second level.

[0045] In some embodiments, the first reference voltage and the second reference voltage are provided by, for example, a resistor string 2411. The resistor string 2411 includes a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6 connected in series between the first power supply terminal VDD and the ground. The intermediate node A between the fourth resistor R4 and the fifth resistor R5 is used to provide the first reference voltage, and the intermediate node B between the fifth resistor R5 and the sixth resistor R6 is used to provide the second reference voltage. By setting the resistance values of the fourth resistor R4 to the sixth resistor R6, the first reference voltage and the second reference voltage can be adjusted, thereby adjusting the preset range of the first start pulse signal STV0, and thus the misjudgment caused by the fluctuation of the first start pulse signal STV0 can be avoided, which is beneficial to improving the reliability of the detection signal.

[0046] It should be noted that, in some embodiments, the second start pulse signal STV1 can be directly reused as the first start pulse signal STV0. However, since the operating voltage range of the second start pulse signal STV1 is usually in the VGL-VGH voltage domain. Wherein, VGL is the gate cut-off voltage for turning off the pixel unit, for example, -7V, and VGH is the gate conduction voltage for selecting the pixel unit, for example, 19V. Then the preset range provided by the first reference voltage and the second reference voltage is also higher. The requirements for the voltage value of the first power supply terminal VDD and the resistance values of the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 are also higher.

[0047] In a preferred embodiment, the first start pulse signal STV0 is generated by a timing control circuit, which has the same timing as the second start pulse signal STV1 but operates in a smaller voltage domain. For example, the second start pulse signal STV1 can operate in a voltage domain of 0V-1.8V. Then correspondingly, the requirement for the voltage value of the first power supply terminal VDD can be reduced, and the resistance values of the fourth resistor R4 - the sixth resistor R6 can be reduced, which is beneficial to reducing power consumption and saving costs.

[0048] In some embodiments, the detection unit 241 further includes a delay module 2412. The start pulse signal STV is transmitted to the first comparator U1 and the second comparator U2 through the delay module 2412, so as to provide a delay for detecting the voltage value of the start pulse signal. Refer to Figure 4 , the delay module 2412 includes, for example, a delay resistor RD and a capacitor C. One end of the delay resistor RD receives the first start pulse signal STV0, and the other end is grounded through the capacitor C. The middle node of the delay resistor RD and the capacitor C is connected to the non-inverting input terminal of the first comparator U1 and the inverting input terminal of the second comparator U2. However, it should be understood that the delay module 2412 can also be other delay circuits, and the present application does not make excessive limitations.

[0049] The trigger unit 242 is connected to the detection unit 241, receives the detection signal DS and the first clock signal CLK0, and provides a trigger signal TS according to the detection signal DS at the active edge of the first clock signal CLK0. Among them, at the active edge of the first clock signal CLK0, the trigger unit 242 generates a valid trigger signal according to the detection signal DS of the first level.

[0050] The trigger unit 242 includes, for example, a single-edge-triggered D flip-flop. The data input terminal of the D flip-flop receives the detection signal DS, the clock input terminal receives the first clock signal CLK0, and the inverted output terminal outputs the trigger signal TS. Correspondingly, the valid level of the trigger signal is a high level.

[0051] The voltage domain in which the trigger unit 242 operates is the same as the voltage domain in which the second start pulse signal STV1 operates. That is, the high potential level of the trigger signal TS is the same as the high potential level of the second start pulse signal STV1, and the low potential level of the trigger signal TS is also the same as the low potential level of the second start pulse signal STV1. Therefore, even when the first start pulse signal STV0 operates in a smaller voltage domain, the trigger signal TS output by the trigger unit 242 can be adapted to the second start pulse signal STV1 and the first clock signal CLK0.

[0052] Figure 6 A schematic waveform diagram of the trigger unit is shown. Combining Figure 6 , taking the rising edge of the first clock signal CLK0 as the trigger edge as an example, according to the working principle of the D flip-flop, only when the effective edge of the first clock signal CLK0 and the detection signal DS are at a low potential level, the high potential level of the trigger signal is provided, which can shield the potential influence of the first start pulse signal STV0 on the detection signal DS at the invalid edge, so that the effective trigger signal TS corresponds to the effective edge of the first start pulse signal STV0, that is, only corresponds to the effective edge of the second start pulse signal STV1.

[0053] The output module 243 receives the first clock signal CLK0 and the trigger signal TS, and generates the second clock signal CLK1. The output module 243 includes a switching transistor M1 and a seventh resistor R7. The control terminal of the switching transistor M1 receives the trigger signal TS, the first terminal receives the first clock signal CLK0, and the second terminal provides the second clock signal CLK1. The seventh resistor R7 is connected between the second terminal of the switching transistor M1 and the low-level power supply terminal. The potential of this low-level power supply terminal is, for example, the gate cut-off voltage VGL provided by the gate drive circuit 220 to the pixel.

[0054] Adapted to the above-mentioned trigger signal TS provided by the inverted output terminal of the D flip-flop, the switching transistor M1 is, for example, a P-type MOSFET. Still taking the trigger signal TS being effective at a high potential level as an example, when the trigger signal TS is invalid, the switching transistor M1 is turned on, and the second clock signal CLK1 follows the first clock signal CLK0; when the trigger signal TS is effective, the switching transistor M2 is turned off, and the second clock signal CLK1 is pulled down to the low potential level VGL.

[0055] In some embodiments, the output module 243 further includes an eighth resistor R8, and the first clock signal CLK0 is provided to the first terminal of the switching transistor M1 through the eighth resistor R8. The resistance value of the eighth resistor R8 is, for example, 1 nΩ, which can not only avoid damage to the switching transistor M1 caused by fluctuations in the first clock signal CLK0, but also reduce the loss of the first clock signal CLK0.

[0056] Figure 7 A schematic waveform diagram of the clock synchronization circuit is shown. Refer toFigure 7 , according to the signal synchronization circuit provided by the present application, the detection unit detects the potential state of the start pulse signal and controls the output of the second clock signal CLK1 according to the detection result. The low level of the second clock signal CLK1 is maintained at the valid edge of the first start pulse signal STV0, thereby avoiding the display abnormality caused by the clock signal that is not at the low level potential at the valid edge of the first start pulse signal STV0, that is, at the valid edge of the second start pulse signal STV1, which is beneficial to improving the display effect.

[0057] The present application also provides a driving method for a display panel. In some embodiments, the driving method can be implemented by the above driving circuit. Figure 8 The schematic flowchart showing the display driving method of the embodiment of the present application is referred to Figure 8 , the driving method includes the following steps:

[0058] In step S11, the first start pulse signal, the second start pulse signal, and the first clock signal provided by the timing control circuit are obtained. Among them, the timings of the first start pulse signal and the second start pulse signal are the same. In some embodiments, the second start pulse signal can be multiplexed as the first start pulse signal; in some embodiments, the voltage domain in which the first start pulse signal operates is smaller than the voltage domain in which the second start pulse signal operates.

[0059] In step S12, the first start pulse signal is detected, and when the voltage value of the first start pulse signal is within a preset range, a detection signal with a first level is generated. Among them, when the first start pulse signal is within the preset range, it indicates that the voltage value of the first start pulse signal has changed, and it can be determined that the first start pulse signal is at the rising edge or the falling edge at this time. Correspondingly, the second start pulse signal is also at the rising edge or the falling edge at this time

[0060] In step S13, at the valid edge of the first clock signal, a valid trigger signal is generated according to the detection signal with the first level.

[0061] Taking the valid edge of the first clock signal as one of the conditions for outputting the valid trigger signal can shield the potential influence of the invalid edge of the start pulse signal on the detection signal, so that the valid trigger signal only corresponds to the valid edges of the first start pulse signal and the second start pulse signal. It should be noted that the voltage domain in which the trigger signal operates is the same as the voltage domain in which the second pulse signal operates.

[0062] In step S14, a second clock signal is generated based on a trigger signal and a first clock signal. Among them, when the trigger signal is invalid, the second clock signal changes following the first clock signal; when the trigger signal is valid, the second clock signal is pulled down to a low level. This low level is, for example, the gate cut-off voltage VGL provided by the gate driving circuit to the pixel.

[0063] Step S15, select / turn off corresponding pixels on the display panel according to the second start pulse signal and the second clock signal.

[0064] According to the driving method provided by the present application, the potential state of the first start pulse signal is detected, and the output of the second clock signal is controlled according to the detection result, so as to maintain the low-level output of the second clock signal at the effective edge of the first start pulse signal, that is, the effective edge of the second start pulse signal, to avoid display anomalies at high temperatures caused by clock signals that are not at a low potential, which is beneficial to improving the display effect.

[0065] As described above in accordance with the embodiments of the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to only the specific embodiments. Obviously, many modifications and variations can be made according to the above description. The present specification selects and specifically describes these embodiments in order to better explain the principle and practical application of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The protection scope of the present application shall be subject to the scope defined by the claims of the present application.

Claims

1. A clock synchronization circuit, wherein: The clock synchronization circuit is connected between the timing control circuit and the gate driving circuit, the timing control circuit generates a first clock signal and a first start pulse signal and a second start pulse signal with the same timing, the clock synchronization circuit receives the first start pulse signal and the first clock signal, and provides a second clock signal to the gate driving circuit, Wherein, the clock synchronization circuit comprises: a detection unit, configured to receive the first start pulse signal, and generate a detection signal having a first level when a voltage value of the first start pulse signal is within a preset range; a trigger unit, configured to receive the first clock signal and the detection signal, wherein the trigger unit is configured to generate a valid trigger signal according to the detection signal of a first level at a valid edge of the first clock signal; and an output unit, configured to generate the second clock signal according to the first clock signal and the trigger signal, wherein the second clock signal and the second start pulse signal are used to turn on / off pixels of the display panel, The output unit is used to control the second clock signal to follow the change of the first clock signal when the trigger signal is invalid, and to pull the second clock signal down to a low level when the trigger signal is valid.

2. The clock synchronization circuit according to claim 1, wherein: The second start pulse signal is multiplexed into the first start pulse signal.

3. The clock synchronization circuit according to claim 1, wherein: The detection unit comprises: A first comparator, wherein a non-inverting input terminal receives the first start pulse signal, and an inverting input terminal receives a first reference voltage; A second comparator, wherein the non-inverting input terminal receives the second reference voltage, and the inverting input terminal receives the first start pulse signal; a first resistor, wherein a first end of the first resistor is connected to an output end of the first comparator; a second resistor, a first end of the second resistor being connected to an output end of the second comparator; and A third resistor, wherein a first end of the third resistor is connected to the second end of the first resistor and the second end of the second resistor and provides the detection signal, and a second end of the third resistor is grounded.

4. The clock synchronization circuit according to claim 3, wherein: The detection unit further includes a delay module, and the first start pulse signal is provided to the first comparator and the second comparator via the delay module.

5. The clock synchronization circuit according to claim 1, wherein: The trigger unit comprises a D trigger, wherein a data input terminal of the D trigger receives the detection signal, a clock input terminal receives the first clock signal, and an inverting output terminal provides the trigger signal.

6. The clock synchronization circuit according to claim 5, wherein: The voltage domain in which the trigger unit operates is the same as the voltage domain in which the second start pulse signal operates, and the voltage domain is greater than the voltage domain in which the first start pulse signal operates.

7. The clock synchronization circuit according to claim 1, wherein: The output unit comprises: A switch tube, a control end receiving the trigger signal, a first end receiving the first clock signal, and a second end providing the second clock signal; and A seventh resistor is connected between the second end of the switch tube and the low-level power supply end.

8. The clock synchronization circuit according to claim 7, wherein: The output unit further includes: an eighth resistor, and the first clock signal is provided to the first end of the switch tube via the eighth resistor.

9. A driving circuit for a display panel, wherein: include: A timing control circuit, used for generating a first clock signal and a first start pulse signal and a second start pulse signal having the same timing; The clock synchronization circuit according to any one of claims 1 to 8, connected to the timing control circuit, and configured to generate a second clock signal according to the first start pulse signal and the first clock signal; as well as The gate driving circuit is connected to the timing control circuit and the clock synchronization circuit, and provides a scanning signal to the display panel according to the second start pulse signal and the second clock signal. The pixels of the display panel are turned on or off according to the corresponding scanning signal.

10. A driving method for a display panel, wherein: include: Acquire a first start pulse signal, a second start pulse signal and a first clock signal provided by a timing control circuit, wherein the first start pulse signal and the second start pulse signal have the same timing; Detecting the start pulse signal, and generating a detection signal with a first level when the voltage value of the start pulse signal is within a preset range; At a valid edge of the first clock signal, generating a valid trigger signal according to the detection signal of the first level; generating the second clock signal according to the trigger signal and the first clock signal; as well as turning on / off corresponding pixels on the display panel according to the second start pulse signal and the second clock signal, When the trigger signal is invalid, the second clock signal changes along with the first clock signal, and when the trigger signal is valid, the second clock signal is pulled down to a low level.

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