Pixel circuit, driving method and display device

Abstract

According to the pixel circuit, the driving method and the display device provided by the invention, a scanning control circuit responds to a signal of a scanning signal end, and provides a data signal of a data signal end to a first latch circuit and a second latch circuit; the first latch circuit responds to a first voltage or a second voltage of a data signal, provides a signal of a second power supply voltage end to the first switch control circuit, responds to a third voltage of the data signal, and provides a signal of a third power supply voltage end to the first switch control circuit; the second latch circuit responds to a first voltage of the data signal, provides a signal of a first power supply voltage end to the second switch control circuit, responds to a second voltage or a third voltage of the data signal, and provides a signal of a third power supply voltage end to the second switch control circuit; the first switch control circuit connects or disconnects the fourth power supply voltage end and the first node; the second switch control circuit connects or disconnects the first node and the second node.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a pixel circuit, a driving method, and a display device. Background Art

[0002] Light-emitting devices such as organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), micro light-emitting diodes (Micro LEDs), and mini light-emitting diodes (Mini LEDs) have advantages such as self-luminescence and low power consumption, and are one of the hotspots in the field of application research of current display devices. In general display devices, pixel circuits are used to drive light-emitting devices to emit light. Summary of the Invention

[0003] The pixel circuit provided by an embodiment of the present disclosure includes: a light-emitting device, a first switch control circuit, a second switch control circuit, a first latch circuit, a second latch circuit, and a scan control circuit;

[0004] The scan control circuit is coupled to the first latch circuit and the second latch circuit, and is configured to provide a data signal of a data signal terminal to the first latch circuit and the second latch circuit in response to a signal of a scan signal terminal;

[0005] The first latch circuit is coupled to the first switch control circuit, and is configured to provide a signal of a second power supply voltage terminal to the first switch control circuit in response to a first voltage or a second voltage of the data signal, and provide a signal of a third power supply voltage terminal to the first switch control circuit in response to a third voltage of the data signal;

[0006] The second latch circuit is coupled to the second switch control circuit, and is configured to provide a signal of a first power supply voltage terminal to the second switch control circuit in response to a first voltage of the data signal, and provide a signal of the third power supply voltage terminal to the second switch control circuit in response to a second voltage or a third voltage of the data signal;

[0007] The first switch control circuit is coupled to a first node, and is configured to conduct or disconnect a fourth power supply voltage terminal and the first node in response to a signal of a first light-emitting control signal terminal and a signal output by the first latch circuit;

[0008] The second switch control circuit, coupled to the first node, the second node, and the light-emitting device, is configured to turn on or off the connection between the first node and the second node in response to a signal output by the second latch circuit.

[0009] In some possible embodiments, the scan control circuit includes: a first transistor and a second transistor;

[0010] The gate of the first transistor is coupled to the scan signal terminal, the first pole of the first transistor is coupled to the data signal terminal, and the second pole of the first transistor is coupled to the first latch circuit;

[0011] The gate of the second transistor is coupled to the scan signal terminal, the first pole of the second transistor is coupled to the data signal terminal, and the second pole of the second transistor is coupled to the second latch circuit.

[0012] In some possible embodiments, the first latch circuit includes: a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;

[0013] The gate of the third transistor is coupled to the scan control circuit, the first pole of the third transistor is coupled to the third power supply voltage terminal, and the second pole of the third transistor is coupled to the first pole of the fifth transistor;

[0014] The gate of the fourth transistor is coupled to the second pole of the third transistor, the first pole of the fourth transistor is coupled to the second power supply voltage terminal, and the second pole of the fourth transistor is coupled to the scan control circuit;

[0015] The gate of the fifth transistor is coupled to the scan control circuit, and the second pole of the fifth transistor is coupled to the second power supply voltage terminal;

[0016] The gate of the sixth transistor is coupled to the first pole of the fifth transistor, the first pole of the sixth transistor is coupled to the scan control circuit, and the second pole of the sixth transistor is coupled to the third power supply voltage terminal.

[0017] In some possible embodiments, the second latch circuit includes: a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

[0018] The gate of the seventh transistor is coupled to the scan control circuit, the first pole of the seventh transistor is coupled to the third power supply voltage terminal, and the second pole of the seventh transistor is coupled to the first pole of the ninth transistor;

[0019] The gate of the eighth transistor is coupled to the second pole of the seventh transistor, the first pole of the eighth transistor is coupled to the first power supply voltage terminal, and the second pole of the eighth transistor is coupled to the scan control circuit;

[0020] The gate of the ninth transistor is coupled to the scan control circuit, and the second pole of the ninth transistor is coupled to the first power supply voltage terminal;

[0021] The gate of the tenth transistor is coupled to the first pole of the ninth transistor, the first pole of the tenth transistor is coupled to the scan control circuit, and the second pole of the tenth transistor is coupled to the third power supply voltage terminal.

[0022] In some possible embodiments, the first switch control circuit includes: an eleventh transistor and a twelfth transistor;

[0023] The gate of the eleventh transistor is coupled to the first latch circuit, the first pole of the eleventh transistor is coupled to the fourth power supply voltage terminal, and the second pole of the eleventh transistor is coupled to the first node;

[0024] The gate of the twelfth transistor is coupled to the first light emission control signal terminal, the first pole of the twelfth transistor is coupled to the fourth power supply voltage terminal, and the second pole of the twelfth transistor is coupled to the first node.

[0025] In some possible embodiments, the second switch control circuit includes: a thirteenth transistor;

[0026] The gate of the thirteenth transistor is coupled to the second latch circuit, the first pole of the thirteenth transistor is coupled to the first node, and the second pole of the thirteenth transistor is coupled to the second node.

[0027] In some possible embodiments, it further includes: a light emission control circuit, coupled to the second node and the light emitting device, and configured to conduct the second node and the light emitting device in response to a signal from the second light emission control signal terminal.

[0028] In some possible embodiments, the light emission control circuit includes: a fourteenth transistor;

[0029] The gate of the fourteenth transistor is coupled to the second light emission control signal terminal, the first pole of the fourteenth transistor is coupled to the second node, and the second pole of the fourteenth transistor is coupled to the light emitting device.

[0030] In some possible embodiments, the first voltage is less than the second voltage, and the second voltage is less than the third voltage.

[0031] The driving method of the pixel circuit provided by the embodiments of the present disclosure includes:

[0032] The scan control circuit provides the data signal of the data signal terminal to the first latch circuit and the second latch circuit in response to the signal of the scan signal terminal;

[0033] When the voltage of the data signal is the first voltage, the first latch circuit provides the signal of the second power supply voltage terminal to the first switch control circuit; the second latch circuit provides the signal of the first power supply voltage terminal to the second switch control circuit; the first switch control circuit conducts the fourth power supply voltage terminal and the first node in response to the signal of the first light emission control signal terminal; the second switch control circuit disconnects the first node and the second node in response to the signal output by the second latch circuit;

[0034] When the voltage of the data signal is the second voltage, the first latch circuit provides the signal of the second power supply voltage terminal to the first switch control circuit; the second latch circuit provides the signal of the third power supply voltage terminal to the second switch control circuit; the first switch control circuit conducts the fourth power supply voltage terminal and the first node in response to the signal of the first light emission control signal terminal; the second switch control circuit conducts the first node and the second node in response to the signal output by the second latch circuit;

[0035] When the voltage of the data signal is the third voltage, the first latch circuit provides the signal of the third power supply voltage terminal to the first switch control circuit; the second latch circuit provides the signal of the third power supply voltage terminal to the first switch control circuit; the first switch control circuit conducts the fourth power supply voltage terminal and the first node in response to the signal of the first light emission control signal terminal and the signal output by the first latch circuit; the second switch control circuit conducts the first node and the second node in response to the signal output by the second latch circuit.

[0036] The display device provided by the embodiments of the present disclosure includes the above pixel circuit. Description of the Drawings

[0037] Figure 1 Some structural schematic diagrams of the light-emitting device provided by the embodiments of the present disclosure;

[0038] Figure 2 Some curve schematic diagrams provided by the embodiments of the present disclosure;

[0039] Figure 3 Some other structural schematic diagrams of the light-emitting device provided by the embodiments of the present disclosure;

[0040] Figure 4 Some other curve schematic diagrams provided by the embodiments of the present disclosure;

[0041] Figure 5 Some structural schematic diagrams of the pixel circuit provided by the embodiments of the present disclosure;

[0042] Figure 6 Some other structural schematic diagrams of the pixel circuit provided by the embodiments of the present disclosure;

[0043] Figure 7 Some other structural schematic diagrams of the pixel circuit provided by the embodiments of the present disclosure;

[0044] Figure 8 Some other structural schematic diagrams of the pixel circuit provided by the embodiments of the present disclosure;

[0045] Figure 9 Flowchart of the driving method of the pixel circuit provided by the embodiments of the present disclosure;

[0046] Figure 10 Some signal timing diagrams provided by the embodiments of the present disclosure;

[0047] Figure 11 Some other signal timing diagrams provided by the embodiments of the present disclosure. Detailed implementation manners

[0048] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. And without conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0049] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. The terms such as "include" or "comprise" mean that the elements or objects appearing before the term cover the elements or objects listed after the term and their equivalents, without excluding other elements or objects. The terms such as "connect" or "couple" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0050] It should be noted that the sizes and shapes of the figures in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the present disclosure. Also, the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0051] The display device provided by an embodiment of the present disclosure includes: a display panel, and a display area of the display panel includes a plurality of pixel units arranged in an array. Exemplarily, each pixel unit includes a plurality of sub-pixels. For example, a pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that color mixing can be performed through red, green, and blue to achieve color display. Or, a pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that color mixing can be performed through red, green, blue, and white to achieve color display. Of course, in actual applications, the emission colors of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, which is not limited herein.

[0052] In an embodiment of the present disclosure, each sub-pixel includes a pixel circuit, and the pixel circuit drives a light-emitting device to emit light, so that the display panel realizes the function of displaying an image.

[0053] Exemplarily, as Figure 1 shown, currently, a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), etc. may include a first semiconductor layer n-GaN, an active layer MQW, a first semiconductor layer p-GaN, an electrode layer ITO, and a display panel 100; wherein, the line segment with an arrow represents current; as Figure 1 shown, the light-emitting diode has a large light-emitting area and a small current density, so its power consumption is high and its luminous efficiency is low. And its gray-scale modulation is distributed in the I segment as Figure 2 shown. Wherein, Figure 2 the abscissa x represents the current density, and the unit is mA / cm 2 ; the ordinate y represents the luminous efficiency, and the unit is cd / A; D represents the optimal light efficiency point; when the gray-scale voltage is L255, the light-emitting area of the display device is 100%.

[0054] Exemplarily, as Figure 3 shown, the future improvement direction is to reduce the area of the electrode layer ITO in the light-emitting diode, then as Figure 3 shown, the light-emitting area of the light-emitting diode will decrease and the current density will increase, so its luminous efficiency will increase accordingly. And its gray-scale modulation is distributed in the II segment as Figure 2 shown. When the gray-scale voltage is L255, the light-emitting area of the display device is 25%.

[0055] Exemplarily, when low gray-scale voltage is used for display, the brightness of the light-emitting diode is low, the current density is low, and the luminous efficiency is also greatly reduced. Since the current density passing through the light-emitting diode is different when different gray-scale voltages are used, a chromaticity drift problem will occur. As Figure 4 shown, x represents the current density and y represents the chromaticity drift; when the gray-scale voltage changes from L0 to L255, the current density gradually increases while the chromaticity drift gradually decreases. Currently, the light-emitting diode has the characteristics of a large light-emitting area and a small current density. Therefore, the chromaticity drift of the current light-emitting diode is relatively large, and it also has high power consumption and low luminous efficiency. Therefore, improvement is still needed.

[0056] Based on the above problems, the pixel circuit provided by the embodiments of the present disclosure, as Figure 5 shown, includes: a light-emitting device L, a first switch control circuit 10, a second switch control circuit 20, a first latch circuit 30, a second latch circuit 40, and a scan control circuit 50;

[0057] The scan control circuit 50 is coupled to the first latch circuit 30 and the second latch circuit 40 and is configured to provide the data signal of the data signal terminal DA to the first latch circuit 30 and the second latch circuit 40 in response to the signal of the scan signal terminal SS(n);

[0058] The first latch circuit 30 is coupled to the first switch control circuit 10 and is configured to provide the signal of the second power supply voltage terminal VSS to the first switch control circuit 10 in response to the first voltage or the second voltage of the data signal, and provide the signal of the third power supply voltage terminal VGH to the first switch control circuit in response to the third voltage of the data signal;

[0059] The second latch circuit 40 is coupled to the second switch control circuit 20 and is configured to provide the signal of the first power supply voltage terminal VGL to the second switch control circuit 20 in response to the first voltage of the data signal, and provide the signal of the third power supply voltage terminal VGH to the second switch control circuit in response to the second voltage or the third voltage of the data signal;

[0060] The first switch control circuit 10 is coupled to the first node N1 and is configured to conduct or disconnect the fourth power supply voltage terminal VDD and the first node N1 in response to the signal of the first light-emitting control signal terminal HF and the signal output by the first latch circuit 30;

[0061] The second switch control circuit 20 is coupled to the first node N1, the second node N2, and the light-emitting device L and is configured to conduct or disconnect the first node N1 and the second node N2 in response to the signal output by the second latch circuit 40.

[0062] In the embodiments of the present disclosure, through the mutual cooperation of the first switch control circuit, the second switch control circuit, the first latch circuit, the second latch circuit, and the scan control circuit, the current in the pixel circuit can operate in the high-efficiency region, ensuring that there are only two states in the pixel circuit: a relatively large current and off states, which can increase the current density, thereby saving power consumption, improving the luminous efficiency, and improving the chromaticity drift problem, and further improving the display effect.

[0063] Exemplarily, as Figure 5 shown, the anode of the light-emitting device L is coupled to the second node N2, and the cathode of the light-emitting device L is coupled to the second power supply voltage terminal VSS. Exemplarily, the light-emitting device L may include at least one of a micro light-emitting diode (Micro LED), an organic light-emitting diode (OLED), and a quantum dot light-emitting diode (QLED). Exemplarily, the light-emitting device L may include an anode, a light-emitting layer, and a cathode stacked. Further, the light-emitting layer may further include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. In practical applications, the specific structure of the light-emitting device can be designed and determined according to the actual application environment, which is not limited herein.

[0064] It should be noted that the voltage of the signal of the first power supply voltage terminal VGL is the same as the first voltage of the data signal, that is, the voltage of the signal of the first power supply voltage terminal VGL is also the first voltage; the voltage of the signal of the second power supply voltage terminal VSS is the same as the second voltage of the data signal, that is, the voltage of the signal of the second power supply voltage terminal VSS is also the second voltage; the voltage of the signal of the third power supply voltage terminal VGH is the same as the third voltage of the data signal, that is, the voltage of the signal of the third power supply voltage terminal VGH is also the third voltage.

[0065] In the embodiments of the present disclosure, as Figure 6 shown, the scan control circuit 50 includes: a first transistor M1 and a second transistor M2; wherein, the gate of the first transistor M1 is coupled to the scan signal terminal SS(n), the first pole of the first transistor M1 is coupled to the data signal terminal DA, and the second pole of the first transistor M1 is coupled to the first latch circuit 30; the gate of the second transistor M2 is coupled to the scan signal terminal SS(n), the first pole of the second transistor M2 is coupled to the data signal terminal DA, and the second pole of the second transistor M2 is coupled to the second latch circuit 40.

[0066] Exemplarily, the first transistor M1 can be turned on under the control of the effective level of the scan signal transmitted by the scan signal terminal SS(n), and can be turned off under the control of the invalid level of the scan signal. Exemplarily, if the first transistor M1 is set as a P-type transistor, the effective level of the scan signal is a low level, and the invalid level of the scan signal is a high level. Alternatively, if the first transistor M1 is set as an N-type transistor, the effective level of the scan signal is a high level, and the invalid level of the scan signal is a low level.

[0067] Exemplarily, the second transistor M2 can be turned on under the control of the effective level of the scan signal transmitted by the scan signal terminal SS(n), and can be turned off under the control of the invalid level of the scan signal. Exemplarily, if the second transistor M2 is set as an N-type transistor, the effective level of the scan signal is a high level, and the invalid level of the scan signal is a low level. Alternatively, if the second transistor M2 is set as a P-type transistor, the effective level of the scan signal is a low level, and the invalid level of the scan signal is a high level.

[0068] In the embodiment of the present disclosure, as Figure 6 shown, the first latch circuit 30 includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6; wherein, the gate of the third transistor M3 is coupled to the scan control circuit 50, the first pole of the third transistor M3 is coupled to the third power supply voltage terminal VGH, and the second pole of the third transistor M3 is coupled to the first pole of the fifth transistor M5; the gate of the fourth transistor M4 is coupled to the second pole of the third transistor M3, the first pole of the fourth transistor M4 is coupled to the second power supply voltage terminal VSS, and the second pole of the fourth transistor M4 is coupled to the scan control circuit 50; the gate of the fifth transistor M5 is coupled to the scan control circuit 50, the second pole of the fifth transistor M5 is coupled to the second power supply voltage terminal VSS; the gate of the sixth transistor M6 is coupled to the first pole of the fifth transistor M5, the first pole of the sixth transistor M6 is coupled to the scan control circuit 50, and the second pole of the sixth transistor M6 is coupled to the third power supply voltage terminal VGH.

[0069] Exemplarily, the third transistor M3 can be turned on under the control of the effective level of the data signal transmitted by the scan control circuit 50, and can be turned off under the control of the invalid level of the data signal. Exemplarily, if the third transistor M3 is set as an N-type transistor, the effective level of the data signal is a high level, and the invalid level of the data signal is a low level. Alternatively, if the third transistor M3 is set as a P-type transistor, the effective level of the data signal is a low level, and the invalid level of the data signal is a high level.

[0070] Exemplarily, the fourth transistor M4 can be turned on under the control of the effective level of the data signal transmitted by the scan control circuit 50, and can be turned off under the control of the invalid level of the data signal. Exemplarily, if the fourth transistor M4 is set as an N-type transistor, the effective level of the data signal is a high level, and the invalid level of the data signal is a low level. Alternatively, if the fourth transistor M4 is set as a P-type transistor, the effective level of the data signal is a low level, and the invalid level of the data signal is a high level.

[0071] Exemplarily, the fifth transistor M5 can be turned on under the control of the effective level of the data signal transmitted by the scan control circuit 50, and can be turned off under the control of the invalid level of the data signal. Exemplarily, if the fifth transistor M5 is set as an N-type transistor, the effective level of the data signal is a high level, and the invalid level of the data signal is a low level. Alternatively, if the fifth transistor M5 is set as a P-type transistor, the effective level of the data signal is a low level, and the invalid level of the data signal is a high level.

[0072] Exemplarily, the sixth transistor M6 can be turned on under the control of the effective level of the data signal transmitted by the scan control circuit 50, and can be turned off under the control of the invalid level of the data signal. Exemplarily, if the sixth transistor M6 is set as an N-type transistor, the effective level of the data signal is a high level, and the invalid level of the data signal is a low level. Alternatively, if the sixth transistor M6 is set as a P-type transistor, the effective level of the data signal is a low level, and the invalid level of the data signal is a high level.

[0073] In the embodiments of the present disclosure, as Figure 6 shown, the second latch circuit 40 includes: a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10; wherein, the gate of the seventh transistor M7 is coupled to the scan control circuit 50, the first pole of the seventh transistor M7 is coupled to the third power supply voltage terminal VGH, and the second pole of the seventh transistor M7 is coupled to the first pole of the ninth transistor M9; the gate of the eighth transistor M8 is coupled to the second pole of the seventh transistor M7, the first pole of the eighth transistor M8 is coupled to the first power supply voltage terminal VGL, and the second pole of the eighth transistor M8 is coupled to the scan control circuit 50; the gate of the ninth transistor M9 is coupled to the scan control circuit 50, the second pole of the ninth transistor M9 is coupled to the first power supply voltage terminal VGL, the gate of the tenth transistor M10 is coupled to the first pole of the ninth transistor M9, the first pole of the tenth transistor M10 is coupled to the scan control circuit 50, and the second pole of the tenth transistor M10 is coupled to the third power supply voltage terminal VGH.

[0074] Exemplarily, the seventh transistor M7 can be turned on under the control of the active level of the data signal transmitted by the scan control circuit 50, and can be turned off under the control of the inactive level of the data signal. Exemplarily, if the seventh transistor M7 is set as an N-type transistor, the active level of the data signal is a high level, and the inactive level of the data signal is a low level. Alternatively, if the seventh transistor M7 is set as a P-type transistor, the active level of the data signal is a low level, and the inactive level of the data signal is a high level.

[0075] Exemplarily, the eighth transistor M8 can be turned on under the control of the active level of the data signal transmitted by the scan control circuit 50, and can be turned off under the control of the inactive level of the data signal. Exemplarily, if the eighth transistor M8 is set as an N-type transistor, the active level of the data signal is a high level, and the inactive level of the data signal is a low level. Alternatively, if the eighth transistor M8 is set as a P-type transistor, the active level of the data signal is a low level, and the inactive level of the data signal is a high level.

[0076] Exemplarily, the ninth transistor M9 can be turned on under the control of the active level of the data signal transmitted by the scan control circuit 50, and can be turned off under the control of the inactive level of the data signal. Exemplarily, if the ninth transistor M9 is set as an N-type transistor, the active level of the data signal is a high level, and the inactive level of the data signal is a low level. Alternatively, if the ninth transistor M9 is set as a P-type transistor, the active level of the data signal is a low level, and the inactive level of the data signal is a high level.

[0077] Exemplarily, the tenth transistor M10 can be turned on under the control of the active level of the data signal transmitted by the scan control circuit 50, and can be turned off under the control of the inactive level of the data signal. Exemplarily, if the tenth transistor M10 is set as an N-type transistor, the active level of the data signal is a high level, and the inactive level of the data signal is a low level. Alternatively, if the tenth transistor M10 is set as a P-type transistor, the active level of the data signal is a low level, and the inactive level of the data signal is a high level.

[0078] In the embodiment of the present disclosure, as Figure 6 shown, the first switch control circuit 10 includes: an eleventh transistor M11 and a twelfth transistor M12; wherein, the gate of the eleventh transistor M11 is coupled to the first latch circuit 30, the first pole of the eleventh transistor M11 is coupled to the fourth power supply voltage terminal VDD, and the second pole of the eleventh transistor M11 is coupled to the first N1 node; the gate of the twelfth transistor M12 is coupled to the first light emission control signal terminal HF, the first pole of the twelfth transistor M12 is coupled to the fourth power supply voltage terminal VDD, and the second pole of the twelfth transistor M12 is coupled to the first N1 node.

[0079] Exemplarily, the eleventh transistor T11 can be turned on under the control of the effective level of the signal transmitted by the first latch circuit 30 and can be turned off under the control of the invalid level of the signal transmitted by the first latch circuit 30. Exemplarily, if the eleventh transistor T11 is set as an N-type transistor, the effective level of the signal transmitted by the first latch circuit 30 is a high level, and the invalid level of the signal transmitted by the first latch circuit 30 is a low level. Alternatively, if the eleventh transistor T11 is set as a P-type transistor, the effective level of the signal transmitted by the first latch circuit 30 is a low level, and the invalid level of the signal transmitted by the first latch circuit 30 is a high level.

[0080] Exemplarily, the twelfth transistor T12 can be turned on under the control of the effective level of the first light emission control signal transmitted by the first light emission control signal terminal HF and can be turned off under the control of the invalid level of the first light emission control signal. Exemplarily, if the twelfth transistor T12 is set as an N-type transistor, the effective level of the first light emission control signal is a high level, and the invalid level of the first light emission control signal is a low level. Alternatively, if the twelfth transistor T12 is set as a P-type transistor, the effective level of the first light emission control signal is a low level, and the invalid level of the first light emission control signal is a high level.

[0081] In the embodiments of the present disclosure, as Figure 6 shown, the second switch control circuit 20 includes: a thirteenth transistor M13; wherein, the gate of the thirteenth transistor M13 is coupled to the second latch circuit 40, the first pole of the thirteenth transistor M13 is coupled to the first node N1, and the second pole of the thirteenth transistor M13 is coupled to the second node N2.

[0082] Exemplarily, the thirteenth transistor M13 can be turned on under the control of the effective level of the signal transmitted by the second latch circuit 40 and can be turned off under the control of the invalid level of the signal transmitted by the second latch circuit 40. Exemplarily, if the thirteenth transistor M13 is set as an N-type transistor, the effective level of the signal transmitted by the second latch circuit 40 is a high level, and the invalid level of the signal transmitted by the second latch circuit 40 is a low level. Alternatively, if the thirteenth transistor M13 is set as a P-type transistor, the effective level of the signal transmitted by the second latch circuit 40 is a low level, and the invalid level of the signal transmitted by the second latch circuit 40 is a high level.

[0083] In the embodiments of the present disclosure, the first voltage is less than the second voltage, and the second voltage is less than the third voltage.

[0084] The embodiments of the present disclosure further provide some structural schematic diagrams of the pixel circuit, as Figure 7 and Figure 8 shown, which are deformations of the implementation manners in the above embodiments. Only the differences between this embodiment and the above embodiments will be described below, and the substantially same parts will not be elaborated herein.

[0085] In the embodiments of the present disclosure, as Figure 7 shown, it further includes: a light emission control circuit 60, coupled to the second node N2 and the light emitting device L, and configured to turn on the second node N2 and the light emitting device L in response to a signal of the second light emission control signal terminal EM(n).

[0086] In the embodiments of the present disclosure, as Figure 8 shown, the light emission control circuit 60 includes: a fourteenth transistor M14; wherein, the gate of the fourteenth transistor M14 is coupled to the second light emission control signal terminal EM(n), the first pole of the fourteenth transistor M14 is coupled to the second node N2, and the second pole of the fourteenth transistor M14 is coupled to the light emitting device L.

[0087] Exemplarily, the first pole of the above transistor may be its source, and the second pole may be its drain. Or, the first pole is its drain and the second pole is its source. This is not limited herein.

[0088] Generally, a transistor using a low temperature poly-silicon (LTPS) material as the active layer has a high mobility and can be made thinner, smaller, and lower in power consumption, etc. In specific implementation, the material of the active layer of the above at least one transistor may be set to a low temperature poly-silicon material. In this way, the above transistor can be set as an LTPS type transistor, so that the pixel circuit can achieve high mobility and can be made thinner, smaller, and lower in power consumption, etc.

[0089] Generally, a transistor using a metal oxide semiconductor material as the active layer has a small leakage current. Therefore, in some embodiments of the present disclosure, the material of the active layer of the above at least one transistor may also include a metal oxide semiconductor material, for example, it may be IGZO (Indium Gallium Zinc Oxide), and of course, it may also be other metal oxide semiconductor materials, which is not limited herein. In this way, the above transistor can be set as an oxide type transistor (Oxide Thin Film Transistor), so that the leakage current of the pixel circuit is reduced.

[0090] Exemplarily, all transistors may be set as LTPS type transistors. Or, all transistors may be set as oxide type transistors. Or, some transistors may be set as oxide type transistors and the remaining transistors may be set as LTPS type transistors.

[0091] In the embodiments of the present disclosure, as Figure 9 shown, the embodiments of the present disclosure provide a driving method for a pixel circuit, including:

[0092] S100. The scanning control circuit provides the data signal at the data signal terminal to the first latch circuit and the second latch circuit in response to the signal at the scanning signal terminal;

[0093] S200. When the voltage of the data signal is the first voltage, the first latch circuit provides the signal at the second power supply voltage terminal to the first switch control circuit; the second latch circuit provides the signal at the first power supply voltage terminal to the second switch control circuit; the first switch control circuit conducts the fourth power supply voltage terminal to the first node in response to the signal at the first light emission control signal terminal; the second switch control circuit disconnects the first node from the second node in response to the signal output by the second latch circuit;

[0094] S300. When the voltage of the data signal is the second voltage, the first latch circuit provides the signal at the second power supply voltage terminal to the first switch control circuit; the second latch circuit provides the signal at the third power supply voltage terminal to the second switch control circuit; the first switch control circuit conducts the fourth power supply voltage terminal to the first node in response to the signal at the first light emission control signal terminal; the second switch control circuit conducts the first node to the second node in response to the signal output by the second latch circuit;

[0095] S400. When the voltage of the data signal is the third voltage, the first latch circuit provides the signal at the third power supply voltage terminal to the first switch control circuit; the second latch circuit provides the signal at the third power supply voltage terminal to the first switch control circuit; the first switch control circuit conducts the fourth power supply voltage terminal to the first node in response to the signal at the first light emission control signal terminal and the signal output by the first latch circuit; the second switch control circuit conducts the first node to the second node in response to the signal output by the second latch circuit.

[0096] Next, taking the Figure 6 shown pixel circuit as an example and combining with the Figure 10 shown signal timing diagram, the working process of the pixel circuit provided by the embodiments of the present disclosure will be described.

[0097] In the embodiments of the present disclosure, as Figure 10 shown, ss(1) represents the scanning signal at the scanning signal terminal corresponding to the pixel circuit in the first row of sub-pixels, ss(2) represents the scanning signal at the scanning signal terminal corresponding to the pixel circuit in the second row of sub-pixels, ss(3) represents the scanning signal at the scanning signal terminal corresponding to the pixel circuit in the third row of sub-pixels, ss(n - 1) represents the scanning signal at the scanning signal terminal corresponding to the pixel circuit in the (n - 1)th row of sub-pixels, ss(n) represents the scanning signal at the scanning signal terminal corresponding to the pixel circuit in the nth row of sub-pixels, da represents the data signal at the data signal terminal DA, hf represents the first light emission control signal at the first light emission control signal terminal, and vdd represents the signal at the fourth power supply voltage terminal VDD.

[0098] Moreover, a sub-frame 1h in a display frame is selected for description.

[0099] Exemplarily, the first voltage is -13V, the second voltage is 0V, the third voltage is 15V, and the voltage of the signal of the fourth power supply voltage terminal VDD is 6V.

[0100] In a sub-frame 1h, the first transistor M1 and the second transistor M2 in the pixel circuits of each row of sub-pixels are both turned on under the control of the low level of the scanning signal at the corresponding scanning signal terminal; in sequence, the first transistor M1 and the second transistor M2 in the pixel circuit of the first row of sub-pixels are turned on under the control of the low level of the scanning signal ss(1), the first transistor M1 and the second transistor M2 in the pixel circuit of the second row of sub-pixels are turned on under the control of the low level of the scanning signal ss(2), the first transistor M1 and the second transistor M2 in the pixel circuit of the third row of sub-pixels are turned on under the control of the low level of the scanning signal ss(3),... the first transistor M1 and the second transistor M2 in the pixel circuit of the (n - 1)-th row of sub-pixels are turned on under the control of the low level of the scanning signal ss(n - 1), until the first transistor M1 and the second transistor M2 in the pixel circuit of the n-th row of sub-pixels are turned on under the control of the low level of the scanning signal ss(n); the turned-on first transistor M1 provides the data signal da at the data signal terminal DA to the first latch circuit 30; the turned-on second transistor M2 provides the data signal da at the data signal terminal DA to the second latch circuit 40;

[0101] When the voltage of the data signal da is the first voltage, the fifth transistor M5 is turned off under the control of the low level of the data signal da; the sixth transistor M6 is turned off; the third transistor M3 is turned on under the control of the low level of the data signal da, and the turned-on third transistor M3 supplies the signal of the third power supply voltage terminal VGH to the gate of the fourth transistor M4; the fourth transistor M4 is turned on under the control of the high level of the signal of the third power supply voltage terminal VGH, and the turned-on fourth transistor M4 supplies the signal of the second power supply voltage terminal VSS to the gate of the eleventh transistor M11; the eleventh transistor M11 is turned off under the control of the low level of the signal of the second power supply voltage terminal VSS, and the turned-off eleventh transistor M11 disconnects the fourth power supply voltage terminal VDD from the first node N1; the ninth transistor M9 is turned off under the control of the low level of the data signal da; the tenth transistor M10 is turned off; the seventh transistor M7 is turned on under the control of the low level of the data signal da, and the turned-on seventh transistor M7 supplies the signal of the third power supply voltage terminal VGH to the gate of the eighth transistor M8; the eighth transistor M8 is turned on under the control of the high level of the signal of the third power supply voltage terminal VGH, and the turned-on eighth transistor M8 supplies the signal of the second power supply voltage terminal VSS to the gate of the thirteenth transistor M13; the thirteenth transistor M13 is turned off under the control of the low level of the signal of the second power supply voltage terminal VSS, and the thirteenth transistor M13 disconnects the first node N1 from the second node N2; the twelfth transistor M12 is turned on under the control of the high level of the first light control signal hf, and the turned-on twelfth transistor M12 supplies the signal of the fourth power supply voltage terminal VDD to the first node N1. Then, when the voltage of the data signal da is the first voltage, the light-emitting device L does not emit light.

[0102] When the voltage of the data signal da is the second voltage, the fifth transistor M5 is turned off under the control of the low level of the data signal da; the sixth transistor M6 is turned off; the third transistor M3 is turned on under the control of the low level of the data signal da, and the turned-on third transistor M3 supplies the signal of the third power supply voltage terminal VGH to the gate of the fourth transistor M4; the fourth transistor M4 is turned on under the control of the high level of the signal of the third power supply voltage terminal VGH, and the turned-on fourth transistor M4 supplies the signal of the second power supply voltage terminal VSS to the gate of the eleventh transistor M11; the eleventh transistor M11 is turned off under the control of the low level of the signal of the second power supply voltage terminal VSS, and the turned-off eleventh transistor M11 disconnects the fourth power supply voltage terminal VDD from the first node N1; the seventh transistor M7 is turned off under the control of the high level of the data signal da; the eighth transistor M8 is turned off; the ninth transistor M9 is turned on under the control of the high level of the data signal da, and the turned-on ninth transistor M9 supplies the signal of the first power supply voltage terminal VGL to the gate of the tenth transistor M10; the tenth transistor M10 is turned on under the control of the low level of the signal of the first power supply voltage terminal VGL, and the turned-on tenth transistor M10 supplies the signal of the third power supply voltage terminal VGH to the gate of the thirteenth transistor M13; the thirteenth transistor M13 is turned on under the control of the high level of the signal of the third power supply voltage terminal VGH, and the turned-on thirteenth transistor M13 connects the first node N1 to the second node N2; the twelfth transistor M12 is turned on under the control of the high level of the first light control signal hf, and the turned-on twelfth transistor M12 supplies the signal of the fourth power supply voltage terminal VDD to the first node N1. Then, when the voltage of the data signal da is the second voltage and the signal of the fourth power supply voltage terminal VDD is a high-level signal, the light-emitting device L emits light. Wherein, the light-emitting duration of the light-emitting device L is the duration formed when both the signal of the fourth power supply voltage terminal VDD and the first light control signal hf are high levels.

[0103] It should be noted that since the voltage of the signal of the first power supply voltage terminal VGL is also the first voltage, the voltage of the signal of the second power supply voltage terminal VSS is also the second voltage, and the voltage of the signal of the third power supply voltage terminal VGH is also the third voltage; and the first voltage is less than the second voltage, and the second voltage is less than the third voltage; the first latch circuit has the second power supply voltage terminal VSS and the third power supply voltage terminal VGH, and the second power supply voltage terminal VSS is close to the voltage of the data signal da; therefore, when the data signal is the second voltage, the first latch circuit will output the signal of the second power supply voltage terminal VSS that is close to the second voltage of the data signal.

[0104] When the voltage of the data signal da is the third voltage, the third transistor M3 is turned off under the control of the high level of the data signal da; the fourth transistor M4 is turned off; the fifth transistor M5 is turned on under the control of the high level of the data signal da, and the conducting fifth transistor M5 supplies the signal of the second power supply voltage terminal VSS to the gate of the sixth transistor M6; the sixth transistor M6 is turned on under the control of the low level of the signal of the second power supply voltage terminal VSS, and the conducting sixth transistor M6 supplies the signal of the third power supply voltage terminal VGH to the gate of the eleventh transistor M11; the eleventh transistor M11 is turned on under the control of the high level of the signal of the third power supply voltage terminal VGH, and the conducting eleventh transistor M11 conducts the fourth power supply voltage terminal VDD and the first node N1; the seventh transistor M7 is turned off under the control of the high level of the data signal da; the eighth transistor M8 is turned off; the ninth transistor M9 is turned on under the control of the high level of the data signal da, and the conducting ninth transistor M9 supplies the signal of the first power supply voltage terminal VGL to the gate of the tenth transistor M10; the tenth transistor M10 is turned on under the control of the low level of the signal of the first power supply voltage terminal VGL, and the conducting tenth transistor M10 supplies the signal of the third power supply voltage terminal VGH to the gate of the thirteenth transistor M13; the thirteenth transistor M13 is turned on under the control of the high level of the signal of the third power supply voltage terminal VGH, and the conducting thirteenth transistor M13 conducts the first node N1 and the second node N2; the twelfth transistor M12 is turned on under the control of the high level of the first light control signal hf, and the conducting twelfth transistor M12 supplies the signal of the fourth power supply voltage terminal VDD to the first node N1. Then, when the voltage of the data signal da is the second voltage and the signal of the fourth power supply voltage terminal VDD is a high level signal, the light emitting device L emits light. Wherein, the light emitting duration of the light emitting device L is the duration when the signal of the fourth power supply voltage terminal VDD is at a high level.

[0105] Taking the Figure 8 pixel circuit shown below as an example, combined with the Figure 11 signal timing diagram shown, the working process of the pixel circuit provided by the embodiments of the present disclosure will be described.

[0106] In the embodiments of the present disclosure, as Figure 10As shown, ss(1) represents the scan signal of the scan signal terminal corresponding to the pixel circuit in the sub-pixels of the first row, ss(2) represents the scan signal of the scan signal terminal corresponding to the pixel circuit in the sub-pixels of the second row, ss(3) represents the scan signal of the scan signal terminal corresponding to the pixel circuit in the sub-pixels of the third row, ss(n - 1) represents the scan signal of the scan signal terminal corresponding to the pixel circuit in the sub-pixels of the (n - 1)-th row, ss(n) represents the scan signal of the scan signal terminal corresponding to the pixel circuit in the sub-pixels of the n-th row, em(1) represents the second light emission control signal of the second light emission control signal terminal corresponding to the pixel circuit in the sub-pixels of the first row, em(2) represents the second light emission control signal of the second light emission control signal terminal corresponding to the pixel circuit in the sub-pixels of the second row, em(n) represents the second light emission control signal of the second light emission control signal terminal corresponding to the pixel circuit in the sub-pixels of the n-th row, da represents the data signal of the data signal terminal DA, and hf represents the first light emission control signal of the first light emission control signal terminal.

[0107] Moreover, one sub-frame 1h in a display frame is selected for description.

[0108] In a sub-frame 1h, the first transistor M1 and the second transistor M2 in the pixel circuit of each row of sub-pixels are both turned on under the control of the low level of the scan signal of the corresponding scan signal terminal; in the order that the first transistor M1 and the second transistor M2 in the pixel circuit of the sub-pixels of the first row are turned on under the control of the low level of the scan signal ss(1), the first transistor M1 and the second transistor M2 in the pixel circuit of the sub-pixels of the second row are turned on under the control of the low level of the scan signal ss(2), the first transistor M1 and the second transistor M2 in the pixel circuit of the sub-pixels of the third row are turned on under the control of the low level of the scan signal ss(3),... the first transistor M1 and the second transistor M2 in the pixel circuit of the sub-pixels of the (n - 1)-th row are turned on under the control of the low level of the scan signal ss(n - 1), until the first transistor M1 and the second transistor M2 in the pixel circuit of the sub-pixels of the n-th row are turned on under the control of the low level of the scan signal ss(n); the turned-on first transistor M1 provides the data signal da of the data signal terminal DA to the first latch circuit 30; the turned-on second transistor M2 provides the data signal da of the data signal terminal DA to the second latch circuit 40;

[0109] The fourteenth transistor M14 in the pixel circuit of each row of sub-pixels is turned on under the control of the low level of the second light emission control signal at the corresponding second light emission control signal terminal; in the order that the fourteenth transistor M14 in the pixel circuit of the first row of sub-pixels is turned on under the control of the low level of the second light emission control signal em(1), the fourteenth transistor M14 in the pixel circuit of the second row of sub-pixels is turned on under the control of the low level of the second light emission control signal em(2), and so on until the fourteenth transistor M14 in the pixel circuit of the nth row of sub-pixels is turned on under the control of the low level of the second light emission control signal em(n).

[0110] When the voltage of the data signal da is the first voltage, the fifth transistor M5 is turned off under the control of the low level of the data signal da; the sixth transistor M6 is turned off; the third transistor M3 is turned on under the control of the low level of the data signal da, and the turned-on third transistor M3 supplies the signal of the third power supply voltage terminal VGH to the gate of the fourth transistor M4; the fourth transistor M4 is turned on under the control of the high level of the signal of the third power supply voltage terminal VGH, and the turned-on fourth transistor M4 supplies the signal of the second power supply voltage terminal VSS to the gate of the eleventh transistor M11; the eleventh transistor M11 is turned off under the control of the low level of the signal of the second power supply voltage terminal VSS, and the turned-off eleventh transistor M11 disconnects the fourth power supply voltage terminal VDD from the first node N1; the ninth transistor M9 is turned off under the control of the low level of the data signal da; the tenth transistor M10 is turned off; the seventh transistor M7 is turned on under the control of the low level of the data signal da, and the turned-on seventh transistor M7 supplies the signal of the third power supply voltage terminal VGH to the gate of the eighth transistor M8; the eighth transistor M8 is turned on under the control of the high level of the signal of the third power supply voltage terminal VGH, and the turned-on eighth transistor M8 supplies the signal of the second power supply voltage terminal VSS to the gate of the thirteenth transistor M13; the thirteenth transistor M13 is turned off under the control of the low level of the signal of the second power supply voltage terminal VSS, and the thirteenth transistor M13 disconnects the first node N1 from the second node N2; the twelfth transistor M12 is turned on under the control of the high level of the first light emission control signal hf, and the turned-on twelfth transistor M12 supplies the signal of the fourth power supply voltage terminal VDD to the first node N1; the fourteenth transistor M14 is turned on under the control of the low level of the second light emission control signal, and the turned-on fourteenth transistor M14 supplies the signal of the second node N2 to the light emitting device L. Then, when the voltage of the data signal da is the first voltage, the light emitting device L does not emit light.

[0111] When the voltage of the data signal da is the second voltage, the fifth transistor M5 is turned off under the control of the low level of the data signal da; the sixth transistor M6 is turned off; the third transistor M3 is turned on under the control of the low level of the data signal da, and the turned-on third transistor M3 supplies the signal of the third power supply voltage terminal VGH to the gate of the fourth transistor M4; the fourth transistor M4 is turned on under the control of the high level of the signal of the third power supply voltage terminal VGH, and the turned-on fourth transistor M4 supplies the signal of the second power supply voltage terminal VSS to the gate of the eleventh transistor M11; the eleventh transistor M11 is turned off under the control of the low level of the signal of the second power supply voltage terminal VSS, and the turned-off eleventh transistor M11 disconnects the fourth power supply voltage terminal VDD from the first node N1; the seventh transistor M7 is turned off under the control of the high level of the data signal da; the eighth transistor M8 is turned off; the ninth transistor M9 is turned on under the control of the high level of the data signal da, and the turned-on ninth transistor M9 supplies the signal of the first power supply voltage terminal VGL to the gate of the tenth transistor M10; the tenth transistor M10 is turned on under the control of the low level of the signal of the first power supply voltage terminal VGL, and the turned-on tenth transistor M10 supplies the signal of the third power supply voltage terminal VGH to the gate of the thirteenth transistor M13; the thirteenth transistor M13 is turned on under the control of the high level of the signal of the third power supply voltage terminal VGH, and the turned-on thirteenth transistor M13 conducts the first node N1 and the second node N2; the twelfth transistor M12 is turned on under the control of the high level of the first light control signal hf, and the turned-on twelfth transistor M12 supplies the signal of the fourth power supply voltage terminal VDD to the first node N1, and the fourteenth transistor M14 is turned on under the control of the low level of the second light control signal, and the turned-on fourteenth transistor M14 supplies the signal of the second node N2 to the light-emitting device L. Then, when the voltage of the data signal da is the second voltage, when the second light control signal is at a low level and the first light control signal is at a high level, the light-emitting device L emits light, and the light-emitting duration of the light-emitting device L is the duration formed by the overlap of the time when the second light control signal is at a low level and the time when the first light control signal is at a high level.

[0112] It should be noted that since the voltage of the signal of the first power supply voltage terminal VGL is also the first voltage, the voltage of the signal of the second power supply voltage terminal VSS is also the second voltage, and the voltage of the signal of the third power supply voltage terminal VGH is also the third voltage; and the first voltage is less than the second voltage, and the second voltage is less than the third voltage; the first latch circuit has the second power supply voltage terminal VSS and the third power supply voltage terminal VGH, and the second power supply voltage terminal VSS is close to the voltage of the data signal da; therefore, when the data signal is the second voltage, the first latch circuit will output the signal of the second power supply voltage terminal VSS that is close to the second voltage of the data signal.

[0113] When the voltage of the data signal da is the third voltage, the third transistor M3 is turned off under the control of the high level of the data signal da; the fourth transistor M4 is turned off; the fifth transistor M5 is turned on under the control of the high level of the data signal da, and the turned-on fifth transistor M5 supplies the signal of the second power supply voltage terminal VSS to the gate of the sixth transistor M6; the sixth transistor M6 is turned on under the control of the low level of the signal of the second power supply voltage terminal VSS, and the turned-on sixth transistor M6 supplies the signal of the third power supply voltage terminal VGH to the gate of the eleventh transistor M11; the eleventh transistor M11 is turned on under the control of the high level of the signal of the third power supply voltage terminal VGH, and the turned-on eleventh transistor M11 conducts the fourth power supply voltage terminal VDD and the first node N1; the seventh transistor M7 is turned off under the control of the high level of the data signal da; the eighth transistor M8 is turned off; the ninth transistor M9 is turned on under the control of the high level of the data signal da, and the turned-on ninth transistor M9 supplies the signal of the first power supply voltage terminal VGL to the gate of the tenth transistor M10; the tenth transistor M10 is turned on under the control of the low level of the signal of the first power supply voltage terminal VGL, and the turned-on tenth transistor M10 supplies the signal of the third power supply voltage terminal VGH to the gate of the thirteenth transistor M13; the thirteenth transistor M13 is turned on under the control of the high level of the signal of the third power supply voltage terminal VGH, and the turned-on thirteenth transistor M13 conducts the first node N1 and the second node N2; the twelfth transistor M12 is turned on under the control of the high level of the first light control signal hf, and the turned-on twelfth transistor M12 supplies the signal of the fourth power supply voltage terminal VDD to the first node N1, and the fourteenth transistor M14 is turned on under the control of the low level of the second light control signal, and the turned-on fourteenth transistor M14 supplies the signal of the second node N2 to the light-emitting device L. Then, when the voltage of the data signal da is the second voltage and the second light control signal is a low-level signal, the light-emitting device L emits light, and the light-emitting duration of the light-emitting device L is the duration when the second light control signal is at a low level.

[0114] Gray scale generally divides the brightness change area between the darkest and the brightest into several parts for easy control of the screen brightness. For example, the displayed image consists of three colors: red, green, and blue. Each color can show different brightness levels, and different combinations of red, green, and blue with different brightness levels can form different colors. For example, if the gray-scale bit number of the display panel is 6bit, then each of the three colors, red, green, and blue, has 64 (i.e., 2 6 ) gray scales, and these 64 gray-scale values are 0 to 63 respectively. If the gray-scale bit number of the display panel is 8bit, then each of the three colors, red, green, and blue, has 256 (i.e., 2 8) grayscales, and these 256 grayscale values ​​are 0 to 255. The grayscale number of the display panel is 9 bits, so the three colors of red, green, and blue have 512 (i.e. 2 9 ) grayscales, and these 512 grayscale values ​​are 0 to 511. The grayscale number of the display panel is 10 bits, so the three colors of red, green, and blue have 1024 (i.e. 2 10 ) grayscales, and these 1024 grayscale values ​​are 0 to 1023. The grayscale number of the display panel is 12 bits, so the three colors of red, green, and blue have 4096 (i.e. 2 12 ) grayscales, and these 4096 grayscale values ​​are 0 to 4095. It should be noted that the realized 64, 256, 512, 1024, 4096 grayscales are linear brightness changes. If it is necessary to realize brightness display based on the Gamma2.2 curve, 256 grayscales require 10-bit data to be written and displayed.

[0115] Exemplarily, in combination with the light emitting time of the light emitting device L in the disclosed embodiment, the display device in the disclosed embodiment can ultimately achieve a grayscale bit number of 9 bits.

[0116] Based on the same inventive concept, the embodiment of the present disclosure also provides a display device, including the above pixel circuit provided by the embodiment of the present disclosure. The principle of solving the problem by the display device is similar to that of the above pixel circuit, so the implementation of the display device can refer to the implementation of the above pixel circuit, and the repeated parts will not be repeated here.

[0117] In specific implementation, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations to the present disclosure.

[0118] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0119] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A pixel circuit, characterized in that, it includes: a light-emitting device, a first switch control circuit, a second switch control circuit, a first latch circuit, a second latch circuit, and a scan control circuit; The scan control circuit is coupled to the first latch circuit and the second latch circuit, and is configured to provide the data signal at the data signal terminal to the first latch circuit and the second latch circuit in response to the signal at the scan signal terminal; The first latch circuit is coupled to the first switch control circuit, and is configured to provide the signal at the second power supply voltage terminal to the first switch control circuit in response to the first voltage or the second voltage of the data signal, and provide the signal at the third power supply voltage terminal to the first switch control circuit in response to the third voltage of the data signal; The second latch circuit is coupled to the second switch control circuit, and is configured to provide the signal at the first power supply voltage terminal to the second switch control circuit in response to the first voltage of the data signal, and provide the signal at the third power supply voltage terminal to the second switch control circuit in response to the second voltage or the third voltage of the data signal; The first switch control circuit is coupled to the first node, and is configured to connect or disconnect the fourth power supply voltage terminal and the first node in response to the signal at the first light-emitting control signal terminal and the signal output by the first latch circuit; The second switch control circuit is coupled to the first node, the second node, and the light-emitting device, and is configured to connect or disconnect the first node and the second node in response to the signal output by the second latch circuit.

2. The pixel circuit according to claim 1, characterized in that, the scan control circuit includes: a first transistor and a second transistor; The gate of the first transistor is coupled to the scan signal terminal, the first pole of the first transistor is coupled to the data signal terminal, and the second pole of the first transistor is coupled to the first latch circuit; The gate of the second transistor is coupled to the scan signal terminal, the first pole of the second transistor is coupled to the data signal terminal, and the second pole of the second transistor is coupled to the second latch circuit.

3. The pixel circuit according to claim 1, characterized in that, the first latch circuit includes: a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; The gate of the third transistor is coupled to the scan control circuit, the first pole of the third transistor is coupled to the third power supply voltage terminal, and the second pole of the third transistor is coupled to the first pole of the fifth transistor; The gate of the fourth transistor is coupled to the second pole of the third transistor, the first pole of the fourth transistor is coupled to the second power supply voltage terminal, and the second pole of the fourth transistor is coupled to the scan control circuit; The gate of the fifth transistor is coupled to the scan control circuit, and the second pole of the fifth transistor is coupled to the second power supply voltage terminal; The gate of the sixth transistor is coupled to the first pole of the fifth transistor, the first pole of the sixth transistor is coupled to the scan control circuit, and the second pole of the sixth transistor is coupled to the third power supply voltage terminal.

4. The pixel circuit according to claim 1, wherein, the second latch circuit includes: a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; the gate of the seventh transistor is coupled to the scan control circuit, the first pole of the seventh transistor is coupled to the third power supply voltage terminal, and the second pole of the seventh transistor is coupled to the first pole of the ninth transistor; the gate of the eighth transistor is coupled to the second pole of the seventh transistor, the first pole of the eighth transistor is coupled to the first power supply voltage terminal, and the second pole of the eighth transistor is coupled to the scan control circuit; the gate of the ninth transistor is coupled to the scan control circuit, and the second pole of the ninth transistor is coupled to the first power supply voltage terminal; the gate of the tenth transistor is coupled to the first pole of the ninth transistor, the first pole of the tenth transistor is coupled to the scan control circuit, and the second pole of the tenth transistor is coupled to the third power supply voltage terminal.

5. The pixel circuit according to claim 1, wherein, the first switch control circuit includes: an eleventh transistor and a twelfth transistor; the gate of the eleventh transistor is coupled to the first latch circuit, the first pole of the eleventh transistor is coupled to the fourth power supply voltage terminal, and the second pole of the eleventh transistor is coupled to the first node; the gate of the twelfth transistor is coupled to the first light emission control signal terminal, the first pole of the twelfth transistor is coupled to the fourth power supply voltage terminal, and the second pole of the twelfth transistor is coupled to the first node.

6. The pixel circuit according to claim 1, wherein, the second switch control circuit includes: a thirteenth transistor; the gate of the thirteenth transistor is coupled to the second latch circuit, the first pole of the thirteenth transistor is coupled to the first node, and the second pole of the thirteenth transistor is coupled to the second node.

7. The pixel circuit according to any one of claims 1-6, wherein, further includes: a light emission control circuit, coupled to the second node and the light emitting device, configured to conduct the second node and the light emitting device in response to a signal of the second light emission control signal terminal.

8. The pixel circuit according to claim 7, wherein, the light emission control circuit includes: a fourteenth transistor; the gate of the fourteenth transistor is coupled to the second light emission control signal terminal, the first pole of the fourteenth transistor is coupled to the second node, and the second pole of the fourteenth transistor is coupled to the light emitting device.

9. The pixel circuit according to any one of claims 1-6, wherein, the first voltage is less than the second voltage, and the second voltage is less than the third voltage.

10. A driving method for a pixel circuit according to any one of claims 1-9, wherein, includes: The scanning control circuit provides the data signal at the data signal terminal to the first latch circuit and the second latch circuit in response to the signal at the scanning signal terminal; When the voltage of the data signal is the first voltage, the first latch circuit provides the signal at the second power supply voltage terminal to the first switch control circuit; the second latch circuit provides the signal at the first power supply voltage terminal to the second switch control circuit; the first switch control circuit conducts the fourth power supply voltage terminal to the first node in response to the signal at the first light emission control signal terminal; the second switch control circuit disconnects the first node from the second node in response to the signal output by the second latch circuit; When the voltage of the data signal is the second voltage, the first latch circuit provides the signal at the second power supply voltage terminal to the first switch control circuit; the second latch circuit provides the signal at the third power supply voltage terminal to the second switch control circuit; the first switch control circuit conducts the fourth power supply voltage terminal to the first node in response to the signal at the first light emission control signal terminal; the second switch control circuit conducts the first node to the second node in response to the signal output by the second latch circuit; When the voltage of the data signal is the third voltage, the first latch circuit provides the signal at the third power supply voltage terminal to the first switch control circuit; the second latch circuit provides the signal at the third power supply voltage terminal to the first switch control circuit; the first switch control circuit conducts the fourth power supply voltage terminal to the first node in response to the signal at the first light emission control signal terminal and the signal output by the first latch circuit; the second switch control circuit conducts the first node to the second node in response to the signal output by the second latch circuit.

11. A display device, characterized in that it includes the pixel circuit according to any one of claims 1-9.

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