Display panel and display device

Abstract

The invention discloses a display panel and a display device, and relates to the technical field of display. The display panel comprises a plurality of pixel circuits arranged in an array. The write-in module of the pixel circuit is electrically connected with the grid electrode of the driving transistor through the coupling module; the compensation module is electrically connected between the grid electrode and the drain electrode of the driving transistor; a plurality of rows of pixel circuits form a pixel group; the display panel further comprises a first driving circuit and a second driving circuit. The first driving circuit comprises a plurality of first shift register units, and the first shift register units are electrically connected with the compensation modules of the multiple rows of pixel circuits in the same pixel group; the second driving circuit comprises a plurality of second shift register units, and each second shift register unit is electrically connected with the write-in module of each row of pixel circuits. By adopting the technical scheme, the uniformity of display image quality can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, users' requirements for display quality are getting higher and higher.

[0003] When a display device is working, it usually emits light by current driving, so the characteristics of the driver device will affect the grayscale brightness of the display. When the characteristics of the driver devices corresponding to different pixels are too different, poor image quality is likely to occur, and with the development of high resolution and high refresh rate, the problem of uneven display is more likely to occur. Summary of the invention

[0004] The invention provides a display panel and a display device to improve the uniformity of display quality.

[0005] According to one aspect of the present invention, there is provided a display panel, comprising: a plurality of pixel circuits arranged in an array;

[0006] The pixel circuit includes a driving transistor, a writing module, a coupling module, a compensation module and a light-emitting element; the writing module is electrically connected to the gate of the driving transistor through the coupling module; the compensation module is electrically connected between the gate and the drain of the driving transistor; the light-emitting element is electrically connected to the driving transistor;

[0007] A plurality of rows of pixel circuits constitute a pixel group;

[0008] The display panel also includes a first driving circuit and a second driving circuit; the first driving circuit is used to sequentially control the compensation modules of multiple rows of pixel circuits in each pixel group to perform threshold compensation on the driving transistor; the second driving circuit is used to sequentially control the writing modules of each row of pixel circuits to write data signals to the gate of the driving transistor;

[0009] The first driving circuit includes a plurality of first shift register units; the first shift register units are electrically connected to compensation modules of a plurality of rows of pixel circuits in the same pixel group;

[0010] The second driving circuit includes a plurality of second shift register units; each second shift register unit is electrically connected to a writing module of each row of pixel circuits.

[0011] According to another aspect of the present invention, a display device is provided, comprising: the above-mentioned display panel.

[0012] According to the technical solution of the present invention, by arranging that the writing module is electrically connected to the driving transistor through the coupling module, the pixel circuit can independently perform the data writing process and the threshold compensation process. The threshold compensation process is no longer affected by the data writing process and is no longer limited by the data writing duration. By arranging that the first shift register unit of the first driving circuit is electrically connected to the compensation modules of multiple rows of pixel circuits in the same pixel group, multiple rows of pixel circuits in the same pixel group can perform threshold compensation simultaneously. Thus, during the display time of one frame of the picture, the number of times the first driving circuit of the display panel controls the pixel circuit to perform threshold compensation can be different from the number of times the second driving circuit controls the pixel circuit to perform data writing, and the duration of the pixel circuit performing threshold compensation can be not limited by the frequency of the pixel circuit performing data writing, which is beneficial to increasing the duration of threshold compensation and improving the charging rate during the threshold compensation process. Even in the case of high resolution and high refresh rate, while the pixel circuit realizes fast data writing, it can also realize complete compensation of the threshold voltage, which is beneficial to improving the uniformity of the display image quality.

[0013] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0015] Figure 1 is a circuit structure schematic diagram of a pixel circuit in the related art;

[0016] Figure 2 is a timing schematic diagram of a pixel circuit in the related art;

[0017] Figure 3 is a top view structure schematic diagram of a display panel provided by an embodiment of the present invention;

[0018] Figure 4 is a circuit structure schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0019] Figure 5 is a timing schematic diagram of a pixel group provided by an embodiment of the present invention;

[0020] Figure 6 is a circuit structure schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0021] Figure 7 is a top - view structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0022] Figure 8 is a timing schematic diagram of another pixel group provided by an embodiment of the present invention;

[0023] Figure 9 is a timing schematic diagram of another pixel group provided by an embodiment of the present invention;

[0024] Figure 10 is a circuit structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0025] Figure 11 is a top - view structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0026] Figure 12 is a timing schematic diagram of another pixel group provided by an embodiment of the present invention;

[0027] Figure 13 is a partial top - view schematic diagram of another display panel provided by an embodiment of the present invention;

[0028] Figure 14 is a top - view structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0029] Figure 15 is a timing schematic diagram of another pixel group provided by an embodiment of the present invention;

[0030] Figure 16 is a partial top - view schematic diagram of another display panel provided by an embodiment of the present invention;

[0031] Figure 17 is a timing schematic diagram of another pixel group provided by an embodiment of the present invention;

[0032] Figure 18 is a partial top - view schematic diagram of another display panel provided by an embodiment of the present invention;

[0033] Figure 19 is a circuit structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0034] Figure 20 is a circuit structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0035] Figure 21 is a top - view structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0036] Figure 22It is another timing schematic diagram of a pixel group provided by an embodiment of the present invention;

[0037] Figure 23 It is another partial top view schematic diagram of a display panel provided by an embodiment of the present invention;

[0038] Figure 24 It is another top view structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0039] Figure 25 It is another timing schematic diagram of a pixel group provided by an embodiment of the present invention;

[0040] Figure 26 It is another partial top view schematic diagram of a display panel provided by an embodiment of the present invention;

[0041] Figure 27 It is another timing schematic diagram of a pixel group provided by an embodiment of the present invention;

[0042] Figure 28 It is another partial top view schematic diagram of a display panel provided by an embodiment of the present invention;

[0043] Figure 29 It is another timing schematic diagram of a pixel group provided by an embodiment of the present invention;

[0044] Figure 30 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0045] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0046] It should be noted that the terms "first", "second", etc. in the description, claims and above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0047] Figure 1 is a schematic circuit diagram of a pixel circuit in the related art. Refer to Figure 1 , the pixel circuit PX' includes a driving transistor M3', a light-emitting element LED', an initialization transistor M5', a compensation transistor M4', a writing transistor M2', a first light-emitting control transistor M1', a second light-emitting control transistor M6', a reset transistor M7' and a storage capacitor Cst.

[0048] The first pole of the initialization transistor M5' receives a reset signal Vref', the second pole of the initialization transistor M5' is electrically connected to the gate of the driving transistor M3' at a first node N1', and the gate of the initialization transistor M5' receives a first scan signal Scan1'. The first pole of the writing transistor M2' receives a data signal Data', the second pole of the writing transistor M2' is electrically connected to the first pole of the driving transistor M3' at a second node N2', and the gate of the writing transistor M2' receives a second scan signal Scan2'. The first pole of the compensation transistor M4' is electrically connected to the second pole of the driving transistor M3' at a third node N3', and the second pole of the compensation transistor M4' is electrically connected to the gate of the driving transistor M3' at the first node N1'. The first pole of the first light-emitting control transistor M1' receives a first power supply signal PVDD', and the second pole of the first light-emitting control transistor M1' is electrically connected to the second node N2'; the first pole of the second light-emitting control transistor M6' is electrically connected to the third node N3', the second pole of the second light-emitting control transistor M6' is electrically connected to the anode of the light-emitting element LED' at a fourth node N4', and the cathode of the light-emitting element LED' receives a second power supply signal PVEE; the gates of the first light-emitting control transistor M1' and the second light-emitting control transistor M6' both receive a light-emitting control signal Emit'. The first plate of the storage capacitor Cst receives a first power supply signal PVDD, and the second plate of the storage capacitor Cst is electrically connected to the first node N1'.

[0049] Figure 2 is a timing diagram of a pixel circuit in the related art.Figure 2 The driving timing corresponds to Figure 1 the pixel circuit. Refer to Figure 1 and Figure 2 When all the transistors in the pixel circuit PX’ are P-type transistors, the low level is the enable level and the high level is the non-enable level.

[0050] In the initialization stage t1’, the first scan signal Scan1’ jumps to the enable level, the initialization transistor M5’ conducts, and the low-potential reset signal Vref’ is written to the first node N1’ through the initialization transistor M5’ to initialize the first node N1’ and control the driving transistor M3’ to conduct. The compensation stage t2’ and the writing stage t3’ overlap. In the compensation stage t2’ and the writing stage t3’, the second scan signal Scan2’ jumps to the enable level, the writing transistor M2’ and the compensation transistor M4’ conduct, and the data signal Data’ can be transmitted to the first node N1’ through the writing transistor M2’, the driving transistor M3’ and the compensation transistor M4’, and the potential of the first node N1’ is continuously raised during this process until the driving transistor M3’ reaches the critical state of turning off (Vgs of the driving transistor M3’ = VN1’ - VN2’ = Vth), and the data signal Data’ stops being transmitted to the first node N1’. The compensated data signal Data’ is written to the first node N1’, and at this time, the potential VN1’ of the first node N1’ = Vdata’ + Vth. In the light-emitting stage t4’, the light-emitting control signal Emit’ jumps to the enable level, the first light-emitting control transistor M1’ and the second light-emitting control transistor M2’ conduct, the potential VN2’ of the second node N2’ = PVDD, Vgs of the driving transistor M3’ = VN1’ - VN2’ = Vdata’ + Vth - PVDD < Vth, the driving transistor M3’ conducts, and the driving current Id’ = B’ × [Vgs - Vth] 2 = B’ × [Vdata’ - PVDD] 2 where B’ = (1 / 2) × μ × Cox ox × (W / L), μ is the electron mobility of the driving transistor M3’, Cox is the channel capacitance per unit area in the driving transistor M3’, and W / L is the channel width / channel length ratio of the driving transistor M3’. At this time, the magnitude of the driving current Id’ is related to Vdata’ and has nothing to do with Vth.

[0051] However, with the development of high resolution and high refresh rate, the time when the second scan signal Scan2' is at the enable level will be continuously shortened. Taking the resolution of 2800×1260 as an example, when the resolution is 120Hz, the time 1H for each line is greater than 2.8us and less than 3.0us, which is barely enough to fully compensate the threshold voltage Vth to the minimum critical time of the driving transistor M3'. Continuing with the example of a resolution of 2800×1260, when the resolution is 240Hz, the time 1H for each row is greater than 1.4us and less than 1.5us, which is far from satisfying the minimum critical time for fully compensating the threshold voltage Vth to the driving transistor M3'. When the driving transistor M3' has not yet reached the critical state of being turned off, the second scanning signal Scan2' jumps to a non-enabled level, resulting in the threshold voltage Vth of the driving transistor M3' not being fully compensated to the first node N1', and the magnitude of the driving current Id' being affected by Vth. At the same time, the Vth of the driving transistor M3' may shift due to manufacturing process deviations, aging or temperature changes, resulting in inconsistent driving currents output under the same data signal Data', which may seriously affect display uniformity.

[0052] Moreover, even if the gate of the write transistor M2' and the gate of the compensation transistor M4' are set to receive different scanning signals so that the write transistor M2' and the compensation transistor M4' are turned on in time-sharing mode, the signal written into the first node N1' later will affect the signal written into the first node N1' earlier, affecting the driving current and thus affecting the display uniformity.

[0053] To solve the above technical problems, an embodiment of the present invention provides a display panel, comprising: a plurality of pixel circuits arranged in an array; the pixel circuit comprises a driving transistor, a writing module, a coupling module, a compensation module and a light-emitting element; the writing module is electrically connected to the gate of the driving transistor through the coupling module; the compensation module is electrically connected between the gate and the drain of the driving transistor; the light-emitting element is electrically connected to the driving transistor; a plurality of rows of pixel circuits constitute a pixel group; the display panel also comprises a first driving circuit and a second driving circuit; the first driving circuit is used to sequentially control the compensation modules of the plurality of rows of pixel circuits in each pixel group to perform threshold compensation on the driving transistor; the second driving circuit is used to sequentially control the writing modules of the plurality of rows of pixel circuits to write data signals to the gate of the driving transistor; the first driving circuit comprises a plurality of first shift register units; the first shift register unit is electrically connected to the compensation modules of the plurality of rows of pixel circuits in the same pixel group; the second driving circuit comprises a plurality of second shift register units; each second shift register unit is electrically connected to the writing module of each row of pixel circuits, respectively.

[0054] Adopting the above technical solution, by setting that the writing module is electrically connected to the driving transistor through the coupling module, the pixel circuit can independently perform the data writing process and the threshold compensation process. The threshold compensation process is no longer affected by the data writing process and is no longer limited by the data writing duration. By setting that the first shift register unit of the first driving circuit is electrically connected to the compensation modules of multiple rows of pixel circuits in the same pixel group, the threshold compensation of multiple rows of pixel circuits in the same pixel group can be performed simultaneously. Thus, during the display time of one frame of the picture, the number of times the first driving circuit of the display panel controls the pixel circuit to perform threshold compensation can be different from the number of times the second driving circuit controls the pixel circuit to perform data writing. The duration of the pixel circuit performing threshold compensation can be not limited by the frequency of the pixel circuit performing data writing, which is beneficial to increasing the duration of threshold compensation and improving the charging rate during the threshold compensation process. Even in the case of high resolution and high refresh rate, while the pixel circuit realizes fast data writing, it can also realize complete compensation of the threshold voltage, which is beneficial to improving the uniformity of the display image quality.

[0055] The above is the core idea of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention. The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention.

[0056] Figure 3 It is a schematic top view structure diagram of a display panel provided by an embodiment of the present invention. Figure 4 It is a schematic circuit structure diagram of a pixel circuit provided by an embodiment of the present invention. Referring to Figure 3 and Figure 4 , the display area AA of the display panel 01 includes a plurality of pixel circuits PX arranged in an array. The pixel circuit PX includes a driving transistor M3, a writing module 11, a coupling module 12, a compensation module 13, and a light-emitting element LED. The writing module 11 is electrically connected to the gate of the driving transistor M3 through the coupling module 12 at the first node N1, and the writing module 11 is electrically connected to the coupling module 12 at the second node N2. The compensation module 13 is also electrically connected to the gate of the driving transistor M3 at the first node N1, and the compensation module 13 is further electrically connected to the drain of the driving transistor M3 at the third node N3. The light-emitting element LED is electrically connected to the driving transistor M3. The pixel circuits PX in the same row form a pixel row PR, and a plurality of pixel rows PR can form a pixel group, that is, multiple rows of pixel circuits PX can form a pixel group.

[0057] The display panel 01 further includes a first driving circuit VSR1 and a second driving circuit VSR2. The first driving circuit VSR1 includes a plurality of first shift register units 21, and the first shift register units VSR1 are electrically connected to the compensation modules 13 of multiple rows of pixel circuits PX in the same pixel group. The second driving circuit VSR2 includes a plurality of second shift register units 22, and each second shift register unit 22 is respectively electrically connected to the writing module 11 of each row of pixel circuits PX. The first driving circuit VSR1 is used to sequentially control the compensation modules 13 of multiple rows of pixel circuits PX in each pixel group to perform threshold compensation on the driving transistor M3, and the second driving circuit VSR2 is used to sequentially control the writing modules 11 of each row of pixel circuits PX to write the data signal data to the gate of the driving transistor M3.

[0058] Specifically, the first end of the writing module 11 can be electrically connected (not shown in the figure) to the data voltage terminal of the display panel 01 through the data line Data_L to receive the data signal Data of the data voltage terminal; when the writing module 11 is turned on, the data signal Data can be transmitted to the coupling module 12 through the writing module 11, and the coupling module 12 can couple the data signal Data to the first node N1 to write the data signal data to the gate of the driving transistor M3. The first end of the compensation module 13 can receive the signal of the third node N3; when the compensation module 13 is turned on, the signal of the third node N3 can be transmitted to the first node N1 through the compensation module 13, so as to compensate the threshold voltage Vth of the driving transistor M3 to the first node N1. In this way, when data is written to the pixel circuit PX, the data signal Data can be superimposed on the signal of the first node N1 without affecting the threshold voltage Vth compensated by the first node N1; when threshold compensation is performed on the pixel circuit PX, it is not necessary to receive the data signal Data, nor is it limited by the conduction duration of the writing module 11, that is, when the writing module 11 is turned off, the pixel circuit PX can still perform threshold compensation.

[0059] Reference Figure 4 , the writing modules 11 of the pixel circuits PX in the same row can be connected to the same writing scan line SP_L to receive the same writing scan signal SP; the writing modules 11 of the pixel circuits PX in different rows can be connected to different writing scan lines SP_L and receive different writing scan signals SP. One second shift register unit 22 is connected to one writing scan line SP_L to provide the same writing scan signal SP to the writing module 11 of one row of pixel circuits PX and control the conduction and cutoff of the writing module 11 of this row; the writing scan signals SP output by the multiple second shift register units 22 can be sequentially transmitted (not shown in the figure), so as to sequentially control each row of pixel circuits PX to write the data signal data to the gate of the driving transistor M3.

[0060] The compensation modules 13 of the pixel circuits PX located in the same row can be connected to the same compensation scan line Scan3_L to receive the same compensation scan signal Scan3; the compensation modules 13 of the pixel circuits PX in the same pixel group but in different rows can be connected to different compensation scan lines Scan3_L, but still can receive the same compensation scan signal Scan3; the compensation modules 13 of the pixel circuits PX in different pixel groups receive different compensation scan signals Scan3. A first shift register unit 21 can be connected to multiple compensation scan lines Scan3_L to provide the same compensation scan signal Scan3 to the compensation modules 13 of multiple rows of pixel circuits PX in the same pixel group, and control the conduction and cut-off of the compensation modules 13 in this pixel group; the compensation scan signals Scan3 output by multiple first shift register units 21 can be successively transmitted (not shown in the figure), so as to successively control the compensation modules 13 of multiple rows of pixel circuits PX in each pixel group to perform threshold compensation on the driving transistor M3.

[0061] Among them, the number of rows of the pixel circuits PX in the pixel group can be an integer greater than or equal to 2. During the display time of one frame of the picture, the number and frequency of the compensation scan signals Scan3 output by the first driving circuit VSR1 are both less than the number and frequency of the write scan signals SP output by the second driving circuit VSR2. The pulse width of the effective pulse of the compensation scan signal Scan3 can be greater than the pulse width of the effective pulse of the write scan signal SP, so that the duration of the pixel circuit PX performing threshold compensation is greater than the duration of the pixel circuit PX performing data writing.

[0062] In an optional implementation, when the resolution of the display panel 01 increases, the total number of rows of the pixel circuits PX increases. During the display time of one frame of the picture, the number and frequency of the write scan signals SP output by the second driving circuit VSR2 both increase, that is, the pulse width of the effective pulse of the write scan signal SP decreases, and the duration of the pixel circuit PX performing data writing shortens. By increasing the number of rows of the pixel circuits PX in the pixel group, the number and frequency of the compensation scan signals Scan3 output by the first driving circuit VSR1 can remain unchanged or change slightly during the display time of one frame of the picture, so that the pulse width of the effective pulse of the write scan signal SP remains unchanged or changes slightly, thereby reducing the influence of high resolution on the duration of the pixel circuit PX performing threshold compensation.

[0063] In another optional implementation, when the refresh frequency of the display panel 01 increases, the display time of one frame of the picture shortens, the pulse width of the effective pulse of the write scan signal SP decreases, and the duration of the pixel circuit PX performing data writing shortens. By increasing the number of rows of the pixel circuits PX in the pixel group, the pulse width of the effective pulse of the compensation scan signal Scan3 can also remain unchanged or change slightly, thereby reducing the influence of high refresh rate on the duration of the pixel circuit PX performing threshold compensation, so that the duration of the pixel circuit PX performing threshold remains unchanged or changes slightly.

[0064] In addition, a plurality of first power supply lines PV1_L and a plurality of second power supply lines PV2_L (not shown in the figure) can be provided in the display area AA of the display panel 01. The display panel 01 can also include a first power supply voltage terminal and a second power supply voltage terminal (not shown in the figure). The first power supply voltage terminal is used to provide a first power signal PV1 to the first power supply line PV1_L, and the first power supply line PV1_L can be electrically connected to the driving transistor M3 of the pixel circuit PX. The second power supply voltage terminal is used to provide a second power signal PV2 to the second power supply line PV2_L, and the second power supply line PV2_L can be electrically connected to the light-emitting element LED.

[0065] It should be noted that in the figure, only the driving transistor M3 is exemplarily shown as a P-type transistor. At this time, the conduction condition of the driving transistor M3 is Vgs < Vth < 0. In other alternative embodiments, the driving transistor M3 can also be an N-type transistor. At this time, the conduction condition of the driving transistor M3 is Vgs > Vth > 0. The channel type of the driving transistor M3 is not specifically limited in the embodiments of the present invention. For the convenience of description, the technical solutions of the embodiments of the present invention are exemplarily described by taking the driving transistor M3 as a P-type transistor as an example.

[0066] It should also be noted that in the figure, only the plurality of first shift register units 21 of the first driving circuit VSR1 and the plurality of second shift register units 22 of the second shift register circuit VSR2 are exemplarily shown to be located in the non-display area NA on opposite sides of the display area AA. In other alternative embodiments, the plurality of first shift register units 21 of the first driving circuit VSR1 and the plurality of second shift register units 22 of the second shift register circuit VSR2 can be located in the non-display area NA on the same side or different sides of the display area AA, or at least some of the plurality of first shift register units 21 of the first driving circuit VSR1 and the plurality of second shift register units 22 of the second shift register circuit VSR2 can also be located in the display area AA. The positions of the first shift register unit 21 and the second shift register unit 22 are not specifically limited in the embodiments of the present invention.

[0067] The working principle of the pixel circuit provided by the embodiments of the present application is described below in conjunction with the timing.

[0068] Exemplarily, it is described by taking the pixel group including two pixel rows PR, the enable levels of the write scan signal SP and the compensation scan signal Scan3 being both low levels, and the non-enable levels being both high levels as an example. Figure 5 It is a timing schematic diagram of a pixel group provided by the embodiments of the present invention. Figure 5 The driving timing of Figure 4corresponds to the pixel circuit. It should be noted that the enable level here is the potential that controls the conduction between the first end and the second end of each module, and the non-enable level is the potential that controls the cut-off and disconnection between the first end and the second end of each module.

[0069] Reference Figures 3 - 5 , the compensation modules 13 of the (2×j - 1)-th pixel row PR(2×j - 1) and the 2×j-th pixel row PR(2×j) of the j-th pixel group can receive the j-th compensation scan signal Scan3(j) output by the j-th first shift register unit 21(j); the writing module 21 of the (2×j - 1)-th pixel row PR(2×j - 1) of the j-th pixel group can receive the (2×j - 1)-th writing scan signal SP(2×j - 1) output by the (2×j - 1)-th second shift register unit 22(2×j - 1); the writing module 21 of the 2×j-th pixel row PR(2×j) of the j-th pixel group can receive the 2×j-th writing scan signal SP(2×j) output by the 2×j-th second shift register unit 22(2×j).

[0070] During the enable period t01 of the j-th compensation scan signal Scan3(j), the compensation modules 13 of the (2×j - 1)-th row PR and the 2×j-th row are both turned on, and the pixel circuits PX of the (2×j - 1)-th row and the 2×j-th row both perform threshold compensation. During the enable period t02 of the (2×j - 1)-th writing scan signal SP(2×j - 1), the writing module 11 of the (2×j - 1)-th row is turned on, and the pixel circuit PX of the (2×j - 1)-th row performs data writing; during the enable period t03 of the 2×j-th writing scan signal SP(2×j), the writing module 11 of the 2×j-th row is turned on, and the pixel circuit PX of the 2×j-th row performs data writing.

[0071] Continue to consider Figures 3 - 5 , the pixel circuits PX in the same column are connected to the same data line Data_L, and different pixel circuits PX in different rows need to write different data signals Data. Therefore, the period (t02) for the pixel circuit PX of the (2×j - 1)-th row to perform data writing and the period (t03) for the pixel circuit PX of the 2×j-th row to perform data writing do not overlap. However, the period for the pixel circuit PX of the (2×j - 1)-th row to perform threshold compensation and the period for the pixel circuit PX of the 2×j-th row to perform threshold compensation can overlap, and the two can also be superimposed, so that the period for the pixel circuit PX of the (2×j - 1)-th row to perform threshold compensation and the period for the pixel circuit PX of the 2×j-th row to perform threshold compensation can both be extended (such as t01). In this way, in the case of high resolution and high refresh rate, it can still be ensured that the pixel circuit PX has enough time to perform threshold compensation to completely compensate the threshold voltage Vth of the driving transistor M3 to the gate of the driving transistor M3, avoiding the influence of the driving current magnitude by Vth and affecting the display uniformity of the display panel 01.

[0072] It should be noted that in the figure, only an exemplary pixel group including two pixel rows PR is shown. In other embodiments, a pixel group may also include three or four or more pixel rows PR. The embodiments of the present invention do not specifically limit the number of pixel rows PR included in the pixel group.

[0073] In the display panel provided by the embodiments of the present invention, by setting the writing module to be electrically connected to the driving transistor through the coupling module, the pixel circuit can independently perform the data writing process and the threshold compensation process. The threshold compensation process is no longer affected by the data writing process and is no longer limited by the data writing duration. By setting the first shift register unit of the first driving circuit to be electrically connected to the compensation modules of multiple pixel circuits in the same pixel group, multiple pixel circuits in the same pixel group can perform threshold compensation simultaneously. Thus, during the display time of one frame of the image, the number of times the first driving circuit of the display panel controls the pixel circuit to perform threshold compensation can be different from the number of times the second driving circuit controls the pixel circuit to perform data writing. The duration of the pixel circuit performing threshold compensation can be not limited by the frequency of the pixel circuit performing data writing, which is beneficial to increasing the duration of threshold compensation and improving the charging rate during the threshold compensation process. Even in the case of high resolution and high refresh rate, while the pixel circuit can achieve fast data writing, it can also achieve complete compensation of the threshold voltage, which is beneficial to improving the uniformity of the display image quality.

[0074] Optionally, referring to Figure 4 and Figure 5 , in the same pixel circuit PX, the period during which the pixel circuit PX performs threshold compensation is before the period during which the pixel circuit PX performs data writing, and the two do not overlap.

[0075] Specifically, during the period when the pixel circuit PX performs threshold compensation, the compensation scan signal Scan3 jumps to the enable level, and the compensation module 13 is turned on. The compensation module 13 can transfer the signal of the third node N3 to the first node N1, changing the signal of the first node N1. During the period when the pixel circuit PX writes data, the write scan signal SP jumps to the enable level, and the write module 11 is turned on. The write module 11 can couple the data signal Data to the first node N1 and superimpose the data signal Data on the first node N1. By setting the period for the pixel circuit PX to perform threshold compensation before the period for the pixel circuit PX to write data, the threshold voltage of the driving transistor M3 can be compensated to the first node N1 first, and then the data signal Data can be superimposed on the first node N1 through the coupling module 13. This is beneficial to completely compensate the threshold voltage Vth to the first node N1 and also beneficial to accurately write the data signal Data to the first node N1, avoiding simultaneous threshold compensation and data writing, which affects the accurate compensation of the threshold voltage Vth, and also avoiding performing threshold compensation after data writing, which affects the data signal Data superimposed on the first node N1 and results in poor display effects.

[0076] Optionally, Figure 6 is a schematic circuit structure diagram of another pixel circuit provided by an embodiment of the present invention. Refer to Figure 3 and Figure 6 , the write module 11 includes a write transistor M2. The first pole of the write transistor M2 receives the data signal Data. The second pole of the write transistor M2 is electrically connected to the first end of the coupling module 12 at the second node N2. The gate of the write transistor M2 can be electrically connected to the second shift register unit 22 through the write scan line SP_L; the compensation module 13 includes a compensation transistor M4. The first pole of the compensation transistor M4 is electrically connected to the drain of the driving transistor M3 at the third node N3. The second pole of the compensation transistor M4 is electrically connected to the gate of the driving transistor M3 at the first node N. The gate of the compensation transistor M4 can be electrically connected to the first shift register unit 21 through the compensation scan line Scan3_L.

[0077] Exemplarily, all the transistors in the pixel circuit 10 are P-type transistors. The active layers of all the transistors in the pixel circuit PX can be arranged on the same layer, reducing the manufacturing process and the manufacturing cost; moreover, the enable levels of the gates of all the transistors are low levels. When the pulse widths of the enable levels are the same, signal multiplexing between the gates of different transistors can also be performed. In an alternative embodiment, at least some of the transistors in the pixel circuit PX can be of a double-gate structure, which is beneficial to improving the stability and mobility of the transistors.

[0078] It should be noted that in other alternative embodiments, the writing transistor M2 and / or the compensation transistor M4 may also be N-type transistors. When the writing transistor M2 and / or the compensation transistor M4 are N-type transistors, the active layer of the writing transistor M2 and / or the compensation transistor M4 may include a metal oxide material. When preparing the active layer of the writing transistor M2 and / or the compensation transistor M4, there is no need to crystallize to form a crystal structure, so that the defect density of the active layer is small, and the carrier mobility of the active layer is high, and the temperature sensitivity is low, which can enable the writing transistor M2 and / or the compensation transistor M4 to conduct quickly. In the case of high resolution and high refresh rate, the charging speed and charging rate are improved, thereby improving the display effect.

[0079] Optionally, the coupling module 12 includes a coupling capacitor C1, and the coupling capacitor C1 is electrically connected between the first node N1 and the second node N2.

[0080] Specifically, the writing transistor M2 is electrically connected to the gate of the driving transistor M3 through the coupling capacitor C1 at the first node N1. On the one hand, the fast charge and discharge characteristics of the coupling capacitor C1 can quickly transfer the change of the data signal Data at the second pole of the writing transistor M2 to the gate of the driving transistor M3, reducing signal delay and improving the response speed of the pixel circuit PX; on the other hand, the coupling capacitor C1 can isolate the direct current signal, superimpose the data signal Data on the first node N1, and avoid level conflict or signal coverage caused by direct connection, ensuring the stable operation of the pixel circuit PX.

[0081] Optionally, Figure 7 is a schematic top view structure diagram of another display panel provided by an embodiment of the present invention. Refer to Figure 6 and Figure 7 , the pixel circuit PX further includes a light emission control module 14, and the light emission control module 14 is electrically connected between the driving transistor M3 and the light emitting element LED. The display panel 01 further includes a fifth driving circuit VSR5, and the fifth driving circuit VSR is used to sequentially turn on the light emission control modules 14 of multiple rows of pixel circuits PX in each pixel group.

[0082] Specifically, the light-emitting control modules 14 of the pixel circuits PX in the same row can be connected to the same light-emitting control line EM_L and receive the same light-emitting control signal EM; the light-emitting control modules 14 of the pixel circuits PX in different rows in the same pixel group can be connected to different compensation scan lines Scan3_L, but can still receive the same light-emitting control signal EM; the light-emitting control modules 14 of the pixel circuits PX in different pixel groups receive different light-emitting control signals EM. The fifth driving circuit VSR5 includes a plurality of fifth shift register units 25, one fifth shift register unit 25 is connected to a plurality of light-emitting control signals EM, provides the same light-emitting control signal EM to the light-emitting control modules 14 of the pixel circuits PX in multiple rows in the same pixel group, and controls the conduction and cutoff of the light-emitting control modules 14 in the pixel group; the light-emitting control signals EM output by the plurality of fifth shift register units 25 can be sequentially transmitted (not shown in the figure), thereby sequentially controlling the light-emitting elements LED in the pixel circuits PX in multiple rows in each pixel group to display light.

[0083] During the display time of one frame, the number and times of the light-emitting control signal EM output by the fifth driving circuit VSR5 can be the same as the number and times of the compensation scanning signal Scan3 output by the first driving circuit VSR1, and both are less than the number and times of the writing scanning signal SP output by the second driving circuit VSR2. In this way, the number of the fifth shift register units 25 in the fifth driving circuit VSR5 is reduced, the circuit layout is simplified, and the space occupied is reduced, thereby realizing the thinness and narrow frame of the display panel 01.

[0084] It can be understood that the figure only exemplarily shows that the fifth shift register unit 25 of the fifth driving circuit VSR5 is located in the non-display area NA on the opposite sides of the display area AA. In other optional embodiments, the fifth shift register unit 25 may be located in the non-display area NA on the same side of the display area AA, or the fifth shift register unit 25 may also be located in the display area AA. The embodiment of the present invention does not specifically limit the position of the fifth shift register unit 25.

[0085] Exemplarily, the light emitting control module 14 includes a light emitting control transistor M6, a first electrode of the light emitting control transistor M6 and the driving transistor M3 are electrically connected to the third node N3, a second electrode of the light emitting control transistor M6 and the light emitting element LED are electrically connected to the fourth node N4, and a gate of the light emitting control transistor M6 can be electrically connected to the fifth shift register unit 25 through the light emitting control line EM_L. Among them, the light emitting control transistor M6 can be a P-type transistor or an N-type transistor, which is not limited in the embodiment of the present invention. For the convenience of description, the embodiment of the present invention takes the transistors in the pixel circuit PX as P-type transistors as an example to exemplarily illustrate the technical solutions of the embodiment of the present invention.

[0086] Optional, continue to refer to Figure 6And Figure 7 The pixel circuit PX further includes a reset module 15, and the reset module 15 is electrically connected to the light-emitting element LED. In the same pixel circuit PX, the reset module 15 and the compensation module 13 are connected to the same first shift register unit 21, and / or the reset module 15 and the writing module 11 are connected to the same second shift register unit 22.

[0087] Exemplarily, the reset module 15 includes a second reset transistor M7; a first pole of the second reset transistor M7 can be electrically connected to a second reference voltage terminal through a second reset line Vref2_L (not shown in the figure) to receive a second reset signal Vref2; a second pole of the second reset transistor M7 is electrically connected to the light-emitting element LED at a fourth node N4. A gate of the second reset transistor M7 can be electrically connected to the first shift register unit 21 through a compensation scan line Scan3_L, and a channel type of the second reset transistor M7 is the same as a channel type of the compensation transistor M4. Alternatively, the gate of the second reset transistor M7 can also be electrically connected to the second shift register unit 22 through a writing scan line SP_L, and the channel type of the second reset transistor M7 is the same as a channel type of the writing transistor M2. In the same pixel circuit PX, the gate of the second reset transistor M7 can be connected to the gate of the compensation transistor M4 to the same compensation scan line Scan3_L, or connected to the gate of the writing transistor M2 to the same writing scan line SP_L. The second reset transistor M7 can be turned on when the light-emitting control transistor M6 is turned off to transmit a second reference signal Vref2 of the second reference voltage terminal to the fourth node N4 to reset the fourth node N4.

[0088] Continuing with the example where the pixel group includes two pixel rows PR, and the enable levels of the writing scan signal SP, the compensation scan signal Scan3, and the light-emitting control signal EM are all low levels, and the non-enable levels are all high levels for illustration. Figure 8 It is a timing diagram of another pixel group provided by an embodiment of the present invention. Figure 8 The driving timing of Figure 6 corresponds to the pixel circuit of Figures 6 - 8, during the display time of a frame of the image, the pixel circuit PX includes a compensation stage T1, a writing stage T2, and a light-emitting stage T3. During the compensation stage T1, the compensation scan signal Scan3 is at the enable level, the writing scan signal SP and the light-emitting control signal EM are both at the non-enable level, the compensation transistor M4 is turned on, the writing transistor M2 and the light-emitting control transistor M6 are turned off, and when light is emitted during the display time of the previous frame of the image, it can make Vgs = VN1 - PV1 < Vth < 0. At the beginning of the compensation stage T1 during the display time of the current frame of the image, the driving transistor M3 can continue to be turned on, and the first power signal PV1 can be transmitted to the first node N1 through the driving transistor M3 and the compensation transistor M4, raising the potential of the first node N1, continuously increasing the gate-source voltage Vgs of the driving transistor M3 until Vgs = VN1 - PV1 = Vth (Vth < 0), the driving transistor M3 is in the critical state of conduction and cutoff, the current in the driving transistor M3 decreases to zero, the first power signal PV1 no longer transmits to the first node N1, and the potential of the first node N1 is stable. At this time, VN1 = VN3 = PV1 + VTH (Vth < 0), and the threshold voltage is compensated to the first node N1.

[0089] During the writing stage T2, the light-emitting control signal EM continues to be at the non-enable level, the compensation scan signal Scan3 jumps to the non-enable level, the writing scan signal SP jumps to the enable level, the writing transistor M2 is turned on, and the compensation transistor M4 and the light-emitting control transistor M6 are turned off. The data signal Data can be written to the second node N2, and the change amount △VN2 of the second node N2 can be coupled to the first node N1 through the coupling capacitor C1, making △VN1 = △VN2, VN1 = PV1 + VTH + △VN1 = PV1 + VTH + △VN2 < PV1 + VTH (△VN2 < 0, Vth < 0), Vgs = VN1 - PV1 = VTH + △VN1 = VTH + △VN2 < Vth < 0, and the driving transistor M3 is fully turned on.

[0090] During the light-emitting stage T3, the compensation scan signal Scan3 continues to be at the non-enable level, the writing scan signal SP jumps to the non-enable level, the light-emitting control signal EM jumps to the enable level, the light-emitting control transistor M6 is turned on, and the writing transistor M2 and the compensation transistor M4 are turned off. The driving transistor M3 forms a driving current Id according to its gate electrical signal PV1 + VTH + △VN2 and the first power signal PV1, and the driving current Id = B × (Vgs - Vth) 2 = B × △VN1 2 = B × △VN2 2 , and the light-emitting element LED can display the corresponding brightness according to the driving current Id. By controlling the brightness and the light-emitting duration of the light-emitting element LED, the display gray level of the pixel circuit PX can be controlled. Among them, B = (1 / 2) × μ × C ox×(W / L), where μ is the electron mobility of the driving transistor M3, Cox is the channel capacitance per unit area of the driving transistor M3, and W / L is the channel width-to-length ratio of the driving transistor M3'.

[0091] Among them, △VN2 is only related to the data signal Data written in the writing stage T2 and the potential of the second node N2 before the writing stage T2, and is independent of the threshold voltage Vth of the driving transistor M3. The device differences of the driving transistor M3 will not affect the magnitude of the driving current Id, nor will they affect the display uniformity.

[0092] In an alternative embodiment, the potential of the second node N2 before the writing stage T2 can be the data signal Data written during the display time of the previous frame, or it can also be the data signal Data written by the pixel circuit PX in the same column and the previous row. As Figure 9 shown, during the display time of one frame, before the writing stage T2, the writing scan signal SP can also jump to the enable level. When writing the data signal Data by the pixel circuit PX in the same column and the previous row (i - 2 rows), the pixel circuit PX in the same column and the current row (i rows) can write the same data signal Data as the potential of the second node N2 before the writing stage T2. However, the potential of the second node N2 before the writing stage T2 is not limited to this.

[0093] Optionally, Figure 10 is a schematic circuit structure diagram of another pixel circuit provided by an embodiment of the present invention. Figure 11 is a schematic top view structure diagram of another display panel provided by an embodiment of the present invention. Referring to Figure 10 and Figure 11 , the writing module 11 further includes a first reset transistor M1. The first pole of the reset transistor M1 receives the third reset signal Vref3, and the second pole of the M1 reset transistor M1 is electrically connected to the second node N2. The display panel 01 further includes a third driving circuit VSR3. The third driving circuit VSR3 includes a plurality of third shift register units 23, and the third shift register units 23 are electrically connected to the gates of the M1 reset transistors M1; the third driving circuit VSR3 is used to sequentially control the first reset transistors M1 of each row of pixel circuits to reset the second node N2. In the same pixel circuit PX, the gate of the second reset transistor M7 of the reset module 15 can also be connected to the gate of the first reset transistor M1 of the writing module 11 to the same third shift register unit 23.

[0094] Exemplarily, a first pole of the first reset transistor M1 can be electrically connected to a third reference voltage terminal through a third reset line Vref3_L (not shown in the figure) to receive a third reset signal Vref3; a gate of the first reset transistor M1 can be electrically connected to the third shift register unit 23 through a reset scan line Scan2_L to receive a reset scan signal Scan2. In an alternative embodiment, the third reference voltage terminal can be multiplexed with the second reference voltage terminal, and the third reset line Vref3_L can be multiplexed with the second reset line Vref2_L.

[0095] During the display time of a frame of a picture, the first reset transistor M1 can be turned on before the writing transistor M2 is turned on to reset the second node N2 and clear the electrical signal remaining at the second node N2 during the display time of the previous frame of the picture. In this way, after the pixel circuit PX writes a data signal Data, the change amount △VN2 of the second node N2 = Data - Vref3. When the pixel circuit PX displays and emits light, the driving current Id = B×(Vgs - Vth) 2 = B×△VN1 2 = B×△VN2 2 = B×(Data - Vref3) 2 , where B = (1 / 2)×μ×C ox ×(W / L).

[0096] On the one hand, the potentials of the second nodes N2 before the writing stage T2 of all pixel circuits PX can be unified to Vref3, which is beneficial to simplifying the control of the driving current and is also beneficial to the uniformity of the pixel circuits PX in the display panel 01, thereby improving the display uniformity of the display panel 01; on the other hand, the third reset signal Vref3 can be set as a positive electrical signal, and the data signal Data can be an electrical signal with a relatively small absolute value, so that the data signal Data on the data line Data_L changes near 0V, which is beneficial to reducing power consumption, increasing the charging rate, and achieving high resolution and high refresh rate.

[0097] Based on the above embodiments, in the same pixel circuit PX, the period during which the pixel circuit PX resets the second node N2 overlaps with the period during which the pixel circuit PX performs threshold compensation.

[0098] Exemplarily, continue to take the example where the pixel group includes two pixel rows PR, the average enable level is a low level, and the average non - enable level is a high level for illustration. Figure 12 It is a timing schematic diagram of another pixel group provided by an embodiment of the present invention. Figure 12 The driving timing corresponds to the pixel circuit of Figure 10 Refer to Figures 10 - 12, the gate of the first reset transistor M1 in the (2×j - 1)-th row can receive the (2×j - 1)-th reset scan signal Scan2(2×j - 1) output by the (2×j - 1)-th third shift register unit 23(2×j - 1); the gate of the first reset transistor M1 in the 2×j-th row can receive the 2×j-th reset scan signal Scan2(2×j) output by the 2×j-th third register unit 23(2×j).

[0099] During the enabling period t04 of the (2×j - 1)-th reset scan signal Scan2(2×j - 1), the first reset transistor M1 in the (2×j - 1)-th row is turned on, and the potential of the second node N2 of the pixel circuit PX in the (2×j - 1)-th row is reset to Vref3; meanwhile, the compensation transistor M4 in the (2×j - 1)-th row is also turned on, and the potential of the second node N2 of the pixel circuit PX in the (2×j - 1)-th row can be compensated to PV1 + VTH. During the enabling period t05 of the 2×j-th reset scan signal Scan2(2×j), the first reset transistor M1 in the 2×j-th row is turned on, and the potential of the second node N2 of the pixel circuit PX in the 2×j-th row is reset to Vref3; meanwhile, the compensation transistor M4 in the 2×j-th row is also turned on, and the potential of the second node N2 of the pixel circuit PX in the 2×j-th row can be compensated to PV1 + VTH.

[0100] In this way, the period when the second node N2 is reset overlaps with the period when the first node N1 is compensated, ensuring that the potential of the first node N1 after threshold compensation is not affected by the potential change of the second node N2, and ensuring that the potential of the second node N2 after reset is not affected by the potential change of the first node N1, which is beneficial to the accurate compensation of the potential of the first node N1 and the accurate reset of the potential of the second node N2.

[0101] In an optional embodiment, each third shift register unit 23 is electrically connected to the gate of the first reset transistor M1 of each row of pixel circuits PX; the third shift register unit 23 multiplexes the second shift register unit 22, and the gate of the first reset transistor M1 of the pixel circuit PX in the i-th row is connected to the gate of the writing transistor M2 of the pixel circuit PX in the (i - e)-th row to the same second shift register unit 22; where i and e are both integers, and i > e ≥ 2.

[0102] Exemplarily, continue to take the pixel group including two pixel rows PR, with the enable levels all being low and the non-enable levels all being high as an example for illustration. Figure 13 It is a partial top view schematic diagram of another display panel provided by an embodiment of the present invention, referring to Figure 10 、 Figure 12 and Figure 13, the gates of the first reset transistors M1 in the (2×j - 1)-th row and the gates of the write transistors M2 in the (2×j - 3)-th row may both be electrically connected to the (2×j - 3)-th second shift register unit 22(2×j - 3). The gate of the first reset transistor M1 in the (2×j - 1)-th row may receive the (2×j - 3)-th write scan signal SP(2×j - 3) output by the (2×j - 3)-th second shift register unit 22(2×j - 3) as the reset scan signal Scan2(2×j - 1).

[0103] The gates of the first reset transistors M1 in the (2×j)-th row and the gates of the write transistors M2 in the (2×j - 2)-th row may both be electrically connected to the (2×j - 2)-th second shift register unit 22(2×j - 2). The gate of the first reset transistor M1 in the (2×j)-th row may receive the (2×j - 2)-th write scan signal SP(2×j - 2) output by the (2×j - 2)-th second shift register unit 22(2×j - 2) as the reset scan signal Scan2(2×j). Thus, through the multiplexing of shift register units and signal multiplexing, the number of driving circuits can be reduced, which is beneficial to achieving a narrow border of the display panel 01 and is also conducive to circuit layout and simplifies the layout difficulty.

[0104] In yet another alternative embodiment, Figure 14 is a top view structural schematic diagram of another display panel provided by an embodiment of the present invention. Refer to Figure 10 and Figure 14 , the third shift register unit 23 is electrically connected to the gates of the first reset transistors M1 in multiple rows of pixel circuits PX in the same pixel group.

[0105] Specifically, the gates of the first reset transistors M1 in the (2×j - 1)-th row and the gates of the first reset transistors M1 in the (2×j)-th row may receive the j-th reset scan signal Scan2(j) output by the j-th third register unit 23(j). During the display time of one frame of the picture, the number and frequency of the reset scan signals Scan2 output by the third driving circuit VSR3 may be the same as the number and frequency of the compensation scan signals Scan3 output by the first driving circuit VSR1, and both are less than the number and frequency of the write scan signals SP output by the second driving circuit VSR2. Thus, it is beneficial to reduce the number of third shift register units 23 in the third driving circuit VSR3, simplify the circuit layout, reduce the occupation of space, and thus achieve the thinning and narrow border of the display panel 01.

[0106] Based on the above embodiments, the third shift register unit 23 can reuse the second shift register unit 22; the gate of the first reset transistor M1 of the pixel circuit PX in the j-th pixel group is connected to the gate of the writing transistor M2 of the pixel circuit PX in the (j - 1)×k - p row, which is connected to the same second shift register unit 22; where j, k, and p are all integers, j > 1, k is the number of rows of the pixel circuit in the pixel group, and p ≥ 0.

[0107] Exemplarily, continuing with the example where the pixel group includes two pixel rows PR, the enable levels are all low, and the non - enable levels are all high for illustration. Figure 15 It is another timing diagram of a pixel group provided by an embodiment of the present invention. Figure 15 The driving timing corresponds to Figure 10 the pixel circuit of Figure 16 It is another partial top - view schematic diagram of a display panel provided by an embodiment of the present invention. Referring to Figure 10 、 Figure 15 and Figure 16 , the gate of the first reset transistor M1 in the 2×j - 1 row, the gate of the first reset transistor M1 in the 2×j row, and the gate of the writing transistor M2 in the 2×j - 2 row can all be electrically connected to the 2×j - 2nd second shift register unit 22(2×j - 2). The gates of the first reset transistor M1 in the 2×j - 1 row and the first reset transistor M1 in the 2×j row can receive the 2×j - 2nd writing scan signal SP(2×j - 2) output by the 2×j - 2nd second shift register unit 22(2×j - 2) as the reset scan signal Scan2(j).

[0108] In other alternative embodiments, the gate of the first reset transistor M1 in the 2×j - 1 row and the gate of the first reset transistor M1 in the 2×j row can also be electrically connected to the 2×j - 3rd or 2×j - 4th second shift register unit 22(2×j - 3) or 22(2×j - 4), and receive the writing scan signal SP(2×j - 3) or SP(2×j - 4) as the reset scan signal Scan2(j), as long as during the display time of one frame of the picture, in the same pixel circuit PX, the period when the pixel circuit PX resets the second node N2 overlaps with the period when the pixel circuit PX performs threshold compensation.

[0109] Thus, through the multiplexing of shift register units and signals, the number of driving circuits can be reduced, which is beneficial to achieving a narrow border of the display panel 01 and is also conducive to circuit layout and simplifies the layout difficulty. At the same time, in the same pixel circuit PX, the compensation scan signal Scan3 and the reset scan signal Scan2 with overlapping enable time periods are respectively connected to different shift register units, which is beneficial to reducing the load on the compensation scan line Scan3_L, reducing the signal delay of the compensation scan signal Scan3, increasing the charging duration of the threshold compensation stage, so that the pixel circuit PX can fully compensate the threshold voltage Vth of the driving transistor M3 to the first node N1, improving the display uniformity of the display panel 01.

[0110] Based on the above embodiments, the third shift register unit 23 can also multiplex the first shift register unit 21; in the same pixel circuit PX, the gates of the first reset transistor M1 and the compensation transistor M4 are connected to the same first shift register unit 21.

[0111] Exemplarily, continue to take the example where the pixel group includes two pixel rows PR, the enable levels are all low, and the non - enable levels are all high for illustration. Figure 17 It is another timing schematic diagram of a pixel group provided by an embodiment of the present invention. Figure 17 The driving timing corresponds to Figure 10 the pixel circuit of Figure 18 It is another partial top - view schematic diagram of a display panel provided by an embodiment of the present invention. Referring to Figure 10 、 Figure 17 and Figure 18 , the gates of the first reset transistors M1 in the 2×j - 1th row and the gates of the first reset transistors M1 in the 2×jth row can both be electrically connected to the jth first shift register unit 21(j). The gates of the first reset transistors M1 in the 2×j - 1th row and the gates of the first reset transistors M1 in the 2×jth row can receive the jth compensation scan signal Scan3(j) output by the jth first shift register unit 21(j) as the reset scan signal Scan2(j). The gates of the first reset transistors M1 and the gates of the compensation transistors M4 in the same row can be connected to the same compensation scan line Scan3_L, which is beneficial to reducing cross - connecting signal lines, simplifying the circuit layout, and reducing the design difficulty.

[0112] Optionally, Figure 19 It is another circuit structure schematic diagram of a pixel circuit provided by an embodiment of the present invention. Figure 20 It is another circuit structure schematic diagram of a pixel circuit provided by an embodiment of the present invention. Referring to Figure 19 and Figure 20, the pixel circuit PX further includes a storage module 16, and the storage module 16 includes a storage capacitor C2. The first electrode plate of the storage capacitor C2 is electrically connected to the first power supply terminal, and the second electrode plate of the storage capacitor C2 is electrically connected to the first electrode plate of the coupling capacitor C1 at the second node N2, or the second electrode plate of the storage capacitor C2 is electrically connected to the second electrode plate of the coupling capacitor C1 at the first node N1.

[0113] Exemplarily, referring to Figure 19 , when the second electrode plate of the storage capacitor C2 is electrically connected to the first electrode plate of the coupling capacitor C1 at the second node N2, the storage capacitor C2 can store the potential of the second node N2. During the period when data is written into the pixel circuit PX, the potential of the second node N2 changes, and the storage capacitor C2 can store the changed potential of the second node N2, and at the same time, it will not affect the change amount △VN2 of the potential of the second node N2 being coupled to the first node N1, and the change amount △VN1 of the first node N1 = △VN2. During the period when the pixel circuit PX drives the light-emitting element LED to display and emit light, the storage capacitor C2 can maintain the potential of the second node N2 stable, thereby maintaining the stability of the first node N1, so that the pixel circuit PX provides a stable driving current to the light-emitting element LED, and the driving current Id = B×△VN1 2 = B×△VN2 2 = B×(Data - Vref3) 2 , B = (1 / 2)×μ×C ox ×(W / L).

[0114] Referring to Figure 20 , when the second electrode plate of the storage capacitor C2 is electrically connected to the second electrode plate of the coupling capacitor C1 at the first node N1, the storage capacitor C2 can store the potential of the first node N1. During the period when data is written into the pixel circuit PX, the potential of the second node N2 changes, and the storage capacitor C2 will affect the change amount △VN2 of the potential of the second node N2 being coupled to the first node N1, so that the change amount △VN1 of the first node N1 = △VN2×[C1 / (C1 + C2)]. During the period when the pixel circuit PX drives the light-emitting element LED to display and emit light, the storage capacitor C2 can maintain the potential of the first node N1 stable, so that the pixel circuit PX provides a stable driving current to the light-emitting element LED, and the driving current Id = B×△VN1 2 = B×[△VN2×C1 / (C1 + C2)] 2 = B×[(Data - Vref3)×C1 / (C1 + C2)] 2 , B = (1 / 2)×μ×C ox ×(W / L).

[0115] When the storage capacitor C2 is connected to the first node N1, the magnitude of the driving current can be adjusted by regulating the magnitudes of the storage capacitor C1 and the coupling capacitor C2. With the same small driving current, the data signal Data can be adjusted by regulating the magnitudes of the storage capacitor C1 and the coupling capacitor C2. For example, when Id = B×4 and 0V < Data < Vref3 = 4V, as C1 / (C1 + C2) decreases, |Data - Vref3| gradually increases and Data gradually decreases, which is beneficial to reducing the power consumption on the data line Data_L, increasing the charging rate, and achieving high resolution and high refresh rate; when Id = B×4 and Data < Vref3 = 0V, as C1 / (C1 + C2) decreases, |Data - Vref3| gradually increases and |Data| gradually increases, which is also beneficial to increasing the adjustment range of Data on the data line Data_L, achieving precise adjustment of the driving current, and increasing the display contrast.

[0116] Optionally, Figure 21 is a schematic top view structure diagram of another display panel provided by an embodiment of the present invention. Refer to Figures 20 - 21 , the pixel circuit PX further includes an initialization module 17, and the initialization module 17 includes an initialization transistor M5. The first pole of the initialization transistor M5 receives an initialization signal Vref1, and the second pole of the initialization transistor M5 is electrically connected to the gate of the driving transistor M3 at the first node N1. The display panel 01 further includes a fourth driving circuit VSR4, and the fourth driving circuit VSR4 includes a plurality of fourth shift register units 24. The fourth shift register unit 24 is electrically connected to the gate of the initialization transistor M5; the fourth driving circuit VSR4 is used to sequentially control the initialization transistors M5 of each row of pixel circuits PX to initialize the first node N1. In the same pixel circuit PX, the gate of the second reset transistor M7 of the reset module 15 can also be connected to the same fourth shift register unit 24 as the gate of the initialization transistor M5 of the initialization module 17.

[0117] Exemplarily, the first pole of the initialization transistor M5 can be electrically connected to the first reference voltage terminal (not shown in the figure) through the first reset line Vref1_L to receive the initialization signal Vref1; the gate of the initialization transistor M5 can be electrically connected to the fourth shift register unit 24 through the initialization scan line Scan1_L to receive the initialization scan signal Scan1. In an optional implementation manner, the first reference voltage terminal can be multiplexed with the second reference voltage terminal, and the first reset line Vref1_L can be multiplexed with the second reset line Vref2_L.

[0118] During the display time of a frame of image, in the same pixel circuit PX, the initialization transistor M5 can be turned on before the compensation transistor M4 is turned on, initialize the first node N1, clear the electrical signal remaining at the first node N1 during the display time of the previous frame of image, and control the driving transistor M3 to be fully turned on. In this way, when the pixel circuit PX starts to perform threshold compensation, the first power signal PV1 from the first power supply terminal can be transmitted to the first node N1 through the driving transistor M3 and the compensation transistor M4, and the Vgs of the driving transistor M3 can continuously approach Vth, so that the driving transistor M3 can reach the critical state of turning off. At this time, VN1 = PV1 + Vth, and the threshold voltage Vth can be fully compensated to the first node N1. When the pixel circuit PX performs display and emits light, the driving current Id is not affected by the Vth of the driving transistor M3.

[0119] Based on the above embodiments, during the display time of a frame of image, in the same pixel circuit PX, the period when the pixel circuit PX initializes the first node N1 is before the period when the pixel circuit PX performs threshold compensation.

[0120] Exemplarily, continue to take the example where the pixel group includes two pixel rows PR, the enable average level is low, and the non - enable average level is high for illustration. Figure 22 It is a timing diagram of another pixel group provided by an embodiment of the present invention. Figure 22 The driving timing of Figure 19 or Figure 20 corresponds to the pixel circuit of Figures 19 - 22 . Referring to

[0121] During the display time of a frame of image, the pixel circuit PX further includes an initialization stage T0 before the compensation stage T1. In the initialization stage T0, the initialization scan signal Scan1 is at the enable level, the compensation scan signal Scan3, the reset scan signal Scan2, the write scan signal SP, and the emission control signal EM are all at the non - enable level. The initialization transistor M5 is turned on, and the compensation transistor M4, the write transistor M2, and the emission control transistor M6 are turned off. The initialization signal Vref1 of the first reset line Vref1_L can be transmitted to the gate of the driving transistor M3 through the initialization transistor M5 to initialize the driving transistor M3, so that the driving transistor M3 is fully turned on.

[0122] In an optional embodiment, each fourth shift register unit 24 is electrically connected to the gates of the initialization transistors M5 of each row of pixel circuits PX respectively; the fourth shift register unit 24 multiplexes the second shift register unit 22, and the gates of the initialization transistors M5 of the pixel circuits PX in the i-th row are connected to the gates of the writing transistors M2 of the pixel circuits PX in the (i-r)-th row to the same second shift register unit 22; where i and r are both integers, and i>r≥2.

[0123] Exemplarily, continuing with the example where the pixel group includes two pixel rows PR, the enable levels are all low, and the non-enable levels are all high for illustration. Figure 23 It is a partial top view schematic diagram of another display panel provided by an embodiment of the present invention, referring to Figure 19 、 Figure 20 、 Figure 22 and Figure 23 , the gates of the initialization transistors M5 of the (2×j + 1)-th row and the gates of the writing transistors M2 of the (2×j - 3)-th row can be both electrically connected to the (2×j - 3)-th second shift register unit 22(2×j - 3), and the gates of the initialization transistors M5 of the (2×j + 1)-th row can receive the (2×j - 3)-th writing scan signal SP(2×j - 3) output by the (2×j - 3)-th second shift register unit 22(2×j - 3) as the initialization scan signal Scan1(2×j + 1).

[0124] The gates of the initialization transistors M5 of the (2×j + 2)-th row and the gates of the writing transistors M2 of the (2×j - 2)-th row can be both electrically connected to the (2×j - 2)-th second shift register unit 22(2×j - 2), and the gates of the initialization transistors M5 of the (2×j + 2)-th row can receive the (2×j - 2)-th writing scan signal SP(2×j - 2) output by the (2×j - 2)-th second shift register unit 22(2×j - 2) as the initialization scan signal Scan1(2×j + 2). Thus, through shift register unit multiplexing and signal multiplexing, the number of driving circuits can be reduced, which is beneficial to achieving a narrow border of the display panel 01 and is also beneficial to circuit layout and simplifies the layout difficulty.

[0125] In another optional embodiment, Figure 24 It is a top view structural schematic diagram of another display panel provided by an embodiment of the present invention, referring to Figure 19 、 Figure 20 and Figure 24 , the fourth shift register unit 24 is electrically connected to the gates of the initialization transistors M5 of multiple rows of pixel circuits PX in the same pixel group.

[0126] Specifically, the gates of the initialization transistors M5 in the (2×j - 1)-th row and the gates of the initialization transistors M5 in the 2×j-th row can receive the j-th initialization scan signal Scan1(j) output by the j-th fourth-bit register unit 24(j). During the display time of one frame of the picture, the number and frequency of the initialization scan signals Scan1 output by the fourth driving circuit VSR4 can be the same as those of the compensation scan signals Scan3 output by the first driving circuit VSR1, and both are less than the number and frequency of the writing scan signals SP output by the second driving circuit VSR2. In this way, it is beneficial to reduce the number of fourth-bit register units 24 in the fourth driving circuit VSR4, simplify the circuit layout, reduce the space occupation, and thus realize the thinning and narrow bezel of the display panel 01.

[0127] Based on the above embodiments, the fourth-bit register unit 24 multiplexes the first-bit register unit 21, and the initialization module 17 of the j-th pixel group is connected to the compensation module 13 of the (j - s)-th pixel group to the same first-bit register unit 21; where j and s are both integers, j > s ≥ 1.

[0128] Exemplarily, continue to take the pixel group including two pixel rows PR, with the enable level being low and the non-enable level being high as an example for illustration. Figure 25 It is another timing diagram of a pixel group provided by an embodiment of the present invention. Figure 25 The driving timing corresponds to Figure 19 or Figure 20 the pixel circuit of Figure 26 It is another partial top view schematic diagram of a display panel provided by an embodiment of the present invention. Referring to Figure 19 、 Figure 20 、 Figure 25 and Figure 26 , the gates of the initialization transistors M5 in the (2×j - 1)-th row and the gates of the initialization transistors M5 in the 2×j-th row can both be electrically connected to the (j - 1)-th first-bit register unit 21(j - 1), and the gates of the initialization transistors M5 in the (2×j - 1)-th row and the gates of the initialization transistors M5 in the 2×j-th row can receive the (j - 1)-th compensation scan signal Scan3(j - 1) output by the (j - 1)-th first-bit register unit 21(j - 1) as the initialization scan signal Scan1(j). Through the multiplexing of the shift register unit and the signal multiplexing, the number of driving circuits can be reduced, which is beneficial to realizing the narrow bezel of the display panel 01, and is also beneficial to the circuit layout and simplifies the layout difficulty.

[0129] Based on the above embodiments, the fourth shift register unit 24 can also reuse the second shift register unit 22. The gate of the initialization transistor M5 of the pixel circuit PX in the j-th pixel group is connected to the gate of the writing transistor M2 of the pixel circuit PX in the ((j - 1)×k - q)-th row, and they share the same second shift register unit 22, where j, k, and q are all integers, j > 1, k is the number of rows of the pixel circuit PX in the pixel group, and q ≥ 1.

[0130] Exemplarily, continuing with the example where the pixel group includes two pixel rows PR, the enable levels are all low, and the non - enable levels are all high for illustration. Figure 27 It is a timing diagram of another pixel group provided by an embodiment of the present invention. Figure 27 The driving timing corresponds to Figure 19 or Figure 20 the pixel circuit of Figure 28 It is a partial top - view schematic diagram of another display panel provided by an embodiment of the present invention. Referring to Figure 19 、 Figure 20 、 Figure 27 and Figure 28 , the gates of the initialization transistors M5 in the (2×j + 1)-th row, the gates of the initialization transistors M5 in the (2×j + 2)-th row, and the gates of the writing transistors M2 in the (2×j - 2)-th row can all be electrically connected to the 2×j - 2 - th second shift register unit 22(2×j - 2). The gates of the initialization transistors M5 in the (2×j + 1)-th row and the gates of the initialization transistors M5 in the (2×j + 2)-th row can receive the 2×j - 2 - th writing scan signal SP(2×j - 2) output by the 2×j - 2 - th second shift register unit 22(2×j - 2) as the initialization scan signal Scan1(j + 1).

[0131] In this way, while reducing the number of driving circuits, reusing the writing scan signal SP as the initialization signal Scan1 is beneficial to shortening the initialization duration of the pixel circuit PX, thereby increasing the threshold compensation duration of the pixel circuit PX, improving the charging rate of threshold compensation, and further improving display uniformity.

[0132] In other alternative embodiments, the gates of the initialization transistors M5 in the (2×j + 1)-th row and the gates of the initialization transistors M5 in the (2×j + 2)-th row can also be electrically connected to the 2×j - 3 - th or 2×j - 4 - th second shift register unit 22(2×j - 3) or 22(2×j - 4), and receive the writing scan signal SP(2×j - 3) or SP(2×j - 4) as the initialization scan signal Scan1(j + 1), as long as in the display time of one frame of the picture, in the same pixel circuit PX, the period when the pixel circuit PX initializes the first node N1 is before the period when the pixel circuit PX performs threshold compensation.

[0133] Optionally,Figure 29 It is another timing diagram of a pixel group provided by an embodiment of the present invention. Figure 29 The driving timing corresponds to Figure 19 or Figure 20 the pixel circuit of Figure 19 , Figure 20 and Figure 29 . During the display time of a frame of the picture, in the same pixel circuit PX, the period when the pixel circuit PX initializes the first node N1 and the period when the pixel circuit PX performs threshold compensation alternate, and the period when the pixel circuit PX performs threshold compensation is the last period among the two.

[0134] Exemplarily, continue to take the example where the pixel group includes two pixel rows PR, the enable levels are all low levels, the non - enable levels are all high levels, and the gates of the initialization transistors M5 in the same pixel group can receive the same initialization scan signal Scan1. During the display time of a frame of the picture, the pixel circuit PX includes an initialization stage T0, a compensation stage T1, a writing stage T2, and a light - emitting stage T3. During the display time of a frame of the picture, the pixel circuit PX may include multiple initialization stages T0 and multiple compensation stages T1; before data is written into the pixel circuit PX, the pixel circuit PX can initialize the first node N1 multiple times, and the pixel circuit PX can also perform threshold compensation multiple times. By alternately resetting the high and low potentials of the first node N1 multiple times, the bias effect of the driving transistor M3 can be eliminated, thus avoiding the problem of hysteresis of the driving transistor M3. When switching from a black picture to a white picture, the white brightness can be quickly achieved, and the afterimage phenomenon can be avoided.

[0135] It should be noted that only two initialization stages T0 and two compensation stages T1 of the pixel circuit PX are exemplarily shown in the figure during the display time of a frame of the picture. In other embodiments, during the display time of a frame of the picture, the pixel circuit PX may further include more than two initialization stages T0, and / or more than two compensation stages T1. The embodiments of the present invention do not specifically limit the number of the initialization stage T0 and the compensation stage T1 of the pixel circuit PX during the display time of a frame of the picture.

[0136] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Figure 30 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. As Figure 30 shown, the display device 02 includes the display panel 01 provided by any embodiment of the present invention. The display device 02 provided by the embodiment of the present invention can be Figure 30The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptop computers, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control devices, touch interaction terminals, etc. The embodiments of the present invention do not make special limitations in this regard.

[0137] Note that the above is only the preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments here, and various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments only. Without departing from the concept of the present invention, it can also include more other equivalent embodiments, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: A plurality of pixel circuits arranged in an array; The pixel circuit includes a driving transistor, a writing module, a coupling module, a compensation module and a light-emitting element; The writing module is electrically connected to the gate of the driving transistor through the coupling module; the compensation module is electrically connected between the gate and the drain of the driving transistor; the light emitting element is electrically connected to the driving transistor; A plurality of rows of the pixel circuits constitute a pixel group; The display panel further includes a first driving circuit and a second driving circuit; the first driving circuit is used to sequentially control the compensation modules of the plurality of rows of pixel circuits in each pixel group to perform threshold compensation on the driving transistor; the second driving circuit is used to sequentially control the writing modules of the pixel circuits in each row to write data signals to the gate of the driving transistor; The first driving circuit comprises a plurality of first shift register units; the first shift register units are electrically connected to the compensation modules of the plurality of rows of pixel circuits in the same pixel group; The second driving circuit includes a plurality of second shift register units; each of the second shift register units is electrically connected to the writing module of each row of the pixel circuits.

2. The display panel according to claim 1, characterized in that: In the same pixel circuit, the time period during which the pixel circuit performs threshold compensation is located before the time period during which the pixel circuit performs data writing, and the two do not overlap.

3. The display panel according to claim 1, characterized in that: The write module includes a write transistor; The first electrode of the write transistor receives a data signal, the second electrode of the write transistor and the first end of the coupling module are electrically connected to a second node; the gate of the write transistor is electrically connected to the second shift register unit; The compensation module includes a compensation transistor; The first electrode of the compensation transistor is electrically connected to the drain of the driving transistor, the second electrode of the compensation transistor is electrically connected to the gate of the driving transistor; and the gate of the compensation transistor is electrically connected to the first shift register unit.

4. The display panel according to claim 3, characterized in that: The writing module further includes a first reset transistor; a first electrode of the first reset transistor receives a first reset signal, and a second electrode of the first reset transistor is electrically connected to the second node; The display panel further includes a third driving circuit; the third driving circuit is used to sequentially control the first reset transistors of the pixel circuits in each row to reset the second node; The third driving circuit includes a plurality of third shift register units; the third shift register units are electrically connected to the gate of the first reset transistor.

5. The display panel according to claim 4, characterized in that: In the same pixel circuit, a period during which the pixel circuit resets the second node overlaps with a period during which the pixel circuit performs threshold compensation.

6. The display panel according to claim 4, characterized in that: Each of the third shift register units is electrically connected to the gate of the first reset transistor of each row of the pixel circuits; The third shift register unit reuses the second shift register unit; the gate of the first reset transistor of the pixel circuit in the i-th row and the gate of the write transistor of the pixel circuit in the ie-th row are connected to the same second shift register unit; wherein i and e are both integers, i>e≥2.

7. The display panel according to claim 4, characterized in that: The third shift register unit is electrically connected to the gates of the first reset transistors of the plurality of rows of pixel circuits in the same pixel group.

8. The display panel according to claim 7, characterized in that: The third shift register unit reuses the second shift register unit; The gate of the first reset transistor of the pixel circuit in the j-th pixel group and the gate of the write transistor of the pixel circuit in the (j-1)×kp-th row are connected to the same second shift register unit; Wherein, j, k, and p are all integers, j>1, k is the number of rows of the pixel circuits in the pixel group, and p≥0.

9. The display panel according to claim 7, characterized in that: The third shift register unit reuses the first shift register unit; In the same pixel circuit, the gate of the first reset transistor and the gate of the compensation transistor are connected to the same first shift register unit.

10. The display panel according to claim 1, characterized in that: The coupling module includes a coupling capacitor; The pixel circuit further includes a storage module, and the storage module includes a storage capacitor; The first plate of the storage capacitor is electrically connected to the first power supply terminal; the second plate of the storage capacitor is electrically connected to the first plate of the coupling capacitor, or the second plate of the storage capacitor is electrically connected to the second plate of the coupling capacitor.

11. The display panel according to claim 1, characterized in that: The pixel circuit further includes an initialization module; the initialization module includes an initialization transistor; a first electrode of the initialization transistor receives an initialization signal, and a second electrode of the initialization transistor is electrically connected to a gate of the driving transistor at a first node; The display panel further includes a fourth driving circuit; the fourth driving circuit is used to sequentially control the initialization transistors of the pixel circuits in each row to initialize the first node; The fourth driving circuit includes a plurality of fourth shift register units; the fourth shift register units are electrically connected to the gate of the initialization transistor.

12. The display panel according to claim 11, characterized in that: During the display time of a frame of picture, in the same pixel circuit, the period during which the pixel circuit initializes the first node is before the period during which the pixel circuit performs threshold compensation.

13. The display panel according to claim 11, characterized in that: The write module includes a write transistor; The first electrode of the write transistor receives a data signal, the second electrode of the write transistor and the first end of the coupling module are electrically connected to a second node; the gate of the write transistor is electrically connected to the second shift register unit; Each of the fourth shift register units is electrically connected to the gate of the initialization transistor of each row of the pixel circuits; The fourth shift register unit reuses the second shift register unit; the gate of the initialization transistor of the pixel circuit in the i-th row and the gate of the write transistor of the pixel circuit in the ir-th row are connected to the same second shift register unit; wherein i and r are both integers, i>r≥2.

14. The display panel according to claim 11, characterized in that: The fourth shift register unit is electrically connected to the gates of the initialization transistors of the plurality of rows of pixel circuits in the same pixel group.

15. The display panel according to claim 14, characterized in that: The fourth shift register unit reuses the first shift register unit; The initialization module of the jth pixel group and the compensation module of the jsth pixel group are connected to the same first shift register unit; wherein j and s are both integers j>s≥1.

16. The display panel according to claim 14, characterized in that: The fourth shift register unit reuses the second shift register unit; The gate of the initialization transistor of the pixel circuit in the j-th pixel group and the gate of the write transistor of the pixel circuit in the (j-1)×kq-th row are connected to the same second shift register unit; Wherein, j, k, and q are all integers, j>1, k is the number of rows of the pixel circuits in the pixel group, and q≥1.

17. The display panel according to claim 11, characterized in that: During the display time of a frame of picture, in the same pixel circuit, the period in which the pixel circuit initializes the first node and the period in which the pixel circuit performs threshold compensation are performed alternately, and the period in which the pixel circuit performs threshold compensation is the last period.

18. The display panel according to claim 1, characterized in that: The pixel circuit further comprises a light emitting control module; the light emitting control module is electrically connected between the driving transistor and the light emitting element; The display panel further includes a fifth driving circuit, and the fifth driving circuit is used to sequentially turn on the light emitting control modules of the plurality of rows of pixel circuits in each of the pixel groups.

19. The display panel according to claim 1, characterized in that: The pixel circuit further includes a reset module; the reset module is electrically connected to the light emitting element; In the same pixel circuit, the reset module and the compensation module are connected to the same first shift register unit, and / or the reset module and the writing module are connected to the same second shift register unit.

20. A display device, characterized in that: include: The display panel according to any one of claims 1 to 19.

Images