Display control method, display driving chip and electronic equipment

Abstract

The invention discloses a display control method, a display driving chip and electronic equipment, relates to the field of image display, and is used for realizing DDIC self-adaptive adjustment of the frame rate of a display screen. The display control method comprises the following steps: S1, receiving image data; s2, scanning the display screen according to the image data in a first scanning interval in the first refreshing time period, the first scanning interval being the minimum time for completing scanning of one frame of image; a time period after the first scanning interval in the first refreshing time period is a first holding interval; step S3, in the first holding interval, sending a plurality of tearing effect TE signals, the TE signals being used for representing that the image data has been refreshed; and S4, if new image data is received in the first holding interval, restarting execution from the step S2.

Description

Technical Field

[0001] This application relates to the field of image display, and in particular, to a display control method, a display driver chip, and an electronic device. Background Art

[0002] With the popularization of organic light-emitting diode (OLED) displays such as low temperature polycrystalline oxide (LTPO) displays and low temperature poly-silicon (LTPS) displays, the displays of many electronic devices support switching between different frame rates.

[0003] The traditional solution is that the upper layer determines the frame rate of the display screen according to the current application scenario of the electronic device, and then sends a command to the display driver integrated circuit (DDIC) to set the frame rate of the display screen. However, since there are a large number of application programs (APPs) in the application layer, it is difficult to accurately identify the application scenario, so the frame rate of the display screen cannot be accurately determined, or the delay in identifying the application scenario is too large, resulting in untimely frame rate switching of the display screen, and thus causing stuttering problems on the display screen, affecting the user experience. Summary of the Invention

[0004] Embodiments of this application provide a display control method, a display driver chip, and an electronic device, which are used to enable the DDIC to adaptively adjust the frame rate of the display screen.

[0005] To achieve the above object, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a display control method is provided, including: Step S1, receiving image data; Step S2, scanning the display screen according to the image data within a first scanning interval in a first refresh period; the period after the first scanning interval in the first refresh period is a first holding interval, and the first scanning interval refers to the minimum time required to complete the scanning of one frame of image; Step S3, sending a plurality of tearing effect (TE) signals within the first holding interval, and the TE signal is used to indicate that the image data has been refreshed; Step S4, if new image data is received within the first holding interval, start executing from Step S2 again.

[0007] In the display control method provided by the embodiment of the present application, during the hold interval of the refresh period, the DDIC sends multiple TE signals to the processor, rather than waiting until the end of the refresh period to send the TE signal. The reciprocal of the time from the start of the scan interval of the refresh period to the transmission of any TE signal is equal to a frame rate (the frame rate is essentially also a frequency). When the processor needs the display screen to be refreshed at a certain frame rate, it does not need to directly instruct the DDIC to set the frame rate of the display screen. It only needs to fixedly respond to the TE signal corresponding to the frame rate and send image data to the DDIC. That is to say, during the hold interval of the refresh period, the DDIC provides multiple TE signals for the processor to select with a finer granularity. The processor can respond to a certain TE signal at any time to send new image data to the DDIC, and the DDIC refreshes the display screen in response to the received new image data. That is, the frequency at which the processor sends image data (i.e., the frame rate expected by the processor) determines the frame rate at which the DDIC refreshes the display screen, thus realizing the adaptive adjustment of the frame rate of the DDIC for the display screen.

[0008] In a possible implementation manner, it further includes: if no new image data is received during the first hold interval, the image displayed on the display screen is held during the first hold interval. Since the DDIC sends multiple TE signals during the first hold interval, it is possible to receive new image data during the first hold interval. If no new image data is received, the current frame is held and does not need to be frequently refreshed, thereby reducing power consumption.

[0009] In a possible implementation manner, it further includes: sending a TE signal shortly before the end of the first scan interval. At the end of the first scan interval, the DDIC can be ready to receive new image data. When new image data is received, it can return to the first scan interval for refreshing, thereby achieving the highest base frame rate (the reciprocal of the duration of the first scan interval).

[0010] In a possible implementation manner, if no new image data is received during the first hold interval, it further includes: scanning the display screen according to the most recently received image data during the second scan interval of the second refresh period after the first refresh period; the period after the second scan interval in the second refresh period is the second hold interval; multiple TE signals are sent during the second hold interval; if new image data is received during the second hold interval, the execution starts again from step S2. There can be more frame rate options for self-refresh.

[0011] In a possible implementation, it further includes: if no new image data is received within the second holding interval, the image displayed on the display screen is held within the second holding interval. Since the DDIC sends multiple TE signals within the second holding interval, it is possible to receive new image data within the second holding interval. If no new image data is received, the current frame is held and displayed without frequent refreshing, thereby reducing power consumption.

[0012] In a possible implementation, it further includes: sending a TE signal before the end of the second scanning interval. When the first scanning interval ends, the DDIC can be ready to receive new image data. When new image data is received, it can return to the first scanning interval for refreshing, which can shorten the DDIC response time.

[0013] In a possible implementation, the difference between the duration of the second holding interval and the duration of the first holding interval is m times the period of the TE signal, where m is a positive integer. The duration of the holding interval between different refreshing periods steps with the period of the TE signal, so that the holding interval can exactly accommodate an integer number of periods of the TE signal, which can improve the utilization rate of the holding interval.

[0014] In a possible implementation, the period of the TE signal is k times the period of the emission (EM) signal, where k is a positive integer, and the EM signal is used to control the pixels of the display screen to emit light. That is, the frequency of the EM signal is k times the frequency of the TE signal.

[0015] In a second aspect, a display control method is provided, including: Step S1, the processor sends image data to the display driver chip DDIC; Step S2, the DDIC scans the display screen according to the image data within the first scanning interval of the first refreshing period; the period after the first scanning interval in the first refreshing period is the first holding interval; the first scanning interval refers to the minimum time to complete the scanning of one frame of image; Step S3, within the first holding interval, the DDIC sends multiple tearing effect TE signals to the processor, and the TE signal is used to indicate that the image data has been refreshed; Step S4, the processor responds to any TE signal within the first holding interval and sends new image data to the DDIC within the first holding interval; if the DDIC receives new image data within the first holding interval, it restarts from Step S2.

[0016] In a possible implementation, it further includes: if the DDIC does not receive new image data within the first holding interval, the image displayed on the display screen is held within the first holding interval.

[0017] In a possible implementation, it further includes: before the end of the first scanning interval, the DDIC sends a TE signal to the processor.

[0018] In a possible implementation, if the DDIC does not receive new image data within the first holding interval, it further includes: within the second scanning interval during the second refresh period after the first refresh period, the DDIC scans the display screen according to the most recently received image data; the period after the second scanning interval during the second refresh period is the second holding interval; within the second holding interval, the DDIC sends multiple TE signals to the processor; the processor, in response to any one of the TE signals within the second holding interval, sends new image data to the DDIC within the first holding interval; if the DDIC receives new image data within the second holding interval, it resumes execution from step S2.

[0019] In a possible implementation, it further includes: if the DDIC does not receive new image data within the second holding interval, the image displayed on the display screen is held within the second holding interval.

[0020] In a possible implementation, it further includes: before the second scanning interval is about to end, the DDIC sends a TE signal to the processor.

[0021] In a possible implementation, the difference between the duration of the second holding interval and the duration of the first holding interval is m times the period of the TE signal, where m is a positive integer.

[0022] In a possible implementation, the period of the TE signal is k times the period of the emitted EM signal, where k is a positive integer, and the EM signal is used to control the pixels of the display screen to emit light.

[0023] In a third aspect, a display driving chip is provided, and the display driving chip is used to execute the method described in the first aspect and any of its embodiments.

[0024] In a fourth aspect, an electronic device is provided, including a processor, a display screen, and a DDIC as described in the third aspect and any of its embodiments. The processor is used to send image data to the DDIC; the DDIC is used to scan the display screen according to the image data within the first scanning interval during the first refresh period; the period after the first scanning interval during the first refresh period is the first holding interval; the first scanning interval refers to the minimum time required to complete the scanning of one frame of image; the DDIC is further used to send multiple tearing effect TE signals to the processor within the first holding interval, and the TE signal is used to indicate that the image data has been refreshed; the processor is further used to, in response to any one of the TE signals within the first holding interval, send new image data to the DDIC within the first holding interval; the DDIC is further used to, if it receives new image data within the first holding interval, return to the first scanning interval during the first refresh period and scan the display screen according to the new image data.

[0025] In a fifth aspect, a computer-readable storage medium is provided, including instructions that, when executed on an electronic device, cause the electronic device to execute the method described in the first aspect and any of its embodiments, or execute the method described in the second aspect and any of its embodiments.

[0026] In a sixth aspect, a computer program product containing instructions is provided. When the instructions run on the above-mentioned electronic device, the electronic device is caused to execute the method described in the first aspect and any of its embodiments, or execute the method described in the second aspect and any of its embodiments.

[0027] For the technical effects of the second aspect to the sixth aspect, reference may be made to the technical effects of the first aspect and any of its embodiments, which will not be repeated here. Description of the Drawings

[0028] Figure 1 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

[0029] Figure 2 It is a schematic structural diagram of a display control circuit provided by an embodiment of the present application;

[0030] Figure 3 It is a schematic diagram of the relationship between a tearing effect (TE) signal and the frame rate of a display screen provided by an embodiment of the present application;

[0031] Figure 4 It is a schematic diagram of the display screen being refreshed row by row provided by an embodiment of the present application;

[0032] Figure 5 It is a schematic diagram of a DDIC performing self-refresh in sequence according to the frame rates corresponding to different sequences provided by an embodiment of the present application;

[0033] Figure 6 It is a schematic diagram of a software architecture provided by an embodiment of the present application;

[0034] Figure 7 It is a schematic diagram of switching the frame rate of a display screen provided by an embodiment of the present application;

[0035] Figure 8 It is a schematic diagram of a display control method provided by an embodiment of the present application;

[0036] Figure 9 It is a schematic diagram of the transmission frequency of a TE signal provided by an embodiment of the present application;

[0037] Figure 10 It is another schematic diagram of the transmission frequency of a TE signal provided by an embodiment of the present application;

[0038] Figure 11 Schematic diagram of another software architecture provided by an embodiment of the present application;

[0039] Figure 12 Schematic diagram of another display control method provided by an embodiment of the present application. Detailed implementation manners

[0040] First, some concepts related to the present application are described.

[0041] Terms such as "first", "second", etc. involved in the embodiments of the present application are only used for the purpose of distinguishing features of the same type and cannot be understood as indicating relative importance, quantity, order, etc.

[0042] Terms such as "exemplary" or "for example" in the embodiments of the present application are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of terms such as "exemplary" or "for example" is intended to present related concepts in a specific manner.

[0043] Terms such as "coupled" and "connected" involved in the embodiments of the present application should be understood in a broad sense. For example, it can refer to a direct physical connection, or an indirect connection implemented through electronic devices, such as a connection implemented through resistors, inductors, capacitors or other electronic devices.

[0044] An embodiment of the present application provides an electronic device, which is an electronic device with a display screen. The electronic device can be mobile or fixed. The electronic device can be deployed on land (such as indoor or outdoor, handheld or vehicle-mounted, etc.), on water (such as a ship, etc.), or in the air (such as an airplane, a balloon, and a satellite, etc.). The electronic device can be referred to as a user equipment (UE), an access terminal, a terminal unit, a subscriber unit, a terminal station, a mobile station (MS), a mobile phone, a terminal agent, or a terminal device, etc. For example, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a smart bracelet, a smart screen, a smart watch, a virtual reality (VR) device, an augmented reality (AR) device, a terminal in industrial control, a terminal in self-driving, a terminal in remote medical, a terminal in smart grid, a terminal in transportation safety, a terminal in smart city, a terminal in smart home, etc. The embodiment of the present application does not limit the specific type and structure of the electronic device. A possible structure of the electronic device will be described below.

[0045] Taking the electronic device as a mobile phone as an example, Figure 1 A possible structure of the electronic device 101 is shown. The electronic device 101 may include a processor 210, an external memory interface 220, an internal memory 221, a universal serial bus (USB) interface 230, a power management module 240, a battery 241, a wireless charging coil 242, antenna 1, antenna 2, a mobile communication module 250, a wireless communication module 260, an audio module 270, a speaker 270A, a receiver 270B, a microphone 270C, a headphone interface 270D, a sensor module 280, a key 290, a motor 291, an indicator 292, a camera 293, a display screen 294, and a subscriber identification module (SIM) card interface 295, etc. Optionally, in some embodiments, it further includes an audio digital signal processor (ADSP) 243.

[0046] It can be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the electronic device 101. In other embodiments of the present application, the electronic device 101 may include more or fewer components than shown in the figures, or combine certain components, or split certain components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0047] The processor 210 may include one or more processing units. For example, the processor 210 may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processing unit (CPU), an application processor (AP), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), a modulation and demodulation processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a baseband processor, and a neural-network processing unit (NPU), etc. Among them, different processing units may be independent devices or integrated in one or more processors. For example, the processor 210 may be an application processor AP. Or, the above-mentioned processor 210 may be integrated in a system on chip (SoC). Or, the above-mentioned processor 210 may be integrated in an integrated circuit (IC) chip. The processor 210 may include an analog front end (AFE) and a microcontroller unit (MCU) in the IC chip.

[0048] The processor 210 executes the display control method provided in the embodiments of the present application by executing the programs and computer instructions stored in the internal memory 221.

[0049] A memory may also be provided in the processor 210 for storing computer instructions and data. In some embodiments, the memory in the processor 210 is a cache memory. This memory can hold the computer instructions or data that the processor 210 has just used or recycled. If the processor 210 needs to use the computer instructions or data again, it can directly call them from the said memory. This avoids repeated accesses, reduces the waiting time of the processor 210, and thus improves the efficiency of the system.

[0050] In some embodiments, the processor 210 may include one or more interfaces. The interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a USB interface, etc.

[0051] The ADSP 243 can be coupled to the audio module 270 and the sensor module 280. The ADSP 243 can be used to process audio signals and also process sensor data. When the processor is in the sleep state, the ADSP 243 can still remain operational, thereby reducing the power consumption of the electronic device.

[0052] It can be understood that the interface connection relationships between the modules illustrated in the embodiments of the present application are only illustrative and do not constitute a structural limitation on the electronic device 101. In other embodiments of the present application, the electronic device 101 may also adopt different interface connection methods as described in the above embodiments, or a combination of multiple interface connection methods.

[0053] The wireless communication function of the electronic device 101 can be implemented through the antenna 1, antenna 2, the mobile communication module 250, the wireless communication module 260, the modulation and demodulation processor, and the baseband processor, etc.

[0054] Antenna 1 and Antenna 2 are used for transmitting and receiving electromagnetic wave signals. Each antenna in the electronic device 101 can be used to cover a single or multiple communication frequency bands. Different antennas can also be multiplexed to improve the utilization rate of the antennas. For example, Antenna 1 can be multiplexed as a diversity antenna for a wireless local area network. In some other embodiments, the antenna can be used in combination with a tuning switch.

[0055] The mobile communication module 250 can provide solutions for wireless communications including 2G / 3G / 4G / 5G, etc. applied to the electronic device 101. The wireless communication module 260 can provide solutions for wireless communications including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared technology (IR), etc. applied to the electronic device 101. In some embodiments, Antenna 1 of the electronic device 101 is coupled to the mobile communication module 250, and Antenna 2 is coupled to the wireless communication module 260, so that the electronic device 101 can communicate with the network and other devices through wireless communication technologies.

[0056] The external memory interface 220 can be used to connect an external memory card, such as a micro SanDisk (Micro SD) card, to implement the storage capacity expansion of the electronic device 101. The external memory card communicates with the processor 210 through the external memory interface 220 to implement the data storage function. For example, files such as music and videos are saved in the external memory card.

[0057] The internal memory 221 can be used to store computer-executable program codes, and the executable program codes include computer instructions. The processor 210 executes various functional applications and data processing of the electronic device 101 by running the computer instructions stored in the internal memory 221. In addition, the internal memory 221 can include high-speed random access memory, and can also include non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc.

[0058] The memory involved in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memories of the systems and methods described herein are intended to include but not be limited to these and any other suitable types of memories.

[0059] The electronic device 101 may implement audio functions through the audio module 270, the speaker 270A, the receiver 270B, the microphone 270C, the headphone jack 270D, and the application processor, etc. For example, music playback, recording, etc.

[0060] The audio module 270 is used to convert digital audio information into an analog audio signal for output, and is also used to convert an analog audio input into a digital audio signal. In some embodiments, the audio module 270 may be disposed in the processor 210, or some functional modules of the audio module 270 may be disposed in the processor 210. The speaker 270A, also referred to as a "loudspeaker", is used to convert an audio electrical signal into a sound signal. The receiver 270B, also referred to as a "handset", is used to convert an audio electrical signal into a sound signal. The microphone 270C, also referred to as a "microphone" or "transmitter", is used to convert a sound signal into an electrical signal. The electronic device 101 may be provided with at least one microphone 270C. The headphone jack 270D is used to connect a wired headphone. The headphone jack 270D may be a USB interface 230, or may be a 3.5 mm open mobile terminal platform (OMTP) standard interface, or a cellular telecommunications industry association of the USA (CTIA) standard interface.

[0061] The keys 290 include a power-on key, volume keys, etc. The keys 290 may be mechanical keys or may be touch keys. The electronic device 101 can receive key inputs and generate key signal inputs related to the user settings and function controls of the electronic device 101. The motor 291 can generate a vibration prompt. The motor 291 can be used for incoming call vibration prompts and can also be used for touch vibration feedback. The indicator 292 may be an indicator light and can be used to indicate the charging state, power change, and can also be used to indicate messages, missed calls, notifications, etc. The SIM card interface 295 is used to connect a SIM card. The SIM card can be in contact with and separated from the electronic device 101 by inserting or removing the SIM card from the SIM card interface 295. The electronic device 101 can support 1 or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 295 can support Nano SIM cards, Micro SIM cards, SIM cards, etc. In some embodiments, the electronic device 101 uses an embedded SIM (eSIM) card, and the eSIM card can be embedded in the electronic device 101 and cannot be separated from the electronic device 101.

[0062] The electronic device 101 can implement the shooting function through the ISP, camera 293, video codec, GPU, display screen 294, application processor, etc. The ISP is used to process the data fed back by the camera 293. In some embodiments, the ISP can be disposed in the camera 293. The camera 293 is used to capture static images or videos. In some embodiments, the electronic device 101 may include one or N cameras 293, where N is a positive integer greater than 1.

[0063] The electronic device 101 can implement the display function through the GPU, display screen 294, application processor, etc. The GPU is a microprocessor for image processing, connected to the display screen 294 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 210 may include one or more GPUs, which execute computer instructions to generate or change display information.

[0064] The sensor module 280 may include a pressure sensor, gyroscope sensor, barometric pressure sensor, magnetic sensor, acceleration sensor, distance sensor, proximity light sensor, fingerprint sensor, temperature sensor, touch sensor, ambient light sensor, angle sensor, etc. When the display screen 294 is a folding screen, the angle sensor can detect the folding angle of the display screen 294, and the range of the folding angle is 0 - 180 degrees.

[0065] The battery 241 may include one or more batteries to supply power to the load.

[0066] The power management module 240 is used to receive the charging input from the charger. Among them, the charger can be a wireless charger, such as a wireless charging base, other electronic devices 101 with reverse wireless charging function, etc. The power management module 240 can receive the wireless charging input through the wireless charging coil 242 of the electronic device. The charger can also be a wired charger. For example, the power management module 240 can receive the charging input of the wired charger through the USB interface 230. The power management module 240 is also called a charging chip.

[0067] Among them, while the power management module 240 charges the battery 241, it can also supply power to the electronic device. The power management module 240 receives the input of the battery 241 and supplies power to the processor 210, internal memory 221, external memory interface 220, display screen 294, camera 293, wireless communication module 260, etc. The power management module 240 can also be used to monitor parameters such as the capacity, voltage, number of battery cycles, and battery health status (leakage, impedance) of the battery 241. In some other embodiments, the power management module 240 can also be disposed in the processor 210.

[0068] The display screen 294 is used to display images, videos, etc. The display screen 294 includes a display panel. In some embodiments, the electronic device 101 may include one or more display screens 294. The display screen related to the embodiments of the present application may be an OLED display screen with variable frame rate. With the popularization of OLED display screens such as LTPO display screens and LTPS display screens, many OLED display screens can support switching between different frame rates. In particular, the LTPO display screen supports lower frame rates. For example, it can support frame rates of 120hz, 90hz, 90hz, 30hz, 10hz, and even supports a flicker-free frame rate of 1hz. The reason is that: in the OLED display screen, there are thin film transistors (TFTs) for driving pixel points to emit light. However, the TFTs in the LTPS display screen are prone to leakage, while the TFTs in the LTPO display screen use indium gallium zinc oxide process, so that the leakage current generated by the TFT after the capacitance coupled to the TFT gate is charged once is extremely small, ensuring that the voltage applied to the TFT gate can be kept constant for a long time, and the pixel points driven by the TFT can keep emitting light for a long time, thus realizing a very low frame rate.

[0069] As Figure 2 shown, the display screen 294 can be connected to the display driver IC (DDIC) 31 through a flexible circuit board. The processor 210 sends image data to the DDIC 31 through the display serial interface (DSI) interface, and the DDIC 31 refreshes the image displayed on the display screen 294 according to the image data. As Figure 2 and Figure 3 shown, after the DDIC 31 finishes refreshing a frame of image data, it feeds back a frame synchronization signal - the tearing effect (TE) signal to the processor 210. The TE signal indicates that a frame of image data has been refreshed. The processor 210 does not send the next frame of image data to the DDIC 31 until it finishes drawing and synthesizing the next frame of image data and receives the TE signal corresponding to the previous frame of image data. Therefore, the frequency of the TE signal changes with the frame rate of the display screen 294.

[0070] The TE signal can achieve frame synchronization between the processor 210 and the DDIC 31, that is, prevent the image data sent by the processor 210 to the DDIC 31 from being out of sync with the image data refreshed by the DDIC 31 to the display screen 294, resulting in tearing of the display screen 294 (part of the area of the display screen 294 displays the previous frame of image, and the rest of the area displays the next frame of image). As Figure 4As shown, since the display screen 294 refreshes one frame of image line by line, the time when the DDIC 31 sends the TE signal cannot be too early. Otherwise, new image data will be received before the refresh of the previous frame of image is completed, resulting in the above-mentioned display tearing problem. The ideal state is that after the DDIC 31 completes the refresh of the previous frame of image, it immediately receives the image data of the next frame, and then starts the refresh of the next frame of image. Therefore, the DDIC 31 can send the TE signal in advance at the earliest when refreshing the last few rows of pixel points of the display screen 294, so that the DDIC 31 can receive new image data earlier.

[0071] The DDIC 31 may or may not include a graphics random access memory (GRAM). This application takes the DDIC 31 including GRAM as an example for illustration, but is not intended to be limited thereto.

[0072] When the DDIC 31 does not include GRAM, the display screen 294 is called a video display screen. The DDIC 31 cannot store image data and cannot achieve self-refresh of the display screen 294. After the processor 210 sends image data to the DDIC 31, the DDIC 31 can refresh the image displayed on the display screen 294 according to the image data.

[0073] When the DDIC 31 includes GRAM, the GRAM can be used to store image data and can achieve self-refresh of the display screen 294. At this time, the display screen 294 is called a command display screen. After the processor 210 completes the drawing and synthesis of one frame of image data, until it receives the TE signal, it sends a command to the DDIC 31 to indicate: the image data to be written into the GRAM in the DDIC 31, and the position coordinates of the image data to be written. Then the processor 210 writes the image data into the GRAM in the DDIC 31, and the DDIC 31 reads the image data from the GRAM to refresh the image displayed on the display screen 294. If the processor 210 does not send new image data to the DDIC 31, the DDIC 31 can read the image data of the previous frame from the GRAM by itself and continuously refresh the display screen 294 to display the previous frame of image, realizing self-refresh of the display screen 294.

[0074] As Figure 5As shown, in the prior art, when the processor 210 does not send new image data to the DDIC 31, the DDIC 31 continuously performs self-refresh on the previous frame of image in sequence according to the frame rates corresponding to different sequences (essentially different refresh periods). Usually, the frame rates corresponding to different sequences can be set differently. For example, the frame rates corresponding to each sequence gradually decrease, so as to reduce power consumption on the basis of ensuring image smoothness. And, the repetition times can be set for each sequence, and the repetition times are used to indicate the number of times of self-refresh repeated according to the frame rate corresponding to the sequence. That is to say, the DDIC 31 can continuously perform self-refresh multiple times at the same frame rate. After each self-refresh is executed, the DDIC 31 will send a TE signal to the processor 210.

[0075] Exemplarily, different sequences can include Sequence 1 to Sequence 8, etc., and the specific sequences are not limited. Taking Sequence 1 - Sequence 5 as an example, the frame rate of Sequence 1 can be set to 120 hz and the repetition times can be set to 0 times (that is, perform self-refresh once at this frame rate); the frame rate of Sequence 2 can be set to 60 hz and the repetition times can be set to 2 times (that is, perform self-refresh three times at this frame rate); the frame rate of Sequence 3 can be set to 30 hz and the repetition times can be set to 2 times (that is, perform self-refresh three times at this frame rate); the frame rate of Sequence 4 can be set to 10 hz and the repetition times can be set to 2 times (that is, perform self-refresh three times at this frame rate); the frame rate of Sequence 5 can be set to 1 hz and the repetition times can be set to 2 times (that is, perform self-refresh three times at this frame rate). In fact, the frame rates of the DDIC 31 for self-refresh from Sequence 1 to Sequence 5 are successively: 120 hz -> 60 hz -> 60 hz -> 60 hz -> 30 hz -> 30 hz -> 30 hz -> 10 hz -> 10 hz -> 10 hz -> 5 hz -> 5 hz -> 5 hz -> 1 hz -> 1 hz -> 1 hz.

[0076] The time consumed to complete one refresh is called a refresh period. Therefore, a sequence can include one or more refresh periods. Each refresh period at least includes a scanning interval, and optionally also includes a holding interval. In the scanning interval, the DDIC 31 performs a line-by-line scan of the display screen according to the most recently received image data, that is, controls the TFTs driving the pixel points to conduct line by line. The scanning interval is the minimum time to complete the scan of one frame of image. The reciprocal of the scanning interval is called the base frame rate (or fundamental frequency), that is, no matter how the frame rate of the display screen is switched, the frame rate of the display screen will not be higher than the base frame rate, otherwise it is not enough time to complete the scan of one frame of image. And in the holding interval, the DDIC 31 holds the image displayed on the display screen, that is, controls the TFTs driving the pixel points to maintain the conductive state after scanning, so that the display screen continuously displays the most recent frame of image.

[0077] If the DDIC 31 still does not receive new image data from the processor 210 after self-refreshing during the last refresh period of the last sequence (e.g., the 3rd refresh period of sequence 5), the DDIC 31 maintains the refresh rate of this sequence (e.g., 1 hz) all the time, so as to achieve self-refreshing with the lowest power consumption. During the process of self-refreshing of the DDIC 31, if new image data is received from the processor 210, it will jump back to the first sequence and repeat the above process.

[0078] In addition to the DDIC 31 being able to control the display screen to perform self-refreshing at a certain frame rate, the processor 210 can also control the DDIC 31 to switch the frame rate of the display screen. For example, when the user performs a sliding operation on the display screen, it is desired that the frame rate of the display screen is 120 hz or 90 hz to avoid display stuttering. When the display screen is displaying a video, it is desired that the frame rate of the display screen is 60 hz or 30 hz to reduce power consumption on the basis of ensuring image smoothness. When the display screen is displaying a still image, it is desired that the frame rate of the display screen is further reduced. For another example, when there are on-screen display (OSD) layers such as bullet screens and user experience (UX) interactions in the video, it is desired that the frame rate of the display screen is 60 hz; when there are no bullet screens or UX in the video, it is desired that the frame rate of the display screen is 30 hz, etc. The control logic for frame rate switching is relatively complex, and it is required that the frame rate of the display screen can be switched quickly.

[0079] The following will explain how the processor 210 executes the control logic for frame rate switching in the prior art from the perspective of the software architecture of the processor 210.

[0080] From the perspective of the software architecture, the program running on the processor 210 can be based on an operating system, such as etc. As Figure 6 shown, taking the program running on the processor 210 based on as an example, the program running on the processor 210 can be layered according to functions, and can include a kernel layer, a hardware abstraction layer (HAL), and an application layer.

[0081] The kernel layer includes the operating system (OS) kernel and hardware drivers for driving hardware resources, such as a display driver. The operating system kernel is used to manage system processes, memory, driver programs, file systems, and network systems. The display driver is used to implement communication between the processor 210 and the DDIC 31. The HAL provides a set of device function interface specifications for implementing a virtual hardware platform to abstract the hardware, hiding the hardware interface details, making the code hardware-independent, and allowing it to be ported across multiple platforms. For example, the HAL includes a drawing and rendering service (SurfaceFlinger). Among them, the drawing and rendering service (SurfaceFlinger) is used to periodically render and draw image data. The application layer may include APPs that need to display images, such as a photo album APP, a video APP, etc.

[0082] As Figure 6 and Figure 7 shown, in the prior art, the control logic for the processor 210 to execute switching the frame rate of the display screen is as follows: The APP in the application layer of the processor 210 performs drawing and rendering to obtain image data and sends it to the drawing and rendering service (SurfaceFlinger). The drawing and rendering service (SurfaceFlinger) identifies the application scenario of the electronic device (for example, the user performs a sliding operation on the display screen as described above, or plays a video, or displays a static image), determines the frame rate of the display screen according to the identified application scenario, and sends a frame rate setting instruction and image data to the DDIC 31 through the display driver. The frame rate setting instruction is used to instruct the DDIC 31 to set the frame rate of the display screen. The DDIC 31 sets the frame rate of the display screen according to the frame rate setting instruction. After refreshing one frame of the image according to the image data, it sends a TE signal to the processor 210. The frequency of the TE signal is equal to the frame rate of the display screen. The display driver sends a vertical synchronization (VSYNC) signal to the APP through the drawing and rendering service (SurfaceFlinger). The frequency of the VSYNC signal is equal to the frequency of the TE signal, which is also equal to the frame rate of the display screen. After receiving the VSYNC signal, the APP performs drawing and rendering on one frame of the image to obtain new image data and sends it to the drawing and rendering service (SurfaceFlinger) to perform the refresh of the next frame of the image, thereby achieving frame synchronization between the processor 210 and the DDIC 31.

[0083] However, since there are a very large number of applications (APPs) in the application layer, it is difficult for the SurfaceFlinger to accurately identify the application scenario, so it is impossible to accurately determine the frame rate of the display screen. Or, the latency in identifying the application scenario is too large, resulting in untimely switching of the frame rate of the display screen, which causes the display screen to freeze and affects the user experience.

[0084] Embodiments of this application provide a display control method. In the holding interval of the self-refresh sequence 1, the DDIC sends multiple TE signals to the processor, rather than waiting until after the self-refresh of the sequence is completed to send the TE signal. The reciprocal of the time period from the start of the scanning interval of sequence 1 to the sending of any TE signal is equal to a frame rate (the frame rate is essentially also a frequency). When the processor needs the display screen to be refreshed at a certain frame rate, it does not need to instruct the DDIC to set the frame rate of the display screen. It only needs to fixedly respond to the TE signal corresponding to the frame rate and send image data to the DDIC. In this way, the DDIC will receive the image data at this frame rate (i.e., frequency), and after each reception of the image data, it will jump back to the scanning interval of sequence 1 and scan the display screen according to the new image data. That is to say, the DDIC provides multiple TE signals at a finer granularity in the holding interval of sequence 1 for the processor to select. The processor can respond to a certain TE signal at any time to send new image data to the DDIC, and the DDIC refreshes the display screen in response to the received new image data. That is, the frequency at which the processor sends image data (i.e., the frame rate expected by the processor) determines the frame rate at which the DDIC refreshes the display screen, thus realizing the adaptive adjustment of the frame rate of the DDIC for the display screen. As Figure 8 shown, the display control method includes:

[0085] S1. The processor sends image data to the DDIC.

[0086] Correspondingly, the DDIC receives the image data from the processor.

[0087] S2. In the first scanning interval of the first refresh period, the DDIC scans the display screen line by line according to the most recently received image data.

[0088] The first refresh period is the sequence 1 described above. As Figure 9 and Figure 10As shown, the first refresh period includes a first scanning interval and a first holding interval following the first scanning interval. In the first scanning interval, the DDIC scans the display screen line by line according to the most recently received image data to complete the scanning of one frame of image. If no new image data is received during the first refresh period, the DDIC holds the image displayed on the display screen in the first holding interval, that is, controls the TFT driving the pixel points to maintain the turned-on state after scanning. At this time, the display screen continuously displays the most recent frame of image.

[0089] The duration of the first refresh period is equal to the reciprocal of the lowest frame rate of Sequence 1. For example, as Figure 9 and Figure 10 shown, assuming the lowest frame rate in the most common application scenario is 30 hz, the duration of the first refresh period is equal to 33.33 ms. The duration of the first scanning interval is equal to the reciprocal of the base frame rate. For example, as Figure 9 and Figure 10 shown, assuming the base frame rate is 120 hz, the duration of the first scanning interval is equal to 8.33 ms. The base frame rate is referred to the previous description and will not be elaborated here.

[0090] S3. During the first refresh period, the DDIC sends multiple TE signals to the processor.

[0091] As Figure 9 shown, the DDIC can send multiple TE signals to the processor throughout the first refresh period. At this time, it can be called a high-frequency TE signal (for example, the frequency is 360 hz). Or, as Figure 10 shown, the DDIC can send a TE signal A (for example, the frequency is 120 hz) to the processor before the end of the first scanning interval, and send multiple high-frequency TE signals (for example, the frequency is 360 hz) to the processor in the first holding interval, so as to form a hybrid TE signal including different frequencies (for example, 120 hz and 360 hz). Among them, the frequency of the TE signal refers to the reciprocal of the time between sending two adjacent TE signals.

[0092] Multiple TE signals can be sent at equal intervals, thus showing periodic sending ( Figure 9 shown); or, multiple TE signals do not show periodic sending or show partial periodic sending ( Figure 10 shown), etc. This application takes the periodic sending or partial periodic sending of multiple TE signals as an example, but is not intended to be limited thereto. The period of the TE signal is k times the period of the emission (EM) signal, and k is a positive integer. Exemplarily, Figure 9 in, the period of the TE signal is 1 times the period of the ordinary EM signal and 6 times the period of the high-frequency EM signal. The duration of the first holding interval is n times the period of the TE signal, and n is a positive integer. Exemplarily,Figure 9 and Figure 10 In Figure 10 , the duration of the first holding interval is 9 times the period of the TE signal.

[0093] The EM signal is used to control the on and off of the TFT in the OLED driving circuit, thereby controlling whether the pixel emits light. Since the TFT is usually of positive channel metal oxide semiconductor (PMOS) structure, when the EM signal is at a high level, the TFT is turned off, causing the OLED pixel driven by the TFT not to emit light. When the EM signal is at a low level, the TFT is turned on, causing the OLED pixel driven by the TFT to emit light.

[0094] When direct current (DC) dimming is adopted, the EM signal is at a low level, and the brightness of the OLED is adjusted by adjusting the power of the OLED driving circuit. When pulse width modulation (PWM) dimming is adopted, the EM signal can be a PWM signal with a variable duty cycle, and the brightness of the OLED is adjusted by adjusting the duty cycle of the EM signal. For PWM dimming, since when performing scanning operations such as refreshing, resetting, compensating, and charging on each row of OLED pixels, it is all carried out when the OLED pixel is not emitting light (i.e., the EM signal is at a high level), the frequency of the TE signal and the frequency of the EM signal are in a multiple relationship, that is, the frequency of the EM signal is k times the frequency of the TE signal, or rather, the period of the TE signal is k times the period of the EM signal, where k is a positive integer.

[0095] Exemplarily, assuming that the basic frame rate (the reciprocal of the duration of the scanning interval) described above is 120 hz, and it takes 18 EM signal pulses to complete the scanning of one frame of image for high-frequency PWM dimming, then the frequency of the EM signal is 2160 hz (120 * 18 = 2160 hz), the frequency of the TE signal can be 360 hz, the duration of the TE signal is 1 / 360 = 2.778 ms, and the duration of each TE signal corresponds to the duration of 6 EM signals.

[0096] It should be noted that this application is not limited to the basic frame rate of 120 hz and the frequency of the TE signal of 360 hz in the above example. The basic frame rate and the frequency of the TE signal can be flexibly set according to the actual product requirements. For example, the basic frame rate can also be 90 hz, 144 hz, etc., and the frequency of the TE signal can also be 120 hz, 240 hz, 360 hz, 480 hz, etc.

[0097] In addition, Figure 10 the shown scheme relative to Figure 9 the shown scheme, its advantages are: Figure 9The solution realizes that the DDIC receives new image data within a holding interval (such as the first holding interval), and does not receive new image data within a scanning interval (such as the first scanning interval). The reason is that even if the DDIC sends a TE signal within the scanning interval, causing the DDIC to receive new image data within the scanning interval, the DDIC cannot respond and refresh the image data, otherwise it will interrupt the currently ongoing scanning process, resulting in image tearing or other display anomalies. Instead, it is necessary to wait until entering the holding interval to process the above image data. Thus, the risk of the DDIC being abnormally interrupted during scanning within the scanning interval can be effectively avoided.

[0098] S4. In response to any TE signal within the first refresh period, the processor sends new image data to the DDIC within the first refresh period. If the DDIC receives new image data within the first refresh period, it resumes execution from step S2 after a first preset time.

[0099] As Figure 11 shown, after the DDIC 31 sends a high-frequency TE signal or a mixed TE signal to the processor 210, the display screen driver of the processor 210 responds to any TE signal (such as the most recently received TE signal) among the multiple TE signals, and sends a vertical synchronization (VSYNC) signal to the APP through the SurfaceFlinger. The frequency of the VSYNC signal is equal to the frame rate at which the processor expects the display screen to be refreshed, such as 120 hz, 90 hz, or 60 hz, etc. After receiving the VSYNC signal, the APP draws and renders a frame of image to obtain new image data, and sends the new image data to the SurfaceFlinger after receiving the TE signal corresponding to the required frame rate, and then sends it to the display screen driver. The display screen driver sends the new image data to the DDIC 31. The DDIC can then refresh the display screen according to the sending frequency of the image data. Compared with Figure 6 the traditional solution shown, the response is more timely and the performance is better.

[0100] The first preset time refers to the later of the following two times: the time when the image data was most recently received, and the time when the first holding interval starts.

[0101] That is to say, if the DDIC receives new image data within the first scanning interval, it waits for the end of the first scanning interval to complete the scanning of the previous frame of image, and then resumes execution from step S2 to re-enter the first scanning interval for scanning the next frame of image. If the DDIC receives new image data within the first holding interval, it can directly stop holding the previous frame of image and resume execution from step S2, that is, re-enter the first scanning interval for scanning the next frame of image.

[0102] The following will describe the above display control method with the examples of Figure 9 or Figure 10 .

[0103] After the DDIC receives image data from the processor, it starts to refresh the display screen according to Sequence 1 (corresponding to the first refresh period). First, the DDIC completes the scanning of the display screen within the first scanning interval and sends a TE signal A (the frequency of this TE signal is 120 hz) to the processor before the end of the first scanning interval. When the processor sends image data to the DDIC in response to this TE signal A, in fact, the frequency of the image data sent by the processor is also 120 hz. The DDIC receives new image data from the processor after the TE signal A and re-enters the first scanning interval to complete the scanning of a new frame of image. At this time, the frame rate of the display screen adaptively becomes 120 hz.

[0104] If the TE signal A of the DDIC is not responded to by the processor, it periodically sends a TE signal to the processor within the first holding interval. When the processor sends new image data to the DDIC in response to the TE signal B (the frequency of this TE signal B is 90 hz) within the first holding interval, in fact, the frequency of the image data sent by the processor is also 90 hz. The DDIC receives new image data from the processor after the TE signal B and re-enters the first scanning interval to complete the scanning of a new frame of image. At this time, the frame rate of the display screen adaptively becomes 90 hz.

[0105] Similarly, when the processor sends new image data to the DDIC in response to the TE signal C (the frequency of this TE signal C is 60 hz) within the first holding interval, in fact, the frequency of the image data sent by the processor is also 60 hz. The DDIC receives new image data from the processor after the TE signal C and re-enters the first scanning interval to complete the scanning of a new frame of image. At this time, the frame rate of the display screen adaptively becomes 60 hz.

[0106] When the processor sends new image data to the DDIC in response to the TE signal D within the first hold interval (the frequency of the TE signal D is 30 hz), in fact, the frequency at which the processor sends the image data is also 30 hz. The DDIC receives the new image data from the processor after the TE signal D and re-enters the first scan interval to complete the scan of a new frame of image. At this time, the frame rate of the display screen adaptively becomes 30 hz.

[0107] In the actual usage process, the DDIC may continuously send TE signals at one or two frequencies, such as 360 hz, 120 hz, 90 hz, 60 hz, 120 hz & 360 hz (a mixture of 120 hz and 360 hz). The frequency of the TE signal determines the highest frequency at which the AP sends image data and the highest frame rate at which the display screen is refreshed - that is, the base frame rate. The above display control method can theoretically achieve adaptive adjustment of the frame rate within the range from the base frame rate to 1 / [(1 / base frame rate) + n*(1 / TE signal frequency)], where n refers to the duration of the first hold interval being n times the period of the TE signal as described above. For example, Figure 9 In the shown example, n is 9, and the DDIC sends the TE signal at 120 hz. Then, the frequency range of the image data sent by the AP and the frame rate range of the display screen are both: from 120 hz to 1 / [(1 / 120) + n*(1 / 360)] hz, that is, frequencies or frame rates such as 120 hz - 60 hz - 40 hz - 30 hz that are divisible by 120 hz. Similarly, if the DDIC sends the TE signal at 60 hz, then the frequency range of the image data sent by the AP and the frame rate range of the display screen are both frequencies or frame rates such as 60 hz - 30 hz - 20 hz - 10 hz that are divisible by 60 hz.

[0108] Optionally, as Figure 12 shown, if the DDIC does not receive new image data within the first refresh period (including the first hold interval) corresponding to sequence 1, then the self-refresh of the subsequent sequence is executed. Specifically, the above display control method further includes:

[0109] S5. In the second scan interval within the second refresh period after the first refresh period, the DDIC scans the display screen according to the most recently received image data.

[0110] The second refresh period may refer to other sequences (such as sequence 2 to sequence 8, etc.) of the self-refresh except for sequence 1. Similar to the first refresh period, as Figure 9 and Figure 10As shown, the second refresh period includes a second scanning interval and a second holding interval located after the second scanning interval. In the second scanning interval, the DDIC performs a line-by-line scan of the display screen according to the most recently received image data to complete the scan of one frame of the image. If no new image data is received during the second refresh period, the DDIC holds the image displayed on the display screen during the second holding interval, that is, controls the TFT driving the pixel points to maintain the turned-on state after scanning. At this time, the display screen continuously displays the most recent frame of the image.

[0111] The duration of each second refresh period is equal to the reciprocal of the lowest frame rate of the corresponding sequence of that refresh period. The lowest frame rates of each sequence can be the same or different. In particular, the lowest frame rates of each sequence can decrease in sequence, so that the durations of the refresh periods corresponding to each sequence increase in sequence. For example, the lowest frame rate of sequence 1 is 30 hz, the lowest frame rate of sequence 2 is 24 hz, the lowest frame rate of sequence 3 is 20 hz, the lowest frame rate of sequence 4 is 15 hz, the lowest frame rate of sequence 5 is 10 hz, the lowest frame rate of sequence 6 is 5 hz, and the lowest frame rate of sequence 7 is 1 hz. At this time, the difference between the duration of the second holding interval and the duration of the first holding interval is m times the period of the TE signal, where m is a positive integer.

[0112] S6. During the second refresh period, the DDIC sends multiple TE signals.

[0113] Similar to step S3, as Figure 9 shown, the DDIC can send multiple TE signals to the processor during the entire second refresh period. At this time, it can be called a high-frequency TE signal (for example, with a frequency of 360 hz). Or, as Figure 10 shown, the DDIC can send a TE signal (for example, with a frequency of 120 hz) to the processor just before the end of the second scanning interval, and send multiple high-frequency TE signals (for example, with a frequency of 360 hz) to the processor during the second holding interval, thereby forming a hybrid TE signal including different frequencies (for example, 120 hz and 360 hz).

[0114] For other contents of step S6, refer to the description in step S3 and will not be elaborated here.

[0115] S7. In response to any TE signal during the second refresh period, the processor sends new image data to the DDIC during the second refresh period. If the DDIC receives new image data during the second refresh period, it restarts from step S2 after a second preset time. If the DDIC does not receive new image data during the second refresh period, it restarts from step S5.

[0116] Regarding the processor 210 sending new image data to the DDIC 31 in response to the TE signal, refer toFigure 11 The related descriptions are not elaborated here. The second preset time refers to the later time of the following two times: the time when the image data was most recently received, and the time when the second holding interval starts.

[0117] That is to say, if the DDIC receives new image data within the second scanning interval, it waits for the end of the second scanning interval to complete the scanning of the previous frame of image, and then starts to execute from step S2 again, so as to re-enter the first scanning interval to scan the next frame of image. If the DDIC receives new image data within the second holding interval, it can directly stop holding the previous frame of image and start to execute from step S2 again, that is, re-enter the first scanning interval to scan the next frame of image. If the DDIC does not receive new image data within the second refresh period, it enters the next second refresh period and starts self-refreshing again.

[0118] Similarly, the number of repetitions can be set for each sequence according to actual needs. For example, the number of repetitions of sequence 1 is set to 1 time, and the number of repetitions of sequences 2 to 7 is 3 times each. Therefore, the next second refresh period can refer to the next sequence. For example, entering from sequence 2 to sequence 3, or the next second refresh period can also refer to the same sequence. For example, repeating according to the number of repetitions to enter sequence 2. For example, when the DDIC never receives new image data from the processor, the DDIC can perform self-refreshing from sequence 1 to sequence 7, and the self-refreshing frame rates are in turn: 120hz -> 30hz -> 24hz -> 24hz -> 24hz -> 20hz -> 20hz -> 20hz -> 15hz -> 15hz -> 15hz -> 10hz -> 10hz -> 10hz -> 5hz -> 5hz -> 5hz -> 1hz. Then the DDIC always maintains the refresh rate of the last sequence (such as 1hz), so as to achieve self-refreshing with the lowest power consumption. It can achieve adaptive adjustment of the frame rate from dynamic image drawing to static no-image drawing.

[0119] In addition, since the DDIC sends high-frequency TE signals during the holding intervals in each refresh period (i.e., sequence), and does not have to wait until the end of the entire refresh period to send the TE signal, after any TE signal, the DDIC can respond to new image data from the processor and re-enter the first scanning interval at a faster speed to refresh the new image data.

[0120] In the display control method provided by the embodiment of the present application, in the holding interval of the refresh period, the DDIC sends multiple TE signals to the processor, rather than waiting until the end of the refresh period to send the TE signal. The reciprocal of the time from the start of the scanning interval of the refresh period to the sending of any TE signal is equal to a frame rate (the frame rate is essentially also a frequency). When the processor needs the display screen to be refreshed at a certain frame rate, it does not need to directly instruct the DDIC to set the frame rate of the display screen. It only needs to fixedly respond to the TE signal corresponding to the frame rate and send image data to the DDIC. That is to say, in the holding interval of the refresh period, the DDIC provides multiple TE signals for the processor to select with a finer granularity. The processor can respond to a certain TE signal at any time to send new image data to the DDIC, and the DDIC refreshes the display screen in response to the received new image data. That is, the frequency at which the processor sends image data (i.e., the frame rate expected by the processor) determines the frame rate at which the DDIC refreshes the display screen, thus realizing the adaptive adjustment of the frame rate of the DDIC for the display screen.

[0121] The embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium includes instructions. When the instructions run on the above-mentioned electronic device, the electronic device is enabled to execute each step in the above-mentioned method embodiment, such as executing Figure 8 and Figure 12 the method shown.

[0122] The embodiment of the present application also provides a computer program product including instructions. When the instructions run on the above-mentioned electronic device, the electronic device is enabled to execute each step in the above-mentioned method embodiment, such as executing Figure 8 and Figure 12 the method shown.

[0123] For the technical effects of the computer-readable storage medium and the computer program product, refer to the technical effects of the foregoing method embodiment.

[0124] It should be understood that in various embodiments of the present application, the magnitudes of the sequence numbers of the foregoing processes do not mean the order of execution. The execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0125] Those of ordinary skill in the art can realize that the modules and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the present application.

[0126] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and modules described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0127] In several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections between each other can be through some interfaces, and the indirect couplings or communication connections of devices or modules can be in electrical, mechanical, or other forms.

[0128] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one device or distributed to multiple devices. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0129] In addition, in each embodiment of the present application, the functional modules can be integrated in one device, or each module can exist physically alone, or two or more modules can be integrated in one device.

[0130] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired manner (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more media integrated therein. The available medium may be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0131] As described above, the above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A display control method, characterized in that, it includes: Step S1, receiving image data; Step S2, scanning the display screen according to the image data within a first scanning interval in a first refresh period; The period after the first scanning interval in the first refresh period is a first holding interval; the first scanning interval refers to the minimum time required to complete the scanning of one frame of image; Step S3, sending a plurality of tearing effect TE signals within the first holding interval, and the TE signal is used to indicate that the image data has been refreshed; Step S4, if new image data is received within the first holding interval, start executing from Step S2 again.

2. The method according to claim 1, characterized in that, it further includes: If no new image data is received within the first holding interval, the image displayed on the display screen is held within the first holding interval.

3. The method according to claim 1 or 2, characterized in that, it further includes: Sending a TE signal immediately before the end of the first scanning interval.

4. The method according to any one of claims 1-3, characterized in that, if no new image data is received within the first holding interval, it further includes: Scanning the display screen according to the most recently received image data within a second scanning interval in a second refresh period after the first refresh period; the period after the second scanning interval in the second refresh period is a second holding interval; Sending a plurality of the TE signals within the second holding interval; If new image data is received within the second holding interval, start executing from Step S2 again.

5. The method according to claim 4, characterized in that, it further includes: If no new image data is received within the second holding interval, the image displayed on the display screen is held within the second holding interval.

6. The method according to claim 4 or 5, characterized in that, it further includes: Sending a TE signal immediately before the end of the second scanning interval.

7. The method according to any one of claims 4-6, characterized in that, the difference between the duration of the second holding interval and the duration of the first holding interval is m times the period of the TE signal, and m is a positive integer.

8. The method according to any one of claims 1-7, characterized in that, the period of the TE signal is k times the period of the emitted EM signal, and k is a positive integer, and the EM signal is used to control the pixel points of the display screen to emit light.

9. A display control method, characterized in that, it includes: Step S1, the processor sends image data to the display driver integrated circuit DDIC; Step S2, the DDIC scans the display screen according to the image data within a first scanning interval in a first refresh period; The period after the first scanning interval in the first refresh period is a first holding interval; the first scanning interval refers to the minimum time required to complete the scanning of one frame of image; Step S3: Within the first holding interval, the DDIC sends multiple tearing effect TE signals to the processor, and the TE signals are used to indicate that the image data has been refreshed; Step S4: In response to any TE signal within the first holding interval, the processor sends new image data to the DDIC within the first holding interval; if the DDIC receives new image data within the first holding interval, it resumes execution from step S2.

10. The method according to claim 9, wherein, it further includes: If the DDIC does not receive new image data within the first holding interval, the image displayed on the display screen is held within the first holding interval.

11. The method according to claim 9 or 10, wherein, it further includes: Before the end of the first scanning interval, the DDIC sends a TE signal to the processor.

12. The method according to any one of claims 9-11, wherein, if the DDIC does not receive new image data within the first holding interval, it further includes: Within the second scanning interval of the second refreshing period after the first refreshing period, the DDIC scans the display screen according to the most recently received image data; the period after the second scanning interval in the second refreshing period is the second holding interval; Within the second holding interval, the DDIC sends multiple TE signals to the processor; In response to any TE signal within the second holding interval, the processor sends new image data to the DDIC within the first holding interval; if the DDIC receives new image data within the second holding interval, it resumes execution from step S2.

13. The method according to claim 12, wherein, it further includes: If the DDIC does not receive new image data within the second holding interval, the image displayed on the display screen is held within the second holding interval.

14. The method according to claim 12 or 13, wherein, it further includes: Before the end of the second scanning interval, the DDIC sends a TE signal to the processor.

15. The method according to any one of claims 12-14, wherein, the difference in duration between the second holding interval and the first holding interval is m times the period of the TE signal, and m is a positive integer.

16. The method according to any one of claims 9-15, wherein, the period of the TE signal is k times the period of the EM signal for emitting, and k is a positive integer, and the EM signal is used to control the pixel points of the display screen to emit light.

17. A display driving chip, wherein, the display driving chip is used to execute the method according to any one of claims 1-8.

18. An electronic device, wherein, it includes a processor, a display screen, and a display driving chip DDIC according to claim 17; the processor is used to send image data to the DDIC; The DDIC is used to scan the display screen according to the image data within a first scanning interval during a first refresh period; A period after the first scanning interval during the first refresh period is a first holding interval; the first scanning interval refers to the minimum time required to complete the scanning of one frame of image; The DDIC is further used to send a plurality of tearing effect TE signals to the processor within the first holding interval, and the TE signal is used to indicate that the image data has been refreshed; The processor is further used to, in response to any TE signal within the first holding interval, send new image data to the DDIC within the first holding interval; The DDIC is further used to, if new image data is received within the first holding interval, return to the first scanning interval during the first refresh period and scan the display screen according to the new image data.

19. A computer-readable storage medium, characterized in that, it includes instructions which, when executed on an electronic device, cause the electronic device to execute the method according to any one of claims 1-8, or execute the method according to any one of claims 9-16.

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