Display panel, driving method, driving circuit and display device

Abstract

The invention discloses a display panel, a driving method, a driving circuit and a display device, relates to the technical field of display, and can improve the problem of uneven brightness of a display screen. The display panel comprises a plurality of pixel circuits, and each pixel circuit comprises a first light emitting control unit electrically connected between a first node and a second node; the second light emitting control unit is electrically connected between the third node and the fourth node; the driving unit is electrically connected with the second node, the third node and the fifth node; the first data writing unit is electrically connected between a third node and a sixth node and comprises an oxide transistor, and the isolation unit is electrically connected between a fifth node and the sixth node and comprises a polycrystalline silicon transistor; one end of the light-emitting unit is electrically connected with the fourth node, and the other end is used for receiving a second driving signal; wherein the first data write-in unit and the isolation unit have a first time period in which the first data write-in unit and the isolation unit are conducted simultaneously, and after the first time period, the isolation unit is disconnected prior to the first data unit.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to a display panel, a driving method, a driving circuit, and a display device. Background Art

[0002] With the increasing maturity of semiconductor display technologies, such as AMOLED (Active-matrix organic light-emitting diode) and OLED (Organic Light-Emitting Diode), etc., and for the current diverse market demands, higher requirements are put forward for aspects such as the frame rate, resolution, and durability of display screens.

[0003] Pixel circuits fabricated using a process combining LTPS (Low Temperature Poly-Silicon) and oxide technologies are widely used because they take into account the characteristics of low leakage of oxide transistors and high maturity of LTPS processes. However, since oxide transistors are sensitive to temperature and voltage fluctuations, they are prone to the problem of characteristic shift, resulting in changes in the driving current in the pixel circuit, causing uneven brightness in the display screen and reducing the display effect of the display screen. Summary of the Invention

[0004] The display panel, driving method, driving circuit, and display device provided by the embodiments of the present application can improve the technical problem of uneven brightness of the display screen caused by the characteristic shift of oxide transistors in the pixel circuit.

[0005] In a first aspect of the embodiments of the present application, a display panel is provided, including a plurality of pixel circuits, and the pixel circuit includes:

[0006] A first light-emitting control unit, the first light-emitting control unit is electrically connected between a first node and a second node, and the first node is used to receive a first driving signal;

[0007] A second light-emitting control unit, the second light-emitting control unit is electrically connected between a third node and a fourth node;

[0008] A driving unit, the driving unit is electrically connected to the second node, the third node, and a fifth node respectively;

[0009] A first data writing unit, the first data writing unit is electrically connected between the third node and a sixth node, and the first data writing unit includes an oxide transistor;

[0010] An isolation unit, electrically connected between the fifth node and the sixth node, the isolation unit including a polysilicon transistor;

[0011] A light-emitting unit, one end of the light-emitting unit being electrically connected to the fourth node and the other end being configured to receive a second driving signal;

[0012] Wherein, there is a first time period during which the first data writing unit and the isolation unit are simultaneously turned on, and after the first time period, the isolation unit turns off before the first data unit.

[0013] In some embodiments, the oxide transistor of the first data writing unit is in the saturation region during the first time period.

[0014] In some embodiments, the oxide transistor of the first data writing unit is an N-type;

[0015] The polysilicon transistor of the isolation unit is a P-type;

[0016] Wherein, before the first time period, the rising edge of the gate signal of the oxide transistor is before the falling edge of the gate signal of the polysilicon transistor;

[0017] After the first time period, the falling edge of the gate signal of the oxide transistor is after the rising edge of the polysilicon transistor.

[0018] In some embodiments, the pixel circuit further includes:

[0019] A first reset unit, electrically connected to the sixth node, the first reset unit configured to transmit a first reset signal to the sixth node;

[0020] Wherein, there is a second time period during which the first data writing unit and the first reset unit are simultaneously turned on, and before the second time period, the first reset unit turns on before the first data writing unit, and after the second time period, the first reset unit turns off before the first data writing unit, and the second time period does not overlap with the first time period.

[0021] In some embodiments, before the second time period, there is at least one third time period during which the isolation unit and the first reset unit are simultaneously turned on, and before the third time period, the first reset unit turns on before the isolation unit.

[0022] In some embodiments, the pixel circuit further includes:

[0023] A second data writing unit, electrically connected to the second node, for transmitting a data signal to the second node;

[0024] Wherein, the switch state of the second data writing unit is the same as that of the isolation unit.

[0025] In some embodiments, the pixel circuit further includes:

[0026] A second reset unit, electrically connected to the fourth node, for transmitting a second reset signal to the fourth node;

[0027] A third reset unit, electrically connected to the second node, for transmitting a third reset signal to the second node;

[0028] A capacitor, one end of which is electrically connected to the first node and the other end is electrically connected to the fifth node.

[0029] In some embodiments, the first reset unit includes an oxide transistor; and / or,

[0030] The second data writing unit includes a polysilicon transistor; and / or,

[0031] The second reset unit includes a polysilicon transistor; and / or,

[0032] The third reset unit includes a polysilicon transistor; and / or,

[0033] The first light emission control unit includes a polysilicon transistor; and / or,

[0034] The second light emission control unit includes a polysilicon transistor; and / or,

[0035] The driving unit includes a polysilicon transistor.

[0036] In some embodiments, when the driving unit is a P-type polysilicon transistor, the potential of the third reset signal is greater than the potential of the first driving signal;

[0037] When the driving unit is an N-type polysilicon transistor, the potential of the third reset signal is less than the potential of the first driving signal.

[0038] In some embodiments, the first light emission control unit conducts for at least one line scanning duration before the second light emission control unit.

[0039] A second aspect of the embodiments of the present application provides a driving method for a display panel, which is applied to the display panel described in any one of the first aspects. The driving method includes:

[0040] Control the first data writing unit and the isolation unit to conduct, so that there is a first time period when the first data writing unit and the isolation unit are simultaneously conducting, and transmit the writing data to the driving unit;

[0041] After the first time period, control to first disconnect the isolation unit and then disconnect the first data writing unit;

[0042] Control the first light emitting control unit and the second light emitting control unit to conduct, so that the light emitting unit emits light under the action of the first driving signal and the second driving signal.

[0043] In some embodiments, when the pixel circuit includes a first reset unit and there is a second time period when the first data writing unit and the first reset unit are simultaneously conducting, the driving method further includes:

[0044] Before the second time period, control the first reset unit to conduct first;

[0045] After the second time period, control the first reset unit to disconnect first;

[0046] Wherein, the second time period lasts for at least one line scanning duration.

[0047] In some embodiments, before the second time period, there is at least one third time period when the isolation unit and the first reset unit are simultaneously conducting. The driving method further includes:

[0048] Before the second time period, control the first reset unit to conduct to transmit a first reset signal to the sixth node;

[0049] After the first reset unit conducts, control the isolation unit to conduct for at least one of the third time periods to transmit the first reset signal to the fifth node, wherein the third time period lasts for at least one line scanning duration.

[0050] In some embodiments, the driving method further includes:

[0051] Before controlling the first light emitting control unit and the second light emitting control unit to conduct, control the first light emitting control unit to conduct first for at least one line scanning duration compared to the second light emitting control unit.

[0052] In a third aspect of the embodiments of the present application, a driving circuit is provided for the driving method of the display panel as described in any one of the second aspects.

[0053] In a fourth aspect of the embodiments of the present application, a display device is provided, including the display panel as described in any one of the first aspects; and / or, the driving circuit as described in the third aspect.

[0054] In summary, the display panel provided by the embodiments of the present application includes a plurality of pixel circuits. The pixel circuit includes: a first light-emitting control unit electrically connected between a first node and a second node, where the first node is used to receive a first driving signal; a second light-emitting control unit electrically connected between a third node and a fourth node; a driving unit electrically connected to the second node, the third node, and a fifth node respectively; a first data writing unit electrically connected between the third node and a sixth node, where the first data writing unit includes an oxide transistor; an isolation unit electrically connected between the fifth node and the sixth node, where the isolation unit includes a polysilicon transistor. One end of the light-emitting unit is electrically connected to the fourth node, and the other end is used to receive a second driving signal. Among them, there is a first time period when the first data writing unit and the isolation unit are simultaneously turned on, and after the first time period, the isolation unit is turned off before the first data unit. In the present application, by providing an isolation unit between the first data writing unit and the driving unit, and the isolation unit includes a polysilicon transistor. When it is necessary to stop writing charge to the fifth node, the polysilicon transistor in the isolation unit is first turned off, and then the oxide transistor of the first data writing unit is turned off. Polysilicon transistors, especially low-temperature polysilicon transistors, have a mature manufacturing process. Their semiconductor layer is made of polysilicon, and polysilicon has stronger stability, stronger electron binding force, and is not easily affected by the external environment. However, oxide transistors have weaker stability. During long-term operation, the device temperature rises, electron activity intensifies, and the electron binding force is further reduced. Therefore, when the gate-source voltage of the transistor fluctuates, it is particularly easy to cause charge accumulation at the defect between the semiconductor layer and the oxide layer, resulting in charge and discharge, causing a threshold voltage shift, and changing the potential of the gate node of the driving transistor written, thus ultimately causing uneven brightness of the display screen. Therefore, in the present application, the polysilicon transistor in the isolation unit is first turned off. By utilizing the strong stability of the polysilicon transistor, when the gate-source voltage fluctuates, the threshold voltage is not easily shifted. Therefore, at the moment of turning off, the potential difference of the gate node of the driving transistor written is greatly reduced. Subsequently, the reduction degree of the driving current generated by the driving transistor is high, and the brightness of the light-emitting unit will not have problems of dimming or brightening, which can improve the technical problem of uneven brightness of the display screen and improve the uniformity of the display picture.

[0055] Correspondingly, the driving method, driving circuit, and display device provided by the embodiments of the present application also have the above technical effects. Description of the Drawings

[0056] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of illustrating the preferred embodiments and are not considered to be a limitation of the present application. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0057] Figure 1 It is a schematic structural block diagram of a pixel circuit provided by an embodiment of the present application;

[0058] Figure 2 It is a relationship diagram between the threshold voltage of an oxide transistor and the OLED brightness provided by an embodiment of the present application;

[0059] Figure 3 It is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application;

[0060] Figure 4 It is a schematic signal timing diagram of a pixel circuit provided by an embodiment of the present application;

[0061] Figure 5 It is a schematic structural block diagram of another pixel circuit provided by an embodiment of the present application;

[0062] Figure 6 It is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application;

[0063] Figure 7 It is a schematic signal timing diagram of another pixel circuit provided by an embodiment of the present application;

[0064] Figure 8 It is a schematic structural block diagram of yet another pixel circuit provided by an embodiment of the present application;

[0065] Figure 9 It is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present application;

[0066] Figure 10 It is a schematic signal timing diagram of yet another pixel circuit provided by an embodiment of the present application;

[0067] Figure 11 It is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present application;

[0068] Figure 12 It is a schematic signal timing diagram of still another pixel circuit provided by an embodiment of the present application;

[0069] Figure 13 Schematic flowchart of a driving method provided by an embodiment of the present application;

[0070] Figure 14 Schematic structural block diagram of a driving circuit connection relationship provided by an embodiment of the present application;

[0071] Figure 15 Schematic structural diagram of a display device provided by an embodiment of the present application.

[0072] Among them, Figure 1 , Figure 3 , Figure 5 , Figure 6 , Figure 8 , Figure 9 , Figure 11 , Figure 14 and Figure 15 The correspondence between the component names and labels in

[0073] 1000 Display device;

[0074] 100 Pixel circuit, 200 Light-emitting array driving circuit, 300 First gate array driving circuit, 400 Second gate array driving circuit;

[0075] 101 First light-emitting control unit, 102 Second light-emitting control unit, 103 Driving unit, 104 First data writing unit, 105 Isolation unit, 106 Light-emitting unit, 107 First reset unit, 108 Second data writing unit, 109 Second reset unit, 110 Third reset unit;

[0076] N1 First node, N2 Second node, N3 Third node, N4 Fourth node, N5 Fifth node, N6 Sixth node, T5 Polysilicon transistor, T6 Oxide transistor, VDD First driving signal, VSS Second driving signal, Vinit1 First reset signal, Vinit2 Second reset signal, Vinit3 Third reset signal, Data Data signal, T5 Polysilicon transistor, T4 Oxide transistor, Ngate First gate driving signal, Pgate Second gate driving signal, Reset_n First reset driving signal, Reset_p Second reset driving signal, EM Light-emitting control signal, EM1 First light-emitting control signal, EM2 Second light-emitting control signal. Specific implementation manners

[0077] The terms "first", "second", "third", "fourth", etc. (if any) in the description, claims and above-mentioned drawings of this application are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments described here can be implemented in an order other than that illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of this application will be described clearly and completely below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all of the embodiments.

[0078] In the first aspect of the embodiments of this application, a display panel is provided, which includes a plurality of pixel circuits. Figure 1 It is a schematic structural block diagram of a pixel circuit provided by the embodiments of this application. As Figure 1 shown, the pixel circuit 100 includes: a first light-emitting control unit 101, the first light-emitting control unit 101 is electrically connected between a first node N1 and a second node N2, and the first node N1 is used to receive a first driving signal VDD; a second light-emitting control unit, the second light-emitting control unit is electrically connected between a third node N3 and a fourth node N4; a driving unit 103, the driving unit 103 is respectively electrically connected to the second node N2, the third node N3 and a fifth node N5; a first data writing unit 104, the first data writing unit 104 is electrically connected between the third node N3 and a sixth node N6, and the first data writing unit 104 includes an oxide transistor; an isolation unit 105, the isolation unit 105 is electrically connected between the fifth node N5 and the sixth node N6, and the isolation unit 105 includes a polysilicon transistor; a light-emitting unit 106, one end of the light-emitting unit 106 is electrically connected to the fourth node N4, and the other end is used to receive a second driving signal VSS; wherein, there is a first time period when the first data writing unit 104 and the isolation unit 105 are simultaneously turned on, and after the first time period, the isolation unit 105 turns off before the first data unit.

[0079] It should be noted that the first light-emitting control unit 101 is used to control the conduction and cutoff between the first node N1 and the second node N2. When the first node N1 and the second node N2 are conducting, the first driving signal VDD is written into the second node N2. The second light-emitting control unit 102 is used to control the conduction and cutoff between the third node N3 and the fourth node N4. The driving unit 103 is used to control the conduction and cutoff between the second node N2 and the third node N3 under the action of the fifth node N5. When the first light-emitting control unit 101, the second light-emitting control unit 102, and the driving unit 103 are all conducting, the light-emitting unit 106 emits light under the action of the first driving signal VDD and the second driving signal VSS. Among them, the isolation unit 105 is used to control the conduction and cutoff between the fifth node N5 and the sixth node N6, and the first data writing unit 104 is used to control the conduction and cutoff between the third node N3 and the sixth node N6. The first time period represents the time period when the isolation unit 105 and the first data writing unit 104 are conducting simultaneously. During the first time period, the potential of the third node N3 can be written into the fifth node N5 through the first data writing unit 104 and the isolation unit 105. After the first time period, the isolation unit 105 is first cut off, and then the first data writing unit 104 is cut off. Moreover, the isolation unit 105 includes a polysilicon transistor, and the first data writing unit 104 includes an oxide transistor.

[0080] It can be understood that oxide transistors such as IGZO (Indium Gallium Zinc Oxide) have the characteristic of low leakage current. Oxide transistors can be used as isolation switches for writing control signals to the gates of driving transistors in the pixel circuit 100, which can prevent the charge of the gate capacitance from leaking when the driving transistor is in the conducting state, thereby ensuring the stability of the conducting state of the driving transistor. However, due to the current low process maturity of oxide transistors and the relatively active nature of oxides, the threshold voltage characteristics of oxide transistors are prone to shift, especially when the voltage fluctuates. In this way, at the instant when the oxide transistor is cut off, the threshold voltage will have a positive shift or a negative shift. Exemplarily, Figure 2 FIG. is a relationship diagram between the threshold voltage of an oxide transistor and the OLED brightness provided by an embodiment of the present application. Figure 2 The horizontal coordinate ΔV th represents the fluctuation of the threshold voltage of the oxide transistor, with the unit of V (volt), and the vertical coordinate ΔIoled / Ioled represents the percentage change in OLED brightness. As Figure 2As shown, when the oxide transistor undergoes a forward shift, the threshold voltage of the oxide transistor increases, resulting in an increase in the amount of charge on the gate of the write driving transistor, a decrease in the absolute value of the gate-source voltage of the driving transistor, a decrease in the driving current generated by the driving transistor, and the brightness of the OLED being darker than normal. Conversely, when the oxide transistor undergoes a reverse shift, the threshold voltage of the oxide transistor decreases, resulting in a decrease in the amount of charge on the gate of the write driving transistor, an increase in the absolute value of the gate-source voltage of the driving transistor, an increase in the driving current generated by the driving transistor, and the brightness of the OLED being brighter than normal. Therefore, based on the shift of the threshold voltage of the oxide transistor, the display screen will produce uneven bright and dark horizontal stripe phenomena.

[0081] In the embodiment of the present application, an isolation unit 105 is provided between the first data writing unit 104 and the driving unit 103. The isolation unit 105 includes a polysilicon transistor. After the first time period, that is, when it is necessary to stop writing charge to the fifth node N5, the polysilicon transistor in the isolation unit 105 is first turned off, and then the oxide transistor of the first data writing unit 104 is turned off. Polysilicon transistors, especially low-temperature polysilicon transistors, have a mature manufacturing process. Their semiconductor layer is made of polysilicon, and polysilicon has stronger stability, stronger electron binding force, and is not easily affected by the external environment. Oxide transistors have weaker stability. During long-term operation, the device temperature rises, electron activity intensifies, and the electron binding force is further reduced. Therefore, when the gate-source voltage of the transistor fluctuates, it is particularly easy to cause charge accumulation at the defect between the semiconductor layer and the oxide layer, resulting in charge and discharge, causing threshold voltage shift, and changing the potential of the gate node of the write driving transistor, thus ultimately forming uneven brightness and darkness on the display screen. Therefore, in the embodiment of the present application, the polysilicon transistor in the isolation unit 105 is first turned off. By utilizing the strong stability of the polysilicon transistor, when the gate-source voltage fluctuates, the threshold voltage is not easily shifted. Therefore, at the moment of turning off, the potential difference of the gate node of the write driving transistor is greatly reduced, and then the reduction degree of the driving current generated by the driving transistor is high, and the brightness of the light-emitting unit will not have problems of dimming or brightening, which can improve the technical problem of uneven brightness and darkness of the display screen and improve the uniformity of the display image. It should be noted that the first light-emitting control unit 101, the second light-emitting control unit 102, the isolation unit 105, and the first data writing unit 104 can be controlled by a driving chip or a processor in the display panel, and the specific control method is not limited.

[0082] Exemplarily, Figure 3 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application, as Figure 3As shown, the first light emission control unit 101 includes a transistor T1, the second light emission control unit 102 includes a transistor T2, the driving unit 103 includes a transistor T3, the first data writing unit 104 includes an oxide transistor T4, the isolation unit 105 includes a polysilicon transistor T5, and the light emission unit 106 includes an OLED. Among them, the oxide transistor T4 is exemplified by an N-type transistor, and the transistors T1, T2, T3, and the polysilicon transistor T5 are exemplified by P-type transistors.

[0083] Figure 4 FIG. is a schematic signal timing diagram of a pixel circuit provided by an embodiment of the present application, in combination with Figure 3 and Figure 4 As shown, under the action of the high potential of the light emission control signal EM, the transistors T1 and T2 are turned off. Under the action of the high potential of the first gate driving signal Ngate, the oxide transistor T4 is turned on. Under the action of the low potential of the second gate driving signal Pgate, the polysilicon transistor T5 is turned on. The first time period when the oxide transistor T4 and the polysilicon transistor T5 are simultaneously turned on is Figure 4 the T period in. In the t time period, the potential of the third node N3 is written to the fifth node N5 through the sixth node N6, and the potential of the fifth node N5 is stored in the gate capacitance of the transistor T3. After the t time period, under the action of the low potential of the second gate driving signal Pgate, the polysilicon transistor T5 is turned off. After the polysilicon transistor T5 is turned off, the oxide transistor T4 can be turned off.

[0084] It is easy to understand that the cut-off interval time between the polysilicon transistor T5 and the oxide transistor T4 can be determined according to the actual situation, as long as the oxide transistor T4 is turned off after the polysilicon transistor T5 is completely turned off.

[0085] According to some embodiments, Figure 1 and Figure 3 the oxide transistor of the first data writing unit 104 in is in the saturation region in the first time period.

[0086] It should be noted that when the oxide transistor in the first data writing unit 104 is in the saturation region, the source-drain current is little affected by the gate potential. Therefore, when writing data to the fifth node N5 in the above first time period, it is possible to prevent the first gate driving signal Ngate from fluctuating and causing the written data to change, thereby improving the accuracy of the charge amount in the gate capacitance of the driving transistor in the writing driving unit 103, and then improving the accuracy of the driving current, and enabling the brightness of the OLED to be accurately restored.

[0087] According to some embodiments, the oxide transistor of the first data writing unit 104 is an N-type; the polysilicon transistor of the isolation unit 105 is a P-type; wherein, before the first time period, the rising edge of the gate signal of the oxide transistor is before the falling edge of the gate signal of the polysilicon transistor; after the first time period, the falling edge of the gate signal of the oxide transistor is after the rising edge of the polysilicon transistor.

[0088] Exemplarily, as shown in combination with Figure 3 and Figure 4 before the time T in the first time period, i.e., Figure 4 the oxide transistor T4 of the first data unit starts to conduct at the rising edge of the first gate driving signal Ngate, the polysilicon transistor T5 of the isolation unit 105 starts to conduct at the falling edge of the second gate driving signal Pagate, and the rising edge of the first gate driving signal Ngate is before the falling edge of the second gate driving signal Pagate; after the time T, the polysilicon transistor T5 of the isolation unit 105 turns off at the rising edge of the second gate driving signal Pagate, the oxide transistor T4 of the first data unit 104 turns off at the falling edge of the first gate driving signal Ngate, and the falling edge of the first gate driving signal Ngate is after the rising edge of the second gate driving signal Pagate. By staggering the conduction and cutoff of the oxide transistor T4 and the polysilicon transistor T5, it is possible to avoid the threshold voltage shift caused by the oxide transistor T4 at the moment of voltage fluctuation, resulting in a change in the potential written to the fifth node N5.

[0089] According to some embodiments, Figure 5 is a schematic structural block diagram of another pixel circuit provided by an embodiment of the present application. As shown in Figure 5 the pixel circuit 100 further includes: a first reset unit 107, the first reset unit 107 is electrically connected to the sixth node N6, and the first reset unit 107 is configured to transmit a first reset signal to the sixth node N6; wherein, there is a second time period when the first data writing unit 104 and the first reset unit 107 conduct simultaneously, and before the second time period, the first reset unit 107 conducts before the first data writing unit 104, and after the second time period, the first reset unit 107 turns off before the first data writing unit 104, and the second time period does not overlap with the first time period.

[0090] It should be noted that the first reset unit 107 is configured to transmit a first reset signal Vinit1 to the sixth node N6 under the action of a control signal. During the second time period when the first data writing unit 104 and the first reset unit 107 are simultaneously turned on, the first reset signal Vinit1 is written into the third node N3. Since in the first time period, the first data writing unit 104 and the isolation unit 105 are simultaneously turned on to write the potential of the third node N3 to the fifth node N5, therefore, in the first time period, the first reset unit 107 cannot write the first reset signal Vinit1 to the third node N3, and the first time period cannot overlap with the second time period.

[0091] Exemplarily, Figure 6 FIG. is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application. As Figure 6 shown, taking the transistor T6 as an N-type transistor as an example, the first reset unit 107 includes a transistor T6. The gate of the transistor T6 receives a first reset driving signal Reset_n, one of the source or the drain is electrically connected to the sixth node N6, and the other pole receives the first reset signal Vinit1.

[0092] Figure 7 FIG. is a schematic signal timing diagram of another pixel circuit provided by an embodiment of the present application. Combining Figure 6 and Figure 7 shown, in the T3 time period, that is, the above-mentioned second time period, the first reset driving signal Reset_n is at a high potential, the transistor T6 is turned on, the first gate driving signal Ngate is at a high potential, the oxide transistor T4 is turned on, and the first reset signal Vinit1 is written into the third node N3 to set the third node N3.

[0093] Before the t3 stage, the transistor T6 is turned on first to pre-charge the sixth node N6 to adjust the gate-source voltage of the oxide transistor T4 to eliminate the influence caused by the residual charge in the previous frame display image.

[0094] After the t3 stage, the transistor T6 is turned off first, which can avoid the continuous writing of the first reset signal Vinit1 to the sixth node N6, so as not to affect the setting of the fifth node N5 in the subsequent stage.

[0095] It should be noted that since the third node N3 is connected to the transistor T3 in the driving unit 103, setting the third node N3 can adjust the threshold voltage of the transistor T3, eliminate the offset of the threshold voltage of the transistor T3 in the previous frame display image, thereby improving the accuracy of the driving current, and then enabling the brightness of the OLED to be accurately restored.

[0096] According to some embodiments, before the second time period, there is at least a third time period during which the isolation unit 105 and the first reset unit 107 are simultaneously turned on, and before the third time period, the first reset unit 107 is turned on prior to the isolation unit 105.

[0097] Exemplarily, as shown in conjunction with Figure 6 and Figure 7 , during the time period t2 when the second gate drive signal Pgate is at at least one low potential, such as in the time period t2' in Figure 7 , the first reset drive signal Reset_n is at a high potential during the time period t2', and the polysilicon transistor T5 in the isolation unit 105 and the transistor T6 in the first reset unit 107 are simultaneously turned on, and the first reset signal Vinit1 is written to the fifth node N5 through the polysilicon transistor T5.

[0098] It should be noted that setting the electrical potential of the fifth node N5 to the first reset signal Vinit1 can clear the residual charge remaining in the fifth node N5, adjust the gate stress of the transistor T3 in the driving unit 103 to control the threshold voltage of the transistor T3, eliminate the offset of the threshold voltage of the transistor T3 in the previous frame display screen, thereby improving the accuracy of the driving current and the luminance reducibility of the OLED, and then improving the afterimage problem of the display screen.

[0099] The transistor T6 is turned on prior to the polysilicon transistor T5 to set the sixth node N6 first, thereby clearing the residual charge in the sixth node N6 and eliminating the influence on the polysilicon transistor T5, and improving the accuracy of writing the first reset signal Vinit1.

[0100] There can be multiple third time periods. By setting the potential of the fifth node N5 multiple times, the residual charge remaining in the fifth node N5 can be better cleared, and the threshold voltage of the transistor T3 can be adjusted multiple times to improve the adjustment effect.

[0101] It should be noted that clearing the residual charge of the fifth node N5 can also reduce the influence on the characteristics of the polysilicon transistor T5.

[0102] According to some embodiments, as shown in Figure 5 , the pixel circuit 100 further includes: a second data writing unit 108, the second data writing unit 108 is electrically connected to the second node N2, and the second data writing unit 108 is configured to transmit a data signal Data to the second node N2; wherein, the second data writing unit 108 has the same switching state as the isolation unit 105.

[0103] It should be noted that the pixel circuit 100 further includes a second data writing unit 108, and the second data writing unit 108 is electrically connected to the second node N2. After the second data writing unit 108 is turned on, the data signal Data is written into the fifth node N5 through the driving unit 103, the first data writing unit 104, and the isolation unit 105. Since the second data writing unit 108 and the isolation unit 105 are connected in series in the same branch, and the second data writing unit 108 and the isolation unit 105 are functionally bound, the switching states of the second data writing unit 108 and the isolation unit 105 can be the same, so that the control logic of the display panel can be simplified and the driving power consumption can be reduced. Moreover, after the first reset unit 107 sets the sixth node N6, and then uses the second data writing unit 108 to write the data signal Data into the fifth node N5, it can avoid the influence of the residual charge of the sixth node N6 on the conduction states of the isolation unit 105 and the first data writing unit 104, thereby improving the accuracy of writing the data signal Data.

[0104] Exemplarily, as Figure 6 shown, taking a P-type transistor as an example, the second data writing unit 108 includes a transistor T7. The gate of the transistor T7 receives the second gate driving signal Pgate, one of the source and the drain receives the data signal Data, and the other of the source and the drain is electrically connected to the second node N2.

[0105] Combined with Figure 6 and Figure 7 shown, in the third time period t2' of the T2 stage, under the low potential of the second gate driving signal Pgate, the transistor T7 and the polysilicon transistor T5 are turned on simultaneously, and the transistor T6 is turned on under the action of the first reset driving signal Reset_n, and the electrical potential of the sixth node N6 is set to the first reset signal Vinit1. In this stage, the sixth node N6 is set first to clear the residual charge therein and eliminate the influence of the previous frame display picture.

[0106] In the t4 stage, under the low potential of the second gate driving signal Pgate, in the first time period, the transistor T7 and the polysilicon transistor T5 are turned on simultaneously, and the data signal Data is written into the fifth node N5 through the transistor T3, the transistor T2, and the transistor T9.

[0107] In some examples, both the second data writing unit 108 and the isolation unit 105 are controlled by the same driving circuit. Therefore, the gate lines in the display panel can be saved, and thus the width of the non-display area in the display panel can be reduced.

[0108] According to some embodiments, Figure 8Another schematic structural block diagram of the pixel circuit provided by the embodiment of the present application, as Figure 8 shown, the pixel circuit 100 further includes: a second reset unit 109, the second reset unit 109 is electrically connected to the fourth node N4, and the second reset unit 109 is configured to transmit a second reset signal Vinit2 to the fourth node N4; a third reset unit 110, the third reset unit 110 is electrically connected to the second node N2, and the third reset unit 110 is configured to transmit a third reset signal Vinit3 to the second node N2; a capacitor Cst, one end of the capacitor Cst is electrically connected to the first node N1, and the other end is electrically connected to the fifth node N5.

[0109] It should be noted that when the second reset unit 109 is turned on, the second reset signal Vinit2 is written into the fourth node N4. When the third reset unit 110 is turned on, the third reset signal Vinit3 is written into the second node N2. Both ends of the capacitor Cst are electrically connected to the first node N1 and the fifth node N5 respectively, and are used to store the charge for turning on the driving transistor T3.

[0110] Exemplarily, Figure 9 Another schematic structural diagram of the pixel circuit provided by the embodiment of the present application, as Figure 9 shown, taking a P-type transistor as an example, the second reset unit 109 includes a transistor T8, the gate of the transistor T8 receives a second reset driving signal Reset_p, one of the source and the drain is connected to the fourth node N4, and the other of the source and the drain receives the second reset signal Vinit2. The third reset unit 110 includes a transistor T9, the gate of the transistor T9 can also receive the second reset driving signal Reset_p, one of the source or the drain is connected to the second node N2, and the other pole receives the third reset signal Vinit3.

[0111] Figure 10 Another schematic signal timing diagram of the pixel circuit provided by the embodiment of the present application, in combination with Figure 9 and Figure 10 to illustrate each working stage of the pixel circuit 100 provided by the embodiment of the present application:

[0112] At the stage of t1, the second reset driving signal Reset_p is at a low potential, the transistor T8 and the transistor T9 are turned on, and the rest of the transistors are in a cut-off state. The second reset signal Vinit2 and the third reset signal Vinit3 are respectively written into the second node N2 and the fourth node N4 to clear the residual charge after the previous frame of the display screen.

[0113] In the t2 stage, the first reset driving signal Reset_n is at a high potential, and the transistor T6 is in an on state. In this stage, the polysilicon transistor T5 can be turned on once or multiple times under the action of the second gate driving signal Pgate, such as in the time period t2'. In the time period t2', the first reset signal Vinit1 is written into the fifth node N5 through the transistor T6 and the polysilicon transistor T5 to clear the residual charge in the fifth node N5, and the gate stress of the transistor T3 in the driving unit 103 can be adjusted to eliminate the influence on its threshold voltage in the previous frame display image, thereby improving the accuracy of the driving current and the luminance reducibility of the OLED, and then improving the afterimage problem of the display screen. Setting multiple t2' time periods can improve the effect of adjusting the gate stress of the transistor T3.

[0114] In the t3 stage, the first reset driving signal Reset_n is at a high potential, the first gate driving signal Ngate is at a high potential, the second gate driving signal Pgate is at a high potential, the transistor T6 and the oxide transistor T4 are turned on, the transistor T5 is turned off, and the first reset signal Vinit1 sets the third node N3 to clear the residual charge in the third node N3 and bias the threshold voltage of the transistor T3 to further eliminate the influence of the display image on its threshold voltage.

[0115] In the t4 stage, the first gate driving signal Ngate is at a high potential, the first reset driving signal Reset_n is at a low potential, the oxide transistor T4 is turned on, and the transistor T6 is turned off. The second gate driving signal Pgate is at a low potential in the time period t4' to turn on the polysilicon transistor T5 and the transistor T7, and the transistor T3 is turned on under the action of the capacitor Cst. In the time period t4', the data signal Data is written into the capacitor Cst through the transistor T7, the transistor T3, the transistor T4, and the polysilicon transistor T5.

[0116] In the t5 stage, the second reset driving signal Reset_p is at a low potential, the transistor T9 and the transistor T8 are turned on, the third reset signal Vinit3 is written into the second node N2 and the third node N3, and the second reset signal Vinit2 is written into the fourth node N4. In this stage, the third node N3 is set, so that after the transistor T2 is turned on, the charge can be quickly transferred to the capacitor of the OLED, thereby improving the lighting rate of the OLED. Setting the second node N2 and the third node N3 can adjust the threshold voltage of the transistor T3 to improve the accuracy of the driving current.

[0117] It should be noted that in the display panel provided in the embodiment of the present application, the duration of the t5 stage can also be set according to the actual situation and is not specifically limited.

[0118] In the t6 stage, the emission control signal EM is at a low level, the transistor T1 and the transistor T2 are turned on, and the transistor T3 is turned on under the action of the capacitor Cst. The OLED emits light under the driving current of the transistor T3, and the magnitude of the current flowing into the OLED can be determined by the following formula:

[0119] I OLED =K(V sg -|V th |) 2 (1)

[0120] Wherein, K represents a process design constant related to the transistor T3, V sg represents the source-gate voltage of the transistor T3, V sg represents the threshold voltage of the transistor T3, and I OLED represents the driving current.

[0121] V sg in formula (1) can be transformed into:

[0122] V sg =V DD -(V data -|V th |) (2)

[0123] Wherein, V DD represents the potential of the first driving signal VDD, and V data represents the potential of the data signal Data.

[0124] Combining formula (1) and formula (2) can obtain formula (3):

[0125] I OLED =K(V DD -V data ) 2 (3)

[0126] It should be noted that after the t1 to t6 stages, the display panel provided by the embodiment of the present application completes the driving process of a frame of display screen.

[0127] According to some embodiments, as Figure 9 shown, the first reset unit 107 includes an oxide transistor; and / or, the second data writing unit 108 includes a polysilicon transistor; and / or, the second reset unit 109 includes a polysilicon transistor; and / or, the third reset unit 110 includes a polysilicon transistor; and / or, the first emission control unit 101 includes a polysilicon transistor; and / or the second emission control unit 102 includes a polysilicon transistor; and / or, the driving unit 103 includes a polysilicon transistor.

[0128] Exemplarily, Figure 9Among them, the transistor T1, transistor T2, transistor T3, transistor T7, transistor T8, and transistor T9 can be polysilicon transistors. The transistor T6 can be an oxide transistor.

[0129] It should be noted that the current process of polysilicon transistors is mature, and the semiconductor layer is made of polysilicon material. As a result, the binding force of the semiconductor layer on electrons is strong. Therefore, the characteristics of polysilicon transistors are relatively stable, and the threshold voltage is not easily affected by the external environment. However, polysilicon transistors are more likely to leak electricity compared to oxide transistors. Therefore, setting the transistors T1, T2, T3, T7, T8, and T9 that are not directly connected to the capacitor Cst as polysilicon transistors can avoid the leakage defect of polysilicon transistors. Moreover, the electron mobility of polysilicon transistors is relatively high, and the conduction effect is good. Directly connecting them to data signals such as VDD and Data can reduce losses.

[0130] It should be noted that since the transistor T6 is connected in series to the branch of the polysilicon transistor T5 and the capacitor Cst, there is a risk of leakage. Therefore, the transistor T6 is set as an oxide transistor to reduce the leakage risk.

[0131] According to some embodiments, such as Figure 9 shown, when the driving unit 103 is a P-type polysilicon transistor, the potential of the third reset signal Vinit3 is greater than the potential of the first driving signal VDD; when the driving unit 103 is an N-type polysilicon transistor, the potential of the third reset signal Vinit3 is less than the potential of the first driving signal VDD.

[0132] Exemplarily, when the driving unit 103 is a P-type polysilicon transistor, its threshold voltage is less than zero. Therefore, in order to ensure the conduction of the transistor T3, the potential of the source or drain of the transistor T3 can be increased, that is, the potential of the third reset signal Vinit3 is greater than the potential of the first driving signal VDD, so that the transistor T3 is in forward bias, thereby enabling both the second node N2 and the third node N3 to be set.

[0133] Exemplarily, when the driving unit 103 is an N-type polysilicon transistor, its threshold voltage is greater than zero. Therefore, in order to ensure the conduction of the transistor T3, the potential of the source or drain of the transistor T3 can be decreased, that is, the potential of the third reset signal Vinit3 is less than the potential of the first driving signal VDD, so that the transistor T3 is in forward bias, thereby enabling both the second node N2 and the third node N3 to be set.

[0134] According to some embodiments, such as Figure 1 、 Figure 5 、 Figure 8As shown, the first light-emitting control unit 101 is turned on for at least one line scanning duration prior to the second light-emitting control unit 102.

[0135] Exemplarily, Figure 11 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present application. As Figure 11 shown, taking a P-type transistor as an example, the first light-emitting control unit 101 includes a transistor T1, the second light-emitting control unit 102 includes a transistor T2, and the gates of the transistor T1 and the transistor T2 receive a first light-emitting control signal EM1 and a second light-emitting control signal EM2 respectively.

[0136] Figure 12 is a schematic signal timing diagram of another pixel circuit provided by an embodiment of the present application. Combining Figure 11 and Figure 12 shown, in the stages from t1 to t5, both the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are at a high potential, and the transistor T1 and the transistor T2 are turned off. The rest is the same as the foregoing and will not be elaborated.

[0137] In the t6 stage, the first light-emitting control signal EM1 is at a low potential, the transistor T1 is turned on, the second light-emitting control signal EM2 is at a high potential, and the transistor T2 is turned off, and the second node N2 can be pre-charged.

[0138] In the t7 stage, both the transistor T1 and the transistor T2 are turned on, and the OLED emits light.

[0139] It should be noted that in the t6 stage, by pre-charging the second node N2, in the subsequent t7 stage, the pre-charged charge of the second node N2 can be quickly transferred to the capacitor of the OLED, thereby improving the light-emitting rate of the OLED. Moreover, the t6 stage lasts for at least one line scanning duration to ensure sufficient pre-charging. This line scanning duration can be understood as the time interval between adjacent frame display pictures.

[0140] It should be noted that the pulse widths of the first light-emitting control signal EM1 and the second light-emitting control signal EM2 can be the same, and there is a difference of one line scanning duration in timing. Thus, in the case of using a driving circuit to provide the first light-emitting control signal EM1 and the second light-emitting control signal EM2, every two rows of pixel circuits 100 can share one driving circuit, and then the width of the non-display area of the display panel can be reduced.

[0141] A second aspect of the embodiments of the present application provides a driving method for a display panel, which is applied to the display panel in any one of the first aspects. Figure 13 is a schematic flowchart of a driving method provided by an embodiment of the present application. As Figure 13 shown, the above driving method includes:

[0142] S110 controls the first data writing unit 104 and the isolation unit 105 to conduct, so that there is a first time period when the first data writing unit 104 and the isolation unit 105 are simultaneously conducting, and write data is transmitted to the driving unit 103.

[0143] Reference Figure 1 , control the first data writing unit 104 and the isolation unit 105 to conduct simultaneously in the first time period, so that write data can be transmitted to the driving unit 103 through the third node N3, the sixth node N6 and the fifth node. As Figure 3 , Figure 6 , Figure 9 and Figure 11 shown, the first data writing unit 104 includes an oxide transistor T4, the isolation unit 105 includes a polysilicon transistor T5, and the driving unit 103 may include a transistor T3.

[0144] It should be noted that the first time period refers to the time period when the first data writing unit 104 and the isolation unit 105 are simultaneously conducting, as shown by the t time period in Figure 4 , but it is not limited to the first data writing unit 104 and the isolation unit 105 being simultaneously conducting and simultaneously cutoff.

[0145] S120, after the first time period, control to disconnect the isolation unit 105 first and then disconnect the first data writing unit 104.

[0146] Exemplarily, after the first time period and after transmitting write data to the driving unit 103, the branch from the third node N3 to the fifth node N5 can be disconnected.

[0147] It should be noted that the manufacturing process of polysilicon transistors is mature, and the semiconductor layer is made of polysilicon material, which has a strong binding force on electrons. The characteristics of the transistor are relatively stable, and the threshold voltage is not easily affected by the external environment. While the semiconductor layer of the oxide transistor is made of oxide, the characteristics are relatively unstable, and the threshold voltage is prone to shift, especially in the case of voltage fluctuations. Reference Figure 3 , Figure 6 , Figure 9 and Figure 11 , after the first time period, first disconnect the polysilicon transistor T5 in the isolation unit 105, and then disconnect the oxide transistor T4 in the first data writing unit 104. Therefore, the current flowing into the fifth node N5 will not mutate due to the possible threshold voltage shift of the oxide transistor T4, resulting in an increase or decrease in the gate-source voltage of the driving transistor in the driving unit 103. Thus, the driving current generated by the driving unit 103 will not change, and the brightness of the OLED will not become darker or brighter, thereby improving the technical problem of uneven brightness of the display screen.

[0148] S130 controls the first light-emitting control unit 101 and the second light-emitting control unit 102 to conduct, so that the light-emitting unit 106 emits light under the action of the first driving signal and the second driving signal.

[0149] Exemplarily, after the cut-off isolation unit 105, the first light-emitting control unit 101 and the second light-emitting control unit 102 are controlled to conduct, and the light-emitting unit 106 emits light under the action of the first driving signal VDD and the second driving signal VSS.

[0150] It should be noted that the driving method provided by the embodiments of the present application is also applicable to Figure 6 and Figure 7 the embodiments of Figure 9 and Figure 10 as well as Figure 11 and Figure 12 the embodiments of.

[0151] According to some embodiments, as Figure 5 shown, when the pixel circuit 100 includes a first reset unit 107 and there is a second time period during which the first data writing unit 104 and the first reset unit 107 are conducting simultaneously, the driving method further includes: before the second time period, controlling the first reset unit to conduct first; after the second time period, controlling the first reset unit 107 to disconnect first; wherein, the second time period lasts for at least one line scanning duration.

[0152] Exemplarily, in combination with Figure 6 and Figure 7 shown, the first reset unit 107 includes a transistor T6, and the above-mentioned second time period corresponds to Figure 7 the t3 stage in. During the t3 stage, the first reset signal Vinit1 sets the third node N3 through the transistor T6 and the oxide transistor T4 to clear the residual charge in the previous frame display screen, and can adjust the threshold voltage of the transistor T3 to improve the accuracy of the driving current. The second time period lasts for at least one line scanning duration, so as to be able to fully clear the charge of the third node N3.

[0153] Before the t3 stage, the transistor T6 conducts first, which can preheat the transistor T6, so that the transistor T6 conducts more fully during the t3 stage, and prepares for writing data to the fifth node N5.

[0154] After the t3 stage, the transistor T6 is disconnected first, which can avoid the threshold voltage shift of the transistor T6 under the condition of voltage fluctuation and improve the accuracy of subsequent writing data to the fifth node N5.

[0155] It should be noted that the driving method provided by the embodiments of the present application is also applicable to Figure 9 andFigure 10 Embodiments of Figure 11 and Figure 12 embodiments of

[0156] According to some embodiments, before the second time period, there is at least a third time period during which the isolation unit 105 and the first reset unit 107 are simultaneously turned on. The driving method further includes: before the second time period, controlling the first reset unit 107 to be turned on to transmit a first reset signal to the sixth node; after the first reset unit 107 is turned on, controlling the isolation unit 105 to be turned on for at least a third time period to transmit the first reset signal to the fifth node, wherein the third time period lasts for at least one line scanning duration.

[0157] Exemplarily, as shown in combination with Figure 6 and Figure 7 , the time period t2’ represents the above-mentioned third time period. During the time period t2’, the first reset driving signal Reset_n is at a high potential, the polysilicon transistor T5 in the isolation unit 105 and the transistor T6 in the first reset unit 107 are simultaneously turned on, and the first reset signal Vinit1 is written into the fifth node N5 through the polysilicon transistor T5, which can clear the residual charge before the fifth node N5, adjust the gate stress of the transistor T3 in the driving unit 103 to eliminate the influence on its threshold voltage in the previous frame display image, thereby improving the accuracy of the driving current, and then the afterimage problem of the display screen can be improved. There can be multiple third time periods. By setting the potential of the fifth node N5 multiple times, the residual charge before the fifth node N5 can be better cleared, and thus the possibility of the threshold voltage shift of the transistor T3 can be further reduced.

[0158] It should be noted that the driving method provided by the embodiments of the present application is also applicable to the embodiments of Figure 9 and Figure 10 embodiments of Figure 11 and Figure 12 embodiments of

[0159] According to some embodiments, the driving method further includes: before controlling the first light-emitting control unit 101 and the second light-emitting control unit 102 to be turned on, controlling the first light-emitting control unit 101 to be turned on earlier than the second light-emitting control unit 102 for at least one line scanning duration.

[0160] Exemplarily, as shown in combination with Figure 11 and Figure 12 , the first light-emitting control unit 101 may include a transistor T1, the second light-emitting control unit 102 may include a transistor T2, the gate of the transistor T1 receives the first light-emitting control signal EM1, and the gate of the transistor T2 receives the second light-emitting control signal EM2.

[0161] The simultaneous conduction of transistor T2 and transistor T1 corresponds to Figure 12 the t7 stage in [reference], and the OLED enters the light-emitting state in the t7 stage. Before the t7 stage, that is, Figure 2 in the T6 stage in [reference], transistor T1 conducts under the action of the first light-emitting control signal EM1, and transistor T2 is cut off under the action of the second light-emitting control signal EM2. The first driving signal VDD can be written into the second node N2 and the third node N3 to pre-charge the transistor T3 in the driving unit 103.

[0162] It should be noted that in the t6 stage, by pre-charging the second node N2, in the subsequent t7 stage, the pre-charged charge of the second node N2 can be quickly transferred to the capacitor of the OLED, thereby improving the light-emitting rate of the OLED. Moreover, the t6 stage lasts for at least one line scanning duration to ensure sufficient pre-charging. This line scanning duration can be understood as the time interval between the display screens of adjacent frames.

[0163] The third aspect of the embodiments of the present application provides a driving circuit for performing the driving method of the display panel in any one of the second aspects.

[0164] Exemplarily, Figure 14 is a schematic structural block diagram of the connection relationship of a driving circuit provided by the embodiments of the present application. As Figure 14 shown, the driving circuit may include an EOA (Emission gate ON Array, light-emitting array driving circuit) circuit and a GOA (Gate ON Array, gate array driving) circuit. Taking Figure 3 as an example, the EOA circuit is the light-emitting array driving circuit 200 for providing the light-emitting control signal EM to the pixel circuit 100. The GOA1 circuit is the first gate array driving circuit 300 for providing the first gate driving signal to the pixel circuit 100, such as Figure 3 Ngate in [reference]. The GOA2 circuit is the second gate array driving circuit 400 for providing the second gate driving signal to the pixel circuit 100, such as Figure 3 Pgate in [reference].

[0165] It should be noted that the driving circuit can transmit control signals to the pixel circuit 100 under the control of the driving chip in the display panel, or in other control modes, such as a remote controller, etc., which is not specifically limited.

[0166] The fourth aspect of the embodiments of the present application provides a display device, Figure 15 is a schematic structural diagram of a display device provided by the embodiments of the present application. As Figure 15 shown, the above display device 1000 includes a display panel in any one of the first aspects; and / or, a driving circuit in the third aspect.

[0167] Exemplarily, the display device 1000 provided in the embodiments of the present application can be applied to scenarios such as in-vehicle displays, smartphones, computers, medical displays, televisions, and smart wearable displays, etc., and the embodiments of the present application do not make specific limitations.

[0168] It can be understood that the display device 1000 provided in the embodiments of the present application includes the display panel of any one in the first aspect, so it also has all the beneficial effects of the above display panel, which will not be elaborated here.

[0169] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that, it includes a plurality of pixel circuits, and the pixel circuits include: a first light-emitting control unit, the first light-emitting control unit is electrically connected between a first node and a second node, and the first node is used to receive a first driving signal; a second light-emitting control unit, the second light-emitting control unit is electrically connected between a third node and a fourth node; a driving unit, the driving unit is electrically connected to the second node, the third node and a fifth node respectively; a first data writing unit, the first data writing unit is electrically connected between the third node and a sixth node, and the first data writing unit includes an oxide transistor; an isolation unit, the isolation unit is electrically connected between the fifth node and the sixth node, and the isolation unit includes a polysilicon transistor; a light-emitting unit, one end of the light-emitting unit is electrically connected to the fourth node, and the other end is used to receive a second driving signal; wherein, there is a first time period when the first data writing unit and the isolation unit are simultaneously turned on, and after the first time period, the isolation unit is turned off before the first data unit.

2. The display panel according to claim 1, characterized in that, the oxide transistor of the first data writing unit is in the saturation region during the first time period.

3. The display panel according to claim 1, characterized in that, the oxide transistor of the first data writing unit is an N-type; the polysilicon transistor of the isolation unit is a P-type; wherein, before the first time period, the rising edge of the gate signal of the oxide transistor is before the falling edge of the gate signal of the polysilicon transistor; after the first time period, the falling edge of the gate signal of the oxide transistor is after the rising edge of the polysilicon transistor.

4. The display panel according to claim 1, characterized in that, the pixel circuit further includes: a first reset unit, the first reset unit is electrically connected to the sixth node, and the first reset unit is used to transmit a first reset signal to the sixth node; wherein, there is a second time period when the first data writing unit and the first reset unit are simultaneously turned on, and before the second time period, the first reset unit is turned on before the first data writing unit, and after the second time period, the first reset unit is turned off before the first data writing unit, and the second time period does not overlap with the first time period.

5. The display panel according to claim 4, characterized in that, before the second time period, there is at least one third time period when the isolation unit and the first reset unit are simultaneously turned on, and before the third time period, the first reset unit is turned on before the isolation unit.

6. The display panel according to claim 4, characterized in that, the pixel circuit further includes: a second data writing unit, the second data writing unit is electrically connected to the second node, and the second data writing unit is used to transmit a data signal to the second node; wherein, the switching state of the second data writing unit is the same as that of the isolation unit.

7. The display panel according to claim 6, wherein, the pixel circuit further includes: a second reset unit, the second reset unit being electrically connected to the fourth node, and the second reset unit being configured to transmit a second reset signal to the fourth node; a third reset unit, the third reset unit being electrically connected to the second node, and the third reset unit being configured to transmit a third reset signal to the second node; a capacitor, one end of the capacitor being electrically connected to the first node and the other end being electrically connected to the fifth node.

8. The display panel according to claim 7, wherein, the first reset unit includes an oxide transistor; and / or, the second data writing unit includes a polysilicon transistor; and / or, the second reset unit includes a polysilicon transistor; and / or, the third reset unit includes a polysilicon transistor; and / or, the first light emission control unit includes a polysilicon transistor; and / or, the second light emission control unit includes a polysilicon transistor; and / or, the driving unit includes a polysilicon transistor.

9. The display panel according to claim 8, wherein, when the driving unit is a P-type polysilicon transistor, the potential of the third reset signal is greater than the potential of the first driving signal; when the driving unit is an N-type polysilicon transistor, the potential of the third reset signal is less than the potential of the first driving signal.

10. The display panel according to any one of claims 1-9, wherein, the first light emission control unit conducts for at least one row scanning duration prior to the second light emission control unit.

11. A driving method for a display panel, wherein, applied to the display panel according to any one of claims 1-10, the driving method includes: controlling the first data writing unit and the isolation unit to conduct, so that there is a first time period during which the first data writing unit and the isolation unit are simultaneously conducting, and transmitting write data to the driving unit; after the first time period, controlling to first disconnect the isolation unit and then disconnect the first data writing unit; controlling the first light emission control unit and the second light emission control unit to conduct, so that the light emitting unit emits light under the action of the first driving signal and the second driving signal.

12. The driving method for a display panel according to claim 11, wherein, when the pixel circuit includes a first reset unit and there is a second time period during which the first data writing unit and the first reset unit are simultaneously conducting, the driving method further includes: controlling the first reset unit to conduct first before the second time period; controlling the first reset unit to disconnect first after the second time period; wherein, the second time period lasts for at least one row scanning duration.

13. The driving method for a display panel according to claim 12, wherein, before the second time period, there is at least one third time period during which the isolation unit and the first reset unit are simultaneously conducting, the driving method further includes: Before the second time period, control the first reset unit to conduct, so as to transmit a first reset signal to the sixth node; After the first reset unit conducts, control the isolation unit to conduct for at least one of the third time periods, so as to transmit the first reset signal to the fifth node, where the third time period lasts for at least one line scanning duration.

14. The driving method of the display panel according to any one of claims 11-13, characterized in that, further comprising: Before controlling the first light-emitting control unit and the second light-emitting control unit to conduct, control the first light-emitting control unit to conduct for at least one line scanning duration earlier than the second light-emitting control unit.

15. A driving circuit, characterized in that, configured to execute the driving method of the display panel according to any one of claims 11 to 14.

16. A display device, characterized in that, comprising the display panel according to any one of claims 1-10; and / or, the driving circuit according to claim 15.

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