Pixel and display device including same

Abstract

The invention discloses a pixel and a display device including the same. The pixel includes a light emitting element, a first capacitor, a first transistor including a gate electrode connected to a first node, a second transistor including a gate electrode connected to a first scan line, a third transistor including a gate electrode connected to a second scan line, and a fourth transistor including a gate electrode connected to the second scan line. During a first initialization period, a first scan signal provided to the first scan line and a second scan signal provided to the second scan line are at an active level.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2023 - 0164656, filed with the Korean Intellectual Property Office on November 23, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] Embodiments of the present disclosure described herein relate to pixels having improved display quality and a display device including the pixels. Background art

[0004] A display device includes pixels connected to data lines and scan lines. Each of the pixels generally includes a light - emitting element and a pixel circuit for controlling the current flowing through the light - emitting element. In response to a data signal, the pixel circuit controls the amount of current flowing from a first voltage line through the light - emitting element to a second voltage line. The light emitted by the light - emitting element has a brightness corresponding to the amount of current flowing through the light - emitting element. Summary of the invention

[0005] Embodiments of the present disclosure provide pixels having improved display quality and a display device including the pixels.

[0006] According to an embodiment, a pixel may include a light - emitting element, a first capacitor, a first transistor, a second transistor, a third transistor, and a fourth transistor. The light - emitting element includes a first electrode electrically connected to a first voltage line through which a first driving voltage is provided, and a second electrode electrically connected to a second voltage line through which a second driving voltage having a voltage level lower than that of the first driving voltage is provided. The first capacitor is connected between a first node and a second node. The first transistor includes a first electrode connected to a third node, a second electrode electrically connected to the first electrode of the light - emitting element, and a gate electrode connected to the first node. The second transistor includes a first electrode connected to the first node, a second electrode connected to a third voltage line, and a gate electrode connected to a first scan line. The third transistor includes a first electrode connected to the first electrode of the light - emitting element, a second electrode connected to a fifth voltage line, and a gate electrode connected to a second scan line. The fourth transistor includes a first electrode connected to a fourth voltage line, a second electrode connected to the third node, and a gate electrode connected to the second scan line. During a first initialization period, a first scan signal provided to the first scan line and a second scan signal provided to the second scan line may be at an active level.

[0007] During the first initialization period, the width of a second activation period of the second scan signal may be narrower than the width of a first activation period of the first scan signal.

[0008] During a first initialization period, a first initialization voltage may be provided from a third voltage line to a first node.

[0009] During the first initialization period, a second initialization voltage may be provided from a fifth voltage line to a first electrode of a light-emitting element.

[0010] During the first initialization period, a bias voltage may be provided from a fourth voltage line to a third node.

[0011] The pixel may further include a fifth transistor including a first electrode connected to a first voltage line, a second electrode connected to the third node, and a gate electrode connected to a third scan line.

[0012] The pixel may further include a sixth transistor including a first electrode connected to a second electrode of the first transistor, a second electrode connected to the first node, and a gate electrode connected to the third scan line.

[0013] Each of the second transistor and the sixth transistor may include a plurality of transistors connected in series.

[0014] The pixel may further include a seventh transistor and an eighth transistor. The seventh transistor includes a first electrode connected to a sixth voltage line through which a reference voltage is provided, a second electrode connected to a second node, and a gate electrode connected to the third scan line. The eighth transistor includes a first electrode connected to a data line, a second electrode connected to the second node, and a gate electrode connected to a fourth scan line.

[0015] The pixel may further include a ninth transistor and a tenth transistor. The ninth transistor includes a first electrode connected to the first voltage line, a second electrode connected to the third node, and a gate electrode connected to an emission line. The tenth transistor includes a first electrode connected to a second electrode of the first transistor, a second electrode connected to a first electrode of the light-emitting element, and a gate electrode connected to the emission line.

[0016] During a compensation period, a third scan signal provided to the third scan line may be at an active level, and a first driving voltage may be provided to the first node through the fifth transistor, the first transistor, and the sixth transistor.

[0017] The first initialization period and the compensation period may be alternately repeated multiple times.

[0018] The plurality of first initialization periods may include a (1-1) initialization period and a (1-2) initialization period provided after the (1-1) initialization period. During the (1-1) initialization period, the bias voltage may have a first voltage level, and during the (1-2) initialization period, the bias voltage may have a second voltage level higher than the first voltage level.

[0019] During a second initialization period, the first scan signal may be at an active level.

[0020] A compensation period may be arranged between the first initialization period and the second initialization period.

[0021] During a data writing period provided after the first initialization period and the compensation period, a fourth scan signal provided to a fourth scan line may be at an active level.

[0022] During a bias period provided after the data writing period, a second scan signal may be at an active level.

[0023] During a emission period provided after the bias period, an emission signal provided to an emission line may be at an active level, and during the emission period, a light emitting element may emit light.

[0024] According to an embodiment, a display device may include a display panel, a driving circuit, a driving controller, and a voltage generator. The display panel includes pixels connected to a plurality of scan lines, emission lines, and data lines. The driving circuit is configured to drive the plurality of scan lines and emission lines in response to a scan control signal. The driving controller is configured to output the scan control signal. The voltage generator is configured to generate a plurality of driving voltages. The pixel may include a light emitting element, a first capacitor, a first transistor, a second transistor, a third transistor, and a fourth transistor. The light emitting element includes a first electrode electrically connected to a first voltage line through which a first driving voltage is provided, and a second electrode electrically connected to a second voltage line through which a second driving voltage having a voltage level lower than that of the first driving voltage is provided. The first capacitor is connected between a first node and a second node. The first transistor includes a first electrode connected to a third node, a second electrode electrically connected to the first electrode of the light emitting element, and a gate electrode connected to the first node. The second transistor includes a first electrode connected to the first node, a second electrode connected to a third voltage line through which a first initialization voltage is provided, and a gate electrode connected to a first scan line. The third transistor includes a first electrode connected to the first electrode of the light emitting element, a second electrode connected to a fifth voltage line through which a second initialization voltage is provided, and a gate electrode connected to a second scan line. The fourth transistor includes a first electrode connected to a fourth voltage line, a second electrode connected to the third node, and a gate electrode connected to the second scan line. During the first initialization period, a first scan signal provided to the first scan line and a second scan signal provided to the second scan line may be at an active level.

[0025] During the first initialization period, a bias voltage may be provided from the fourth voltage line to the third node, a first initialization voltage may be provided from the third voltage line to the first node, and a second initialization voltage may be provided from the fifth voltage line to the first electrode of the light emitting element.

[0026] The pixel may further include a fifth transistor and a sixth transistor. The fifth transistor includes a first electrode connected to a first voltage line, a second electrode connected to a third node, and a gate electrode connected to a third scan line. The sixth transistor includes a first electrode connected to the second electrode of the first transistor, a second electrode connected to a first node, and a gate electrode connected to the third scan line.

[0027] Each of the second transistor and the sixth transistor may include a plurality of transistors connected in series.

[0028] The pixel may further include a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor. The seventh transistor includes a first electrode connected to a sixth voltage line through which a reference voltage is provided, a second electrode connected to a second node, and a gate electrode connected to the third scan line. The eighth transistor includes a first electrode connected to a data line, a second electrode connected to the second node, and a gate electrode connected to a fourth scan line. The ninth transistor includes a first electrode connected to the first voltage line, a second electrode connected to the third node, and a gate electrode connected to an emission line. The tenth transistor includes a first electrode connected to the second electrode of the first transistor, a second electrode connected to the first electrode of a light-emitting element, and a gate electrode connected to the emission line.

[0029] During a compensation period, a third scan signal provided to the third scan line may be at an active level, and a first driving voltage may be provided to the first node through the fifth transistor, the first transistor, and the sixth transistor.

[0030] The first initialization period and the compensation period may be alternately repeated multiple times. The plurality of first initialization periods may include a (1-1) initialization period and a (1-2) initialization period provided after the (1-1) initialization period. During the (1-1) initialization period, the bias voltage may have a first voltage level, and during the (1-2) initialization period, the bias voltage may have a second voltage level higher than the first voltage level. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other objects and features of the present disclosure will become apparent by referring to the embodiments of the present disclosure described in detail with reference to the accompanying drawings.

[0032] Figure 1 is a perspective view showing a display device according to an embodiment of the present disclosure.

[0033] Figure 2 is a block diagram of a display device according to an embodiment of the present disclosure.

[0034] Figure 3 is a block diagram showing a first driving circuit according to an embodiment of the present disclosure.

[0035] Figure 4 is a block diagram showing a second driving circuit according to an embodiment of the present disclosure.

[0036] Figure 5 is a circuit diagram of a pixel according to an embodiment of the present disclosure.

[0037] Figure 6 and Figure 7 is a timing diagram for describing the operation of a display device according to an embodiment of the present disclosure.

[0038] Figure 8 and Figure 9 is a timing diagram for describing the operation of a pixel according to an embodiment of the present disclosure.

[0039] Figures 10A to 10G is a diagram for describing the operation of a pixel according to an embodiment of the present disclosure.

[0040] Figure 11 is a graph showing the relationship between the G value and the gray level according to an embodiment of the present disclosure.

[0041] Figure 12 is a graph showing the relationship between the G value and the gray level according to an embodiment of the present disclosure.

[0042] Figure 13 is a graph showing the relationship between the JEITA value and the gray level according to an embodiment of the present disclosure.

[0043] Figure 14 is a graph showing the luminance for each time according to an embodiment of the present disclosure.

[0044] Figure 15 is a timing diagram for describing the operation of a pixel according to an embodiment of the present disclosure.

[0045] Figure 16 is a timing diagram for describing the operation of a pixel according to an embodiment of the present disclosure.

[0046] Figure 17 is a graph showing the relationship between the G value and the gray level according to an embodiment of the present disclosure.

[0047] Figure 18 is a graph showing the relationship between the JEITA value and the gray level according to an embodiment of the present disclosure.

[0048] Figure 19A is a circuit diagram of a pixel according to an embodiment of the present disclosure.

[0049] Figure 19B is a timing diagram for describing the operation of a pixel according to an embodiment of the present disclosure. Detailed Description

[0050] In the specification, the expression that a first component (or region, layer, part, or portion) is "on", "connected to", or "coupled to" a second component means that the first component is directly on, directly connected to, or directly coupled to the second component, or means that a third component is interposed therebetween.

[0051] Like reference numerals indicate like components. Additionally, in the drawings, the thickness, proportion, and dimensions of components may be exaggerated to effectively describe technical features. As used herein, the word "or" means a logical "or", such that unless the context otherwise indicates, the expression "A, B, or C" means "A and B and C", "A and B but not C", "A and C but not B", "B and C but not A", "A but not B and not C", "B but not A and not C", and "C but not A and not B".

[0052] Although terms such as "first", "second", etc. may be used to describe respective components, the components should not be construed as being limited by the terms. The terms are only used to distinguish one component from another. For example, without departing from the scope and spirit of the present invention, the first component may be referred to as the "second component", and similarly, the second component may be referred to as the "first component". Unless the context clearly indicates otherwise, the singular form is intended to include the plural form.

[0053] Moreover, terms such as "under", "below", "on", "above", etc. are used to describe the relative relationship of components shown in the drawings. The conceptually opposite terms are described based on the directions shown in the drawings.

[0054] It should also be understood that terms such as "comprising", "including", "having", etc. specify the presence of the stated features, numbers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof.

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used in the specification have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Additionally, terms, such as those defined in a commonly used dictionary, should be interpreted as having a meaning consistent with the context of the relevant art, and should not be interpreted as ideal or overly formal meanings unless expressly defined herein.

[0056] Embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0057] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0058] Referring to Figure 1, the display device DD may have a shape in which the short side (or edge) extends in the first direction DR1 and the long side (or edge) extends in the second direction DR2 that intersects the first direction DR1. However, the shape of the display device DD is not limited thereto. For example, the display device DD can be implemented in various shapes.

[0059] The display device DD according to the present disclosure can be a small or medium-sized electronic device such as a mobile phone, a tablet computer, a car navigation system, or a game console, and a large-sized electronic device such as a television or a monitor. The above examples are only provided as embodiments, and it is obvious that the display device DD can be applied to any other electronic device without departing from the scope and spirit of the present invention.

[0060] The display device DD may include a display panel DP (refer to Figure 2 ). The display panel DP (refer to Figure 2 ) may display an image IM by facing a third direction DR3 that intersects the first direction DR1 and the second direction DR2 on a display surface FS parallel to each of the first direction DR1 and the second direction DR2. The display surface FS on which the image IM is displayed may correspond to the front surface of the display device DD.

[0061] The display surface FS of the display panel DP (refer to Figure 2 ) may be divided into a plurality of regions. A display region DA and a non-display region NDA may be defined on the display surface FS of the display device DD.

[0062] The display region DA may be a region for displaying the image IM, and a user can visually perceive the image IM through the display region DA. The shape of the display region DA may be substantially defined by the non-display region NDA. However, this is shown as an example, and the non-display region NDA may be arranged only adjacent to one side of the display region DA or may be omitted. The display device DD according to an embodiment of the present disclosure may include various embodiments and is not limited to any one embodiment.

[0063] The non-display region NDA as a region adjacent to the display region DA may be a region that does not display the image IM. The border region of the display device DD may be defined by the non-display region NDA.

[0064] The non-display region NDA may surround the display region DA. However, this is shown as an example. The non-display region NDA may be arranged only adjacent to a part of the boundary of the display region DA or may be omitted.

[0065] Figure 2 is a block diagram of a display device according to an embodiment of the present disclosure.

[0066] Refer to Figure 2, the display device DD includes a display panel DP, a driving controller 100, a data driving circuit 200, and a voltage generator 500.

[0067] The display panel DP according to an embodiment of the present disclosure may be a light-emitting display panel, but the present disclosure is not limited thereto. For example, the display panel DP may be an organic light-emitting display panel, a quantum dot light-emitting display panel, a micro-LED display panel, or a nano-LED display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots, quantum rods, etc. The light-emitting layer of the micro-LED display panel may include micro-LEDs. The light-emitting layer of the nano-LED display panel may include nano-LEDs.

[0068] The driving controller 100 may receive an input signal including an input image signal RGB and a control signal CTRL. The driving controller 100 may generate an output image signal DS by converting the data format of the input image signal RGB according to the specification for the interface with the data driving circuit 200. The driving controller 100 may output a first scan control signal SCS1, a second scan control signal SCS2, and a data control signal DCS for controlling the display panel DP so as to be able to display an image.

[0069] Each of the first scan control signal SCS1 and the second scan control signal SCS2 may include a plurality of clock signals and a plurality of start signals.

[0070] The data driving circuit 200 may receive the data control signal DCS and the output image signal DS from the driving controller 100. The data driving circuit 200 may convert the output image signal DS into a data signal, and may output the data signal to a plurality of data lines DL1 to DLm, which will be described later. Herein, m may be a natural number greater than 0. The data signal refers to an analog voltage corresponding to the gray value of the output image signal DS.

[0071] The voltage generator 500 may generate voltages required for the operation of the display panel DP. In an embodiment, the voltage generator 500 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, a second initialization voltage VAINT, a reference voltage VREF, and a bias voltage Vbias.

[0072] The display panel DP may include scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and EBL1 to EBLn, emission lines EML1 to EMLn, data lines DL1 to DLm, and pixels PX. Herein, n may be a natural number greater than 0. The display panel DP may include a first driving circuit 300 and a second driving circuit 400. In an embodiment, the first driving circuit 300 is disposed on a first side of the display panel DP, and the second driving circuit 400 is disposed on a second side of the display panel DP. The scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and EBL1 to EBLn and the emission lines EML1 to EMLn may be electrically connected to the first driving circuit 300 and the second driving circuit 400. The data lines DL1 to DLm may be electrically connected to the data driving circuit 200.

[0073] The scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and EBL1 to EBLn and the emission lines EML1 to EMLn extend in a first direction DR1 and are arranged to be spaced apart from each other in a second direction DR2. The data lines DL1 to DLm extend in the second direction DR2 and are arranged to be spaced apart from each other in the first direction DR1.

[0074] In Figure 2 the example shown, the first driving circuit 300 and the second driving circuit 400 are arranged to face each other with the intervening pixels PX therebetween. However, the present disclosure is not limited thereto. In another embodiment, the display panel DP may include only one of the first driving circuit 300 and the second driving circuit 400.

[0075] The plurality of pixels PX are electrically connected to the scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and EBL1 to EBLn, the emission lines EML1 to EMLn, and the data lines DL1 to DLm. Each of the plurality of pixels PX may be electrically connected to four scan lines and one emission line. For example, as Figure 1 shown, the pixels PX belonging to the first row may be connected to the scan lines GIL1, GCL1, GWL1, and GBL1 and the emission line EML1. Additionally, the pixels PX belonging to the i-th row may be connected to the scan lines GILi, GCLi, GWLi, and EBLi and the emission line EMLi. Herein, i may be a natural number greater than 0 and less than or equal to n.

[0076] Each of the plurality of pixels PX includes a light-emitting element ED (refer to Figure 5 ) and controls the light-emitting element ED (refer to Figure 5) The pixel circuit for emission. The pixel circuit may include one or more transistors and one or more capacitors. The first driving circuit 300 and the second driving circuit 400 may include transistors formed by the same process as the transistors of the pixel circuit.

[0077] Each of the plurality of pixels PX may receive a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, a second initialization voltage VAINT, a reference voltage VREF, and a bias voltage Vbias.

[0078] The first driving circuit 300 may receive a first scan control signal SCS1 from the driving controller 100. In response to the first scan control signal SCS1, the first driving circuit 300 may output scan signals to scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and EBL1 to EBLn and may output emission signals to emission lines EML1 to EMLn.

[0079] The second driving circuit 400 may receive a second scan control signal SCS2 from the driving controller 100. In response to the second scan control signal SCS2, the second driving circuit 400 may output scan signals to scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and EBL1 to EBLn and may output emission signals to emission lines EML1 to EMLn.

[0080] In an embodiment, the scan signals output from the first driving circuit 300 to scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and EBL1 to EBLn and the emission signals output from the first driving circuit 300 to emission lines EML1 to EMLn may be substantially the same as the scan signals output from the second driving circuit 400 to scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and EBL1 to EBLn and the emission signals output from the second driving circuit 400 to emission lines EML1 to EMLn, respectively.

[0081] In an embodiment, the display panel DP may include only one of the first driving circuit 300 and the second driving circuit 400.

[0082] Figure 3 is a block diagram showing a first driving circuit according to an embodiment of the present disclosure.

[0083] Referring to Figure 3 FIG., the first driving circuit 300 may include an emission driving circuit 310, a first scan driving circuit 320, a second scan driving circuit 330, and a third scan driving circuit 340.

[0084] The emission driving circuit 310 may receive at least one corresponding clock signal among a plurality of clock signals and a corresponding start signal among a plurality of start signals through the first scan control signal SCS1. The emission driving circuit 310 may output, in response to the first scan control signal SCS1, emission signals EM1 to EMn to be provided to the emission lines EML1 to EMLn shown in Figure 2 Emission signals EM1 to EMn to be provided to the emission lines EML1 to EMLn shown in

[0085] The first scan driving circuit 320 may receive at least one corresponding clock signal among a plurality of clock signals and a corresponding start signal among a plurality of start signals through the first scan control signal SCS1. In response to the first scan control signal SCS1, the first scan driving circuit 320 may output scan signals GI1 to GIn to be provided to the scan lines GIL1 to GILn shown in Figure 2 And scan signals GC1 to GCn to be provided to the scan lines GCL1 to GCLn shown in Figure 2 Some of the scan signals GI1 to GIn may be the same as some of the scan signals GC1 to GCn. For example, the scan signal GI2 may be the same as the scan signal GC1, and the scan signal GIn may be the same as the scan signal GCn-1.

[0086] The second scan driving circuit 330 may receive at least one corresponding clock signal among a plurality of clock signals and a corresponding start signal among a plurality of start signals through the first scan control signal SCS1. The second scan driving circuit 330 may output, in response to the first scan control signal SCS1, scan signals GW1 to GWn to be provided to the scan lines GWL1 to GWLn shown in Figure 2 Scan signals GW1 to GWn to be provided to the scan lines GWL1 to GWLn shown in

[0087] The third scan driving circuit 340 may receive at least one corresponding clock signal among a plurality of clock signals and a corresponding start signal among a plurality of start signals through the first scan control signal SCS1. The third scan driving circuit 340 may output, in response to the first scan control signal SCS1, scan signals EB1 to EBn to be provided to the scan lines EBL1 to EBLn shown in Figure 2 Scan signals EB1 to EBn to be provided to the scan lines EBL1 to EBLn shown in

[0088] Figure 4 Is a block diagram showing a second driving circuit according to an embodiment of the present disclosure.

[0089] Referring to Figure 4 , the second driving circuit 400 may include an emission driving circuit 410, a first scan driving circuit 420, a second scan driving circuit 430, and a third scan driving circuit 440.

[0090] The emission driving circuit 410 can receive at least one corresponding clock signal among a plurality of clock signals and a corresponding start signal among a plurality of start signals through the second scan control signal SCS2. The emission driving circuit 410 can output emission signals EM1 to EMn to be provided to the emission lines EML1 to EMLn shown in Figure 2 in response to the second scan control signal SCS2.

[0091] The first scan driving circuit 420 can receive at least one corresponding clock signal among a plurality of clock signals and a corresponding start signal among a plurality of start signals through the second scan control signal SCS2. In response to the second scan control signal SCS2, the first scan driving circuit 420 can output scan signals GI1 to GIn to be provided to the scan lines GIL1 to GILn shown in Figure 2 , and scan signals GC1 to GCn to be provided to the scan lines GCL1 to GCLn shown in Figure 2 . Some of the scan signals GI1 to GIn can be the same as some of the scan signals GC1 to GCn. For example, the scan signal GI2 can be the same as the scan signal GC1, and the scan signal GIn can be the same as the scan signal GCn-1.

[0092] The second scan driving circuit 430 can receive at least one corresponding clock signal among a plurality of clock signals and a corresponding start signal among a plurality of start signals through the second scan control signal SCS2. The second scan driving circuit 430 can output scan signals GW1 to GWn to be provided to the scan lines GWL1 to GWLn shown in Figure 2 in response to the second scan control signal SCS2.

[0093] The third scan driving circuit 440 can receive at least one corresponding clock signal among a plurality of clock signals and a corresponding start signal among a plurality of start signals through the second scan control signal SCS2. The third scan driving circuit 440 can output scan signals EB1 to EBn to be provided to the scan lines EBL1 to EBLn shown in Figure 2 in response to the second scan control signal SCS2.

[0094] Figure 5 is a circuit diagram showing a pixel according to an embodiment of the present disclosure.

[0095] Shown in Figure 5 is related to Figure 2As an example, a pixel PXij is connected to a j-th data line DLj (also referred to hereinafter as the data line DLj), an i-th gate lines GILi, GCLi, GWLi, and EBLi (also referred to hereinafter as the gate lines GILi, GCLi, GWLi, and EBLi), and an i-th emission line EMLi (also referred to hereinafter as the emission line EMLi). Herein, j may be a natural number greater than 0 and less than or equal to m.

[0096] Figure 2 Each of the plurality of pixels PX shown in Figure 5 may have a circuit configuration the same as that of the pixel PXij shown in

[0097] In an embodiment, the pixel circuit of the pixel PXij includes ten transistors T1 to T10, a first capacitor Cst, and a second capacitor Chold. That is, the pixel circuit of the pixel PXij may be defined as having a "10T2C" structure. The circuit configuration of the pixel PXij according to the present disclosure is not limited to Figure 5 . The number of transistors included in the pixel PXij or the number of capacitors included in the pixel PXij and the connection relationship between the transistors and the capacitors may be variously changed or modified.

[0098] Referring to Figure 5 , in an embodiment, each of the first transistor T1 to the tenth transistor T10 may be a P-type transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. However, the present disclosure is not limited thereto. In an embodiment, each of the first transistor T1 to the tenth transistor T10 may be an N-type transistor using an oxide semiconductor as a semiconductor layer. In another embodiment, at least one of the first transistor T1 to the tenth transistor T10 may be an N-type transistor, and the remaining transistors may be P-type transistors.

[0099] The gate lines GILi, GCLi, GWLi, and EBLi may respectively transmit gate signals GIi, GCi, GWi, and EBi, and the emission line EMLi may transmit an emission signal EMi. The data line DLj transmits a data signal Dj. The data signal Dj may have the same as the input image signal RGB input to the display device DD (refer to Figure 1 ) (refer to Figure 2)The corresponding voltage levels. The first voltage line VL1, the second voltage line VL2, the third voltage line VL3, the fourth voltage line VL4, the fifth voltage line VL5, and the sixth voltage line VL6 may respectively transmit a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, a bias voltage Vbias, a second initialization voltage VAINT, and a reference voltage VREF.

[0100] The first transistor T1 may include a first electrode connected to the first voltage line VL1 through an eighth transistor T8, a second electrode electrically connected to a first electrode AND of a light-emitting element ED through a sixth transistor T6, and a gate electrode connected to a first node N1.

[0101] The second transistor T2 includes a first electrode connected to a data line DLj, a second electrode connected to a second node N2, and a gate electrode connected to a scan line GWLi. The second transistor T2 may be turned on according to a scan signal GWi transmitted through the scan line GWLi, and may transmit a data signal Dj transmitted through the data line DLj to the second node N2.

[0102] The third transistor T3 includes a first electrode connected to a first electrode AND of a light-emitting element ED through a sixth transistor T6, a second electrode connected to the first node N1, and a gate electrode connected to a scan line GCLi. The first electrode of the third transistor T3 may be connected to the second electrode of the first transistor T1. The third transistor T3 may be turned on according to a scan signal GCi transmitted through the scan line GCLi, and may connect the first node N1 (i.e., the gate electrode of the first transistor T1) and the second electrode of the first transistor T1.

[0103] The fourth transistor T4 may include a first electrode connected to the first node N1, a second electrode connected to the third voltage line VL3, and a gate electrode connected to a scan line GILi. The fourth transistor T4 may be turned on according to a scan signal GIi transmitted through the scan line GILi, and may transmit the first initialization voltage VINT to the first node N1, i.e., the gate electrode of the first transistor T1.

[0104] The fifth transistor T5 includes a first electrode connected to the sixth voltage line VL6, a second electrode connected to the second node N2, and a gate electrode connected to the scan line GCLi. The fifth transistor T5 may be turned on according to a scan signal GCi transmitted through the scan line GCLi, and may transmit the reference voltage VREF of the sixth voltage line VL6 to the second node N2.

[0105] According to an embodiment of the present disclosure, the first electrode of the fifth transistor T5 may be connected to the first voltage line VL1 instead of the sixth voltage line VL6.

[0106] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first electrode AND of the light-emitting element ED, and a gate electrode connected to the emission line EMLi.

[0107] The seventh transistor T7 includes a first electrode connected to the first electrode AND of the light-emitting element ED, a second electrode connected to the fifth voltage line VL5, and a gate electrode connected to the scan line EBLi. The seventh transistor T7 can be turned on according to the scan signal EBi transmitted through the scan line EBLi, and can initialize the first electrode AND of the light-emitting element ED with the second initialization voltage VAINT of the fifth voltage line VL5.

[0108] The eighth transistor T8 includes a first electrode connected to the first voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the emission line EMLi.

[0109] The sixth transistor T6 and the eighth transistor T8 can be turned on simultaneously according to the emission signal EMi transmitted through the emission line EMLi. When the sixth transistor T6 and the eighth transistor T8 are turned on, a current path can be formed between the first voltage line VL1 and the light-emitting element ED through the eighth transistor T8, the first transistor T1, and the sixth transistor T6.

[0110] The ninth transistor T9 includes a first electrode connected to the fourth voltage line VL4, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the scan line EBLi. The ninth transistor T9 can be turned on according to the scan signal EBi transmitted through the scan line EBLi, and can transmit the bias voltage Vbias to the first electrode of the first transistor T1.

[0111] The tenth transistor T10 includes a first electrode connected to the first voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the scan line GCLi. The tenth transistor T10 can be turned on according to the scan signal GCi transmitted through the scan line GCLi, and can transmit the first driving voltage ELVDD to the first electrode of the first transistor T1.

[0112] The first capacitor Cst is connected between the first node N1 and the second node N2.

[0113] The second capacitor Chold is connected between the first voltage line VL1 and the second node N2.

[0114] Figure 6 and Figure 7 are timing diagrams for describing the operation of the display device according to an embodiment of the present disclosure.

[0115] The following refers toFigure 2 , Figure 6 and Figure 7 , examples in which the display panel DP operates at a first driving frequency (e.g., 240 Hz) and a second driving frequency (e.g., 120 Hz) will be described. However, the present disclosure is not limited thereto. The driving frequency of the display panel DP can be variously changed. In an embodiment, one of the first driving frequency and the second driving frequency can be selected as the driving frequency of the display panel DP. Moreover, the display panel DP can operate in a variable frequency mode in which the driving frequency is frequently changed during the operation of the display panel DP rather than fixed to a specific frequency. In an embodiment, the driving frequency of the display panel DP can be determined according to the frequency of the input image signal RGB or the control signal CTRL.

[0116] The driving controller 100 provides the first scan control signal SCS1 and the second scan control signal SCS2 to the first driving circuit 300 and the second driving circuit 400, respectively, in response to the control signal CTRL. The control signal CTRL can include a synchronization signal V_SYNC. The first driving circuit 300 can output a scan signal corresponding to the driving frequency in response to the first scan control signal SCS1, and the second driving circuit 400 can output a scan signal corresponding to the driving frequency in response to the second scan control signal SCS2.

[0117] Figure 6 and Figure 7 The scan signals GW1 to GWn shown in Figure 2 can be provided to the scan lines GWL1 to GWLn shown in Figure 2 respectively, and the scan signals EB1 to EBn can be provided to the scan lines EBL1 to EBLn shown in

[0118] Figure 6 is a timing diagram of a start signal and a scan signal when the driving frequency of the display panel DP is the first driving frequency (e.g., 240 Hz).

[0119] Referring to Figure 2 and Figure 6 , when the driving frequency is the first driving frequency (e.g., 240 Hz), each of the frames F11 and F12 can include a write period WP and a hold period HP. The synchronization signal V_SYNC can be a signal indicating the start of each of the write period WP and the hold period HP.

[0120] In the write period WP of each of the frames F11 and F12, the first driving circuit 300 and the second driving circuit 400 sequentially activate the scan signals GW1 to GWn to an active level (e.g., low level), and sequentially activate the scan signals EB1 to EBn to a low level. Although in Figure 6Only the scan signals GW1 to GWn and the scan signals EB1 to EBn are shown, but during the write period WP of each of the frames F11 and F12, the scan signals to be provided to the scan lines GCL1 to GCLn and GBL1 to GBLn and the emission signals to be provided to the emission lines EML1 to EMLn may also be sequentially activated.

[0121] During the hold period HP, the first driving circuit 300 and the second driving circuit 400 may hold the scan signals GW1 to GWn at an inactive level (e.g., high level), and may sequentially activate the scan signals EB1 to EBn. Although not shown in Figure 6 During the hold period HP, the first driving circuit 300 and the second driving circuit 400 may hold the scan signals to be provided to the scan lines GCL1 to GCLn and GBL1 to GBLn and the emission signals to be provided to the emission lines EML1 to EMLn at an inactive level (e.g., high level) in the same manner as the scan signals GW1 to GWn.

[0122] During the hold period HP, the first driving circuit 300 and the second driving circuit 400 may sequentially activate the scan signals EB1 to EBn. In other words, during the hold period HP of each of the frames F11 and F12, only the scan signals EB1 to EBn may be sequentially activated, and the remaining scan signals and emission signals may be held at an inactive level.

[0123] Figure 7 is a timing diagram of the start signal and the scan signal when the driving frequency of the display panel DP is the second driving frequency (e.g., 120 Hz).

[0124] Referring to Figure 2 and Figure 7 When the driving frequency is the second driving frequency (e.g., 120 Hz), the period (or duration) of the frame F21 may be Figure 6 twice the period of each of the frames F11 and F12 shown in. The frame F21 may include one write period WP and three hold periods HP. During the write period WP of the frame F21, the first driving circuit 300 and the second driving circuit 400 sequentially activate the scan signals GW1 to GWn to a low level and sequentially activate the scan signals EB1 to EBn to a low level. Although only the scan signals GW1 to GWn and the scan signals EB1 to EBn are shown in Figure 7 During the write period WP of the frame F21, the scan signals to be provided to the scan lines GCL1 to GCLn and GBL1 to GBLn and the emission signals to be provided to the emission lines EML1 to EMLn may also be sequentially activated.

[0125] During the holding period HP, the first driving circuit 300 and the second driving circuit 400 may hold the scan signals GW1 to GWn at an inactive level (e.g., high level), and may sequentially activate the scan signals EB1 to EBn. Although not shown in Figure 7 , during the holding period HP, the first driving circuit 300 and the second driving circuit 400 may hold the scan signals to be provided to the scan lines GCL1 to GCLn and GBL1 to GBLn and the emission signals to be provided to the emission lines EML1 to EMLn at an inactive level (e.g., high level) in the same manner as the scan signals GW1 to GWn.

[0126] During the holding period HP, the first driving circuit 300 and the second driving circuit 400 may sequentially activate the scan signals EB1 to EBn. In other words, during each of the three holding periods HP of the frame F21, only the scan signals EB1 to EBn may be sequentially activated, and the remaining scan signals and emission signals may be held at an inactive level.

[0127] Figure 8 and Figure 9 are timing diagrams for describing the operation of a pixel according to an embodiment of the present disclosure, and Figures 10A to 10G is a diagram for describing the operation of a pixel according to an embodiment of the present disclosure. When describing Figures 10A to 10G , the components described with reference to Figure 5 are identified by the same reference numerals, and thus, additional descriptions will be omitted to avoid redundancy.

[0128] As Figure 8 shown, the writing period WP may include a first period P1, a second period P2, a third period P3, a fourth period P4, a fifth period P5, a sixth period P6, and a seventh period P7. As Figure 9 shown, the holding period HP may include an eighth period P8.

[0129] Referring to Figure 8 and Figure 10A , during the first period P1 of the writing period WP, the scan signals GCi, GWi, and EBi and the emission signal EMi are at an inactive level (e.g., high level), and the scan signal GIi is at an active level (e.g., low level). The fourth transistor T4 is turned on in response to the active-level scan signal GIi. Accordingly, during the first period P1, the first initialization voltage VINT may be transmitted to the first node N1 through the fourth transistor T4.

[0130] The first period P1 may be a first initialization period in which the first node N1 (i.e., the gate electrode of the first transistor T1) is initialized with the first initialization voltage VINT.

[0131] Referring toFigure 8 and Figure 10B During the second period P2 of the writing period WP, the scan signals GIi, GWi, and EBi and the emission signal EMi are at an inactive level (e.g., high level), and the scan signal GCi is at an active level (e.g., low level). The third transistor T3, the fifth transistor T5, and the tenth transistor T10 are turned on in response to the scan signal GCi at the active level.

[0132] As the third transistor T3 and the tenth transistor T10 are turned on, the first driving voltage ELVDD can be transmitted to the first node N1 through the tenth transistor T10, the first transistor T1, and the third transistor T3. The gate electrode of the first transistor T1 can be provided with a voltage (“ELVDD - Vth”) obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the first driving voltage ELVDD.

[0133] The second period P2 can refer to a compensation period for compensating the threshold voltage (Vth) of the first transistor T1.

[0134] As the fifth transistor T5 is turned on, the reference voltage VREF can be transmitted to the second node N2 through the fifth transistor T5.

[0135] The voltage of the second node N2 can be changed from the voltage of the data signal Dj provided to the data line DLj in the previous frame (hereinafter referred to as voltage Vdata) to the reference voltage VREF. The change in the voltage of the second node N2 can be transmitted to the first node N1 through the coupling of the first capacitor Cst.

[0136] Refer to Figure 8 and Figure 10C During the third period P3 of the writing period WP, the scan signals GCi and GWi and the emission signal EMi are at an inactive level (e.g., high level), and the scan signals GIi and EBi are at an active level (e.g., low level).

[0137] The fourth transistor T4 is turned on in response to the scan signal GIi at the active level. In this case, during the third period P3, the first initialization voltage VINT can be transmitted to the first node N1 through the fourth transistor T4.

[0138] The seventh transistor T7 is turned on in response to the scan signal EBi at the active level. In this case, during the third period P3, the second initialization voltage VAINT can be transmitted to the first electrode AND of the light emitting element ED through the seventh transistor T7.

[0139] The ninth transistor T9 is turned on in response to the scanning signal EBi at an active level. In this case, during the third period P3, the bias voltage Vbias can be transmitted to the third node N3 through the ninth transistor T9.

[0140] The width PD2 of the active period of the scanning signal EBi can be narrower than the width PD1 of the active period of the scanning signal GIi. However, this is an example, and the width PD2 of the active period of the scanning signal EBi according to an embodiment of the present disclosure is not limited thereto. For example, the width PD2 of the active period of the scanning signal EBi can be equal to the width PD1 of the active period of the scanning signal GIi.

[0141] The third period P3 can be a second initialization period in which the first node N1 (i.e., the gate electrode of the first transistor T1) is initialized with the first initialization voltage VINT.

[0142] By providing the bias voltage Vbias to the first electrode of the first transistor T1, the hysteresis effect caused by the characteristic change of the threshold voltage (Vth) of the first transistor T1 can be minimized.

[0143] According to the present disclosure, during the third period P3, the reference voltage VREF can be applied to the second node N2 due to the second period P2, and the light-emitting element ED can be prevented from emitting light due to the emission signal EMi at a non-active level. Moreover, through the active scanning signal EBi, the bias voltage Vbias can be applied to the third node N3 which is the source electrode of the first transistor T1. An environment in which the first transistor T1 performs a desired function based on the operating point can be achieved through the bias voltage Vbias. Accordingly, a pixel PXij with improved reliability and a display device DD including the same can be provided (refer to Figure 1 ).

[0144] Refer to Figure 8 and Figure 10D , during the fourth period P4 of the writing period WP, the scanning signals GIi, GWi, and EBi and the emission signal EMi are at non-active levels (e.g., high levels), and the scanning signal GCi is at an active level (e.g., low level). The third transistor T3, the fifth transistor T5, and the tenth transistor T10 are turned on in response to the scanning signal GCi at an active level.

[0145] As the third transistor T3 and the tenth transistor T10 are turned on, the first driving voltage ELVDD can be transmitted to the first node N1 through the tenth transistor T10, the first transistor T1, and the third transistor T3.

[0146] In this case, the first transistor T1 can operate as a source follower.

[0147] The gate electrode of the first transistor T1 may be provided with a voltage (“ELVDD - Vth”) obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the first driving voltage ELVDD.

[0148] According to the present disclosure, since the scan signal EBi is activated in the third period P3 which is the previous period, in the fourth period P4, the third node N3 serving as the source electrode of the first transistor T1 may not be in a floating state, but in a state where the bias voltage Vbias is applied to the source electrode of the first transistor T1. In this case, an offset of the threshold voltage (Vth) of the first transistor T1 caused when the third node N3 is in a floating state can be prevented. In the third period P3, the bias voltage Vbias may be applied to the third node N3; in the fourth period P4, since the first transistor T1 operates as a source follower, a voltage of an accurate level (i.e., “ELVDD - Vth”) may be applied to the gate electrode of the first transistor T1. Accordingly, a pixel PXij with improved reliability and a display device DD including the same can be provided (refer to Figure 1 ).

[0149] The fourth period P4 may refer to a compensation period for compensating the threshold voltage (Vth) of the first transistor T1.

[0150] As the fifth transistor T5 is turned on, the reference voltage VREF may be transmitted to the second node N2 through the fifth transistor T5.

[0151] The voltage of the second node N2 is the reference voltage VREF in the second period P2, and in the fourth period P4, the reference voltage VREF is supplied to the second node N2 again through the fifth transistor T5. Accordingly, there may be no change in the voltage level in the voltage of the second node N2.

[0152] As described above, the reference voltage VREF may be repeatedly provided to the second node N2 multiple times in the second period P2 and the fourth period P4, and thus, the first node N1 can be prevented from being affected by the voltage (Vdata) of the data signal Dj provided in the previous frame.

[0153] In Figure 8 an example in which two periods (i.e., the second period P2 and the fourth period P4) called “compensation periods” are provided is shown, but the number of compensation periods according to embodiments of the present disclosure is not limited thereto.

[0154] During the fourth period P4, the first driving voltage ELVDD may be applied to the third node N3 serving as the source electrode of the first transistor T1 through the tenth transistor T10. Moreover, as the third transistor T3 and the fifth transistor T5 are turned on, the threshold voltage (Vth) can be compensated.

[0155] Refer to Figure 8 and Figure 10E During the fifth period P5 of the writing period WP, only the scan signal GWi is at the active level. When the second transistor T2 is turned on by the scan signal GWi at the active level, the data signal Dj from the data line DLj can be transmitted to the second node N2.

[0156] The voltage of the second node N2 changes from the reference voltage VREF to the voltage (Vdata) of the data signal Dj. The change "Vdata - VREF" in the voltage of the second node N2 can be transmitted to the first node N1 through the coupling of the first capacitor Cst.

[0157] Since the voltage of the first node N1 is "ELVDD - Vth" in the fourth period P4, in the fifth period P5, the voltage of the first node N1 (i.e., the voltage of the gate electrode of the first transistor T1) is "ELVDD - Vth+(Vdata - VREF)".

[0158] The fifth period P5 can refer to the data writing period in which the voltage corresponding to the data signal Dj is stored in the first capacitor Cst.

[0159] Refer to Figure 8 and Figure 10F During the sixth period P6 of the writing period WP, the scan signals GIi, GCi, and GWi and the emission signal EMi are at the non - active level, and the scan signal EBi is at the active level (e.g., low level).

[0160] Each of the seventh transistor T7 and the ninth transistor T9 can be turned on by the scan signal EBi at the active level. The second initialization voltage VAINT is provided to the anode of the light - emitting element ED through the seventh transistor T7. The bias voltage Vbias is provided to the first electrode of the first transistor T1 through the ninth transistor T9.

[0161] By providing the bias voltage Vbias to the first electrode of the first transistor T1, the hysteresis effect caused by the characteristic change of the threshold voltage (Vth) of the first transistor T1 can be minimized.

[0162] The sixth period P6 can be the anode initialization and bias period for initializing the anode of the light - emitting element ED and the first electrode of the first transistor T1.

[0163] Refer to Figure 8 and Figure 10G During the seventh period P7, all the scan signals GIi, GCi, GWi, and EBi are at the non - active level, and the emission signal EMi is at the active level. Each of the sixth transistor T6 and the eighth transistor T8 can be turned on by the emission signal EMi at the active level.

[0164] When the sixth transistor T6 and the eighth transistor T8 are turned on, a current path from the first voltage line VL1 to the light-emitting element ED can be formed through the eighth transistor T8, the first transistor T1, and the sixth transistor T6.

[0165] In this case, the amount of drive current transmitted to the light-emitting element ED can be determined based on the voltage level of the first node N1 (i.e., the voltage level of the gate electrode of the first transistor T1). In the fifth period P5, the voltage of the gate electrode of the first transistor T1 is "ELVDD - Vth + (Vdata - VREF)".

[0166] The current flowing through the first transistor T1 is proportional to the square of the difference between the voltage (Vgs) corresponding to the voltage difference between the first electrode and the gate electrode of the first transistor T1 and the threshold voltage (Vth) of the first transistor T1, i.e., "(Vgs - Vth) 2 ".

[0167] Since the voltage of the first electrode of the first transistor T1 is the first drive voltage ELVDD, and the voltage of the gate electrode of the first transistor T1 is "ELVDD - Vth + (Vdata - VREF)", the voltage difference (Vgs) between the first electrode and the gate electrode of the first transistor T1 is "ELVDD - (ELVDD - Vth + (Vdata - VREF))".

[0168] Accordingly, the current flowing through the first transistor T1 is proportional to "((ELVDD - (ELVDD - Vth + (Vdata - VREF))) - Vth) 2 ". That is, the drive current ID flowing through the first transistor T1 can be proportional to "(VREF - Vdata) 2 ".

[0169] The seventh period P7 can refer to an emission period during which the light-emitting element ED emits light.

[0170] According to the present disclosure, in the fourth period P4, since the first transistor T1 operates as a source follower, a voltage of an accurate level (i.e., "ELVDD - Vth") can be applied to the gate electrode of the first transistor T1. During the fourth period P4, the influence caused by the threshold voltage (Vth) of the first transistor T1 can be compensated for each pixel PXij. Accordingly, during the seventh period P7, the influence of the threshold voltage (Vth) of the first transistor T1 can be removed, and a current proportional to the voltage (Vdata) of the data signal Dj can be provided to the light-emitting element ED. Accordingly, pixels PXij with improved display quality and a display device DD including the same can be provided (refer to Figure 1 ).

[0171] Refer to Figure 9 During the eighth period P8 of the hold period HP, the scan signals GIi, GCi, and GWi and the emission signal EMi are at inactive levels, and the scan signal EBi is at an active level (e.g., a low level).

[0172] The seventh transistor T7 and the ninth transistor T9 can be turned on by the scan signal EBi at the active level. The initialization voltage VINT is provided to the anode of the light-emitting element ED through the seventh transistor T7. The bias voltage Vbias is provided to the first electrode of the first transistor T1 through the ninth transistor T9.

[0173] By providing the bias voltage Vbias to the first electrode of the first transistor T1, the hysteresis effect caused by the characteristic variation of the threshold voltage (Vth) of the first transistor T1 can be minimized.

[0174] As Figure 6 shown, when the driving frequency of the display panel DP is the first driving frequency, each of the frames F11 and F12 includes a hold period HP.

[0175] As Figure 7 shown, when the driving frequency of the display panel DP is the second driving frequency, the frame F21 includes three hold periods HP.

[0176] Different from the present disclosure, in the comparative example, since the data signal Dj is not provided during the hold period HP, when the number of hold periods HP in a frame increases, the characteristics of the threshold voltage (Vth) of the first transistor T1 may change. However, according to the present disclosure, by providing the bias voltage Vbias to the first electrode of the first transistor T1 during the eighth period P8 of the hold period HP, the hysteresis effect caused by the characteristic variation of the threshold voltage (Vth) of the first transistor T1 can be minimized. Accordingly, pixels PXij with improved reliability and a display device DD including the same can be provided (refer to Figure 1 ).

[0177] The eighth period P8 can be a hysteresis compensation period for compensating the hysteresis characteristics of the first transistor T1.

[0178] In an embodiment, Figure 8 the width of the fifth period P5 shown in Figure 2 can correspond to one horizontal period. One horizontal period can refer to the time during which the data signal Dj is provided to the pixels PX (refer to Figure 8The width of each of the second period P2 and the fourth period P4 (i.e., the first compensation period and the second compensation period) shown in the figure may correspond to a time longer than one horizontal period. Since each of the second period P2 and the fourth period P4 is longer than one horizontal period, even if the driving frequency of the display device DD (refer to Figure 1 ) becomes higher, the time required to sufficiently compensate for the threshold voltage (Vth) of the first transistor T1 can be ensured. Accordingly, the pixel PXij can operate stably at a high driving frequency.

[0179] The pixel PXij includes ten transistors T1 to T10 and two capacitors Cst and Chold. By minimizing the number of transistors in the pixel PXij, the circuit area of the pixel PXij can be minimized. The pixel PXij includes a first voltage line VL1, a second voltage line VL2, a third voltage line VL3, a fourth voltage line VL4, a fifth voltage line VL5, and a sixth voltage line VL6 for receiving a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, a bias voltage Vbias, a second initialization voltage VAINT, and a reference voltage VREF, respectively. In addition, the pixel PXij operates in response to four scan signals GIi, GCi, GWi, and EBi and one emission signal EMi. By minimizing the number of voltage lines connected to the pixel PXij, the number of scan lines connected to the pixel PXij, and the number of emission lines connected to the pixel PXij, the circuit area of the pixel PXij can be reduced.

[0180] According to the present disclosure, compared with the case where different first and second emission signals are respectively provided to the sixth transistor T6 and the eighth transistor T8, the number of lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, EBL1 to EBLn, and EML1 to EMLn (refer to Figure 2 ) extending in the first direction DR1 can be reduced. The area of the pixel circuit of each of the plurality of pixels PX can be reduced. That is, the number of pixels PX (refer to Figure 2 ) arranged in the same area can be increased. Accordingly, the pixels per inch (PPI) of the display device DD (refer to Figure 2 ) can be improved. Figure 1 ) can be improved.

[0181] Moreover, the sixth transistor T6 and the eighth transistor T8 included in one pixel PX (refer to Figure 2 ) can be connected to the same emission line (e.g., Figure 2 one of the emission lines EML1 to EMLn). Compared with the case where different first and second emission signals are respectively provided to the sixth transistor T6 and the eighth transistor T8, the emission driving circuits 310 and 410 (refer toFigure 3 and Figure 4 ) quantity. Accordingly, the area of the non-display area NDA (refer to Figure 1 ) can be reduced.

[0182] Figure 11 is a graph showing the relationship between the G value and the gray level according to an embodiment of the present disclosure.

[0183] In Figure 11 , the horizontal axis represents the gray level of the gray-scale image displayed on the display panel DP (refer to Figure 2 ), and the vertical axis represents the G value.

[0184] The G value can be obtained by quantitatively measuring the brightness difference of the same image according to the driving frequency. The G value can be defined by Equation 1 below.

[0185] [Equation 1]

[0186] G-Value = (LUM(HIGHFREQ) – LUM(LOWFREQ)) / LUM(HIGHFREQ)

[0187] Referring to Equation 1 above, G-Value can represent the G value, LUM(HIGHFREQ) can represent the brightness of the display panel DP (refer to Figure 2 ) driven at the first driving frequency among the variable driving frequencies, and LUM(LOWFREQ) can represent the brightness of the display panel DP (refer to Figure 2 ) driven at the second driving frequency lower than the first driving frequency among the variable driving frequencies. The unit of the G value can be %.

[0188] Referring to Figure 11 , the first graph GP1 shows the G value according to the gray level when the first driving frequency is 45 Hertz (Hz), the second graph GP2 shows the G value according to the gray level when the first driving frequency is 60 Hz, and the third graph GP3 shows the G value according to the gray level when the first driving frequency is 90 Hz.

[0189]

Table 1

[0190] 11G 23G 35G 51G 87G 127G 151G 203G 255G CE1 0.35％ 1.23％ 1.52％ 1.61％ 1.59％ 1.39％ 1.28％ 1.13％ 1.11％ CE2 -1.20％ 0.82％ 1.16％ 1.31％ 1.28％ 1.19％ 1.05％ 0.92％ 0.93％ CE3 -3.60％ -0.47％ 0.15％ 0.44％ 0.58％ 0.56％ 0.53％ 0.46％ 0.55％ GP1 -1.06％ -0.85％ -0.56％ -0.05％ 0.49％ 0.65％ 0.73％ 0.74％ 0.87％ GP2 -1.04％ -1.09％ -0.79％ -0.32％ 0.15％ 0.30％ 0.46％ 0.53％ 0.61％ GP3 -1.20％ -1.32％ -1.00％ -0.63％ -0.03％ 0.22％ 0.26％ 0.23％ 0.46％

[0191] Table 1 shows the values that the first graph GP1, the second graph GP2, and the third graph GP3 have for each gray level. Referring to Table 1 and Figure 5 、 Figure 8 and Figure 11 , as the scan signal EBi is activated during the third period P3, the bias voltage Vbias can be applied to the third node N3 which is the source electrode of the first transistor T1.

[0192] In Table 1, Comparative Example 1 CE1 shows the G values according to the gray levels when the first driving frequency is 45 Hz, Comparative Example 2 CE2 shows the G values according to the gray levels when the first driving frequency is 60 Hz, and Comparative Example 3 CE3 shows the G values according to the gray levels when the first driving frequency is 90 Hz.

[0193] Different from the present disclosure, when the bias voltage Vbias is not applied to the third node N3, the threshold voltage (Vth) may shift due to the floating state of the third node N3. For this reason, referring to the comparative examples in Table 1, at 11G belonging to the low gray level region, for each driving frequency, a G value deviation of up to 3.25% may occur. For example, assuming that the G value deviation is relatively large, when the driving frequency is variable, the brightness difference may be visually perceived by the user and may be perceived as flicker. However, according to the present disclosure, the bias voltage Vbias may be applied to the third node N3 during the third period P3, and thus, the threshold voltage shift may be prevented in the fourth period P4. Referring to the first graph GP1, the second graph GP2, and the third graph GP3 in Table 1, at 11G belonging to the low gray level region, for each driving frequency, a G value deviation of up to 0.16% may occur. That is, the G value deviation for each driving frequency can be improved. Accordingly, a display device DD with improved display quality can be provided (refer to Figure 2 ).

[0194]

Table 2

[0195] Comparative Example The present disclosure 1 0.0129 0.0085 2 0.0139 0.0090 3 0.0131 0.0120 4 0.0135 0.0104 5 0.0137 0.0101 Average value 0.0134 0.0100

[0196] Table 2 shows the F values of the display panel DP (refer to Figure 2 ). Table 2 shows the average value obtained from 5 measurement results. The F value can be defined by Equation 2 below.

[0197] [Equation 2]

[0198] F - Value = (LUM(HIGHFREQ, 255G) – LUM(LOWFREQ, 255G)) / (HIGHFREQ – LOWFREQ)

[0199] Referring to Equation 2 above, F - Value can represent the F value, LUM(HIGHFREQ, 255G) can represent the brightness corresponding to the gray level of 255G when the display panel DP (refer to Figure 2 ) is driven at the first driving frequency among the variable driving frequencies, and LUM(LOWFREQ, 255G) can represent the brightness corresponding to the gray level of 255G when the display panel DP (refer to Figure 2)The brightness corresponding to the gray level of 255G when driven at a second driving frequency lower than the first driving frequency among the variable driving frequencies, and (HIGHFREQ - LOWFREQ) can represent a value obtained by subtracting the second driving frequency from the first driving frequency.

[0200] In Table 2, the comparative example is associated with the case where the scan signal EBi is not provided in the third period P3, and the present disclosure is associated with the pixel PXij of the writing period WP in which the scan signal EBi is provided in the third period P3. Figure 8 applied.

[0201] According to the present disclosure, the phenomenon of the threshold voltage (Vth) shifting in the fourth period P4 can be prevented by the third period P3. In this case, the F value of the display panel DP (refer to Figure 2 ) can have an average value of 0.0100. Compared with the comparative example in which the bias voltage Vbias is not applied to the third node N3, the F value can be improved by about 30%. Accordingly, a display device DD with improved display quality can be provided (refer to Figure 2 ).

[0202] Figure 12 is a graph showing the relationship between the G value and the gray level according to an embodiment of the present disclosure. In the Figure 12 description, the horizontal axis represents the gray level of the gray image displayed on the display panel DP (refer to Figure 2 ), and the vertical axis represents the G value.

[0203] Refer to Figure 12 , the first graph P1-1, the second graph P2-1, the third graph P3-1, the fourth graph P4-1, and the fifth graph P5-1 are respectively associated with five display panels DP (refer to Figure 2 ), and show the G value according to the gray level when the first driving frequency is 360 Hz and the second driving frequency is 45 Hz.

[0204]

Table 3

[0205] 11G 23G 35G 51G 87G 127G 151G 203G 255G CE1 0.19％ 1.54％ 1.63％ 1.83％ 1.64％ 1.46％ 1.48％ 1.20％ 1.01％ CE2 0.01％ 1.79％ 2.09％ 1.89％ 1.84％ 1.62％ 1.48％ 1.26％ 1.08％ CE3 0.02％ 1.57％ 1.86％ 1.87％ 1.82％ 1.64％ 1.52％ 1.20％ 1.02％ CE4 0.21％ 1.54％ 1.83％ 1.62％ 1.62％ 1.48％ 1.30％ 1.15％ 1.06％ CE5 0.25％ 1.42％ 1.60％ 1.67％ 1.58％ 1.37％ 1.29％ 1.10％ 1.07％ P1-1 0.01％ -0.25％ -0.13％ 0.12％ 0.57％ 0.67％ 0.69％ 0.74％ 0.68％ P2-1 0.84％ 0.47％ 0.14％ 0.28％ 0.58％ 0.72％ 0.70％ 0.67％ 0.71％ P3-1 0.18％ 0.04％ 0.08％ 0.29％ 0.73％ 0.90％ 0.86％ 0.93％ 0.94％ P4-1 -0.79％ -0.20％ -0.18％ 0.15％ 0.59％ 0.72％ 0.81％ 0.80％ 0.82％ P5-1 0.34％ 0.40％ 0.35％ 0.59％ 0.94％ 0.99％ 0.98％ 0.93％ 0.80％

[0206] Table 3 shows the values that the first graph P1-1, the second graph P2-1, the third graph P3-1, the fourth graph P4-1, and the fifth graph P5-1 have for each gray level. Refer to Table 3 and Figure 5 , Figure 8 and Figure 12 , as the scan signal EBi is activated during the third period P3, the bias voltage Vbias can be applied to the third node N3 which is the source electrode of the first transistor T1.

[0207] In Table 3, Comparative Examples 1 CE1 to 5 CE5 show the G values when the first driving frequency is 360 Hz and the second driving frequency is 45 Hz.

[0208] Different from the present disclosure, when the bias voltage Vbias is not applied to the third node N3, the threshold voltage (Vth) may shift due to the floating state of the third node N3. For this reason, at each gray level, the maximum value of the G value deviation for each driving frequency may be about 2%. However, according to the present disclosure, the phenomenon of the threshold voltage (Vth) shifting in the fourth period P4 can be prevented by the third period P3. At each gray level, the maximum value of the G value deviation for each driving frequency may be about 1%. That is, the G value deviation for each driving frequency can be improved. Accordingly, a display device DD with improved display quality can be provided (refer to Figure 2 ).

[0209] Figure 13 is a graph showing the relationship between the JEITA value and the gray level according to an embodiment of the present disclosure.

[0210] Refer to Figure 13 , the first graph P1-2, the second graph P2-2, the third graph P3-2, the fourth graph P4-2, and the fifth graph P5-2 are respectively associated with five display panels DP (refer to Figure 2 ) and show the JEITA values according to the gray level.

[0211] For the purpose of quantitatively evaluating the flicker level of the display device DD (refer to Figure 2 ), the flicker level can be measured using the JEITA flicker measurement method. The JEITA value can be a quantitative value of flicker defined by the Japan Electronics and Information Technology Industries Association. The unit of the JEITA value can be dB (decibel).

[0212]

Table 4

[0213] 11G 23G 35G 51G 87G 127G 151G 203G 255G CE1 -37.2 dB -44.4 dB -47.4 dB -48.0 dB -51.0 dB -52.1 dB -52.7 dB -53.9 dB -55.7 dB CE2 -38.2 dB -46.1 dB -48.9 dB -50.1 dB -51.9 dB -53.1 dB -53.7 dB -54.4 dB -56.1 dB CE3 -39.0 dB -46.1 dB -48.8 dB -50.4 dB -52.2 dB -53.3 dB -53.9 dB -54.5 dB -56.2 dB CE4 -38.7 dB -46.2 dB -49.0 dB -50.3 dB -52.3 dB -53.6 dB -54.3 dB -54.8 dB -56.4 dB CE5 -38.8 dB -46.6 dB -49.7 dB -51.6 dB -53.1 dB -54.4 dB -55.0 dB -56.4 dB -57.0 dB P1-2 -40.2 dB -49.0 dB -52.2 dB -55.5 dB -55.3 dB -55.5 dB -55.6 dB -55.9 dB -56.8 dB P2-2 -39.6 dB -49.0 dB -53.7 dB -55.8 dB -58.4 dB -57.5 dB -57.5 dB -57.6 dB -57.3 dB P3-2 -39.1 dB -48.5 dB -53.7 dB -56.2 dB -58.1 dB -57.1 dB -57.1 dB -56.8 dB -56.5 dB P4-2 -39.1 dB -48.4 dB -53.1 dB -57.2 dB -57.3 dB -56.7 dB -56.6 dB -57.0 dB -56.5 dB P5-2 -42.0 dB -52.2 dB -56.6 dB -55.8 dB -57.4dB -57.0dB -56.6dB -57.2dB -58.0dB

[0214] Table 4 shows the JEITA values that the first graph P1-2, the second graph P2-2, the third graph P3-2, the fourth graph P4-2, and the fifth graph P5-2 have for each gray level. In Table 4, Comparative Examples 1 CE1 to 5 CE5 show the JEITA values according to the gray level when the first driving frequency is 360 Hz and the second driving frequency is 45 Hz.

[0215] Refer to Table 4 and Figure 5 , Figure 8 and Figure 13, as the scan signal EBi is activated during the third period P3, a bias voltage Vbias can be applied to the third node N3 which serves as the source electrode of the first transistor T1.

[0216] Different from the present disclosure, in a display panel operating in a variable frequency mode, the brightness of the display panel can vary according to the driving frequency; in this case, when the driving frequency of the display panel changes, it may cause flicker. However, according to the present disclosure, the phenomenon of threshold voltage (Vth) shift in the fourth period P4 can be prevented by the third period P3. In this case, when the reference gray level of 400 nits is 127G, the JEITA value can be improved to about -4 dB. A decrease in the JEITA value can mean that the flicker is improved. Accordingly, a display device DD with improved display quality can be provided (refer to Figure 2 ).

[0217] Figure 14 is a graph showing the brightness for each time according to an embodiment of the present disclosure.

[0218] In Figure 14 , the horizontal axis can represent time and can represent the frames FR1 and FR4 driven by the display panel DP (refer to Figure 2 ). The first frame FR1 and the fourth frame FR4 are shown as examples in Figure 14 . The vertical axis can represent the brightness of the display panel DP (refer to Figure 2 ).

[0219] Refer to Figure 14 , the first graph I1 shows the brightness measured when the display panel is driven for each display frame during the change from a black screen to a white screen in a comparative example where the bias voltage Vbias is not applied to the third node N3 during the third period P3.

[0220] The second graph I2 shows the brightness measured when the display panel DP (refer to Figure 2 ) is driven for each display frame during the change from a black screen to a white screen in the configuration of the present disclosure where the bias voltage Vbias is applied to the third node N3 during the third period P3.

[0221]

Table 5

[0222] Comparative Example The present disclosure 1 90.9％ 98.1％ 2 89.7％ 97.5％ 3 90.7％ 98.0％ 4 90.3％ 97.7％ 5 88.9％ 97.4％ 6 90.9％ 97.7％ 7 90.4％ 97.6％ 8 89.9％ 97.5％ 9 91.0％ 98.0％ 10 91.2％ 97.9％ Average value 90.4％ 97.7％

[0223] Table 5 shows the ratio of the brightness of the white screen in the first frame FR1 to the brightness of the white screen in the fourth frame FR4. The ratio can be referred to as "step efficiency". Table 5 shows the average value obtained from ten measurement results. In Table 5, the comparative example is associated with the case where the scan signal EBi is not provided in the third period P3, and the present disclosure is associated with the application of Figure 8associated with a pixel PXij of a write period WP that provides a scan signal EBi in a third period P3.

[0224] According to the present disclosure, the phenomenon of threshold voltage (Vth) shift in a fourth period P4 can be prevented by the third period P3. In this case, the step efficiency of a display panel DP (refer to Figure 2 ) can have an average value of 97.7%. Compared with a comparative example in which a bias voltage Vbias is not applied to a third node N3, the step efficiency can be improved. Accordingly, a display device DD (refer to Figure 2 ) having improved display quality can be provided.

[0225] Figure 15 is a timing diagram for describing the operation of a pixel according to an embodiment of the present disclosure. In the Figure 15 description, the signals and periods described with reference to Figure 8 are identified by the same reference numerals, and thus, additional description will be omitted to avoid redundancy.

[0226] Referring to Figure 5 and Figure 15 , the write period WP can include a first period P1-1, a second period P2, a third period P3, a fourth period P4, a fifth period P5, a sixth period P6, and a seventh period P7.

[0227] During a first period P1-1 of the write period WP, a scan signal GCi, GWi, and an emission signal EMi are at an inactive level (e.g., a high level), and a scan signal GIi and EBi-1 are at an active level (e.g., a low level).

[0228] A seventh transistor T7 is turned on in response to an active-level scan signal EBi-1. In this case, during the first period P1-1, a second initialization voltage VAINT can be transmitted to a first electrode AND of a light-emitting element ED through the seventh transistor T7.

[0229] The operation in the first period P1-1 can be substantially the same as the operation in the third period P3. The first period P1-1 and the third period P3 can be referred to as an "initialization period". The second period P2 and the fourth period P4 can be referred to as a "compensation period".

[0230] That is, the initialization periods P1-1 and P3 and the compensation periods P2 and P4 can be alternately repeated multiple times.

[0231] According to an embodiment of the present disclosure, the bias voltage Vbias may have a first voltage level during a first period P1-1 and may have a second voltage level higher than the first voltage level during a third period P3. However, this is only an example, and according to an embodiment of the present disclosure, the bias voltage Vbias may have the same voltage level in the first period P1-1 and the third period P3.

[0232] According to the present disclosure, as the scan signal EBi-1 is activated in the first period P1-1 and the third period P3, in the fourth period P4, the third node N3, which is the source electrode of the first transistor T1, may not be in a floating state but in a state where the bias voltage Vbias is applied to the third node N3. In this case, an offset of the threshold voltage (Vth) of the first transistor T1 caused when the third node N3 is in a floating state can be prevented. The bias voltage Vbias may be applied to the third node N3 in the first period P1-1 and the third period P3, and since the first transistor T1 operates as a source follower in the fourth period P4, a voltage of an exact level (i.e., "ELVDD-Vth") may be applied to the gate electrode of the first transistor T1. Accordingly, a pixel PXij with improved reliability and a display device DD including the same can be provided (refer to Figure 1 ).

[0233] Figure 16 is a timing diagram for describing the operation of a pixel according to an embodiment of the present disclosure. In the Figure 16 description, the signals and periods described with reference to Figure 8 are identified by the same reference numerals, and thus, additional descriptions will be omitted to avoid redundancy.

[0234] Referring to Figure 5 and Figure 16 , the write period WP may include a first period P1-2, a second period P2, a third period P3-2, a fourth period P4, a fifth period P5, a sixth period P6, and a seventh period P7.

[0235] During the first period P1-2 of the write period WP, the scan signals GCi and GWi and the emission signal EMi are at an inactive level (e.g., high level), and the scan signals GIi and EBi-2 are at an active level (e.g., low level).

[0236] During the third period P3-2 of the write period WP, the scan signals GCi, GWi, and EBi-2 and the emission signal EMi are at an inactive level (e.g., high level), and the scan signal GIi is at an active level (e.g., low level).

[0237] According to the present disclosure, as the scan signal EBi-2 is activated in the first period P1-2, in the fourth period P4, the third node N3, which is the source electrode of the first transistor T1, may not be in a floating state, but in a state where the bias voltage Vbias is applied to the source electrode of the first transistor T1. In this case, an offset of the threshold voltage (Vth) of the first transistor T1 caused when the third node N3 is in a floating state can be prevented. The bias voltage Vbias may be applied to the third node N3 in the first period P1-2, and since the first transistor T1 operates as a source follower in the fourth period P4, a voltage of an accurate level (i.e., "ELVDD - Vth") can be applied to the gate electrode of the first transistor T1. Accordingly, a pixel PXij with improved reliability and a display device DD including the same can be provided (refer to Figure 1 ).

[0238] Figure 17 is a graph showing the relationship between the G value and the gray level according to an embodiment of the present disclosure, and Figure 18 is a graph showing the relationship between the JEITA value and the gray level according to an embodiment of the present disclosure.

[0239] Refer to Figure 17 and Figure 18 , the first graphs GP1-1 and GP1-2 show embodiments in which the bias voltage Vbias is not applied to the third node N3, the second graphs GP2-1 and GP2-2 show embodiments in which the pixel PXij is driven based on the timing shown in Figure 8 , the third graphs GP3-1 and GP3-2 show embodiments in which the pixel PXij is driven based on the timing shown in Figure 15 , and the fourth graphs GP4-1 and GP4-2 show embodiments in which the pixel PXij is driven based on the timing shown in Figure 16 .

[0240]

Table 6

[0241] 11G 23G 35G 51G 87G 127G 151G 203G 255G GP1-1 -0.38％ 1.50％ 1.84％ 1.87％ 1.79％ 1.52％ 1.43％ 1.22％ 1.05％ GP2-1 0.34％ 0.40％ 0.35％ 0.59％ 0.94％ 0.99％ 0.98％ 0.93％ 0.80％ GP3-1 -0.26％ -0.60％ -0.40％ 0.07％ 0.64％ 0.97％ 0.96％ 1.00％ 0.88％ GP4-1 0.28％ -0.65％ -0.33％ 0.11％ 0.74％ 0.96％ 1.03％ 1.02％ 0.89％

[0242] Table 6 shows the values of the first graph GP1-1, the second graph GP2-1, the third graph GP3-1, and the fourth graph GP4-1 for each gray level. Refer to Table 6 and Figure 5 , Figure 8 , Figure 15 , Figure 16 and Figure 17 , as the scan signal EBi-1 / EBi-2 or EBi is activated during the first period P1-1 / P1-2 or the third period P3, the bias voltage Vbias can be applied to the third node N3, which is the source electrode of the first transistor T1.

[0243] According to the present disclosure, the phenomenon of threshold voltage (Vth) shift in the fourth period P4 can be prevented by the first period P1-1 / P1-2 or the third period P3. At each gray level, the deviation of the G value for each driving frequency can be approximately 1%. That is, the deviation of the G value for each driving frequency can be improved. Accordingly, a display device DD with improved display quality can be provided (refer to Figure 2 ).

[0244]

Table 7

[0245] 11G 23G 35G 51G 87G 127G 151G 203G 255G GP1-2 -39.4dB -46.6dB -49.0dB -50.4dB -52.1dB -53.5dB -54.1dB -55.2dB -56.3dB GP2-2 -42.0dB -52.2dB -56.6dB -55.8dB -57.4dB -57.0dB -56.6dB -57.2dB -58.0dB GP3-2 -29.5dB -37.7dB -43.4dB -48.2dB -53.8dB -55.9dB -56.4dB -56.9dB -57.9dB GP4-2 -39.2dB -48.1dB -53.6dB -56.1dB -59.1dB -57.2dB -56.8dB -56.4dB -56.7dB

[0246] Table 7 shows the JEITA values of the first graph GP1-2, the second graph GP2-2, the third graph GP3-2, and the fourth graph GP4-2 for each gray level. Referring to Table 7 and Figure 5 , Figure 8 , Figure 15 , Figure 16 and Figure 18 , as the scanning signal EBi-1 / EBi-2 or EBi is activated during the first period P1-1 / P1-2 or the third period P3, a bias voltage Vbias can be applied to the third node N3 serving as the source electrode of the first transistor T1.

[0247] According to the present disclosure, the phenomenon of threshold voltage (Vth) shift in the fourth period P4 can be prevented by the first period P1-1 / P1-2 or the third period P3. In this case, when the gray level is 87G or higher, the JEITA value can be improved compared with the comparative example. A decrease in the JEITA value can mean that the flicker is improved. That is, when the pixel PXij is driven based on the Figure 15 and Figure 16 timing diagrams, the JEITA value can be improved in the high gray level region. Accordingly, a display device DD with improved display quality can be provided (refer to Figure 2 ).

[0248] Figure 19A is a circuit diagram of a pixel according to an embodiment of the present disclosure, and Figure 19B is a timing diagram for describing the operation of a pixel according to an embodiment of the present disclosure. In the Figure 19A description, the components described with reference to Figure 5 are identified by the same reference numerals, and thus, additional description will be omitted to avoid redundancy.

[0249] Referring to Figure 19A , the pixel circuit of the pixel PX-1ij includes eight transistors T1-1 to T8-1, a first capacitor Cst-1, and a second capacitor Cse.

[0250] The first transistor T1-1 may include a first electrode connected to a first voltage line VL1 through a fifth transistor T5-1, a second electrode electrically connected to a first electrode of a light-emitting element ED through a sixth transistor T6-1, and a gate electrode connected to a first node N1-1.

[0251] The second transistor T2-1 includes a first electrode connected to a data line DLj, a second electrode connected to a second node N2-1, and a gate electrode connected to a scan line GWLi. The second transistor T2-1 may be turned on in accordance with a scan signal GWi transmitted through the scan line GWLi, and may transmit a data signal Dj transmitted from the data line DLj to the second node N2-1.

[0252] The third transistor T3-1 includes a first electrode connected to a second electrode of the first transistor T1-1, a second electrode connected to the first node N1-1, and a gate electrode connected to a scan line GCLi. The third transistor T3-1 may include a plurality of transistors connected in series. The third transistor T3-1 may be turned on in accordance with a scan signal GCi transmitted through the scan line GCLi, and may connect the first node N1-1 (i.e., the gate electrode of the first transistor T1-1) to the second electrode of the first transistor T1-1.

[0253] The fourth transistor T4-1 may include a first electrode connected to the first node N1-1, a second electrode connected to a third voltage line VL3, and a gate electrode connected to a scan line GILi. The fourth transistor T4-1 may include a plurality of transistors connected in series. The fourth transistor T4-1 may be turned on in accordance with a scan signal GIi transmitted through the scan line GILi, and may transmit a first initialization voltage VINT to the first node N1-1, i.e., the gate electrode of the first transistor T1-1.

[0254] The fifth transistor T5-1 may include a first electrode connected to the first voltage line VL1, a second electrode connected to the first electrode of the first transistor T1-1, and a gate electrode connected to an emission line EMLi.

[0255] The sixth transistor T6-1 may include a first electrode connected to the second electrode of the first transistor T1-1, a second electrode connected to the first electrode of the light-emitting element ED, and a gate electrode connected to the emission line EMLi.

[0256] The fifth transistor T5-1 and the sixth transistor T6-1 may be simultaneously turned on in accordance with an emission signal EMi transmitted through the emission line EMLi. When the fifth transistor T5-1 and the sixth transistor T6-1 are turned on, a current path may be formed between the first voltage line VL1 and the light-emitting element ED through the fifth transistor T5-1, the first transistor T1-1, and the sixth transistor T6-1.

[0257] The seventh transistor T7-1 includes a first electrode connected to the first electrode of the light-emitting element ED, a second electrode connected to the fifth voltage line VL5, and a gate electrode connected to the scan line EBLi. The seventh transistor T7-1 can be turned on according to the scan signal EBi transmitted through the scan line EBLi, and the first electrode of the light-emitting element ED can be initialized with the second initialization voltage VAINT of the fifth voltage line VL5.

[0258] The eighth transistor T8-1 may include a first electrode connected to the fourth voltage line VL4, a second electrode connected to the first electrode of the first transistor T1-1, and a gate electrode connected to the scan line EBLi. The eighth transistor T8-1 can be turned on according to the scan signal EBi transmitted through the scan line EBLi, and the bias voltage Vbias can be transmitted to the first electrode of the first transistor T1-1.

[0259] The first capacitor Cst-1 may be connected between the first voltage line VL1 and the first node N1-1.

[0260] The second capacitor Cse may be connected between the first voltage line VL1 and the second node N2-1.

[0261] During the initialization period P1-3, the scan signals GCi and GWi and the emission signal EMi are at an inactive level (e.g., high level), and the scan signals GIi and EBi are at an active level (e.g., low level).

[0262] The fourth transistor T4-1 is turned on in response to the active-level scan signal GIi. In this case, during the initialization period P1-3, the first initialization voltage VINT can be transmitted to the first node N1-1 through the fourth transistor T4-1.

[0263] The seventh transistor T7-1 is turned on in response to the active-level scan signal EBi. In this case, during the initialization period P1-3, the second initialization voltage VAINT can be transmitted to the first electrode of the light-emitting element ED through the seventh transistor T7-1.

[0264] The eighth transistor T8-1 is turned on in response to the active-level scan signal EBi. In this case, during the initialization period P1-3, the bias voltage Vbias can be transmitted to the second node N2-1 through the eighth transistor T8-1.

[0265] By providing the bias voltage Vbias to the first electrode of the first transistor T1-1, the hysteresis effect caused by the characteristic variation of the threshold voltage (Vth) of the first transistor T1-1 can be minimized.

[0266] According to the present disclosure, the bias voltage Vbias can be applied to the second node N2-1 serving as the source electrode of the first transistor T1-1 through the scan signal EBi activated during the initialization period P1-3. An environment in which the pixel PX-1ij performs an expected function based on the operating point can be achieved through the bias voltage Vbias. Accordingly, a pixel PX-1ij with improved reliability and a display device DD including the same can be provided (refer to Figure 1 ). Moreover, the second node N2-1 serving as the source electrode of the first transistor T1-1 may not be in a floating state, but in a state where the bias voltage Vbias is applied thereto. In this case, an offset of the threshold voltage (Vth) of the first transistor T1 caused when the second node N2-1 is in a floating state can be prevented. During the initialization period P1-3, the bias voltage Vbias can be applied to the second node N2-1; then, since the first transistor T1-1 operates as a source follower, a voltage of an exact level (i.e., "ELVDD - Vth") can be applied to the gate electrode of the first transistor T1-1. Accordingly, a pixel PX-1ij with improved reliability and a display device DD including the same can be provided (refer to Figure 1 ).

[0267] As described above, as the scan signal is activated during the initialization period of the pixel, in the compensation period, the source electrode of the first transistor may not be in a floating state, but in a state where the bias voltage is applied thereto. Accordingly, an offset of the threshold voltage (Vth) of the first transistor caused when the source electrode is in a floating state can be prevented. During the initialization period, the bias voltage can be applied to the source electrode, and as the first transistor operates as a source follower in the compensation period, the voltage "(ELVDD - Vth)" can be applied to the gate electrode of the first transistor. During the compensation period, the threshold voltage (Vth) of the first transistor can be compensated. Accordingly, the influence that the threshold voltage (Vth) of the first transistor undergoes during the emission period can be removed, and a current proportional to the voltage of the data signal can be provided to the light-emitting element. Accordingly, a pixel with improved display quality and a display device including the pixel can be provided.

[0268] Although the present disclosure has been described with reference to embodiments of the present disclosure, those of ordinary skill in the art will clearly understand that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as recited in the appended claims.

Claims

1. A pixel comprising: a light emitting element including a first electrode electrically connected to a first voltage line and a second electrode electrically connected to a second voltage line, a first driving voltage being provided through the first voltage line, and a second driving voltage having a voltage level lower than that of the first driving voltage being provided through the second voltage line; a first capacitor connected between the first node and the second node; a first transistor including a first electrode connected to a third node, a second electrode electrically connected to the first electrode of the light emitting element, and a gate electrode connected to the first node; a second transistor including a first electrode connected to the first node, a second electrode connected to a third voltage line, and a gate electrode connected to the first scan line; a third transistor including a first electrode connected to the first electrode of the light emitting element, a second electrode connected to a fifth voltage line, and a gate electrode connected to a second scan line; as well as a fourth transistor including a first electrode connected to a fourth voltage line, a second electrode connected to the third node, and a gate electrode connected to the second scan line, During the first initialization period, the first scan signal supplied to the first scan line and the second scan signal supplied to the second scan line are at an activation level.

2. The pixel according to claim 1, wherein: In the first initialization period, a width of a second activation period of the second scan signal is narrower than a width of a first activation period of the first scan signal.

3. The pixel according to claim 1, wherein: During the first initialization period, a first initialization voltage is supplied from the third voltage line to the first node.

4. The pixel according to claim 1, wherein: During the first initialization period, a second initialization voltage is supplied from the fifth voltage line to the first electrode of the light emitting element.

5. The pixel according to claim 1, wherein: During the first initialization period, a bias voltage is supplied from the fourth voltage line to the third node.

6. The pixel of claim 5, further comprising: A fifth transistor includes a first electrode connected to the first voltage line, a second electrode connected to the third node, and a gate electrode connected to a third scan line.

7. The pixel of claim 6, further comprising: A sixth transistor includes a first electrode connected to the second electrode of the first transistor, a second electrode connected to the first node, and a gate electrode connected to the third scan line.

8. The pixel according to claim 7, wherein: Each of the second transistor and the sixth transistor includes a plurality of transistors connected in series.

9. The pixel of claim 7, further comprising: a seventh transistor, the seventh transistor comprising a first electrode connected to a sixth voltage line, a second electrode connected to the second node, and a gate electrode connected to the third scan line, and a reference voltage is provided through the sixth voltage line; as well as An eighth transistor includes a first electrode connected to the data line, a second electrode connected to the second node, and a gate electrode connected to a fourth scan line.

10. The pixel of claim 9, further comprising: a ninth transistor including a first electrode connected to the first voltage line, a second electrode connected to the third node, and a gate electrode connected to an emission line; as well as A tenth transistor includes a first electrode connected to the second electrode of the first transistor, a second electrode connected to the first electrode of the light emitting element, and a gate electrode connected to the emission line.

11. The pixel according to claim 10, wherein: During a compensation period, the third scan signal supplied to the third scan line is at the activation level, and the first driving voltage is supplied to the first node through the fifth transistor, the first transistor, and the sixth transistor.

12. The pixel according to claim 11, wherein: The first initialization period and the compensation period are repeated alternately a plurality of times.

13. The pixel of claim 12, wherein: the plurality of first initialization periods include a (1-1)th initialization period and a (1-2)th initialization period provided after the (1-1)th initialization period, wherein, during the (1-1)th initialization period, the bias voltage has a first voltage level, and During the (1-2)th initialization period, the bias voltage has a second voltage level higher than the first voltage level.

14. The pixel according to claim 11, wherein: During a second initialization period, the first scan signal is at the activation level.

15. The pixel of claim 14, wherein: The compensation period is arranged between the first initialization period and the second initialization period.

16. The pixel of claim 11, wherein: During a data writing period provided after the first initialization period and the compensation period, a fourth scan signal provided to the fourth scan line is at the activation level.

17. The pixel of claim 16, wherein: The second scan signal is at the active level during a bias period provided after the data write period.

18. The pixel of claim 17, wherein: During a transmission period provided after the bias period, a transmission signal provided to the transmission line is at the activation level, and During the emission period, the light emitting element emits light.

19. A display device comprising: a display panel including pixels connected to a plurality of scan lines, emission lines, and data lines; a driving circuit configured to drive the plurality of scan lines and the emission lines in response to a scan control signal; a drive controller configured to output the scanning control signal; as well as a voltage generator configured to generate a plurality of driving voltages, Wherein, the pixels include: a light emitting element including a first electrode electrically connected to a first voltage line and a second electrode electrically connected to a second voltage line, a first driving voltage being provided through the first voltage line, and a second driving voltage having a voltage level lower than that of the first driving voltage being provided through the second voltage line; a first capacitor connected between the first node and the second node; a first transistor including a first electrode connected to a third node, a second electrode electrically connected to the first electrode of the light emitting element, and a gate electrode connected to the first node; a second transistor, the second transistor comprising a first electrode connected to the first node, a second electrode connected to a third voltage line, and a gate electrode connected to the first scan line, and a first initialization voltage is provided through the third voltage line; a third transistor including a first electrode connected to the first electrode of the light emitting element, a second electrode connected to a fifth voltage line, and a gate electrode connected to a second scan line, and a second initialization voltage is provided through the fifth voltage line; and a fourth transistor including a first electrode connected to a fourth voltage line, a second electrode connected to the third node, and a gate electrode connected to the second scan line, and During the first initialization period, the first scan signal supplied to the first scan line and the second scan signal supplied to the second scan line are at an activation level.

20. The display device according to claim 19, wherein: During the first initialization period, A bias voltage is supplied from the fourth voltage line to the third node, The first initialization voltage is supplied from the third voltage line to the first node, and The second initialization voltage is supplied from the fifth voltage line to the first electrode of the light emitting element.

21. The display device according to claim 20, wherein: The pixel also includes: a fifth transistor including a first electrode connected to the first voltage line, a second electrode connected to the third node, and a gate electrode connected to a third scan line; and A sixth transistor includes a first electrode connected to the second electrode of the first transistor, a second electrode connected to the first node, and a gate electrode connected to the third scan line.

22. The display device according to claim 21, wherein: Each of the second transistor and the sixth transistor includes a plurality of transistors connected in series.

23. The display device according to claim 21, wherein: The pixel also includes: a seventh transistor, the seventh transistor comprising a first electrode connected to a sixth voltage line, a second electrode connected to the second node, and a gate electrode connected to the third scan line, and a reference voltage is provided through the sixth voltage line; an eighth transistor including a first electrode connected to the data line, a second electrode connected to the second node, and a gate electrode connected to a fourth scan line; a ninth transistor including a first electrode connected to the first voltage line, a second electrode connected to the third node, and a gate electrode connected to the emission line; and A tenth transistor includes a first electrode connected to the second electrode of the first transistor, a second electrode connected to the first electrode of the light emitting element, and a gate electrode connected to the emission line.

24. The display device according to claim 23, wherein: During a compensation period, the third scan signal supplied to the third scan line is at the activation level, and the first driving voltage is supplied to the first node through the fifth transistor, the first transistor, and the sixth transistor.

25. The display device according to claim 24, wherein: The first initialization period and the compensation period are repeated alternately for multiple times, The plurality of first initialization periods include a (1-1)th initialization period and a (1-2)th initialization period provided after the (1-1)th initialization period, wherein, during the (1-1)th initialization period, the bias voltage has a first voltage level, and During the (1-2)th initialization period, the bias voltage has a second voltage level higher than the first voltage level.

Images