Display device and level shifter

Abstract

Embodiments of the present disclosure relate to a display device and a level shifter, and more specifically, may provide a level shifter including a scan channel circuit generating a scan start signal for a plurality of sub-pixels according to a first input signal, a charge pump circuit generating a high potential light emitting voltage using a circuit power supply of a host system, and a control circuit generating a high potential light emitting voltage using the charge pump circuit. And a light-emitting channel circuit reflecting a change in the circuit power supply and controlling the light-emitting start signal according to the second input signal.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2023 - 0170308, filed on November 30, 2023, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical field

[0003] Embodiments of the present disclosure relate to a display device and a level shifter, and more particularly, to a display device and a level shifter capable of preventing an accident caused by an error in a display panel. Background art

[0004] The development of the intelligent society has led to an increased demand for image display devices, and various types of display devices such as liquid crystal displays and organic light - emitting displays are used.

[0005] Among these display devices, an organic light - emitting display device uses self - emitting organic light - emitting diodes and provides advantages such as fast response and better contrast, luminous efficiency, brightness, and viewing angle.

[0006] A display device may include light - emitting elements respectively disposed in a plurality of sub - pixels provided on a display panel, and the light - emitting diodes emit light by controlling the voltage applied to the light - emitting elements, thereby displaying an image while controlling the brightness of each sub - pixel.

[0007] Recently, the usage fields of display devices have gradually expanded to include not only portable computers but also desktop computer monitors, in - vehicle displays, and wall - mounted televisions.

[0008] Such display devices may provide various functions according to the use of the electronic device on which the display panel is installed. For example, for an in - vehicle display device, a navigation function can be said to be an essential function.

[0009] Meanwhile, a display device may be abnormally turned off due to shock or over - current during the driving process. In this case, if the screen flickers or display errors such as horizontal stripes occur during the abnormal turn - off process of the display device such as a navigation device, there is a possibility of an accident due to the sudden reaction of the driver. Summary of the invention

[0010] Therefore, the inventors of the present disclosure have invented a display device and a level shifter that can prevent an accident caused by a display error when the display panel is abnormally turned off.

[0011] Embodiments of the present disclosure may provide a display device and a level shifter that can eliminate display errors by cutting off a light-emitting control transistor that controls a light-emitting element when a display panel is abnormally turned off.

[0012] Embodiments of the present disclosure may provide a display device and a level shifter that can prevent accidents caused by display errors by controlling a light-emitting signal applied to a sub-pixel in a cut-off state when a display panel is abnormally turned off.

[0013] Embodiments of the present disclosure may provide a display device including: a display panel including a plurality of sub-pixels; a gate driving circuit that supplies a scan signal and a light-emitting signal to the display panel through a plurality of gate lines; a level shifter that controls the gate driving circuit; and a timing controller that controls the level shifter, wherein the level shifter includes a scan channel circuit that generates a scan start signal for the plurality of sub-pixels according to a first input signal, a charge pump circuit that generates a high-potential light-emitting voltage using a circuit power supply of a host system, and a light-emitting channel circuit that controls a light-emitting start signal according to a second input signal in response to a change in the circuit power supply.

[0014] Embodiments of the present disclosure may provide a level shifter including a scan channel circuit that generates a scan start signal for a plurality of sub-pixels according to a first input signal, a charge pump circuit that generates a high-potential light-emitting voltage using a circuit power supply of a host system, and a light-emitting channel circuit that controls a light-emitting start signal according to a second input signal in response to a change in the circuit power supply.

[0015] According to an embodiment of the present disclosure, accidents caused by display errors can be prevented when a display panel is abnormally turned off.

[0016] According to an embodiment of the present disclosure, display errors can be eliminated and power consumption can be reduced by cutting off a light-emitting control transistor that controls a light-emitting element when a display panel is abnormally turned off.

[0017] According to an embodiment of the present disclosure, accidents caused by display errors can be prevented by controlling a light-emitting signal applied to a sub-pixel in a cut-off state when a display panel is abnormally turned off. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0019] Figure 1 is a view showing an example interior of a vehicle according to an embodiment of the present disclosure;

[0020] Figure 2 is a view schematically showing an in-vehicle display device according to an embodiment of the present disclosure;

[0021] Figure 3 is a system example view showing a display device according to an embodiment of the present disclosure;

[0022] Figure 4 is a block diagram showing an example gate driving circuit including a scan driving circuit and a light emitting driving circuit in a display device according to an embodiment of the present disclosure;

[0023] Figure 5 is a view showing an example sub - pixel circuit in a display device according to an embodiment of the present disclosure;

[0024] Figure 6 is a view showing an example power supply waveform supplied to a host system of a display device according to an embodiment of the present disclosure;

[0025] Figure 7 is a view showing an example signal error when the power supply supplied to the host system in a display device according to an embodiment of the present disclosure is abnormally cut off;

[0026] Figure 8 is a circuit block diagram showing a level converter in a display device according to an embodiment of the present disclosure;

[0027] Figure 9 and Figure 10 is a signal waveform diagram showing the operation of a level converter in a display device according to an embodiment of the present disclosure; and

[0028] Figure 11 is a view showing an example screen state of a display panel when a vehicle - mounted display device is abnormally cut off. Detailed Description of Specific Embodiments

[0029] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the exemplary drawings. In the following description of the examples or embodiments of the present disclosure, reference will be made to the drawings, in which specific examples or embodiments that can be implemented are shown as examples, and in the drawings, the same reference numerals may be used to denote the same or similar components, even if they are shown in different drawings from each other. In addition, in the following description of the examples or embodiments of the present disclosure, when it is determined that the detailed description of well - known functions and components incorporated herein may make the subject matter in some embodiments of the present disclosure quite unclear, the detailed description will be omitted. Terms such as "including", "having", "containing", "constituting", "consisting of", and "formed of" used herein generally intend to allow the addition of other components, unless these terms are used together with the term "only". As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise.

[0030] Terms such as “first”, “second”, “A”, “B”, “(A)”, or “(B)” may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the nature, order, sequence, quantity, etc. of an element, but is only used to distinguish the corresponding element from other elements.

[0031] When referring to a first element being “connected or coupled”, “contacting or overlapping” etc. with a second element, it should be interpreted that not only can the first element be “directly connected or coupled” or “directly contacting or overlapping” with the second element, but also a third element can be “interposed” between the first element and the second element, or the first element and the second element can be “connected or coupled”, “contacting or overlapping” etc. with each other through a fourth element. Here, the second element may be included in at least one of two or more elements that are “connected or coupled”, “contacting or overlapping” etc. with each other.

[0032] When time - related terms such as “after”, “subsequent to”, “then”, “before” etc. are used to describe a process or operation of an element or configuration, or a process or step in an operation, process, or manufacturing method, these terms can be used to describe a non - continuous or non - sequential process or operation, unless used together with the terms “directly” or “immediately”.

[0033] In addition, when referring to any dimension, relative size, etc., even if the relevant description is not explicitly stated, the numerical value or corresponding information (e.g., level, range, etc.) of an element or feature should be considered to include a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term “may” fully encompasses all meanings of the term “can”.

[0034] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 is a view showing an example interior of a vehicle according to an embodiment of the present disclosure.

[0036] Reference Figure 1 , a vehicle 1000 according to an embodiment of the present disclosure may include a driver's seat, a passenger seat, an instrument panel located in front of the driver's seat and the passenger seat and provided with various meters required for driving, and a center instrument panel having a control panel with electronic devices.

[0037] The instrument panel may include a first display panel 111 that displays information required for driving (including a speedometer). The first display panel 111 may be referred to as an instrument panel display panel.

[0038] The first display panel 111 is a display panel that enables the safe driving of the vehicle 1000 by transmitting information about the driving state of the vehicle 1000 and the operation of various electronic devices installed in the vehicle 1000 to the driver. A speedometer indicating the driving speed, an odometer indicating the driving distance, a tachometer indicating the engine revolutions per minute (RPM), a fuel gauge, a water temperature gauge, an engine thermometer, and various warning lights can be displayed through the first display panel 111, which is located behind the steering wheel relative to the driver's seat.

[0039] The center instrument panel is located between the driver's seat and the front passenger seat, and can correspond to the area where the instrument panel and the shift lever intersect vertically. An audio system, an air conditioner, a heater controller, a navigator, a blower, a cigarette lighter socket, an ashtray, a cup holder, etc. can be provided therein. In addition, the center instrument panel may include a second display panel 112.

[0040] The second display panel 112 can guide the route to the destination or display a map image corresponding to the current location, and display a user interface related to the control of various electronic devices installed in the vehicle 1000. In addition, when the vehicle 1000 is connected to a mobile terminal, the screen provided by the mobile terminal can be displayed.

[0041] The second display panel 112 located between the driver's seat and the front passenger seat of the vehicle 1000 can be referred to as the center instrument panel display panel.

[0042] In addition, for the convenience of the passenger in the front passenger seat, a third display panel 113 can be additionally installed in front of the front passenger seat. The third display panel 113 located at the front passenger seat can be referred to as the front passenger seat display panel.

[0043] In addition, in addition to the instrument panel display panel 111, the center instrument panel display panel 112, and the front passenger seat display panel 113, the display panel 110 may further include at least one of a windshield display panel, a side mirror display panel, a rearview mirror display panel, and a side window display panel. In addition, various types of display panels can be installed.

[0044] The windshield display panel can be a display panel that projects a virtual image onto a partial area of the windshield where the front of the vehicle 1000 can be seen. By displaying the vehicle speed, the remaining fuel amount, the route direction information, etc. via the windshield display panel, unnecessary line-of-sight changes of the driver in different directions can be minimized.

[0045] The side mirror display panel may be a display panel capable of displaying a side image captured by a side camera in a partial area or the entire area of the side mirror formed to observe the side of the vehicle 1000. Therefore, the driver can not only recognize the side image reflected by the side mirror, but also recognize the side image captured by the side camera through the side mirror display panel.

[0046] The rearview mirror display panel may be a display panel capable of displaying a rear image captured by a rear camera in a partial area or the entire area of the rearview mirror formed to observe the rear of the vehicle 1000. Therefore, the driver can not only recognize the rear image reflected by the rearview mirror, but also recognize the rear image captured by the rear camera through the rearview mirror display panel.

[0047] The side window display panel may be a display panel that projects a virtual image onto a partial area of the side window where the side of the vehicle 1000 can be seen. Various information about the vehicle can be displayed through the side window display panel.

[0048] Figure 2 is a view schematically showing an in-vehicle display device according to an embodiment of the present disclosure.

[0049] Reference Figure 2 , the display device 100 according to an embodiment of the present disclosure may include a display panel 110, a gate driving circuit 120, a data driving circuit 130, a timing controller 140, and a level shifter 180.

[0050] In the display panel 110, a plurality of data lines DL and a plurality of gate lines GL may cross each other, and sub-pixels SP may be arranged in a matrix form in each crossing area, thereby forming a sub-pixel array.

[0051] In the case of a liquid crystal display device, the display panel 110 may include a liquid crystal layer formed between two substrates and may operate in any known mode such as a twisted nematic (TN) mode, a vertical alignment (VA) mode, an in-plane switching (IPS) mode, or an fringe field switching (FFS) mode. In the case of an organic light emitting display device, the display panel 110 may be implemented in a top emission scheme, a bottom emission scheme, or a double-sided emission scheme.

[0052] For example, one sub-pixel SP may include a thin film transistor (TFT) disposed in an area formed by one data line DL and one gate line GL, a light emitting element that emits light according to a data voltage, and a storage capacitor electrically connected to the light emitting element to maintain the voltage. The thin film transistor may include a driving transistor and one or more switching transistors and may be implemented as a P-type transistor or an N-type transistor. Alternatively, the thin film transistor may be implemented in a hybrid form of a P-type transistor and an N-type transistor.

[0053] For example, when the display device 100 with a resolution of 2160×3840 includes four sub-pixels SP of white (W), red (R), green (G), and blue (B), 3840 data lines DL can be connected to 2160 gate lines GL and the four sub-pixels WRGB. Therefore, 3840×4 = 15360 data lines DL can be set. Each sub-pixel SP is disposed in an area formed by the gate line GL and the data line DL.

[0054] The timing controller 140 receives the image data DATA from an external host system (not shown) through various interface methods. The timing controller 140 can correct the image data DATA based on the sensing result of the characteristic value of the sub-pixel (e.g., the threshold voltage or mobility of the driving transistor) to compensate for the driving deviation of the sub-pixel SP, and then transmit it to the data driving circuit 130.

[0055] The timing controller 140 can receive timing signals such as a vertical synchronization signal, a horizontal synchronization signal, and a data enable signal from the host system. The timing controller 140 generates a source control signal SCS for controlling the operation timing of the data driving circuit 130 and a timing control signal TCS for controlling the operation timing of the gate driving circuit 120 based on the timing signals input from the host system.

[0056] The source control signal SCS includes a source sampling clock, a source output enable signal, etc. The source sampling clock is a clock for controlling the sampling timing of the image data DATA in the data driving circuit 130 based on the rising edge or falling edge. The source output enable signal is a signal for controlling the output timing of the analog data voltage applied to the display panel 110.

[0057] The data driving circuit 130 may include a plurality of source driver integrated chips SDIC. The data driving circuit 130 receives the image data DATA from the timing controller 140. The data driving circuit 130 generates a data voltage by converting the image data DATA into a gamma compensation voltage in response to the source control signal SCS transmitted from the timing controller 140, and supplies the data voltage to the data line DL of the display panel 110 in synchronization with the scan signal of the gate driving circuit 120.

[0058] The data driving circuit 130 can be connected to the data line DL of the display panel 110 through a chip on glass (COG) process or a tape automated bonding (TAB) process.

[0059] The display device 100 may include a level shifter 180 that generates a gate control signal GCS using a timing control signal TCS output from a timing controller 140 and supplies the generated gate control signal GCS to a gate driving circuit 120. The level shifter 180 may be located inside the gate driving circuit 120 or may be located on a source printed circuit board where the data driving circuit 130 is provided.

[0060] The level shifter 180 may convert a transistor-transistor logic (TTL) level voltage of the timing control signal TCS input from the timing controller 140 into a conduction level voltage and a cut-off level voltage capable of switching transistors formed on the display panel 110. Then, the level shifter 180 supplies the gate control signal GCS to the gate driving circuit 120.

[0061] The timing control signal TCS may include a conduction clock, a cut-off clock, an alternating control pulse, and the like.

[0062] The gate control signal GCS may include a gate start signal, a gate clock, an even alternating current (AC) voltage, an odd AC voltage, a gate line signal, a reset signal, and a panel turn-on signal. The gate clock may be composed of N (where N is a natural number) phase clocks with different phases. When the gate driving circuit 120 includes a scan driving circuit and a light emitting driving circuit, the gate start signal may include a scan start signal and a light emitting start signal, and the gate clock may include a scan clock and a light emitting clock.

[0063] For example, in the display device 100 with a resolution of 2160×3840, for 2160 gate lines GL, when the gate signals are output sequentially from the first gate line to the 2160th gate line, it may be referred to as 2160-phase driving. Or, when the gate signals are output sequentially based on every four gate lines GL, such as when the gate signals are output sequentially from the first gate line to the fourth gate line and then the gate signals are output sequentially from the fifth gate line to the eighth gate line, it is called four-phase driving. In other words, when the gate signals are output sequentially for every N gate lines GL, it may be referred to as N-phase driving.

[0064] When the gate driving circuit 120 includes a scan driving circuit and a light emitting driving circuit, the gate signals may include scan signals and light emitting signals.

[0065] In addition, the gate driving circuit 120 may include one or more gate driving integrated circuits GDICs.

[0066] Based on the gate control signal GCS input from the level shifter 180 and one or more power supply voltages GVDD and GVSS input from a power management circuit (not shown), the gate driving circuit 120 can output a display gate signal during the display driving period and a sensing gate signal for sensing the characteristic value of the sub-pixel SP during the blank period.

[0067] The gate driving circuit 120 can be directly formed on the substrate of the display panel 110 in a gate-in-panel (GIP) manner.

[0068] The gate driving circuit 120 can be formed in the border area of the display panel 110 where no image is displayed, but is not limited thereto. The gate driving circuit 120 can be formed in a double bank structure, where the first gate driving circuit 120a is disposed in the first border area of the display panel 110 and the second gate driving circuit 120b is disposed in the second border area of the display panel 110 to minimize the distortion of the gate signal caused by signal delay.

[0069] The timing controller 140 can control the display driving operation and the sensing driving operation of the sub-pixel rows of the display panel 110 based on the source control signal SCS and the timing control signal TCS, so as to sense the characteristic value of the sub-pixel SP in real time even during the period of displaying an image.

[0070] Here, the sub-pixel row refers to a set of a row number of sub-pixels SP adjacent to each other in the horizontal direction.

[0071] The sensing driving operation refers to an operation of sensing the characteristic value of a corresponding sub-pixel SP by applying sensing data to the sub-pixels SP provided in a specific sub-pixel row, and updating a compensation value for compensating for the change in the characteristic value of the corresponding sub-pixel SP based on the sensing result.

[0072] The display device 100 can include a power management circuit that supplies various voltages or currents to the display panel 110, the gate driving circuit 120, the data driving circuit 130, etc., or controls the various voltages or currents to be supplied.

[0073] The power management circuit generates the power required to drive the display panel 100, the gate driving circuit 120, and the data driving circuit 130 by adjusting the direct current (DC) voltage supplied from an external host system.

[0074] The display device 100 can be one of various types of devices such as a liquid crystal display, an organic light emitting diode display, or a plasma display panel.

[0075] Figure 3 It is a system example view of a display device according to an embodiment of the present disclosure.

[0076] Figure 3 The following example is shown: In the display device 100 according to an embodiment of the present disclosure, the data driving circuit 130 is implemented by a chip - on - film (COF) type among various types (e.g., TAB, COG, and COF), and the gate driving circuit 120 is implemented by an in - panel gate (GIP) type among various types (e.g., TAB, COG, COF, and GIP).

[0077] When the gate driving circuit 120 is implemented in the GIP type, a plurality of gate driving integrated circuits GDICa and GDICb included in the gate driving circuit 120 can be directly formed in the border area of the display panel 110. In this case, the gate driving integrated circuits GDICa and GDICb can receive various signals (e.g., gate clock, gate high signal, gate low signal, etc.) required to generate gate signals through gate - driving - related signal lines provided in the border area.

[0078] Similarly, each of one or more source driving integrated circuits SDIC included in the data driving circuit 130 can be mounted on the source film SF, and one side of the source film SF can be electrically connected to the display panel 110. Signal lines for electrically connecting the source driving integrated circuit SDIC and the display panel 110 can be provided on the source film SF.

[0079] The display device 100 may include at least one source printed circuit board SPCB for circuit connection between a plurality of source driving integrated circuits SDIC and other devices, and a control printed circuit board CPCB for mounting control components and various electronic devices.

[0080] The other side of the source film SF on which the active source driving integrated circuit SDIC is mounted can be connected to at least one source printed circuit board SPCB. In other words, one side of the source film SF on which the active source driving integrated circuit SDIC is mounted can be electrically connected to the display panel 110, and the other side thereof can be electrically connected to the source printed circuit board SPCB.

[0081] The timing controller 140 and the power management circuit 150 can be mounted on the control printed circuit board CPCB. The timing controller 140 can control the operations of the data driving circuit 130 and the gate driving circuit 120. The power management circuit 150 can supply driving voltage or current to the display panel 110, the data driving circuit 130, and the gate driving circuit 120, and control the supplied voltage or current.

[0082] At least one source printed circuit board SPCB and a control printed circuit board CPCB can be circuit-connected through at least one connection member. For example, the connection member can include a flexible printed circuit FPC or a flexible flat cable FFC. At least one source printed circuit board SPCB and the control printed circuit board CPCB can be integrated into a single printed circuit board.

[0083] The display device 100 can further include a setting board 170 electrically connected to the control printed circuit board CPCB. In this case, the setting board 170 can also be referred to as a power supply board. A main power management circuit 160 for managing the total power supply of the display device 100 can be present on the setting board 170. The main power management circuit 160 can interact with the power management circuit 150.

[0084] In the display device 100 configured as such, a driving voltage is generated in the setting board 170 and is transmitted to the power management circuit 150 in the control printed circuit board CPCB. The power management circuit 150 transmits the driving voltage required for display driving or eigenvalue sensing to the source printed circuit board SPCB through the flexible printed circuit FPC or the flexible flat cable FFC. The driving voltage transmitted to the source printed circuit board SPCB is supplied through a source driver integrated circuit SDIC to emit light or sense a specific sub-pixel SP in the display panel 110.

[0085] Each sub-pixel SP in the display panel 110 arranged in the display device 100 can include a light-emitting element (e.g., an organic light-emitting diode), and a circuit element (e.g., a driving transistor) for driving the light-emitting element.

[0086] The type and number of circuit elements constituting each sub-pixel SP can vary according to the function to be provided and the design scheme.

[0087] According to the configuration of the sub-pixel SP, the gate driving circuit 120 can be formed by a scan driving circuit that outputs a scan signal, or can include a scan driving circuit that outputs a scan signal and a light-emitting driving circuit that outputs a light-emitting signal.

[0088] Figure 4 is a block diagram showing an example gate driving circuit including a scan driving circuit and a light-emitting driving circuit in a display device according to an embodiment of the present disclosure.

[0089] Reference Figure 4, the gate driving circuit 120 of the display device 100 according to an embodiment of the present disclosure may include a plurality of scan driving circuits SCD1 to SCD4 that output scan signals SCAN[1] to SCAN[4] for controlling switching transistors included in a plurality of sub-pixels SP1 to SP4, and a plurality of emission driving circuits EMD1 to EMD4 that output emission signals for controlling emission control transistors included in the plurality of sub-pixels SP1 to SP4.

[0090] In this case, the scan driving circuit and the emission driving circuit may be collectively referred to as a gate driving integrated circuit.

[0091] When the gate driving circuit 120 is implemented in a gate-in-panel (GIP) type, the scan driving circuit SCD and the emission driving circuit EMD may be disposed in multi-stages ST1, ST2, ST3, and ST4 in a border area of the display panel 110.

[0092] The emission driving circuit EMD may generate row emission signals EM[1], EM[2], EM[3], and EM[4] by operating based on an emission clock ECLK, an emission start signal EVST, a low-potential emission voltage VEL, and a high-potential emission voltage VEH.

[0093] In this case, the emission driving circuit EMD1 of the first row may generate the first row emission signal EM[1] using the emission start signal EVST, and the emission driving circuit EMD2 of the second row may generate the second row emission signal EM[2] using the first row emission signal EM[1] output from the emission driving circuit EMD1 of the first row. As described above, starting from the emission driving circuit EMD2 of the second row, the row emission signal generated by the front-end emission driving circuit may be used as the emission start signal.

[0094] The row emission signals EM[1], EM[2], EM[3], and EM[4] may be supplied to the display panel 110 through their respective corresponding sub-pixel rows, and each of the row emission signals EM[1], EM[2], EM[3], and EM[4] may include one or more emission signals according to the structure of the sub-pixel SP.

[0095] The scan driving circuit SCD may generate row scan signals SCAN[1], SCAN[2], SCAN[3], and SCAN[4] by operating based on a scan clock SCLK, a scan start signal SVST, a low-potential scan voltage VSL, and a high-potential scan voltage VSH.

[0096] In this case, the scan driving circuit SCD1 of the first row can generate a first row scan signal SCAN[1] using a scan start signal SVST, and the scan driving circuit SCD2 of the second row can generate a second row scan signal SCAN[2] using the first row scan signal SCAN[1] output from the scan driving circuit SCD1 of the first row. As described above, starting from the scan driving circuit SCD2 of the second row, the row scan signal generated by the front-end scan driving circuit can be used as a scan start signal.

[0097] The row scan signals SCAN[1], SCAN[2], SCAN[3], and SCAN[4] can be supplied to the display panel 110 through their respective corresponding sub-pixel rows, and each of the row scan signals SCAN[1], SCAN[2], SCAN[3], and SCAN[4] can include one or more scan signals according to the structure of the sub-pixel SP.

[0098] Figure 5 is a view showing an example sub-pixel circuit in a display device according to an embodiment of the present disclosure.

[0099] Reference Figure 5 , the sub-pixel circuit of the display device 100 according to an embodiment of the present disclosure may include a light-emitting element ED, a driving transistor DRT, a plurality of switching transistors T1 to T5, and a storage capacitor Cst.

[0100] The driving transistor DRT and the plurality of switching transistors T1 to T5 included in the sub-pixel circuit can be implemented as PMOS-type low-temperature polycrystalline silicon (LTPS) transistors, thereby ensuring desired response characteristics.

[0101] Alternatively, at least one of the plurality of switching transistors T1 to T5 can be implemented as an NMOS-type or PMOS-type oxide transistor having good leakage current characteristics in the off state, and the remaining switching transistors can be implemented as PMOS-type LTPS transistors having good response characteristics.

[0102] The light-emitting element ED emits light through a driving current adjusted according to the gate-source voltage Vgs of the driving transistor DRT. The anode of the light-emitting element ED is connected to the fourth node P4, and the cathode of the light-emitting element ED is connected to a low-potential pixel voltage EVSS.

[0103] When the light-emitting element ED is an organic light-emitting diode, an organic compound layer is provided between the anode and the cathode.

[0104] The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, a light-emitting layer EML, an electron transport layer ETL, and an electron injection layer EIL. For example, two or more organic compound layers emitting light of different colors can be stacked according to a series structure.

[0105] When a driving current flows through the light-emitting element ED, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the light-emitting layer EML to form excitons. Therefore, the light-emitting layer EML can emit visible light.

[0106] The driving transistor DRT controls the current flowing through the light-emitting element ED according to the gate-source voltage Vgs. The gate of the driving transistor DRT is connected to the second node P2, the drain (or source) is connected to the driving voltage line supplying the high-potential pixel voltage EVDD, and the source (or drain) is connected to the third node P3.

[0107] The sub-pixel circuit may include first to fifth switching transistors T1 to T5 capable of sampling the gate-source voltage Vgs, and a storage capacitor Cst for compensating the threshold voltage or mobility of the driving transistor DRT.

[0108] The first switching transistor T1 is connected between the data line DL and the first node P1 and is switched according to the first scan signal SCAN1. The gate of the first switching transistor T1 is connected to the first gate line to which the first scan signal SCAN1 is applied, the drain (or source) is connected to the data line DL, and the source (or drain) is connected to the first node P1.

[0109] The second switching transistor T2 is connected between the second node P2 and the third node P3 and is switched according to the second scan signal SCAN2. The gate of the second switching transistor T2 is connected to the second gate line to which the second scan signal SCAN2 is applied, the drain (or source) is connected to the third node P3, and the source (or drain) is connected to the second node P2.

[0110] Since one electrode of the second switching transistor T2 is connected to the gate of the driving transistor DRT, preferably, the second switching transistor T2 has good cut-off current characteristics. Therefore, the second switching transistor T2 can be designed with a double-gate structure to suppress leakage current at cut-off.

[0111] In the double-gate structure, the first gate and the second gate are connected to each other to have the same potential, and the channel length of the double-gate structure is longer than that of the single-gate structure. As the channel length increases, the resistance increases, and the leakage current at cut-off decreases, thereby ensuring the stability of the operation. However, the second switching transistor T2 can be implemented as a single-gate structure, and in this case, the second switching transistor T2 can be implemented as an oxide transistor.

[0112] The third switching transistor T3 is connected between the first node P1 and a reference voltage line to which a reference voltage Vref is applied, and is switched according to a light emission signal EM. The gate of the third switching transistor T3 is connected to a third gate line to which the light emission signal EM is applied, the drain (or source) is connected to the first node P1, and the source (or drain) is connected to the reference voltage line.

[0113] The fourth switching transistor T4 is connected between the third node P3 and a fourth node P4 which is the anode of a light emitting element ED, and is switched according to a light emission signal EM. The gate of the fourth switching transistor T4 is connected to a third gate line to which the light emission signal EM is applied, the drain (or source) is connected to the third node P3, and the source (or drain) is connected to the fourth node P4. Since the fourth switching transistor T4 controls the drive current flowing through the light emitting element ED, it may be referred to as a light emission control transistor.

[0114] The fifth switching transistor T5 is connected between the fourth node P4 and the reference voltage line, and is switched according to a second scan signal SCAN2. The gate of the fifth switching transistor T5 is connected to a second gate line to which the second scan signal SCAN2 is applied, the drain (or source) is connected to the fourth node P4, and the source (or drain) is connected to the reference voltage line.

[0115] A storage capacitor Cst is connected between the first node P1 and the second node P2.

[0116] The display device 100 according to the present disclosure can operate a drive circuit and a display panel using a power supply supplied from a host system.

[0117] Figure 6 is a view showing an example power supply waveform of a host system supplied to a display device according to an embodiment of the present disclosure.

[0118] Reference Figure 6 , the display device 100 according to an embodiment of the present disclosure can operate drive circuits such as a timing controller 140 and a power management circuit 150 using a first power supply VCC supplied from a host system, and can drive the display panel 110 using a second power supply VDD supplied from the host system.

[0119] The first power supply VCC supplied from the host system for operating drive circuits such as the timing controller 140 and the power management circuit 150 may be referred to as a circuit power supply, and the first power supply VCC may be 3.3V. In addition, the second power supply VDD supplied from the host system for driving the display panel 110 may be referred to as a panel power supply, and the second power supply VDD may be 20V.

[0120] In this case, in order to turn on the display device 100 normally, preferably, the driving circuit is first operated by the first power supply VCC, and after an on-delay time d1 has elapsed, the display panel 110 is driven by the second power supply VDD.

[0121] In addition, in order to turn off the display device 100 normally, preferably, the second power supply VDD is cut off to turn off the display panel 110, and after a off-delay time d2 has elapsed, the first power supply VCC is cut off to turn off the driving circuit.

[0122] However, when the first power supply VCC and the second power supply VDD applied from the host system are abnormally cut off, a gate signal may be applied before the display panel 110 is turned off, resulting in a display error.

[0123] Figure 7 FIG. is a view showing an example signal error in a display device according to an embodiment of the present disclosure when the power supply supplied to the host system is abnormally cut off.

[0124] Refer to Figure 7 , in order to turn off the display device 100 according to an embodiment of the present disclosure normally, it is necessary to turn off the second power supply VDD that drives the display panel 110, and after a predetermined off-delay time d2 has elapsed, turn off the first power supply VCC that operates the driving circuit.

[0125] However, when the host system is abnormally cut off, for example, when the battery power supply is turned off, the first power supply VCC that operates the driving circuit may be cut off while the second power supply VDD that drives the display panel 110 is turned on.

[0126] In this case, when the gate control signal GCS supplied to the gate driving circuit 120 is cut off in the level shifter 180, a display error may occur in which some sub-pixels SP emit light due to the light emission signal EM and the scan signal SCAN applied to the display panel 110.

[0127] For example, when the light emission control transistor ( Figure 5 T4 in ) is a PMOS transistor, the light emission control transistor emits light through a low-level light emission signal EM, and thus a display error occurs in which a partial region of the display panel 110 emits light through the applied low-level light emission signal EM while the gate control signal GCS is cut off.

[0128] When the power supply of the host system is abnormally cut off, the display device 100 according to the present disclosure detects this and cuts off the light emission control transistor of the display panel 110, thereby preventing an accident caused by a display error.

[0129] Figure 8is a circuit diagram of a level shifter in a display device according to an embodiment of the present disclosure.

[0130] Reference Figure 8 , the level shifter 180 of the display device 100 according to an embodiment of the present disclosure may include a scan channel circuit 182 that generates a scan start signal SVST of the sub-pixel SP according to a first input signal Vinl, a charge pump circuit 184 that generates a high potential emission voltage VEH using the circuit power supply VCC of the host system, and a light emission channel circuit l86 that controls a light emission start signal EVST according to a second input signal Vin2 in response to a change in the circuit power supply of the host system.

[0131] The scan channel circuit 182 may include a first input pad IP1 that receives the first input signal Vinl, one or more scan inverters SINl and SIN2 connected in series to the first input pad IP1, and a scan amplifier SA that generates a scan start signal SVST using the signals of the scan inverters SINl and SIN2.

[0132] The first input signal Vinl is a pulse signal for generating the scan start signal SVST, and may be a scan clock GCLK.

[0133] One or more scan inverters SINl and SIN2 connected in series to the first input pad IP1 may include an even number or an odd number of inverters. When an even number of scan inverters are connected in series to the first input pad IP1, a scan start signal SVST having the same phase as the first input signal Vin1 may be output, and when an odd number of scan inverters are connected in series to the first input pad IP1, a scan start signal SVST having a phase opposite to that of the first input signal Vin1 may be output.

[0134] The scan amplifier SA may be an operational amplifier that uses a high potential scan voltage VSH as a positive power supply, uses a low potential scan voltage VSL as a negative power supply, and outputs a scan start signal SVST to convert between the level of the high potential scan voltage VSH and the level of the low potential scan voltage VSL.

[0135] The charge pump circuit 184 may include one or more diodes D1, D2, and D3 connected in series to transfer the circuit power supply VCC of the host system, and one or more capacitors C1 and C2 that connect the output nodes of the scan inverters SIN1 and SIN2 constituting the scan channel circuit 182 to the output nodes of the diodes D1 and D2.

[0136] One or more diodes D1, D2, and D3 connected in series in the charge pump circuit 184 sequentially transfer the circuit power supply VCC charged through the capacitors C1 and C2. When two capacitors C1 and C2 are provided in the charge pump circuit 184, a high potential light emission voltage VEH of 3VCC can be output through the charging voltage VCC of each of the capacitors C1 and C2.

[0137] Since the charge pump circuit 184 uses the capacitors C1 and C2 to store the circuit power supply VCC, the charge pump circuit 184 can be formed to have a smaller size than when using an inductor.

[0138] The light emission channel circuit 186 may include a second input pad IP2 that receives a second input signal Vin2, two switches S1 and S2 connected in parallel to the second input pad IP2, a first light emission inverter EIN1 and a second light emission inverter EIN2 connected in series to the first switch S1, an oscillation circuit ST that converts the circuit power supply VCC of the host system into a pulse voltage V1, a switch control circuit that controls the two switches S1 and S2 according to the pulse voltage V1, and a light emission amplifier EA that generates a light emission start signal EVST using the signals of the light emission inverters EIN1 and EIN2.

[0139] The second input signal Vin2 is a pulse signal for generating the light emission start signal EVST and may be a light emission clock ECLK. The second input signal Vin2 may be the same as or different from the first input signal Vin1.

[0140] One or more light emission inverters connected in series to the second input pad IP2 may be formed of an even number or an odd number of inverters. When an even number of light emission inverters are connected in series to the second input pad IP2, a light emission start signal EVST having the same phase as the second input signal Vin2 can be output, and when an odd number of light emission inverters are connected in series to the second input pad IP2, a light emission start signal EVST having a phase opposite to that of the second input signal Vin2 can be output.

[0141] The oscillation circuit ST may be a Schmitt trigger circuit that outputs a pulse voltage V1 according to the level of the circuit power supply VCC of the host system. When the level of the circuit power supply VCC of the host system drops below a threshold, the Schmitt trigger circuit can generate a pulse voltage V1 having a high level opposite to the level of the circuit power supply VCC.

[0142] Meanwhile, the signal input to the oscillation circuit ST can be the circuit power supply VCC of the host system, or can be a signal that interacts with the circuit power supply VCC. For example, the circuit power supply VCC of the host system can be used to generate a high-potential scan voltage VSH. In this case, since the high-potential scan voltage VSH fluctuates in association with the circuit power supply VCC of the host system, the high-potential scan voltage VSH can be used as the input signal of the oscillation circuit ST.

[0143] The switch control circuit can control the first switch S1 through the third light-emitting inverter EIN3 that transmits the pulse voltage V1 of the oscillation circuit ST, and can control the second switch S2 through the pulse voltage V1 of the oscillation circuit ST. In other words, the first switch S1 and the second switch S2 are controlled such that the open state and the short-circuit state are opposite to each other.

[0144] Therefore, in the state where the first switch S1 is short-circuited, the light-emitting start signal EVST can be generated through the second input signal Vin2, and in the state where the second switch S2 is short-circuited, the level of the light-emitting start signal EVST can be controlled by the pulse voltage V1 of the oscillation circuit ST.

[0145] The light-emitting amplifier EA can be an operational amplifier that outputs a light-emitting start signal EVST to convert between the level of the high-potential light-emitting voltage VEH and the level of the low-potential light-emitting voltage VEL.

[0146] The high-potential light-emitting voltage VEH output from the charge pump circuit 184 can be applied to the high-potential node of the light-emitting amplifier EA, and the high-potential scan voltage VSH can be applied simultaneously through the fourth diode D4. Therefore, when the high-potential scan voltage VSH is applied at a high level, the light-emitting channel circuit 186 can operate, but even when the high-potential scan voltage VSH drops to a low level, the light-emitting channel circuit 186 can operate through the high-potential light-emitting voltage VEH output from the charge pump circuit 184.

[0147] Since the high-potential scan voltage VSH is generated in association with the circuit power supply VCC of the host system, when the circuit power supply VCC of the host system changes to a low level, the high-potential scan voltage VSH can also change to a low level. Therefore, the output voltage VEH of the charge pump circuit 184 can be supplied to the light-emitting amplifier EA of the light-emitting channel circuit 186 together, so that the light-emitting channel circuit 186 can operate even if the circuit power supply VCC of the host system is abnormally cut off.

[0148] Figure 9 and Figure 10 is a signal waveform diagram showing the operation of the level converter in the display device according to an embodiment of the present disclosure. Figure 11It is a view showing an example screen state of a display panel when the display device is abnormally cut off.

[0149] Reference Figure 9 and Figure 10 When the display device 100 according to an embodiment of the present disclosure is normally turned off, the panel power supply VDD that drives the display panel 110 is turned off, and after a predetermined turn-off delay time has elapsed, the circuit power supply VCC that operates the drive circuit is turned off.

[0150] However, when the host system is abnormally cut off, for example, when the battery power supply is turned off, the circuit power supply VCC that operates the drive circuit may drop to the ground voltage GND less than or equal to the threshold value in a state where the high-potential pixel voltage EVDD of the display panel 110 is turned on.

[0151] As described above, when the circuit power supply VCC supplied from the host system abnormally drops, the high-potential scan voltage VSH that interacts with the circuit power supply VCC may also drop. In this case, the scan start signal SVST output through the scan channel circuit 182 may also drop to a low level through the low-level high-potential scan voltage VSH. Therefore, the PMOS-type switching transistors of the sub-pixels that receive the scan start signal SVST (for example, Figure 5 T1 and T2 of

[0152] However, since the level shifter 180 of the present disclosure maintains the high-potential light-emitting voltage VEH at a high level (for example, 3VCC) through the charge pump circuit 184, the light-emitting start signal EVST output through the light-emitting channel circuit 186 is maintained at a high level. Therefore, the PMOS-type light-emitting control transistor of the sub-pixel that receives the light-emitting start signal EVST (for example, Figure 5 T4 of

[0153] In other words, when the display device 100 according to the present disclosure is operating normally, the light-emitting channel circuit 186 of the level shifter 180 can output the light-emitting start signal EVST according to the second input signal Vin2 corresponding to the light-emitting clock ECLK. However, when the display device 100 is abnormally cut off and the circuit power supply VCC is turned off before the panel power supply VDD, the light-emitting start signal EVST of the cut-off level can be output by generating a pulse voltage V1 opposite to the level of the circuit power supply VCC via the oscillation circuit ST.

[0154] Therefore, although the conventional in-vehicle display device 100 may experience a display error on the display panel 110 as shown in Figure 11 (a) of Figure 11as shown in (b) of, by turning off the light-emitting control transistor ( Figure 5 T4 thereof) to prevent display errors and accidents on the display panel 110.

[0155] Embodiments of the present disclosure described above are briefly described below.

[0156] A display device according to the present disclosure may include: a display panel including a plurality of sub-pixels; a gate driving circuit supplying a scan signal and a light-emitting signal to the display panel through a plurality of gate lines; a level shifter controlling the gate driving circuit; and a timing controller controlling the level shifter. The level shifter may include a scan channel circuit generating a scan start signal for a plurality of sub-pixels according to a first input signal, a charge pump circuit generating a high-potential light-emitting voltage using a circuit power supply of a host system, and a light-emitting channel circuit controlling a light-emitting start signal according to a second input signal in response to a change in the circuit power supply.

[0157] The sub-pixel may include a light-emitting element, a driving transistor controlling a current flowing to the light-emitting element according to a gate-source voltage, a first switching transistor connected between a data line and a first node and switching according to a first scan signal, a second switching transistor connected between a second node and a third node and switching according to a second scan signal, a third switching transistor connected between the first node and a reference voltage line and switching according to a light-emitting signal, a fourth switching transistor connected between the third node and an anode of the light-emitting element and switching according to a light-emitting start signal, a fifth switching transistor connected between the anode and the reference voltage line and switching according to the second scan signal, and a storage capacitor connected between the first node and the second node.

[0158] The driving transistor may be a PMOS-type low-temperature polycrystalline silicon (LTPS) transistor.

[0159] At least one of the first to fifth switching transistors may be a PMOS-type oxide transistor.

[0160] The light-emitting element may be an organic light-emitting diode.

[0161] The gate driving circuit may include a first scan driving circuit generating a first row scan signal using a scan start signal, one or more back-end scan driving circuits generating a back-end row scan signal using a row scan signal output from a front-end scan driving circuit, a first light-emitting driving circuit generating a first light-emitting signal using a light-emitting start signal, and one or more back-end light-emitting driving circuits generating a back-end light-emitting signal using a light-emitting signal output from a front-end light-emitting driving circuit.

[0162] The scan channel circuit may include a first input pad that receives a first input signal, one or more scan inverters connected in series to the first input pad, and a scan amplifier that generates a scan start signal using the output signals of the one or more scan inverters.

[0163] The first input signal may be a scan clock.

[0164] The scan amplifier may use a high-potential scan voltage generated using the circuit power supply as the positive power supply.

[0165] The charge pump circuit may include one or more diodes connected in series to transfer the circuit power supply, and one or more capacitors connecting the output node of the scan inverter constituting the scan channel circuit and the output node of the diode.

[0166] The light-emitting channel circuit may include a second input pad that receives a second input signal, a first switch and a second switch connected in parallel to the second input pad, a first light-emitting inverter and a second light-emitting inverter connected in series to the first switch, an oscillation circuit that converts the circuit power supply or a high-potential scan voltage generated using the circuit power supply into a pulse voltage, a switching control circuit that controls the first switch and the second switch according to the pulse voltage, and a light-emitting amplifier that generates a light-emitting start signal using the signal of the second light-emitting inverter.

[0167] The second input signal may be a light-emitting clock.

[0168] The oscillation circuit may be a Schmitt trigger circuit.

[0169] When the level of the circuit power supply drops below a threshold, the oscillation circuit may generate a pulse voltage with a high level opposite to the level of the circuit power supply.

[0170] The first switch and the second switch may perform opposite operations to each other through a third light-emitting inverter.

[0171] The light-emitting amplifier may receive a high-potential light-emitting voltage as the positive power supply, and may receive a high-potential scan voltage as the positive power supply through a diode.

[0172] A level shifter according to the present disclosure may include a scan channel circuit that generates a scan start signal for a plurality of sub-pixels according to a first input signal, a charge pump circuit that generates a high-potential light-emitting voltage using the circuit power supply of the host system, and a light-emitting channel circuit that controls the light-emitting start signal according to a second input signal in response to a change in the circuit power supply.

[0173] The foregoing description is provided to enable any person skilled in the art to make and use the inventive concept of the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. The foregoing description and the drawings provide examples of the inventive concept of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the inventive concept of the present disclosure.

Claims

1. A display device, comprising: A display panel, the display panel comprising a plurality of sub-pixels; a gate driving circuit configured to supply a scanning signal and a light emitting signal to the display panel through a plurality of gate lines; a level converter configured to control the gate drive circuit; as well as a timing controller configured to control the level converter, Wherein, the level converter comprises: a scanning channel circuit configured to generate a scanning start signal for the plurality of sub-pixels according to a first input signal; a charge pump circuit configured to generate a high potential light emitting voltage using a circuit power supply of a host system; and A light-emitting channel circuit is configured to reflect the change of the circuit power supply and control the light-emitting start signal according to the second input signal.

2. The display device according to claim 1, wherein: The sub-pixel comprises: Light emitting element; a driving transistor, the driving transistor controlling a current flowing to the light emitting element according to a gate-source voltage; a first switch transistor connected between the data line and the first node and switched according to a first scan signal; a second switch transistor, the second switch transistor being connected between the second node and the third node and being switched according to a second scan signal; a third switch transistor, the third switch transistor being connected between the first node and a reference voltage line and being switched according to the light emitting signal; a fourth switch transistor, the fourth switch transistor being connected between the third node and the anode of the light emitting element and being switched according to the light emitting start signal; a fifth switching transistor connected between the anode and the reference voltage line and switched according to the second scanning signal; and A storage capacitor is connected between the first node and the second node.

3. The display device according to claim 2, wherein: The driving transistor is a PMOS low temperature polysilicon transistor, ie, an LTPS transistor.

4. The display device according to claim 2, wherein: At least one of the first to fifth switch transistors is a PMOS type oxide transistor.

5. The display device according to claim 2, wherein: The light emitting element is an organic light emitting diode.

6. The display device according to claim 1, wherein: The gate drive circuit comprises: a first scan driving circuit, the first scan driving circuit being configured to generate a first row scan signal using the scan start signal; one or more back-end scan driving circuits, the one or more back-end scan driving circuits being configured to generate back-end row scan signals using row scan signals output from the front-end scan driving circuits; a first light emitting driving circuit configured to generate a first light emitting signal using the light emitting start signal; and One or more back-end light emitting driving circuits are configured to generate a back-end light emitting signal using the light emitting signal output from the front-end light emitting driving circuit.

7. The display device according to claim 1, wherein: The scanning channel circuit comprises: a first input pad, the first input pad receiving the first input signal; one or more scan inverters connected in series to the first input pad; and A scan amplifier is configured to generate the scan start signal using output signals of the one or more scan inverters.

8. The display device according to claim 7, wherein: The first input signal is a scan clock.

9. The display device according to claim 7, wherein: The scan amplifier uses a high potential scan voltage generated by the circuit power supply as a positive power supply.

10. The display device according to claim 1, wherein: The charge pump circuit comprises: one or more diodes connected in series to transmit the circuit power; and One or more capacitors, the one or more capacitors connecting an output node of a scan inverter constituting the scan channel circuit and an output node of the diode.

11. The display device according to claim 1, wherein: The light-emitting channel circuit comprises: a second input pad, the second input pad receiving a second input signal; a first switch and a second switch, the first switch and the second switch being connected in parallel to the second input pad; a first light emitting inverter and a second light emitting inverter, wherein the first light emitting inverter and the second light emitting inverter are connected in series to the first switch; an oscillation circuit configured to convert the circuit power supply or a high potential scanning voltage generated using the circuit power supply into a pulse voltage; a switch control circuit configured to control the first switch and the second switch according to the pulse voltage; and A light emitting amplifier is configured to generate the light emitting start signal using the signal of the second light emitting inverter.

12. The display device according to claim 11, wherein: The second input signal is a lighting clock.

13. The display device according to claim 11, wherein: The oscillation circuit is a Schmitt trigger circuit.

14. The display device according to claim 13, wherein: When the level of the circuit power supply drops below a threshold value, the oscillation circuit generates a pulse voltage of a high level opposite to the level of the circuit power supply.

15. The display device according to claim 11, wherein: The first switch and the second switch perform operations opposite to each other through a third light emitting inverter.

16. The display device according to claim 11, wherein: The light emitting amplifier receives the high potential light emitting voltage as a positive power supply, and receives the high potential scanning voltage as a positive power supply through a diode.

17. A level converter, comprising: a scanning channel circuit configured to generate a scanning start signal for a plurality of sub-pixels according to a first input signal; a charge pump circuit configured to generate a high potential light emitting voltage using a circuit power supply of a host system; as well as A light-emitting channel circuit is configured to reflect the change of the circuit power supply and control the light-emitting start signal according to the second input signal.

18. The level converter according to claim 17, wherein: The scanning channel circuit comprises: a first input pad, the first input pad receiving the first input signal; one or more scan inverters connected in series to the first input pad; and A scan amplifier is configured to generate the scan start signal using output signals of the one or more scan inverters.

19. The level converter according to claim 17, wherein: The charge pump circuit comprises: one or more diodes connected in series to transmit the circuit power; and One or more capacitors, the one or more capacitors connecting an output node of a scan inverter constituting the scan channel circuit and an output node of the diode.

20. The level converter according to claim 17, wherein The light-emitting channel circuit comprises: a second input pad, the second input pad receiving a second input signal; a first switch and a second switch, the first switch and the second switch being connected in parallel to the second input pad; a first light emitting inverter and a second light emitting inverter, wherein the first light emitting inverter and the second light emitting inverter are connected in series to the first switch; an oscillation circuit configured to convert the circuit power supply or a high potential scanning voltage generated using the circuit power supply into a pulse voltage; a switch control circuit configured to control the first switch and the second switch according to the pulse voltage; and A light emitting amplifier is configured to generate the light emitting start signal using the signal of the second light emitting inverter.

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