Display device

Abstract

A display device includes a gate driver for applying a scan signal, a light emission signal, and an inverted light emission signal to a pixel circuit, in which the gate driver includes at least one scan driver for outputting the scan signal. The display device further includes: a light emission driver for outputting a light emission signal; and inverting drivers, at least some of which output an inverted light emission signal whose phase is inverted with a phase of the light emission signal using the scan signal output from the at least one scan driver and the light emission signal output from the light emission driver. Accordingly, it is possible to prevent a charging delay of the light-emitting element when driven at a low frequency in the variable refresh rate mode, and it is possible to adjust the characteristics and on-bias stress of the driving transistor.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2023 - 0170641, filed on November 30, 2024, and the entire content of the Korean patent application is incorporated herein by reference for all purposes. Technical field

[0003] This application relates to a display device for preventing charging delay when a light - emitting element is driven at a low frequency in a variable refresh rate mode and improving the characteristics and on - bias stress of a driving transistor. Background art

[0004] With the development of the information society, various demands for display devices for displaying images are increasing day by day, and various types of display devices such as liquid crystal display (LCD) devices and organic light - emitting diode (OLED) display devices are utilized.

[0005] The image displayed on the display device may be a static image or a dynamic image, and the dynamic image may include various types such as moving images, game images, and movies. The display device is driven in a variable refresh rate (VRR) mode in which the driving frequency changes according to the type of the image, thereby reducing power consumption and extending the life of the display device. Summary of the invention

[0006] The inventors of the present application have recognized that when a variable refresh rate mode is applied to drive pixels at various refresh rates, a brightness difference is generated between pixels due to different refresh rates, resulting in quality degradation such as image warping or flickering. Various embodiments of the present application address various technical problems including the above - identified problems in the related art.

[0007] For example, some embodiments of the present application aim to provide a display device including a transistor configured to have a gate electrode receiving an inverted light - emitting signal, thereby improving the charge / discharge delay of the light - emitting element, and forming a capacitor between the inverted light - emitting line and a node of the pixel, thereby reducing the on - bias stress of the driving transistor.

[0008] A display device according to an embodiment of the present application includes: a display panel including a display area provided with a pixel circuit and a non-display area near the display area; and a gate driver configured to apply a scan signal, a light emission signal, and an inverted light emission signal to the pixel circuit, wherein the gate driver includes: at least one scan driver configured to output the scan signal; a light emission driver configured to output the light emission signal; and an inversion driver, at least some of the inversion drivers output the inverted light emission signal whose phase is inverted from that of the light emission signal using the scan signal output from the at least one scan driver and the light emission signal output from the light emission driver.

[0009] The technical effects of the present application are not limited to the above effects, and those skilled in the art will be able to clearly understand other effects not mentioned from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram schematically showing a display device according to an embodiment of the present application.

[0011] Figure 2 is a method of driving a display device according to the related art.

[0012] Figure 3 is a diagram showing a method of driving a display device according to an embodiment of the present application.

[0013] Figure 4 is a block diagram showing the configuration of a gate driver in a display device according to an embodiment of the present application.

[0014] Figures 5A to 5D is a circuit diagram of a pixel according to the first embodiment.

[0015] Figure 6 is showing driving Figures 5A to 5D the pixel shown in.

[0016] Figure 7 is a block diagram showing the configuration of a scan driver in a display device according to an embodiment of the present application.

[0017] Figure 8 is a block diagram showing the configuration of a light emission driver in a display device according to an embodiment of the present application.

[0018] Figure 9 is a block diagram showing the configuration of an inverted gate driver in a display device according to an embodiment of the present application.

[0019] Figure 10It is a cross-sectional view showing a stacked form of a display device according to an embodiment of the present application. Detailed Embodiments

[0020] The advantages and features of the present application and methods for implementing them will become clear through the embodiments described in detail below with reference to the accompanying drawings. However, the present application is not limited to the embodiments disclosed below, but can be implemented in various different forms, and these embodiments are provided only to make the disclosure of the present application complete and fully convey it to those skilled in the art to which the present application pertains. Throughout the application, the same reference numerals denote the same components.

[0021] When a first component "is connected to" or "is coupled to" a second component, it includes cases where the first component is directly connected to or coupled to the second component or cases where other components are interposed between them. On the other hand, when a first component "is directly connected to" or "is directly coupled to" a second component, it means that no other components are interposed between them. The term "and / or" includes each recited item and any combination of one or more recited items.

[0022] The terms used in the present application are intended to describe these embodiments and are not intended to limit the present application. In the present application, unless specifically stated in a phrase, the singular form includes the plural form. The terms "comprises" and / or "comprising" used herein mean that the recited components, steps, operations, and / or elements do not exclude the presence or addition of one or more other components, steps, operations, and / or elements.

[0023] Although terms such as "first" and "second" are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are only used to distinguish one component from another.

[0024] Therefore, it goes without saying that within the technical spirit of the present application, the first component described below may be the second component.

[0025] The term "unit" may include any circuit, feature, component, assembly of electronic components, etc. That is to say, a "unit" may include any processor-based or microprocessor-based system, which includes systems using a microcontroller, integrated circuit, chip, microchip, reduced instruction set computer (RISC), application specific integrated circuit (ASIC), field programmable gate array (FPGA), graphics processing unit (GPU), logic circuit, and any other circuit or processor capable of performing the various operations and functions described herein. The above examples are only examples and are not intended to limit the definition or meaning of the term "unit" in any way.

[0026] In some embodiments, the various units described herein may be included in a processing circuit such as a microprocessor, microcontroller, etc. or implemented in other ways.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used in this application can be used with the meanings commonly understood by those skilled in the art to which this application pertains. In addition, terms defined in commonly used dictionaries are not ideally or overly interpreted unless clearly and specifically defined.

[0028] Figure 1 is a block diagram schematically showing a display device according to an embodiment of the present application.

[0029] Referring to Figure 1 , the display device 1 includes a timing controller 10, a gate driver 20, a data driver 30, a power supply unit 40, and a display panel 50.

[0030] The timing controller 10 can receive an image signal RGB and a control signal CS from an external host system or the like. The image signal RGB can include a plurality of grayscale data. The control signal CS can include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a main clock signal.

[0031] The timing controller 10 can process the image signal RGB and the control signal CS according to the operating conditions of the display panel 60, and generate and output image data DATA, a gate driving control signal CONT1, a light emitting driving control signal CONT2, a data driving control signal CONT3, and a power control signal CONT4.

[0032] The gate driver 20 can include a scan driver 20A that generates a scan signal based on the gate driving control signal CONT1 output from the timing controller 10. The scan driver 20A can provide the generated scan signal to the pixel circuit PX through a plurality of gate lines GL1. In one embodiment, one pixel circuit PX can be configured to receive a plurality of scan signals having different waveforms. In an embodiment, the scan driver 20A can provide a plurality of scan signals to the pixel circuit PX through corresponding gate lines GL1 and GL2.

[0033] The gate driver 20 can further include a light emitting driver 20B that generates a light emitting control signal based on the light emitting driving control signal CONT2 output from the timing controller 10. The light emitting driver 20B can provide the generated light emitting control signal to the pixel circuit PX through a light emitting line EL.

[0034] The gate driver 20 can be configured in the form of an in-panel gate mounted on the display panel 50. The gate driver 20 can be disposed on one side of the display panel 50 or can be disposed on both sides of the display panel 50 as shown (e.g., the left side and the right side). Depending on the driving method, panel design method, etc., the gate driver 20 can be disposed on both sides of the display panel 50 as shown (e.g., the left side and the right side), or connected to two or more of the four side surfaces of the display panel 50.

[0035] The data driver 30 can generate data signals based on the image data DATA output from the timing controller 10 and the data driving control signal CONT3. The data driver 30 can provide the generated data signals to the pixel circuits PX through a plurality of data lines DL.

[0036] The power supply unit 40 can generate a high-potential driving voltage VDD and a low-potential driving voltage VSS to be provided to the display panel 50 based on the power control signal CONT4. The power supply unit 40 can provide the generated driving voltages VDD and VSS to the pixel circuits PX through the corresponding voltage lines PL1 and PL2. In addition, the power supply unit 40 can further generate a reference voltage Vref and / or an initialization voltage Vini required for driving the pixel circuits PX, and provide the reference voltage Vref and / or the initialization voltage Vini to the pixel circuits PX through the corresponding voltage lines VrefL and ViniL.

[0037] A plurality of pixel circuits PX (or referred to as "sub-pixel circuits") are provided on the display panel 50. For example, the pixel circuits PX can be arranged in a matrix form on the display panel 50. The pixel circuits PX provided in one pixel row are connected to the same gate lines GL1 and GL2 and the emission line EL, and the pixel circuits PX provided in one pixel column are connected to the same data line DL. The pixel circuits PX can emit light having a brightness corresponding to the gate signals and data signals provided through the gate lines GL1 and GL2 and the data line DL in response to the emission control signal applied through the emission line EL.

[0038] In one embodiment, each pixel circuit PX can display any one of red, green, and blue. In another embodiment, each pixel circuit PX can display any one of cyan, magenta, and yellow. In various embodiments, each pixel circuit PX can display any one of red, green, blue, and white.

[0039] In one embodiment, one or more optical regions OA1 and OA2 may be provided in the display panel 50. The one or more optical regions OA1 and OA2 may be provided to overlap with one or more optoelectronic devices such as a photographing device or a detection sensor, for example, a camera (image sensor) as the photographing device, and a proximity sensor and an illuminance sensor as the detection sensors.

[0040] For the operation of the optoelectronic devices, the one or more optical regions OA1 and OA2 may include a light transmission structure and have a transmittance at or above a selected (in some cases, predetermined) level. The light transmission structure may be formed by patterning a cathode in a portion where the pixel circuit PX is not provided. The cathode may be removed using a laser, or the cathode may be patterned by selectively forming the cathode via a cathode anti-deposition layer.

[0041] Alternatively, the light transmission structure may be formed by separating a light-emitting element from the pixel circuit PX. In an embodiment, the light-emitting element of the pixel circuit PX may be located on the optical regions OA1 and OA2, a plurality of transistors constituting the pixel circuit PX may be provided near the optical regions OA1 and OA2, and the light-emitting element and the pixel may be electrically connected through a transparent metal layer.

[0042] The number of pixel circuits PX per unit area in the one or more optical regions OA1 and OA2 may be less than the number of pixel circuits PX per unit area in the remaining regions other than the optical regions OA1 and OA2. In other words, the resolution of the one or more optical regions OA1 and OA2 may be lower than that of the remaining regions. The timing controller 10, the gate driver 20, the data driver 30, and the power supply unit 40 may be configured as separate integrated circuits (ICs) or an IC integrating at least some of them.

[0043] In one embodiment, the display device 1 may be driven in a variable refresh rate mode in which the drive frequency can be changed. For example, the display device 1 may be driven at a refresh rate higher or lower than a selected (in some cases, predetermined) reference refresh rate. When the display device 1 is driven at a rate lower than the reference refresh rate, it may be referred to as "low-frequency driving", and when the display device 1 is driven at a rate higher than the reference refresh rate, it may be referred to as "high-frequency driving". The refresh rate may be determined according to the type of image to be displayed and the like, but is not limited thereto.

[0044] The timing controller 10 may generate control signals CONT1 to CONT4 so that the pixel circuit PX can be driven at various refresh rates. For example, the timing controller 10 may change the refresh rate by changing the frequency of the clock signal included in the control signals CONT1 to CONT4, adjusting the timing of the horizontal synchronization signal or the vertical synchronization signal, or driving the gate driver 20 in a mask manner.

[0045] Figure 2 is a method for driving a display device according to related art.

[0046] In a variable refresh rate mode, a frame can be configured with a combination of at least one refresh period RP and at least one skip period SP. During the refresh period RP, each pixel circuit PX (see Figure 1 ) can be programmed with a new data voltage, and the light-emitting element of the pixel circuit PX can emit light in response to the programmed data voltage. The refresh period RP can be subdivided into an initialization period, a sampling period, a holding period, etc. for programming the data voltage. The refresh period RP can also be referred to as a "refresh frame".

[0047] During the skip period SP, the process of applying a new data voltage to the pixel circuit PX is omitted. During the skip period SP, the light-emitting element of each pixel circuit PX can emit light in response to the data voltage programmed during the previous refresh period RP. The skip period SP can be referred to as a "skip frame", a "hold frame", etc.

[0048] In one embodiment, in order to change the refresh rate, the length of a frame can be changed by adjusting the number or length of the skip periods SP. Then, the length of the refresh period RP can be sufficiently ensured so that the data voltage is programmed stably.

[0049] In an embodiment, the generation period of the refresh period RP can be changed according to the variable refresh rate. The generation period of the refresh period RP increases as the refresh rate decreases, and the number of skip periods SP between the refresh periods RP increases as the refresh rate decreases.

[0050] For example, the generation period of the refresh period RP can be 120 / 1 seconds at 120 Hz, 60 / 1 seconds at 60 Hz, 24 / 1 seconds at 24 Hz, and 1 / 1 seconds at 1 Hz. The number of skip periods SP between two adjacent refresh periods RP can be 0 at 120 Hz, 1 at 60 Hz, 4 at 24 Hz, and 9 at 1 Hz, and in Figure 2 an example of 24 Hz is shown. However, this embodiment is not limited thereto.

[0051] The refresh period RP includes a programming period PP and a light-emitting period EP. During the programming period PP, a new data voltage is programmed into the pixel circuit PX, and during the light-emitting period EP, the pixel circuit PX emits light in response to the programmed data voltage.

[0052] The skip period SP only includes the light-emitting period EP during which the light-emitting signal EM (see Figure 4 ) has a conductive level. During the light-emitting period EP, the pixel circuit PX maintains the light-emitting brightness of the previous refresh period RP.

[0053] In one embodiment, the length of the emission period EP of the skip period SP may be greater than the length of the emission period EP of the refresh period RP. Therefore, when comparing the integrated luminance amount within a selected (in some cases, predetermined) time, the lower the refresh rate (i.e., the greater the number of skip periods SP), the relatively greater the integrated luminance amount. For example, the integrated luminance amount within a selected (in some cases, predetermined) time is greater at 60 Hz than at 120 Hz, greater at 24 Hz than at 60 Hz, and greater at 1 Hz than at 24 Hz.

[0054] Due to the difference in the integrated luminance amount according to the refresh rate, flicker can be visible when the refresh rate changes.

[0055] Figure 3 is a diagram showing a method of driving a display device according to an embodiment of the present application.

[0056] In one embodiment, during the skip period SP, the anode of the light-emitting element included in the pixel circuit PX (see Figure 1 ) may be reset to a selected (in some cases, predetermined) reset voltage (e.g., an initialization voltage). In an embodiment, the skip period SP may be referred to as an "anode initialization period" or an "anode initialization frame".

[0057] The refresh period RP includes a programming period PP and an emission period EP. During the programming period PP, a new data voltage is programmed into the pixel circuit PX, and during the emission period EP, the pixel circuit PX emits light in response to the programmed data voltage.

[0058] The skip period SP includes an anode initialization period ARP in which the emission signal EM (see Figure 4 ) has a cut-off level, and an emission period EP in which the emission signal EM has a conductive level. During the anode initialization period ARP, a selected (in some cases, predetermined) reset voltage (e.g., an initialization voltage) is applied to the anode of the light-emitting element included in the pixel circuit PX. During the initialization period ARP, the light-emitting element may not emit light due to the reset voltage. During the emission period EP, the pixel circuit PX emits light having the emission luminance of the immediately preceding refresh period RP.

[0059] The length of the anode initialization period ARP may be equal to the length of the programming period PP, so that the integrated luminance amounts of the skip period SP and the refresh period RP are equal to each other. As described above, in an embodiment including the anode initialization period ARP, there is no deviation in the integrated luminance amount according to the refresh rate, and flicker caused by the difference in the integrated luminance amount can be suppressed.

[0060] Figure 4It is a block diagram showing the configuration of a gate driver in a display device according to an embodiment of the present application.

[0061] Referring to Figure 4 , the display panel 50 may include a display area AA for displaying an image and a non-display area NAA near the display area AA that does not display an image.

[0062] An array of pixel circuits PX is provided in the display area AA. At least some of the driving units may be mounted on or connected to the non-display area NAA. For example, in the non-display area NAA, the gate driver 20 may be provided on one or both sides (e.g., the left and right sides) of the display area AA. The gate drivers 20 provided on both sides of the display area AA may be symmetrically configured (in a mirror image form). Hereinafter, the configuration will be described based on the gate driver 20 provided on the left side of the display area AA.

[0063] The gate driver 20 may include first to fourth shift registers 21, 22, 23, and 24. The first shift register 21 and the second shift register 22 may be scan drivers, the third shift register 23 may be a light-emitting driver, and the fourth shift register 24 may be an inverted driver.

[0064] The first shift register 21 and the second shift register 22 are configured to output scan signals. For example, the first shift register 21 may sequentially output a first scan signal S1 through a first gate line GL1, and the second shift register 22 may sequentially output a second scan signal S2 through a second gate line GL2.

[0065] Each of the first shift register 21 and the second shift register 22 may be composed of cascaded circuits connected in a slave manner. Each cascaded circuit may be connected to the corresponding gate lines GL1 and GL2 to output the scan signals S1 and S2 to the gate lines GL1 and GL2.

[0066] The first scan signal S1 and the second scan signal S2 may be used to drive at least one transistor provided in the pixel circuit PX. For example, the first scan signal S1 and the second scan signal S2 may be used to program image data DATA (see Figure 1 ) into the pixel circuit PX, initialize the voltage stored in the pixel circuit PX, or compensate for the characteristics of circuit elements.

[0067] The third shift register 23 and the fourth shift register 24 are configured to output a light-emitting signal and an inverted light-emitting signal. For example, the third shift register 23 may output a light-emitting signal EM through a light-emitting line EL, and the fourth shift register 24 may obtain an inverted light-emitting signal from a first inverting unit 241 (also referred to as a first inverting circuit 241; see Figure 9)Output an inverted signal having a phase inverted with respect to the light emission signal EM, and when at least one of the inverted signal generated from the first inverter unit 241 or the scan signal S2 output from the second shift register 22 has a conductive level, the second inverter unit 242 (also referred to as the second inverter circuit 242; see Figure 9 ) can output the second gate low voltage VEL as an inverted light emission signal IEM through the inverted light emission line IEL. In an embodiment, the fourth shift register 24 can be configured to receive the scan signal S2 output from the second shift register 22 and the light emission signal EM output from the third shift register 23, and is configured to generate and output an inverted light emission signal IEM by setting at least one circuit element for inverting the phase of the input light emission signal EM.

[0068] The light emission signal EM and the inverted light emission signal IEM can be used to drive at least one transistor provided in the pixel circuit PX. For example, the light emission signal EM can be used to change or control the light emission time of the pixel circuit PX.

[0069] In the illustrated embodiment, the first shift register 21 and the second shift register 22 can be arranged close to the display area AA, and the third shift register 23 can be arranged relatively far from the display area AA. In addition, the fourth shift register 24 that outputs the inverted light emission signal IEM can be arranged relatively closer to the display area AA compared to the third shift register 23 to receive the scan signal S2 output from the second shift register 22 to the pixel circuit PX and receive the light emission signal EM output from the third shift register 23 to the pixel circuit PX.

[0070] However, the arrangement of the shift registers 21, 22, 23, and 24 is not limited to that shown. According to the specifications of the display panel 50, the arrangement of the shift registers 21, 22, 23, and 24 can be variously changed within a possible range to reduce the size of the non-display area NAA and reduce the length and amount of the lines.

[0071] In addition, although not shown, the voltage lines VrefL and ViniL that provide the reference voltage Vref and / or the initialization voltage Vini can be arranged between the gate driver 20 and the display area AA.

[0072] The voltage lines VrefL and ViniL can be arranged adjacent to the display area AA in the order of the initialization voltage line ViniL and the reference voltage line VrefL. Alternatively, the voltage lines VrefL and ViniL can be arranged adjacent to the display area AA in the order of the reference voltage line VrefL and the initialization voltage line ViniL.

[0073] The voltage lines VrefL and ViniL may be symmetrically arranged on both sides of the display area AA. The voltage lines VrefL and ViniL are not limited thereto, and may be located only on one of the left and right sides, and even when located on one side, the position on the left or right side is not limited.

[0074] The voltage lines VrefL and ViniL may be branched respectively to supply the reference voltage Vref and the initialization voltage Vini of the DC voltage from the power supply unit 40 to the pixel circuit PX.

[0075] The voltage lines VrefL and ViniL may be made of the same material in the same layer as the source or drain electrode 140, and may also be made of the same material in the same layer as the connection electrode 155.

[0076] At least some of the voltage lines branched from the voltage lines VrefL and ViniL and connected to the pixel circuit PX may be made of the same material in the same layer as the gate electrodes 125 and 126, or at least some of the voltage lines may be made of the same material in the same layer as the touch electrodes 194, 195 and 196, or made of the same material in the same layer as the semiconductor layers 115 and 116.

[0077] Figures 5A to 5D is a circuit diagram of a pixel according to the first embodiment. In Figures 5A to 5D For the sake of easy description, as an example, pixels connected to the nth pixel row (n is an integer greater than 0) are shown.

[0078] Refer to Figure 5A and Figure 5B According to an embodiment, the pixel circuit PX may include: a driving transistor DT, a light emitting element LD connected to the driving transistor DT, and a control circuit for controlling the amount of driving current applied to the light emitting element LD through the driving transistor DT. For example, the control circuit may include a first transistor T1 to a fifth transistor T5, and a first capacitor C1 and a second capacitor C2.

[0079] The first electrode of the driving transistor DT is formed to receive a high potential driving voltage VDD (connected to the high potential driving voltage line PL1), and the second electrode of the driving transistor DT is connected to the third node N3. The gate electrode of the driving transistor DT is connected to the second node N2. The driving transistor DT may be turned on according to the voltage applied to the second node N2 to control the amount of driving current flowing to the light emitting element LD.

[0080] The first electrode of the first transistor T1 is connected to the data line DL, and the second electrode of the first transistor T1 is connected to the first node N1. The gate electrode of the first transistor T1 can be connected to the first gate line GL1 to receive the first scan signal S1. The first transistor T1 can be turned on according to the first scan signal S1 applied to the first gate line GL1 to transfer the data voltage Vdata applied to the data line DL to the first node N1. The first transistor T1 can be referred to as the "first switching transistor".

[0081] The first capacitor C1 is connected between the first node N1 and the second node N2. The first capacitor C1 can store a voltage corresponding to the voltage difference between the first node N1 and the second node N2. For example, the first capacitor C1 can store a voltage corresponding to the difference between the data voltage Vdata applied to the data line DL and the voltage of the second node N2, and hold the stored voltage for one frame period, so as to stabilize the voltage of the gate electrode (i.e., the second node N2) of the driving transistor DT. The first capacitor C1 can be referred to as the "storage capacitor".

[0082] The second transistor T2 is connected between the second node N2 and the third node N3. The gate electrode of the second transistor T2 can be connected to the second gate line GL2 to receive the second scan signal S2. The second transistor T2 can be turned on according to the second scan signal S2 applied to the second gate line GL2 to electrically connect the gate electrode (the second node N2) of the driving transistor DT to the second electrode (the third node N3). The second transistor T2 can be referred to as the "second switching transistor".

[0083] The first electrode of the third transistor T3 is formed to receive the reference voltage Vref (connected to the reference voltage line Vref1), and the second electrode of the third transistor T3 is connected to the first node N1. The gate electrode of the third transistor T3 can be connected to the emission line EL to receive the emission signal EM. The third transistor T3 can be turned on according to the emission signal EM applied to the emission line EL to transfer the reference voltage Vref to the first node N1. The third transistor T3 can be referred to as the "third switching transistor".

[0084] The fourth transistor T4 is connected between the third node N3 and the fourth node N4. The gate electrode of the fourth transistor T4 can be connected to the emission line EL to receive the emission signal EM. The fourth transistor T4 can be turned on according to the emission signal EM applied to the emission line EL to electrically connect the driving transistor DT (the third node N3) to the light-emitting element LD (the fourth node N4). The fourth transistor T4 can be referred to as the "light-emitting transistor".

[0085] The first electrode of the fifth transistor T5 is formed to receive the initialization voltage Vini, and the second electrode of the fifth transistor T5 is connected to the fourth node N4. The gate electrode of the fifth transistor T5 may be connected to the inverted emission line IEL to receive the inverted emission signal IEM. The fifth transistor T5 may be turned on according to the inverted emission signal IEM applied to the inverted emission line IEL to apply the initialization voltage Vini to the anode (the fourth node N4) of the light-emitting element LD. The fifth transistor T5 may be referred to as an "initialization transistor".

[0086] The second capacitor C2 is connected between the inverted emission line IEL and the second node N2. When the inverted emission signal IEM is applied to the inverted emission line IEL, the second capacitor C2 may be formed to transmit the coupling voltage to the second node N2. The second capacitor C2 may be referred to as a "coupling capacitor".

[0087] The anode of the light-emitting element LD may be connected to the fourth node N4, and the cathode of the light-emitting element LD may be connected to the low-potential driving voltage VSS. When the driving transistor DT and the fourth transistor T4 are turned on, a current path may be formed between the high-potential driving voltage VDD and the low-potential driving voltage VSS to allow the driving current to flow to the light-emitting element LD. The light-emitting element LD may emit light having a brightness corresponding to the amount of the applied driving current.

[0088] Compared with Figure 5A the embodiment of Figure 5B Referring to

[0089] In the illustrated embodiment, the second transistor T2 is formed of two switching transistors T21 and T22, but the embodiment is not limited thereto. In another embodiment, the second transistor T2 may be formed of a larger number of sub-transistors.

[0090] Referring to Figure 5C a second capacitor C2' is connected between the inverted emission line IEL and the first node N1. When the inverted emission signal IEM is applied to the inverted emission line IEL, the second capacitor C2' may be formed to transmit the coupling voltage to the first node N1. The second capacitor C2' is referred to as a "coupling capacitor".

[0091] Referring to Figure 5D, the voltage line ViniL can be formed to apply the same initialization voltage Vini to the first electrode of the third transistor T3 and the first electrode of the fifth transistor T5.

[0092] In Figures 5A to 5D the embodiment shown in

[0093] the pixel circuit PX includes low-temperature polycrystalline silicon (LTPS) thin film transistors.

[0094] The LTPS thin film transistors include gate electrodes, source electrodes, and drain electrodes. The LTPS thin film transistors have an active layer made of polycrystalline silicon. The LTPS thin film transistors can be formed as p-type thin film transistors or n-type thin film transistors. The LTPS thin film transistors have a high electron mobility and thus have fast driving characteristics.

[0095] However, this embodiment is not limited thereto. In another embodiment, at least one of the transistors DT and T1 to T6 can be formed as an oxide semiconductor thin film transistor.

[0096] Figure 6 is a diagram showing a method of driving Figures 5A to 5D the pixel shown in

[0097] Referring to Figure 6 and Figures 5A to 5D , in the variable refresh rate mode, 1 frame can be configured as a combination of at least one refresh period RP and at least one skip period SP.

[0098] The refresh period RP can include an initialization period t1, a sampling period t2, a holding period t3, and a light emission period t4.

[0099] During the initialization period t1, the second scan signal S2 at the conductive level is further applied to turn on the second transistor T2. In addition, during the initialization period t1, the light emission signal EM at the conductive level is applied to turn on the third transistor T3 and the fourth transistor T4. Therefore, during the initialization period t1, the reference voltage Vref is applied to the first node N1, and the initialization voltage Vini is applied to the fourth node N4 and the third node N3.

[0100] When the second transistor T2 is turned on, the voltage at the third node N3 can be transferred to the second node N2. Therefore, the initial voltage at the second node N2 can correspond to the initialization voltage Vini. During the initialization period t1, the first capacitor C1 can be gradually charged to a voltage corresponding to the difference between the reference voltage Vref and the initialization voltage Vini. In addition, during the initialization period t1, in response to the charging voltage of the first capacitor C1, the voltage at the second node N2 can gradually reach a voltage corresponding to the difference between the reference voltage Vref and the initialization voltage Vini.

[0101] In addition, during the initialization period t1, in response to the voltage at the fourth node N4, the anode of the light-emitting element LD can be initialized to the initialization voltage Vini.

[0102] During the sampling period t2, the first scan signal S1 at the conductive level is further applied to turn on the first transistor T1. In addition, during the sampling period t2, the light-emitting signal EM can be switched to the cut-off level to turn off the third transistor T3 and the fourth transistor T4. On the contrary, during the sampling period t2, the inverted light-emitting signal IEM is switched to the conductive level. Then, the fifth transistor T5 can be turned on in response to the inverted light-emitting signal IEM at the conductive level. Therefore, during the sampling period t2, the data voltage Vdata applied to the data line DL is applied to the first node N1, and the initialization voltage Vini is applied to the fourth node N4.

[0103] During the sampling period t2, the first capacitor C1 can be gradually charged to a voltage corresponding to the difference between the data voltage, the reference voltage Vref, and the initialization voltage Vini. In addition, during the sampling period t2, in response to the charging voltage of the first capacitor C1, the voltage at the second node N2 can gradually reach a voltage corresponding to the difference between the data voltage Vdata, the reference voltage Vref, and the initialization voltage Vini.

[0104] When the charging voltage of the first capacitor C1 is transferred to the gate electrode of the driving transistor DT, the source-gate voltage of the driving transistor DT is higher than the threshold voltage Vth, so the driving transistor DT can be turned on. At this time, the source-gate current of the driving transistor DT can be determined according to the data voltage Vdata, the reference voltage Vref, the initialization voltage Vini, and the threshold voltage of the driving transistor DT.

[0105] The driving transistor DT can supply a source-drain current to the third node N3 until the source-gate voltage reaches the threshold voltage of the driving transistor DT. In addition, the second transistor T2 can supply the voltage at the third node N3 to the second node N2. In this way, while the driving transistor DT is turned on, the voltage at the second node N2 and the source-drain current of the driving transistor DT can change, and the voltage at the second node N2 can ultimately converge to a voltage corresponding to the difference between the data voltage Vdata and the threshold voltage Vth of the driving transistor DT.

[0106] In addition, during the sampling period t2, since the initialization voltage Vini is applied to the fourth node N4 through the fifth transistor T5, the anode of the light-emitting element LD can maintain the initialization voltage Vini in response to the voltage at the fourth node N4.

[0107] During the holding period t3, the first scan signal S1 and the second scan signal S1 are switched to the cut-off level to turn off the first transistor T1 and the second transistor T2. During the holding period t3, the voltage at the second node N2 can be stably held by the first capacitor C1.

[0108] During the light-emitting period t4, the light-emitting signal EM at the conduction level is applied to turn on the third transistor T3 and the fourth transistor T4. During the light-emitting period t4, a current path is formed from the high-potential driving voltage VDD through the driving transistor DT to the light-emitting element LD. Therefore, a driving current having a magnitude corresponding to the voltage programmed into the driving transistor DT can flow along the current path to cause the light-emitting element LD to emit light with a corresponding brightness.

[0109] The skip period SP can include an anode initialization period t5 and a light-emitting period t6.

[0110] During the anode initialization period t5, the light-emitting signal EM can be switched to the cut-off level to turn off the third transistor T3 and the fourth transistor T4. Instead, during the anode initialization period t5, the inverted light-emitting signal IEM is switched to the conduction level. Then, the fifth transistor T5 can be turned on in response to the inverted light-emitting signal IEM at the conduction level. Therefore, during the anode initialization period t5, the initialization voltage Vini is applied to the fourth node N4.

[0111] During the anode initialization period t5, due to the initialization voltage Vini applied to the anode of the light-emitting element LD, the light-emitting element LD does not emit light. Instead, the voltage of the gate electrode of the driving transistor DT can be held at the voltage programmed during the previous refresh period RP through the first capacitor C1.

[0112] During the anode initialization period t5, when an inverted emission signal IEM is applied to the inverted emission line IEL, a parasitic capacitance (coupling voltage) can be generated in the second capacitor C2. Therefore, the voltage at the second node N2 can be reduced (kickback) by a selected (in some cases, predetermined) level Δ. When the source voltage of the driving transistor DT is held, the reduction in the voltage at the second node N2 increases the source-gate voltage of the driving transistor DT. Therefore, the driving transistor DT can remain in the on state during the anode initialization period t5, and the hysteresis of the driving transistor DT can be reduced.

[0113] In this case, in the case of the pixel circuit PX of Figure 5C , since one end of the second capacitor C2' is connected to the first node N1 instead of the second node N2, the voltage at the first node N1 can be reduced (kickback) by a selected (in some cases, predetermined) level Δ, and the source-gate voltage of the driving transistor DT can increase according to the change in the voltage at the first node N1.

[0114] In addition, during the anode initialization period t5 before the emission period t6, since the initialization voltage Vini is directly applied to the anode of the light-emitting element LD, the voltage of the anode can be discharged at a relatively fast rate, thereby minimizing the charging delay of the light-emitting element LD. Through anode initialization, no deviation in the luminance integration amount according to the refresh rate occurs, and flicker caused by differences in the luminance integration amount can be suppressed.

[0115] During the emission period t6, an emission signal EM at a conductive level is applied to turn on the third transistor T3 and the fourth transistor T4. During the emission period t4, the light-emitting element LD can emit light having a luminance corresponding to the voltage programmed during the previous refresh period RP.

[0116] In addition, during the anode initialization period t5 before the emission period t6, the anode of the light-emitting element LD is charged to the initialization voltage Vini. Therefore, during the emission period t6, the luminance of the light-emitting element LD can reach the target luminance faster, thereby minimizing the charging delay of the light-emitting element LD. Specifically, since the initialization voltage Vini can be separated from the reference voltage Vref and supplied to the anode of the light-emitting element LD, the voltage level of the initialization voltage Vini can be independently adjusted, and the charging and discharging delay timings of the light-emitting element LD can be effectively controlled.

[0117] Figure 7 is a block diagram showing the configuration of a scan driver in a display device according to an embodiment of the present application.

[0118] Referring to Figure 7, the first shift register 21 and / or the second shift register 22 operating as a scan driver may include 1-1 transistors T11 to 1-8 transistors T18, 1-1 capacitor CQ1, and 1-2 capacitor CQB1.

[0119] In this application, the transistors included in the first shift register 21 and / or the second shift register 22 may be implemented as p-type thin film transistors, but are not limited thereto.

[0120] The gate electrode of the 1-1 transistor T11 is connected to the input terminal of the scan start signal VST, the first electrode of the 1-1 transistor T11 is connected to the input terminal of the first gate low voltage VGL, and the second electrode of the 1-1 transistor T11 is connected to the 1-2 transistor T12 switched by the (n-1)th scan clock signal CLK(n-1).

[0121] The gate electrode of the 1-2 transistor T12 is connected to the input terminal of the (n-1)th scan clock signal CLK(n-1), the first electrode of the 1-2 transistor T12 is connected to the second electrode of the 1-1 transistor T11, and the second electrode of the 1-2 transistor T12 is connected to the Q1 node.

[0122] The gate electrode of the 1-3 transistor T13 is connected to the QB1 node, the first electrode of the 1-3 transistor T13 is connected to the Q1 node and the second electrode of the 1-2 transistor T12, and the second electrode of the 1-3 transistor T13 is connected to the input terminal of the first gate high voltage VGH.

[0123] The 1-1 transistor T11, the 1-2 transistor T12, and the 1-3 transistor T13 activate or deactivate the Q1 node. When both the 1-1 transistor T11 and the 1-2 transistor T12 are turned on, the Q1 node is activated to the first gate low voltage VGL. The 1-2 transistor T12 is turned on according to the (n-1)th scan clock signal CLK(n-1) whose phase is earlier than the phase of the nth scan clock signal CLK(n) to activate the Q1 node to the first gate low voltage VGL. In addition, the 1-1 transistor T11 is turned on according to the scan start signal VST synchronized with the (n-1)th scan clock signal CLK(n-1) to activate the Q1 node to the first gate low voltage VGL.

[0124] The gate electrode of the 1-4 transistor T14 is connected to the input terminal of the (n+2)th scan clock signal CLK(n+2) whose phase is later than the phase of the nth scan clock signal CLK(n), the first electrode of the 1-4 transistor T14 is connected to the input terminal of the first gate low voltage VGL, and the second electrode of the 1-4 transistor T14 is connected to the QB1 node.

[0125] The gate electrode of the 1-5 transistor T15 is connected to the input terminal of the scan start signal VST, the first electrode of the 1-5 transistor T15 is connected to the QB1 node, and the second electrode of the 1-5 transistor T15 is connected to the input terminal of the first gate high voltage VGH.

[0126] The 1-4 transistor T14 is turned on according to the (n + 2)th scan clock signal CLK(n + 2) to activate the QB1 node to the first gate low voltage VGL. The 1-5 transistor T15 is turned on according to the scan start signal VST to inactivate the QB1 node to the first gate high voltage VGH.

[0127] The gate electrode of the 1-6 transistor T16 is connected to the Q1 node, the first electrode of the 1-6 transistor T16 is connected to the input terminal of the nth scan clock signal CLK(n), and the second electrode of the 1-6 transistor T16 is connected to the output terminal SCO of the scan driver. The 1-6 transistor T16 is a pull-up transistor that outputs the scan signals S1 and S2 of the first gate low voltage VGL to the output terminal SCO of the scan driver when the potential at the Q1 node rises according to the nth scan clock signal CLK(n).

[0128] The gate electrode of the 1-7 transistor T17 is connected to the QB1 node, the first electrode is connected to the output terminal SCO of the scan driver, and the second electrode is connected to the input terminal of the first gate high voltage VGH. The 1-7 transistor T17 is a pull-down transistor that outputs the scan signals S1 and S2 of the first gate high voltage VGH to the output terminal SCO of the scan driver when the QB1 node is activated.

[0129] The gate electrode of the 1-8 transistor T18 is switched through the Q1 node, the first electrode of the 1-8 transistor T18 is connected to the QB1 node, and the second electrode of the 1-8 transistor T18 is connected to the input terminal of the first gate high voltage VGH.

[0130] Instead, the 1-8 transistor T18 controls the potential at the Q1 node and the potential at the QB1 node, and when the Q1 node is activated to the first gate low voltage VGL, the QB1 node is inactivated to the first gate high voltage VGH. When the 1-8 transistor T18 is turned off, the QB1 node is activated to the first gate low voltage VGL.

[0131] Since the QB1 node should remain active for a relatively long time in a frame, the first shift register 21 and / or the second shift register 22 according to an embodiment of the present application may further include 1-2 capacitors CQB1. One end of the 1-2 capacitors CQB1 is connected to the contact points of the 1-5 transistor T15 and the 1-8 transistor T18 and the QB1 node, and the other end of the 1-2 capacitors CQB1 is connected to the contact points of the 1-5 transistor T15 and the 1-8 transistor T18 and the input terminal of the first gate high voltage VGH. The 1-2 capacitor QB1 can be a stabilizing capacitor.

[0132] The 1-1 capacitor CQ1 is connected between the Q1 node and the output terminal SCO of the scan driver. When the nth scan clock signal CLK(n) decreases to the first gate low voltage VGL, due to the coupling effect of the 1-1 capacitor CQ1, the potential of the Q1 node decreases to a boosted level lower than the first gate low voltage VGL. Due to this bootstrap, the potential of the output terminal SCO of the scan driver rapidly decreases to the first gate low voltage VGL. Using the bootstrap effect, the scan signals S1 and S2 of the first gate low voltage VGL can be quickly output without distortion or delay. In other words, the 1-1 capacitor CQ1 can be a bootstrap capacitor.

[0133] As Figure 7 shown, the 1-3 transistor T13, the 1-5 transistor T15, and the 1-8 transistor T18 can each be designed with a double-gate structure to suppress the leakage current during cutoff. In the double-gate structure, the two gate electrodes are connected to have the same potential, and the channel length is greater than that of the single-gate structure. Since the channel length increases, the resistance increases, so the leakage current decreases during cutoff, thus ensuring the operation stability.

[0134] Figure 8 is a block diagram showing the configuration of a light-emitting driver in a display device according to an embodiment of the present application.

[0135] Referring to Figure 8 , the third shift register 23 operating as a light-emitting driver may include 2-1 transistors T21 to 2-10 transistors T30, and 2-1 capacitors CQ2 to 2-3 capacitors CQ'2.

[0136] The 2-1 transistors T21 to 2-10 transistors T30 included in the third shift register 23 can be implemented as p-type thin-film transistors, but are not limited thereto. The 2-1 transistors T21 to 2-10 transistors T30 implemented as p-type thin-film transistors are turned on under the condition of being applied with a low voltage and turned off under the condition of being applied with a high voltage.

[0137] The 2-1 transistor T21 has a gate electrode connected to the input terminal of the second emission clock signal ECLK2, a first electrode connected to the input terminal of the emission start signal EVST, and a second electrode connected to the first electrode of the 2-2 transistor T22 and the Q2 node. The 2-1 transistor T21 is turned on or off in response to the second emission clock signal ECLK2.

[0138] The 2-2 transistor T22 has a gate electrode connected to the input terminal of the first emission clock signal ECLK1, a first electrode connected to the second electrode of the 2-1 transistor T21 and the Q2 node, and a second electrode connected to the first node of the 2-3 transistor T23. The 2-2 transistor T22 is turned on or off in response to the first emission clock signal ECLK1.

[0139] The 2-3 transistor T23 has a gate electrode connected to the second electrode of the 2-4 transistor T24, a first electrode connected to the second electrode of the 2-2 transistor T22, and a second electrode connected to the input terminal of the second gate high voltage VEH. When the 2-4 transistor T24 is turned on, the 2-3 transistor T23 is turned on in response to the second gate low voltage VEL.

[0140] The 2-4 transistor T24 has a gate electrode connected to the second emission clock signal ECLK2, a first electrode connected to the input terminal of the second gate low voltage VEL, and a second electrode connected to the gate electrode of the 2-3 transistor T23. The 2-4 transistor T24 is turned on or off in response to the second emission clock signal ECLK2. The 2-4 transistor T24 is turned on or off simultaneously with the 2-1 transistor T21.

[0141] The 2-5 transistor T25 has a gate electrode connected to the Q2 node, a first electrode connected to the second electrode of the 2-9 transistor T29, and a second electrode connected to the input terminal of the second gate high voltage VEH. The 2-5 transistor T25 is turned on or off in response to the potential at the Q2 node.

[0142] The 2-6 transistor T26 has a gate electrode connected to the Q2 node and one end of the 2-1 capacitor CQ2, a first electrode connected to the input terminal of the second gate low voltage VEL, and a second electrode connected to the output terminal EMO of the emission driver. The 2-6 transistor T26 is turned on or off in response to the potential of the Q2 node.

[0143] The 2-7 transistor T27 has a gate electrode connected to the QB2 node, a first electrode connected to the output terminal EMO of the emission driver, and a second electrode connected to the input terminal of the second gate high voltage VEH. The 2-7 transistor T27 is turned on or off in response to the potential at the QB2 node.

[0144] The 2-8 transistor T28 has a gate electrode connected to the Q'2 node, a first electrode connected to the input terminal of the first light-emitting clock signal ECLK1, and a second electrode connected to the first electrode of the 2-9 transistor T29. The 2-8 transistor T28 is turned on or off in response to the potential at the Q'2 node.

[0145] The 2-9 transistor T29 has a gate electrode connected to the input terminal of the first light-emitting clock signal ECLK1, a first electrode connected to the second electrode of the 2-8 transistor T28, and a second electrode connected to the first electrode of the 2-5 transistor T25 and the QB2 node. The 2-9 transistor T29 is turned on or off in response to the first light-emitting clock signal ECLK1.

[0146] The 2-10 transistor T30 has a gate electrode connected to the Q2 node, a first electrode connected to the input terminal of the second light-emitting clock signal ECLK2, and a second electrode connected to the Q'2 node. The 2-10 transistor T30 is turned on or off in response to the potential at the Q2 node.

[0147] One end of the 2-1 capacitor CQ2 is connected to the Q2 node and the other end is connected to the input terminal of the first light-emitting clock signal ECLK1. One end of the 2-2 capacitor CQ'2 is connected to the Q'2 node and the other end is connected to the second electrode of the 2-8 transistor T28. One end of the 2-3 capacitor CQB2 is connected to the QB2 node and the other end is connected to the input terminal of the second gate high voltage VEH.

[0148] The 2-1 capacitor CQ2 and the 2-2 capacitor CQ2 can be used as bootstrap capacitors, and the 2-3 capacitor CQB2 can be used as a stabilizing capacitor.

[0149] In addition, the 2-1 capacitor CQ2 or the 2-2 capacitor CQ2 can be designed to have a larger capacitance than the 2-3 capacitor CQB2. In other words, the 2-1 capacitor CQ2 or the 2-2 capacitor CQ'2 can have a larger area than the 2-3 capacitor CQB2.

[0150] The transistors included in the third shift register 23 are shown as single-gate structures, but are not limited thereto. The 2-1 transistor T21 to the 2-5 transistor T25, the 2-8 transistor T28 to the 2-10 transistor T30 except for the 2-6 transistor T26 and the 2-7 transistor T27 can be implemented as double-gate structures to prevent leakage current and improve driving reliability. In addition, some transistors can be formed as double-gate structures and other transistors can be formed as single-gate structures.

[0151] Figure 9 is a block diagram showing the configuration of an inverting gate driver in a display device according to an embodiment of the present application.

[0152] Reference Figure 9 As shown in Figure 9 , the fourth shift register 24 that operates as an inverting driver may include transistors T31 to T43 of 3-1, and capacitors CQ3 to CQ'3 of 3-1 to 3-4.

[0153] The transistors T31 to T43 of 3-1 included in the fourth shift register 24 may be implemented as p-type thin film transistors, but are not limited thereto. The transistors T31 to T43 of 3-1 implemented as p-type thin film transistors are turned on under the condition of being applied with a low voltage and turned off under the condition of being applied with a high voltage.

[0154] In the fourth shift register 24 formed by the transistors T31 to T43 of 3-1, the transistors T31 to T40 of 3-1 may be included in the first inverting unit 241. In addition, the transistors T41 to T43 of 3-11 may be included in the second inverting unit 242.

[0155] The transistor T31 of 3-1 has a gate electrode connected to the input terminal of the first emission clock signal ECLK1, a first electrode connected to the input terminal of the emission signal EM output from the third shift register 23, and a second electrode connected to the node QB3. The transistor T31 of 3-1 is turned on or off in response to the first emission clock signal ECLK1.

[0156] The transistor T32 of 3-2 has a gate electrode connected to the input terminal of the first emission clock signal ECLK1, a first electrode connected to the second electrode of the transistor T31 of 3-1, and a second electrode connected to the first electrode of the transistor T33 of 3-3. The transistor T32 of 3-2 is turned on or off in response to the first emission clock signal ECLK1. The transistor T32 of 3-2 is turned on or off simultaneously with the transistor T31 of 3-1.

[0157] The transistor T33 of 3-3 has a gate electrode connected to the second electrode of the transistor T34 of 3-4, a first electrode connected to the second electrode of the transistor T32 of 3-2, and a second electrode connected to the input terminal of the second gate high voltage VEH. When the transistor T34 of 3-4 is turned on, the transistor T33 of 3-3 is turned on in response to the second gate low voltage VEL.

[0158] The transistor T34 of 3-4 has a gate electrode connected to the input terminal of the second emission clock signal ECLK2, a first electrode connected to the input terminal of the second gate low voltage VEL, and a second electrode connected to the first electrode of the transistor T33 of 3-3. The transistor T34 of 3-4 is turned on or off in response to the second emission clock signal ECLK2.

[0159] The 3-5 transistor T35 has a gate electrode connected to the QB3 node and the second electrode of the 3-1 transistor T31, a first electrode connected to the Q3 node and the second electrode of the 3-9 transistor T39, and a second electrode connected to the input terminal of the second gate high voltage VEH. The 3-5 transistor T35 conducts or cuts off in response to the potential at the QB3 node.

[0160] The 3-6 transistor T36 has a gate electrode connected to the Q3 node and one end of the 3-1 capacitor CQ3, a first electrode connected to the input terminal of the second gate low voltage VEL, and a second electrode connected to the INV node. The 3-6 transistor T36 conducts or cuts off in response to the potential at the Q3 node.

[0161] The 3-7 transistor T37 has a gate electrode connected to the QB3 node, a first electrode connected to the second electrode of the 3-6 transistor T36, and a second electrode connected to the input terminal of the second gate high voltage VEH. The 3-7 transistor T37 conducts or cuts off in response to the potential of the QB3 node.

[0162] The 3-8 transistor T38 has a gate electrode connected to the Q'3 node, a first electrode connected to the input terminal of the first light emission clock signal ECLK1, and a second electrode connected to the first electrode of the 3-9 transistor T39. The 3-8 transistor T38 conducts or cuts off in response to the potential at the Q'3 node.

[0163] The 3-9 transistor T39 has a gate electrode connected to the input terminal of the first light emission clock signal ECLK1, a first electrode connected to the second electrode of the 3-8 transistor T38, and a second electrode connected to the first electrode of the 3-5 transistor T35 and the Q3 node. The 3-9 transistor T39 conducts or cuts off in response to the first light emission clock signal ECLK1.

[0164] The 3-10 transistor T40 has a gate electrode connected to the input terminal of the light emission signal EM output from the third shift register 23, a first electrode connected to the input terminal of the second light emission clock signal ECLK2, and a second electrode connected to the Q'3 node. The 3-10 transistor T40 conducts or cuts off in response to the light emission signal EM.

[0165] One end of the 3-1 capacitor CQ3 is connected to the Q3 node and the other end is connected to the INV node. One end of the 3-2 capacitor CQ'3 is connected to the Q'3 node and the other end is connected to the second electrode of the 3-8 transistor T38. Although not shown in the figure, if necessary, a 3-3 capacitor CQB3 can be further included between the QB2 node and the input terminal of the second gate high voltage VEH.

[0166] The 3-1 capacitor CQ3 and the 3-2 capacitor CQ3 can be used as bootstrap capacitors. In addition, the 3-1 capacitor CQ3 can be designed to have a larger capacitance than the 3-2 capacitor CQ3. In other words, the 3-1 capacitor CQ3 can have a larger area than the 3-2 capacitor CQ3.

[0167] The fourth shift register 24 can generate an inverted signal whose phase is inverted from the phase of the light emission signal EM output from the third shift register 23 through the operations of the 3-1 transistor T31 and the 3-10 transistor T40 included in the first inverter unit 241.

[0168] The 3-11 transistor T41 has a gate electrode connected to the INV node, a first electrode connected to the OR node, and a second electrode connected to the input terminal of the second gate high voltage VEH. The 3-11 transistor T41 conducts or cuts off in response to the inverted signal having an inverted phase of the light emission signal EM generated in the first inverter unit 241.

[0169] The 3-12 transistor T42 has a gate electrode connected to the input terminal of the second scan signal S2 output from the second shift register 22, a first electrode connected to the OR node, and a second electrode connected to the input terminal of the second gate high voltage VEH. The 3-12 transistor T42 conducts or cuts off in response to the second scan signal S2.

[0170] The 3-13 transistor T43 has a gate electrode connected to the OR node, a first electrode connected to the output terminal IEMO of the inverter driver, and a second electrode connected to the input terminal of the second gate high voltage VEH. The 3-13 transistor T43 conducts or cuts off in response to the potential of the OR node.

[0171] One end of the first resistor R1 is connected to the first electrode of the 3-11 transistor T41 and the other end is connected to the input terminal of the second gate low voltage VEL. One end of the second resistor R2 is connected to the input terminal of the second gate low voltage VEL and the other end is connected to the output terminal IEMO of the inverter driver.

[0172] The fourth shift register 24 is configured to receive an inverted signal whose phase is inverted from the phase of the light emission signal EM output from the third shift register 23 and the scan signal S2 output from the second shift register 22 through the operations of the 3-11 transistor T41 and the 3-12 transistor T42 included in the second inverter unit 242.

[0173] When at least one of an anti-phase signal whose phase is inverted from that of the light-emission signal EM and the scan signal S2 is at a conductive level, the 3-11 transistor T41 or the 3-12 transistor T42 can be turned on, the second gate high voltage VEH can be applied to the gate electrode of the 3-13 transistor T43, and the 3-13 transistor T43 can be turned off to output the second gate low voltage VEL as an inverted light-emission signal IEM.

[0174] In addition, when an anti-phase signal whose phase is inverted from that of the light-emission signal EM and the scan signal S2 are at a cut-off level, the 3-11 transistor T41 or the 3-12 transistor T42 can be turned off, the 3-13 transistor T43 can be turned on, and the second gate high voltage VEH can be output as the inverted light-emission signal IEM.

[0175] The transistors included in the fourth shift register 24 are shown implemented as a single-gate structure, but are not limited thereto. The 3-1 transistor T31 to the 3-5 transistor T35, and the 3-8 transistor T38 to the 3-10 transistor T40 other than the 3-6 transistor T36, the 3-7 transistor T37, and the 3-11 transistor T41 to the 3-13 transistor T43 can be implemented as a double-gate structure to prevent current leakage and improve driving reliability. In addition, some transistors can be formed in a double-gate structure, and other transistors can be formed in a single-gate structure.

[0176] Figure 10 is a cross-sectional view showing a stacked form of a display device according to an embodiment of the present application.

[0177] Referring to Figure 10 , a thin-film transistor TFT for driving a light-emitting element LD can be provided on a substrate 101 in a display area AA. In Figure 10 , for ease of description, only the driving transistor DT (see Figure 7 ) among various thin-film transistors that can be included in the display device 1 is shown, but the thin-film transistor TFT is not limited thereto. Hereinafter, although an example in which the thin-film transistor TFT has a coplanar structure will be described, the thin-film transistor TFT can be implemented as any one of various other structures such as a staggered structure.

[0178] The driving transistor DT can control the current supplied from the high-potential driving voltage VDD to the light-emitting element LD in response to a data signal provided to the gate electrode 125. Therefore, the driving transistor DT can control the amount of light emitted from the light-emitting element LD. In this case, a constant current can be supplied to the light-emitting element LD until through a storage capacitor (for example, Figure 7The voltage charged in the first capacitor C1) provides the data signal for the next frame, so that the light-emitting state of the light-emitting element LD can be maintained. The high-potential driving voltage line PL1 that provides the high-potential driving voltage VDD (see Figure 1 ) can be formed parallel to the data line DL (see Figure 1 ).

[0179] The thin-film transistor TFT may include: a semiconductor layer 115 disposed on the first insulating layer 110; a gate electrode 125 overlapping the semiconductor layer 115 with a second insulating layer 120 therebetween; and a source electrode and a drain electrode 140 formed on the third insulating layer 135 and in contact with the semiconductor layer 115.

[0180] The semiconductor layer 115 may be a region where a channel is formed when the thin-film transistor TFT is driven. The semiconductor layer 115 may be formed of an oxide semiconductor, amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or various organic semiconductors such as pentacene, but is not limited thereto.

[0181] The semiconductor layer 115 may be formed on the first insulating layer 110. The semiconductor layer 115 may include a channel region, a source region, and a drain region. The channel region may overlap the gate electrode 125 with the first insulating layer 110 therebetween, thereby forming a channel region between the source electrode and the drain electrode 140. The source region is electrically connected to the source electrode 140 through a contact hole passing through the second insulating layer 120 and the third insulating layer 135. The drain region is electrically connected to the drain electrode 140 through a contact hole passing through the second insulating layer 120 and the third insulating layer 135.

[0182] The buffer layer 105 and the first insulating layer 110 may be disposed between the semiconductor layer 115 and the substrate 101. The buffer layer 105 may delay the diffusion of moisture and / or oxygen that has passed through the substrate 101. The first insulating layer 110 may protect the semiconductor layer 115 and block various types of defects introduced from the substrate 101.

[0183] The uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be made of a material having etching characteristics different from those of the remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135. The uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be made of any one of silicon nitride (SiNx) and silicon oxide (SiOx). The remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135 may be made of the other of silicon nitride (SiNx) and silicon oxide (SiOx). For example, the uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be made of silicon nitride (SiNx), and the remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135 may be made of silicon oxide (SiOx), but is not limited thereto.

[0184] The gate electrode 125 may be formed on the second insulating layer 120 and may overlap with the channel region of the semiconductor layer 115 with the second insulating layer 120 therebetween. The gate electrode 125 may be made of a first conductive material, which is a single layer or multiple layers made of any one of magnesium (Mg), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys, but is not limited thereto.

[0185] The source electrode 140 may be connected to the source region of the semiconductor layer 115 exposed through a contact hole penetrating the second insulating layer 120 and the third insulating layer 135. The drain electrode 140 may face the source electrode 140 and may be connected to the drain region of the semiconductor layer 115 through a contact hole penetrating the second insulating layer 120 and the third insulating layer 135. The source electrode and the drain electrode 140 may be made of a second conductive material, which is a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy of two or more of them, but is not limited thereto.

[0186] A connection electrode 155 may be provided between the first intermediate layer 150 and the second intermediate layer 160. The connection electrode 155 may be exposed through a connection electrode contact hole 156 penetrating the protective film 145 and the first intermediate layer 150 and may be connected to the drain electrode 140. The connection electrode 155 may be made of a material having the same or similar low specific resistance as the material of the drain electrode 140, but is not limited thereto.

[0187] The light-emitting element LD including the light-emitting layer 172 may be disposed on the second intermediate layer 160 and the bank layer 165. The light-emitting element LD may include an anode 171, at least one light-emitting layer 172 formed on the anode 171, and a cathode 173 formed on the light-emitting layer 172.

[0188] The anode 171 may be disposed on the first intermediate layer 150 through a contact hole passing through the second intermediate layer 160 and electrically connected to the connection electrode 155 exposed upward from the second intermediate layer 160.

[0189] The anode 171 of each pixel is formed to be exposed through the bank layer 165. The bank layer 165 may be made of an opaque material (e.g., black) to prevent light interference between adjacent pixels. In this case, the bank layer 165 may include a light-shielding material made of at least any one of a colored pigment, an organic black, and carbon, but is not limited thereto.

[0190] At least one light-emitting layer 172 may be formed on the anode 171 in the light-emitting region provided through the bank layer 165. The at least one light-emitting layer 172 may include a hole transport layer, a hole injection layer, a hole blocking layer, a light-emitting layer 172, an electron injection layer, an electron blocking layer, an electron transport layer, etc. on the anode 171, and may be formed to be stacked sequentially or reversely in the light-emitting direction. In addition, the light-emitting layer 172 may include a first light-emitting stack and a second light-emitting stack facing each other with a charge generation layer interposed therebetween. In this case, since the light-emitting layer 172 of any one of the first light-emitting stack and the second light-emitting stack may generate blue light, and the light-emitting layer 172 of the other of the first light-emitting stack and the second light-emitting stack may generate yellow-green light, white light may be generated by the first light-emitting stack and the second light-emitting stack. The white light emitted from the light-emitting stack is incident on a color filter located above or below the light-emitting layer 172, and a color image may be realized. As another example, a color image may be realized by emitting color light corresponding to each pixel from each light-emitting layer 172 without a separate color filter. For example, the light-emitting layer 172 of a red pixel may emit red light, the light-emitting layer 172 of a green pixel may emit green light, and the light-emitting layer 172 of a blue pixel may emit blue light.

[0191] The cathode 173 may be formed to face the anode 171 with the light-emitting layer 172 therebetween and may receive a high-potential driving voltage VDD.

[0192] The encapsulation layer 180 may block external moisture or oxygen from being introduced into the light-emitting element LD vulnerable to external moisture or oxygen. To this end, the encapsulation layer 180 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer, but is not limited thereto. Hereinafter, as an example, the structure of the encapsulation layer 180 in which the first encapsulation layer 181, the second encapsulation layer 182, and the third encapsulation layer 183 are sequentially stacked will be described.

[0193] A first encapsulation layer 181 is formed on a substrate 101 having a cathode 173. A third encapsulation layer 183 may be formed on the substrate 101 having a second encapsulation layer 182, and the third encapsulation layer 183 is formed to surround the upper surface, lower surface, and side surfaces of the second encapsulation layer 182 together with the first encapsulation layer 181. The first encapsulation layer 181 and the third encapsulation layer 183 may minimize or prevent external moisture or oxygen from flowing into the light-emitting element LD. The first encapsulation layer 181 and the third encapsulation layer 183 may be made of an inorganic insulating material capable of low-temperature deposition, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al 2 O 3 )). Since the first encapsulation layer 181 and the third encapsulation layer 183 are deposited in a low-temperature atmosphere, the light-emitting element LD, which is vulnerable to a high-temperature atmosphere, can be prevented from being damaged during the deposition process of the first encapsulation layer 181 and the third encapsulation layer 183.

[0194] The second encapsulation layer 182 may serve as a buffer for alleviating stress between these layers due to bending of the display device 1 and flattening the step difference between these layers. The second encapsulation layer 182 may be formed on the substrate 101 on which the first encapsulation layer 181 is formed, and is made of a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and polyethylene or silicon oxynitride (SiOC), or a photosensitive organic insulating material such as polyacrylic acid, but is not limited thereto. When the second encapsulation layer 182 is formed by an inkjet method, a dam portion DAM may be provided to prevent the second encapsulation layer 182 in liquid form from spreading to the edge of the substrate 101. The dam portion DAM may be provided closer to the edge of the substrate 101 than the second encapsulation layer 182. The dam portion DAM may prevent the second encapsulation layer 182 from spreading to the pad region where the conductive pads provided at the outermost side of the substrate 101 are provided.

[0195] The dam portion DAM may be designed to prevent the spread of the second encapsulation layer 182. However, when the second encapsulation layer 182 is formed to exceed the height of the dam portion DAM in this process, the second encapsulation layer 182, which is an organic layer, may be exposed to the outside, so moisture and the like may easily flow into the light-emitting element. Therefore, in order to prevent this, at least 10 dam portions DAM overlapping each other may be formed.

[0196] The dam portion DAM can be provided on the protective film 145 in the non-display area NAA. In addition, the dam portion DAM can be formed simultaneously with the first intermediate layer 150 and the second intermediate layer 160. When forming the first intermediate layer 150, the lower layer of the dam portion DAM can be formed together, and when forming the second intermediate layer 160, the upper layer of the dam portion DAM can be formed together. Therefore, the dam portion DAM can be formed by stacking into a double structure. Therefore, the dam portion DAM can be made of the same material as the first intermediate layer 150 and the second intermediate layer 160, but is not limited thereto.

[0197] The dam portion DAM can be formed to overlap with the low-potential driving voltage line PL2. For example, the low-potential driving voltage line PL2 can be formed on the lower layer of the area where the dam portion DAM is located in the non-display area NAA.

[0198] The low-potential driving voltage line PL2 formed in the form of GIP and the gate driver 20 can be formed in a form surrounding the outside of the display panel, and the low-potential driving voltage line PL2 can be located outside the gate driver 20. In addition, the low-potential driving voltage line PL2 can be connected to the anode 171 to apply a common voltage. The gate driver 20 is briefly shown in the plan view and the cross-sectional view, but can be configured using thin film transistors TFT having the same structure as the thin film transistors TFT in the display area AA.

[0199] The low-potential driving voltage line PL2 is provided outside the gate driver 20. The low-potential driving voltage line PL2 is provided outside the gate driver 20 and surrounds the display area AA. The low-potential driving voltage line PL2 can be made of the same material as the source electrode and the drain electrode 140 of the thin film transistor TFT, but is not limited thereto. For example, the low-potential driving voltage line PL2 can be made of the same material as the gate electrode 125.

[0200] In addition, the low-potential driving voltage line PL2 can be electrically connected to the anode 171. The low-potential driving voltage line PL2 can supply the low-potential driving voltage VSS to a plurality of pixels in the display area AA.

[0201] The touch layer 190 can be provided on the encapsulation layer 180. In the touch layer, the touch buffer film 191 can be located between the touch sensor metal including the touch electrode connection lines 192 and 194 and the touch electrodes 195 and 196 and the cathode 173 of the light-emitting element LD.

[0202] The touch buffer film 191 can block chemical solutions (developer, etchant, etc.) or external moisture used in the process of manufacturing the touch sensor metal provided on the touch buffer film 191 from flowing into the light-emitting layer 172 including organic materials. Therefore, the touch buffer film 191 can prevent damage to the light-emitting layer 172 that is vulnerable to chemical solutions or moisture.

[0203] The touch buffer layer 191 can be formed at a selected (in some cases, predetermined) temperature (e.g., a low temperature of 100 °C or lower) to prevent damage to the light-emitting layer 172 made of an organic insulating material with a low dielectric constant of 1 to 3 and containing organic materials vulnerable to high temperatures. For example, the touch buffer film 191 can be made of an acrylic-based, epoxy-based, or siloxane-based material. The touch buffer film 191 made of an organic insulating material and having a planarization property can prevent damage to the encapsulation layer 180 due to the bending of the organic light-emitting diode display device and the rupture of the touch sensor metal formed on the touch buffer film 191.

[0204] According to the mutual capacitance-based touch sensor structure, the touch electrodes 195 and 196 can be disposed on the touch buffer film 191, and the touch electrodes 195 and 196 can be disposed to cross each other.

[0205] The touch electrode connection lines 192 and 194 can electrically connect the touch electrodes 195 and 196. The touch electrode connection lines 192 and 194 and the touch electrodes 195 and 196 can be located in different layers with a touch insulating film 193 therebetween.

[0206] The touch electrode connection lines 192 and 194 can be disposed to overlap with the bank layer 165, thereby preventing a decrease in the aperture ratio.

[0207] In addition, a part of the touch electrode connection line 192 can be electrically connected to a touch driving circuit (not shown) through the touch pad 198 after passing through the upper and side surfaces of the encapsulation layer 180 and the upper and side surfaces of the dam portion DAM.

[0208] A part of the touch electrode connection line 192 can transmit the touch driving signal to the touch electrodes 195 and 196 and transmit the touch sensing signal from the touch electrodes 195 and 196 to the touch driving circuit after receiving the touch driving signal from the touch driving circuit.

[0209] A touch protection film 197 can be disposed on the touch electrodes 195 and 196. In the drawings, the touch protection film 197 is shown as being disposed only on the touch electrodes 195 and 196, but is not limited thereto, and the touch protection film 197 can extend to the area before or after the dam portion DAM and can be disposed on the touch electrode connection line 192.

[0210] In addition, a color filter (not shown) can be further disposed on the encapsulation layer 180, and the color filter can be located on the touch layer or between the encapsulation layer 180 and the touch layer 190.

[0211] The display device according to an embodiment of the present application can be described as follows.

[0212] A display device according to an embodiment of the present application may include: a display panel including a display area provided with pixel circuits and a non-display area near the display area; and a gate driver configured to apply a scan signal, a light emission signal, and an inverted light emission signal to the pixel circuits, wherein the gate driver may include: at least one scan driver configured to output the scan signal; a light emission driver configured to output the light emission signal; and an inversion driver, at least some of the inversion drivers outputting the inverted light emission signal having a phase inverted from that of the light emission signal using the scan signal output from the at least one scan driver and the light emission signal output from the light emission driver.

[0213] In a display device according to an embodiment of the present application, the pixel circuit may include: a light emitting element; a driving transistor receiving a high-potential driving voltage through a first electrode, having a second electrode connected to the light emitting element, and controlling an amount of driving current provided to the light emitting element in response to a voltage of a gate electrode; a first switching transistor transmitting a data voltage to the gate electrode of the driving transistor in response to a first scan signal; a light emitting transistor forming a current path between the driving transistor and the light emitting element in response to the light emission signal; and an initialization transistor transmitting an initialization voltage to an anode of the light emitting element in response to the inverted light emission signal.

[0214] In a display device according to an embodiment of the present application, the gate driver may be disposed on each of the left and right sides of the display area in the non-display area and symmetrically configured.

[0215] In a display device according to an embodiment of the present application, the scan driver may include: a first scan driver configured to output the first scan signal; and a second scan driver configured to output a second scan signal, and the second scan signal may be applied to the inversion driver.

[0216] In a display device according to an embodiment of the present application, the inversion driver may be disposed closer to the display area than the light emission driver and the at least one scan driver.

[0217] In a display device according to an embodiment of the present application, the inversion driver may include: a first inversion unit configured to generate an inverted signal having a phase inverted from that of the light emission signal; and a second inversion unit configured to output the inverted light emission signal according to the inverted signal or the scan signal.

[0218] In the display device according to an embodiment of the present application, the first inverter unit may operate based on the light emission signal, the first light emission clock signal, and the second light emission clock signal, and may include a Q node, a QB node, and a Q' node for controlling the QB node, and may output the inverted signal in response to the potential at the Q node or the QB node.

[0219] In the display device according to an embodiment of the present application, the first inverter unit may include: a first transistor having a gate electrode connected to an input terminal of the first light emission clock signal, a first electrode connected to an input terminal of the light emission signal, and a second electrode connected to the QB node; a second transistor having a gate electrode connected to an input terminal of the first light emission clock signal and a first electrode connected to the QB node; a third transistor having a first electrode connected to a second electrode of the second transistor and a second electrode connected to an input terminal of a high gate voltage; a fourth transistor having a gate electrode connected to an input terminal of the second light emission clock signal, a first electrode connected to an input terminal of a low gate voltage, and a second electrode connected to a gate electrode of the third transistor; a fifth transistor having a gate electrode connected to the QB node, a first electrode connected to the Q node, and a second electrode connected to an input terminal of the high gate voltage; a sixth transistor having a gate electrode connected to the Q node, a first electrode connected to an input terminal of the low gate voltage, and a second electrode connected to an INV node to which the inverted signal is applied to the second inverter unit; a seventh transistor having a gate electrode connected to the QB node, a first electrode connected to the INV node to which the inverted signal is applied to the second inverter unit, and a second electrode connected to an input terminal of the high gate voltage; an eighth transistor having a gate electrode connected to the Q' node and a first electrode connected to an input terminal of the first light emission clock signal; a ninth transistor having a gate electrode connected to an input terminal of the first light emission clock signal, a first electrode connected to a second electrode of the eighth transistor, and a second electrode connected to the Q node; and a tenth transistor having a gate electrode connected to an input terminal of the light emission signal, a first electrode connected to an input terminal of the second light emission clock signal, and a second electrode connected to the Q' node.

[0220] In the display device according to an embodiment of the present application, the first inverter unit may further include: a first capacitor having one end connected to the Q node and the other end connected to the INV node; and a second capacitor having one end connected to the Q' node and the other end connected to the second electrode of the eighth transistor.

[0221] In the display device according to an embodiment of the present application, the first capacitor or the second capacitor may be a bootstrap capacitor.

[0222] In the display device according to an embodiment of the present application, the first capacitor may have a larger capacitance than the second capacitor.

[0223] In the display device according to an embodiment of the present application, the second inverter unit may include: an eleventh transistor that is turned on according to the inverted signal applied to the INV node; a twelfth transistor that is turned on by receiving a scan signal output from the at least one scan driver; and a thirteenth transistor that is turned on while the eleventh transistor or the twelfth transistor is turned on.

[0224] In the display device according to an embodiment of the present application, the second inverter unit may include: an eleventh transistor having a gate electrode connected to the INV node, a first electrode connected to the OR node, and a second electrode connected to the input terminal of the gate high voltage; a twelfth transistor having a gate electrode connected to the input terminal of the scan signal, a first electrode connected to the OR node, and a second electrode connected to the input terminal of the gate high voltage; and a thirteenth transistor having a gate electrode connected to the OR node, a first electrode connected to the output terminal of the inverter driver, and a second electrode connected to the input terminal of the gate high voltage.

[0225] In the display device according to an embodiment of the present application, when at least one of the inverted signal and the scan signal is at a conductive level, the second inverter unit may output the gate low voltage as the inverted emission signal.

[0226] In the display device according to an embodiment of the present application, when both the inverted signal and the scan signal are at a cut-off level, the second inverter unit may output the gate high voltage as the inverted emission signal.

[0227] The display device according to an embodiment of the present application may further include a coupling capacitor, and the coupling capacitor may be connected between the inverted emission line to which the inverted emission signal is applied and the gate electrode of the driving transistor.

[0228] In the display device according to an embodiment of the present application, the coupling capacitor may transmit a coupling voltage corresponding to the inverted light emission signal to the gate electrode of the driving transistor.

[0229] In the display device according to an embodiment of the present application, the pixel circuit may further include a storage capacitor, the storage capacitor is connected to the first switching transistor through a first node and to the gate electrode of the driving transistor through a second node, and may further include a coupling capacitor, the coupling capacitor is connected between the input terminal of the inverted light emission signal and the first node.

[0230] In the display device according to an embodiment of the present application, the storage capacitor may have a larger capacitance than the coupling capacitor.

[0231] In the display device according to an embodiment of the present application, the pixel circuit may be driven at a low frequency in a variable refresh rate mode in which 1 frame includes an anode initialization period and a light emission period, the gate driver may apply a light emission signal at a cut-off level to the pixel circuit during the anode initialization period, and may apply the light emission signal at a conductive level to the pixel circuit during the light emission period, and the initialization transistor may apply an initialization voltage to the anode of the light emitting element in response to the inverted light emission signal during the anode initialization period.

[0232] In the display device according to an embodiment of the present application, the pixel circuit may be driven in a case where 1 frame includes at least one refresh period and at least one skip period, the refresh period may include a programming period and a light emission period, and the skip period may include an anode initialization period and a light emission period, and the initialization transistor may apply an initialization voltage to the anode of the light emitting element in response to the inverted light emission signal during the anode initialization period.

[0233] In the display device according to an embodiment of the present application, the length of the anode initialization period may be equal to the length of the programming period.

[0234] In the display device according to an embodiment of the present application, the voltage at the gate electrode of the driving transistor may be reduced by a selected (in some cases, predetermined) level due to the coupling voltage corresponding to the inverted light emission signal in the coupling capacitor.

[0235] The display device according to an embodiment of the present application can prevent the charging delay of the light emitting element when driven at a low frequency in the variable refresh rate mode, and adjust the characteristics and conduction bias stress of the driving transistor.

[0236] The display device according to an embodiment of the present application can minimize the flicker phenomenon in the variable refresh rate mode and uniformly control the overall brightness.

[0237] The effects according to the present application are not limited to the above, and those skilled in the art to which the present application pertains will be able to clearly understand other effects not mentioned from the following description.

[0238] The above description and the drawings merely illustrate the technical spirit of the present application, and those of ordinary skill in the art to which the present application pertains can make various changes or modifications without departing from the essential features of the present application, such as the combination, separation, replacement, and change of components. Therefore, the embodiments disclosed in the present application are not intended to limit the technical spirit of the present application, but are intended to describe it, and the scope of the technical spirit of the present application is not limited by these embodiments. The scope of the present application should be interpreted according to the appended claims, and all technical spirits within the equivalent scope should be interpreted as being included within the scope of the present application.

[0239] The above various embodiments can be combined to provide additional embodiments. If necessary, each aspect of the embodiments can be modified to adopt the concepts of various patents, applications, and publications to provide additional embodiments.

[0240] In view of the above detailed description, these and other changes can be made to these embodiments. Generally, in the following claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in the specification and the claims, but should be construed as including all possible embodiments and the entire equivalent scope enjoyed by these claims. Therefore, the claims are not limited by the present disclosure.

Claims

1. A display device, comprising: A display panel, the display panel comprising a display area provided with a pixel circuit and a non-display area near the display area; as well as a gate driver configured to apply a scan signal, a light emitting signal and an inverted light emitting signal to the pixel circuit, The gate driver comprises: at least one scan driver, the at least one scan driver configured to output the scan signal; a light emitting driver configured to output the light emitting signal; and Inverting drivers, at least some of which output the inverted light emitting signals whose phases are inverted from the phases of the light emitting signals based on the scan signals output from the at least one scan driver and the light emitting signals output from the light emitting drivers.

2. The display device according to claim 1, wherein the pixel circuit comprises: a light emitting element having an anode; a driving transistor that receives a high potential driving voltage through a first electrode, has a second electrode connected to the light emitting element, and controls an amount of driving current supplied to the light emitting element in response to a voltage of a gate electrode; a first switching transistor, the first switching transistor transmitting a data voltage to a gate electrode of the driving transistor in response to a first scanning signal; a light emitting transistor, the light emitting transistor forming a current path between the driving transistor and the light emitting element in response to the light emitting signal; and An initialization transistor transmits an initialization voltage to the anode of the light emitting element in response to the inverted light emitting signal. 3 . The display device according to claim 1 , wherein the gate driver is provided on each of a left side and a right side of the display area in the non-display area and is symmetrically configured.

4. The display device according to claim 2, wherein the scan driver comprises: a first scan driver configured to output the first scan signal; and a second scan driver configured to output a second scan signal, and The second scanning signal is applied to the inverting driver. 5 . The display device according to claim 1 , wherein the inversion driver is disposed closer to the display area than the light emitting driver and the at least one scanning driver.

6. The display device according to claim 1, wherein the inverting driver comprises: a first inverting circuit configured to generate an inverted signal whose phase is inverted from a phase of the light emitting signal; and A second inverting circuit, wherein the second inverting circuit is configured to output the inverted light emitting signal according to the inverted signal or the scanning signal.

7. The display device according to claim 6, wherein the first inverting circuit operates based on the light emitting signal, the first light emitting clock signal, and the second light emitting clock signal, and comprises a Q node, a QB node, and a Q' node controlling the QB node, and The inversion signal is output in response to a potential at the Q node or the QB node.

8. The display device according to claim 7, wherein the first inverter circuit comprises: a first transistor having a gate electrode connected to an input terminal of the first light emitting clock signal, a first electrode connected to an input terminal of the light emitting signal, and a second electrode connected to the QB node; a second transistor having a gate electrode connected to an input terminal of the first light emitting clock signal and a first electrode connected to the QB node; a third transistor having a first electrode connected to the second electrode of the second transistor and a second electrode connected to an input terminal of a gate high voltage; a fourth transistor having a gate electrode connected to an input terminal of the second light emitting clock signal, a first electrode connected to an input terminal of a gate low voltage, and a second electrode connected to the gate electrode of the third transistor; a fifth transistor having a gate electrode connected to the QB node, a first electrode connected to the Q node, and a second electrode connected to an input terminal of the gate high voltage; a sixth transistor having a gate electrode connected to the Q node, a first electrode connected to an input terminal of the gate low voltage, and a second electrode connected to an INV node for applying the inverted signal to the second inverter circuit; a seventh transistor having a gate electrode connected to the QB node, a first electrode connected to the INV node for applying the inverted signal to the second inverter circuit, and a second electrode connected to an input terminal of the gate high voltage; an eighth transistor having a gate electrode connected to the Q' node and a first electrode connected to an input terminal of the first light emitting clock signal; a ninth transistor having a gate electrode connected to an input terminal of the first light emitting clock signal, a first electrode connected to the second electrode of the eighth transistor, and a second electrode connected to the Q node; as well as A tenth transistor having a gate electrode connected to the input terminal of the light emitting signal, a first electrode connected to the input terminal of the second light emitting clock signal, and a second electrode connected to the Q' node.

9. The display device according to claim 8, wherein the first inverter circuit further comprises: a first capacitor having one end connected to the Q node and another end connected to the INV node; and a second capacitor having one end connected to the Q' node and the other end connected to the second electrode of the eighth transistor. 10 . The display device according to claim 9 , wherein the first capacitor or the second capacitor is a bootstrap capacitor.

11. The display device according to claim 9, wherein the first capacitor has a larger capacity than the second capacitor.

12. The display device according to claim 9, wherein the second inverter circuit comprises: an eleventh transistor, the eleventh transistor being turned on according to the inverted signal applied to the INV node; a twelfth transistor that is turned on by receiving a scan signal output from the at least one scan driver; and A thirteenth transistor, wherein the thirteenth transistor is turned on while the eleventh transistor or the twelfth transistor is turned on.

13. The display device according to claim 9, wherein the second inverter circuit comprises: an eleventh transistor having a gate electrode connected to the INV node, a first electrode connected to an OR node, and a second electrode connected to an input terminal of the gate high voltage; a twelfth transistor having a gate electrode connected to the input terminal of the scan signal, a first electrode connected to the OR node, and a second electrode connected to the input terminal of the gate high voltage; and A thirteenth transistor having a gate electrode connected to the OR node, a first electrode connected to the output terminal of the inverter driver, and a second electrode connected to the input terminal of the gate high voltage.

14. The display device according to claim 8, wherein when at least one of the inversion signal and the scanning signal is at an on level, the second inversion circuit outputs the gate low voltage as the inversion light emitting signal.

15. The display device according to claim 6, wherein when both the inversion signal and the scanning signal are at an off level, the second inversion circuit outputs a gate high voltage as the inversion light emitting signal. 16 . The display device according to claim 2 , wherein the pixel circuit further comprises a coupling capacitor connected between the inverse phase light emitting line to which the inverse phase light emitting signal is applied and a gate electrode of the driving transistor. 17 . The display device according to claim 16 , wherein the coupling capacitor transmits a coupling voltage corresponding to the reverse phase light emitting signal to a gate electrode of the driving transistor.

18. The display device according to claim 2, wherein the pixel circuit further comprises a storage capacitor connected to the first switching transistor through a first node and connected to the gate electrode of the driving transistor through a second node; and A coupling capacitor is connected between the input end of the inverted light emitting signal and the first node.

19. The display device according to claim 18, wherein the storage capacitor has a larger capacity than the coupling capacitor.

20. The display device according to claim 2, wherein the pixel circuit is driven at a low frequency in which 1 frame includes an anode initialization period and a light emitting period in a variable refresh rate mode, wherein the gate driver applies a light emission signal at an off level to the pixel circuit during the anode initialization period, and applies the light emission signal at an on level to the pixel circuit during the light emission period, and The initialization transistor applies an initialization voltage to the anode of the light emitting element in response to the inverted light emitting signal during the anode initialization period.

21. The display device according to claim 2, wherein the pixel circuit is driven in a case where 1 frame includes at least one refresh period and at least one skip period, wherein the refresh period includes a programming period and a light emitting period, and the skip period includes an anode initialization period and a light emitting period, and The initialization transistor applies an initialization voltage to the anode of the light emitting element in response to the inverted light emitting signal during the anode initialization period.

22. The display device according to claim 21, wherein a length of the anode initialization period is equal to a length of the programming period.

23. The display device according to claim 16, wherein a voltage at a gate electrode of the driving transistor is lowered by a selected level due to a coupling voltage in the coupling capacitor corresponding to the inverted light emitting signal.

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