Source driving chip, display panel and driving method thereof

Abstract

The invention provides a source electrode driving chip, a display panel and a driving method thereof, and the source electrode driving chip has a first mode and a second mode, and comprises a counting module which is used for generating first data according to a first to-be-counted signal in the first mode, and generating second data according to a second to-be-counted signal in the second mode; the latch signal generation module is electrically connected to the counting module and is used for generating a first latch signal according to the first data in the first mode and generating a second latch signal according to the second data in the second mode; the first latch signal comprises a first delay sub-signal, the second latch signal comprises a second delay sub-signal, the end moment of the first delay sub-signal in the first latch signal is used for controlling latching of an initial data signal, and the end moment of the second delay sub-signal in the second latch signal is used for controlling latching of the initial data signal; and the ending time of the second delay sub-signal is earlier than the ending time of the first delay sub-signal, so that the risk of a split screen phenomenon is reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular to the manufacture of display devices, specifically to a source driver chip, a display panel, and a driving method thereof. Background Art

[0002] As a currently widely used display, liquid crystal displays currently introduce DLS architectures (adjacent sub-pixels on the left and right share a data line) and Tri-gate architectures (the number of gate lines is increased to 3 times to reduce the data lines to 1 / 3) in consideration of the cost of data driver chips.

[0003] Among them, although the above architectures reduce the number of source driver chips by more than half compared with the 1G1D architecture, the differences in the distances between the main board and different source driver chips, as well as the differences in the distances between each source driver chip and data lines at different positions, require differential settings of parameters in source driver chips at different positions to narrow the differences in the charging durations of corresponding data signals acting on corresponding sub-pixels caused by the above "distance differences". However, currently, the minimum gear of the parameters in the source driver chip is relatively large, being 9UI (UI is the minimum unit of delay). For two source driver chips corresponding to relatively small "distance differences", such as corresponding to two adjacent display areas, since the two source driver chips cannot perform settings with relatively small "time differences" in output, the time differences when the data signals respectively output by the two are transmitted to the corresponding two display areas are too large, resulting in a split screen phenomenon and reducing the quality of the display screen.

[0004] Therefore, the relatively large minimum gear of the parameters in the source driver chip in the existing display panel leads to the above defects and urgently needs improvement. Summary of the Invention

[0005] The purpose of the present invention is to provide a source driver chip, a display panel, and a driving method thereof to improve the split screen phenomenon caused by the relatively large minimum gear of the parameters in the source driver chip in the existing display panel.

[0006] The present invention provides a source driver chip. The source driver chip has a first mode and a second mode, and the source driver chip includes:

[0007] A counting module, configured to generate first data according to a first signal to be counted in the first mode, and generate second data according to a second signal to be counted in the second mode;

[0008] A latch signal generation module, electrically connected to the counting module, configured to generate a first latch signal according to the first data in the first mode, and generate a second latch signal according to the second data in the second mode;

[0009] Wherein, the first latch signal includes a first delay sub-signal, the second latch signal includes a second delay sub-signal, the end moment of the first delay sub-signal in the first latch signal is used to control latching of an initial data signal, the end moment of the second delay sub-signal in the second latch signal is used to control latching of the initial data signal, and the end moment of the second delay sub-signal is earlier than the end moment of the first delay sub-signal.

[0010] In one embodiment, both the first signal to be counted and the second signal to be counted are periodic signals, and the period of the second signal to be counted is less than the period of the first signal to be counted.

[0011] In one embodiment, the source driver chip further includes:

[0012] A signal to be counted generation module, electrically connected to the counting module, for generating the second signal to be counted;

[0013] Wherein, the signal to be counted generation module is used to generate the second signal to be counted according to an initial signal to be counted or the first signal to be counted, the initial signal to be counted, the first signal to be counted, and the second signal to be counted are all periodic signals, and the period of the initial signal to be counted is less than the period of the first signal to be counted.

[0014] In one embodiment, the signal to be counted generation module includes a first switch unit, a first switch unit and a frequency-up conversion unit which are electrically connected, and the frequency-up conversion unit is electrically connected to the counting module;

[0015] Wherein, the first switch unit is used to control transmission of the initial signal to be counted or the first signal to be counted to the frequency-up conversion unit according to a first switch signal in the second mode;

[0016] Wherein, the frequency-up conversion unit is used to generate the second signal to be counted according to the initial signal to be counted or the first signal to be counted in the second mode.

[0017] In one embodiment, the frequency-up conversion unit includes:

[0018] A first delay sub-unit, electrically connected to the first switch unit, for generating a first transition signal according to one of the initial signal to be counted and the first signal to be counted and a first control signal in the second mode, the first transition signal being a signal obtained by delaying the first signal to be counted by a first preset duration, and the first preset duration is not equal to 0;

[0019] The first XOR sub-unit, electrically connected to the first delay sub-unit and the first switch unit, is configured to generate the second count signal or the second transition signal according to one of the initial signal to be counted, the first signal to be counted and the first transition signal in the second mode. The second transition signal is used to generate the second count signal. The second count signal or the second transition signal generated by the XOR module is the signal obtained by performing an XOR operation on one of the initial signal to be counted, the first signal to be counted and the first transition signal. The period of one of the second count signal and the second transition signal generated by the first XOR sub-unit is half of the period of one of the initial signal to be counted and the first signal to be counted transmitted thereto.

[0020] In one embodiment, the first XOR sub-unit is configured to generate the second transition signal, and the frequency-up unit further includes:

[0021] A second delay sub-unit, electrically connected to the first XOR sub-unit, is configured to generate a third transition signal according to the second transition signal and a second control signal in the second mode. The third transition signal is the signal obtained by delaying the second transition signal by a second preset duration, and the second preset duration is not equal to 0;

[0022] A second XOR sub-unit, electrically connected to the second delay sub-unit and the first XOR sub-unit, is configured to generate the second count signal according to the third transition signal and the second transition signal. The second count signal generated by the XOR module is the signal obtained by performing an XOR operation on the third transition signal and the second transition signal. The period of the second count signal generated by the second XOR sub-unit is half of the period of the second transition signal.

[0023] In one embodiment, the source driver further includes:

[0024] A selection module, electrically connected to the counting module, is configured to control the counting module to load the first signal to be counted to be in the first mode or control the counting module to load the second signal to be counted to be in the second mode according to an input signal.

[0025] In one embodiment, the source driver further includes:

[0026] A logic module, electrically connected between the counting module and the latch signal generation module, is configured to generate first judgment data according to the first data in the first mode and generate second judgment data according to the second data in the second mode;

[0027] Wherein, the latch signal generation module includes:

[0028] A second switch unit, electrically connected to the logic module, is configured to control an end time of the first delay sub-signal in the first latch signal according to the first judgment data in the first mode, and control an end time of the second delay sub-signal in the second latch signal according to the second judgment data in the second mode.

[0029] The present invention further provides a display panel, including a panel body and a driving chip electrically connected to the panel body, where the driving chip includes:

[0030] At least two source driving chips as described in any one of the above, each source driving chip is configured to generate a target data signal according to the initial data signal and transmit the target data signal to the panel body;

[0031] A timing control chip, electrically connected to the source driving chip, is configured to control the source driving chip to generate the first latch signal in the first mode and control the source driving chip to generate the second latch signal in the second mode.

[0032] The present invention further provides a driving method for a display panel, configured to drive the display panel as described above, including:

[0033] Generating the first latch signal in the first mode, the first latch signal includes a first delay sub-signal, an end time of the first delay sub-signal in the first latch signal is used to control latching of the initial data signal, and latching the initial data signal according to the first latch signal;

[0034] Generating the second latch signal in the second mode, the second latch signal includes a second delay sub-signal, an end time of the second delay sub-signal in the second latch signal is used to control latching of the initial data signal, and latching the initial data signal according to the second latch signal;

[0035] Wherein, the step of generating the first latch signal in the first mode includes:

[0036] Generating first data according to a first signal to be counted in the first mode;

[0037] Generating the first latch signal according to the first data;

[0038] Wherein, the step of generating second data according to a second signal to be counted in the second mode includes:

[0039] Generating second data according to a second signal to be counted in the second mode;

[0040] Generate the second latch signal according to the second data.

[0041] In one embodiment, the driving method of the display panel further includes:

[0042] According to the input signal, obtain a first signal to be counted for generating the first latch signal to be in the first mode, or obtain a second signal to be counted for generating the second latch signal to be in the second mode.

[0043] The present invention provides a source driver chip, a display panel and a driving method thereof. The source driver chip has a first mode and a second mode, and is configured to generate first data according to a first signal to be counted in the first mode, and generate a first latch signal according to the first data, and generate second data according to a second signal to be counted in the second mode, and generate a second latch signal according to the second data; wherein, the first latch signal includes a first delay sub-signal, the second latch signal includes a second delay sub-signal, the end moment of the first delay sub-signal in the first latch signal is used to control the latching of the initial data signal, and the end moment of the second delay sub-signal in the second latch signal is used to control the latching of the initial data signal; wherein, by setting the end moment of the second delay sub-signal to be earlier than the end moment of the first delay sub-signal, the "minimum gear" is different in the two modes. For two source driver chips corresponding to a relatively small "distance difference", they can be set to work in the second mode, so that the difference between the end moments of the delay sub-signals in the two latch signals is relatively small, so that the difference between the moments when the corresponding two target data signals are output to the corresponding multiple sub-pixels is relatively small, thereby reducing the risk of the split screen phenomenon. Description of the Drawings

[0044] The present invention will be further described below with reference to the drawings. It should be noted that the drawings in the following description are only used to explain some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.

[0045] Figure 1 , Figure 3 , Figure 7 and Figure 8 are respectively block diagrams of multiple structures of the source driver chip provided by the embodiments of the present invention.

[0046] Figure 2 , Figure 4 , Figure 5 and Figure 6 are respectively waveform diagrams of some signals in the display panel provided by the embodiments of the present invention.

[0047] Figure 9 and Figure 10 are respectively two flowcharts of the driving method of the display panel provided by the embodiments of the present invention.

[0048] Figure 11 is the circuit diagram of the first delay sub-unit provided by the embodiments of the present invention.

[0049] Figure 12 is the circuit diagram of the first exclusive OR sub-unit provided by the embodiments of the present invention. Detailed implementation manners

[0050] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts fall within the protection scope of the present invention.

[0051] In the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second" may explicitly or implicitly include one or more of the described features. Additionally, it should be noted that the accompanying drawings only provide structures that are relatively closely related to the present invention, omitting some details that are not closely related to the invention, aiming to simplify the drawings and make the invention points clear at a glance, rather than indicating that the actual device is exactly the same as the attached Figure 1 model, and it is not a limitation of the actual device.

[0052] Referring to "embodiments" in this article means that the specific features, structures, or characteristics described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of this phrase at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0053] The present invention provides a source driver chip 10, and the source driver chip 10 may include but is not limited to the following embodiments and combinations of the following embodiments.

[0054] In one embodiment, as Figure 1 and Figure 2As shown, the source driver chip 10 has a first mode M1 and a second mode M2. The source driver chip 10 includes: a counting module 101, configured to generate first data according to a first signal to be counted CT in the first mode M1, and generate second data according to a second signal to be counted CK3 in the second mode M2; a latch signal generation module 102, electrically connected to the counting module 101, configured to generate a first latch signal TP1 according to the first data in the first mode M1, and generate a second latch signal TP2 according to the second data in the second mode M2; wherein, as Figure 2 shown, the first latch signal TP1 includes a first delay sub-signal (with a duration of "TPdelay1"), the second latch signal TP2 includes a second delay sub-signal (with a duration of "TP delay2"), the end moment of the first delay sub-signal in the first latch signal TP1 is used to control the latching of the initial data signal data0, the end moment of the second delay sub-signal in the second latch signal TP2 is used to control the latching of the initial data signal data0, and the end moment of the second delay sub-signal is earlier than the end moment of the first delay sub-signal.

[0055] Specifically, as Figure 3 shown, the source driver chip 10 may further include a shift register 103 loaded with a source sampling clock signal SCLK, a latch 104 (including a first latch 1041 or a second latch 1042) loaded with a corresponding image signal RGB Data and a corresponding latch signal TP (the first latch signal TP1 or the second latch signal TP2), a digital-to-analog converter 105, and a buffer 106. Among them, the shift register 103 can generate a sampling signal input to the first latch 1041 based on the source sampling clock signal SCLK. The first latch 1041 can sample the corresponding image signal RGBData according to the sampling signal to obtain a plurality of initial data voltages (included in a corresponding initial data signal data0) corresponding to a plurality of sub-pixels in the same row, and after being latched by itself and another sub-latch in sequence, transmit them to the digital-to-analog converter 105. The digital-to-analog converter 105 can convert a plurality of data voltages (essentially digital voltages) in the initial data signal data0 into analog data voltages based on a gamma reference voltage. Further, the buffer can amplify the analog data voltage to obtain a plurality of target data voltages (constituting a target data signal data1) loaded to the corresponding plurality of sub-pixels.

[0056] It should be noted that an initial data signal corresponding to multiple sub-pixels at each level will sequentially pass through the first latch 1041 and the second latch 1042 and then be transmitted to the digital-to-analog converter 105. For example, here, taking the source driver chip 10 as an example of processing the initial data signal data0(i) corresponding to multiple sub-pixels at the i-th level, the first latch 1041 can be used to latch the initial data signal data0(i + 1) including multiple initial data voltages corresponding to multiple sub-pixels at the (i + 1)-th level, and the second latch 1042 can be used to latch the initial data signal data0(i) including multiple data voltages corresponding to multiple sub-pixels at the i-th level before the (i + 1)-th level. Further, multiple initial data voltages in the initial data signal data0(i) output by the second latch 1042 pass through the corresponding digital-to-analog converter 105 and buffer 106 in sequence to generate multiple target data voltages loaded to the corresponding multiple sub-pixels.

[0057] Among them, the second latch 1042 can control the time when the initial data signal data0 enters the second latch 1042 and the time when it leaves the second latch 1042 under the control of the latch signal. Specifically, as Figure 2 shown, the source driver chip 10 can also receive a P2P signal to generate a corresponding latch signal according to the P2P signal. For example, the P2P signal can include a row end sub-signal CE, a signal to be counted (the first signal to be counted CT or the second signal to be counted CK3), and a row start sub-signal CS arranged in sequence. Then, it can be considered that when the source driver chip 10 recognizes the signal to be counted after the row end sub-signal CE, it can start generating the latch signal, that is, the start time of the latch signal is the same as the start time of the signal to be counted, and the specific waveform of the latch signal can be determined at least by the specific waveform of the signal to be counted. Each latch signal (the first latch signal TP1 or the second latch signal TP2) can include a delay sub-signal arranged in sequence (the first delay sub-signal included in the first latch signal TP1, the second delay sub-signal included in the second latch signal TP2) and a latch sub-signal (the first latch sub-signal after the first delay sub-signal, the second latch sub-signal after the second delay sub-signal), and the end time of the delay sub-signal can be equal to the start time of the corresponding latch sub-signal. Taking the initial data signal data0(i) at the i-th level as an example, it can be considered that at the start time of the latch sub-signal (for example, the end time of the corresponding first delay sub-signal or second delay sub-signal, that is, the end time of "TPdelay1" or "TP delay2"), the initial data signal data0 is input to the second latch 1042, and at the end time of the latch sub-signal, the second latch 1042 outputs the initial data signal data0.

[0058] Among them, in the present invention, the case where the amplitude of the delay sub-signal in each latch signal is smaller than the amplitude of the corresponding latch sub-signal is taken as an example for illustration. That is, it can be considered that at the end moment of the delay sub-signal (i.e., the start moment of the latch sub-signal), the latch signal is at the rising edge.

[0059] That is to say, for the source driver chips 10 located at different positions, when the start moment of the delay sub-signal and the duration of the latch sub-signal are fixed, by differentially setting the end moment of the delay sub-signal or the duration of the delay sub-signal, the output moments of the corresponding initial data signals data0 can be made different, so as to compensate for the difference in charging duration caused by the distance difference between different source driver chips 10 and multiple sub-pixels, and make the output moments of the corresponding target data signals data1 and data0 to the corresponding multiple sub-pixels the same. Among them, the duration of the delay sub-signal in each source driver chip 10 increases based on the "minimum gear", that is, the end moment of the delay sub-signal is delayed based on the "minimum gear", that is, the difference in the duration of the two delay sub-signals in the two latch signals corresponding to any two source driver chips 10 can be equal to an integer multiple of the "minimum gear".

[0060] It should be noted that for the two source driver chips 10 corresponding to the relatively small "distance difference", the current minimum gear is relatively large, which is 9UI (UI is the minimum unit of delay). For the two source driver chips 10 corresponding to the relatively small "distance difference", for example, corresponding to two adjacent display areas, since the two source driver chips 10 cannot perform a relatively small "output moment difference" setting (at least the difference is 9UI), the time difference between the data signals respectively output by the two and transmitted to the corresponding two display areas is too large, resulting in a split screen phenomenon.

[0061] Among them, the above-mentioned first mode M1 and second mode M2 are only used to represent two modes in which the source driver chip 10 generates the first latch signal and the second latch signal respectively, and are only for conceptual explanation. Of course, when the source driver chip 10 generates the first latch signal and when it generates the second latch signal can be judged according to other signals, that is, when the driver chip is in the first mode M1 and when it is in the second mode M2 will be discussed later.

[0062] It can be understood that the source driver chip 10 in this embodiment can at least have two operating modes, namely a first mode M1 and a second mode M2, and the moments for controlling and latching the corresponding initial data signals (the end moments of the delay sub-signals in the two latching signals) generated in the two modes are different, that is, the above-mentioned "minimum gear" is different. For the two source driver chips 10 corresponding to a relatively small "distance difference", they can be set to operate in the second mode M2, so that the difference between the end moments of the delay sub-signals in the two latching signals is relatively small, so that the moments when the corresponding two target data signals data1 are output to the corresponding multiple sub-pixels are relatively small, thereby reducing the risk of the occurrence of the split screen phenomenon; of course, for the two source driver chips 10 corresponding to a relatively large "distance difference", they can be set to operate in the first mode M1 to compensate for the relatively large difference in the charging duration of their respective sub-pixels caused by the relatively large "distance difference".

[0063] In one embodiment, as Figure 4 and Figure 5 shown, the first signal to be counted CT and the second signal to be counted CK3 are both periodic signals, and the period of the second signal to be counted CK3 is less than the period of the first signal to be counted CT.

[0064] Specifically, in combination with Figure 2 、 Figure 4 and Figure 5 shown, as discussed above, the starting moment of the delay sub-signal in the latching signal is equal to the starting moment of the signal to be counted, and the duration of the continuous time period of the delay sub-signal in the latching signal can be at least determined according to the signal to be counted. Here, taking the signal to be counted (the first signal to be counted CT and the second signal to be counted CK3) as a periodic signal and a square wave signal as an example, the counting module 101 can count once at each rising edge of the signal to be counted, and can set the number of times that has been counted currently as the data (the first data or the second data) at any moment, that is, the data is related to both the duration maintained by the counting and the period of the signal to be counted. At any moment, the value of the corresponding latching signal at this time can be determined according to the magnitude relationship between the specific value of the current data and the preset value.

[0065] As Figure 2 and Figure 4 shown, for example, the first signal to be counted CT is a square wave signal with a period equal to 9UI (1UI can be understood as a unit duration), and the counting module 101 can count once at each rising edge of the first signal to be counted CT, and take the first rising edge as the starting point of counting. Then, at the moment of "18UI", the first data is equal to 2( Figure 4The value of the "first data" in is equal to the number of arrows generated at the current moment and before (each rising edge in the first signal to be counted CT generates an arrow), and so on. At the moment of "n*UI", the first data is equal to n / 9. If the first preset value is equal to x1, since the first data starts increasing from 0, it can be considered that when the first data is less than or equal to x1, the value corresponding to the first latching signal TP1 is the first value (corresponding to the first delay sub-signal), and when the first data is greater than x1, the value corresponding to the first latching signal TP1 is the second value (corresponding to the first latching sub-signal). For example, when the second value is greater than the first value, it is considered that when the first data changes from less than or equal to x1 to greater than x1, the first latching signal TP1 has an upward jump.

[0066] As Figure 2 and Figure 5 shown, the difference is that the period of the second signal to be counted CK3 is equal to UI. Then at the moment of "n*UI", the first data is equal to n. If the second preset value is equal to x2, it can be considered that when the second data is less than or equal to x2, the value corresponding to the second latching signal TP2 is the first value (corresponding to the second delay sub-signal), and when the second data is greater than x2, the value corresponding to the second latching signal TP2 is the second value (corresponding to the second latching sub-signal). For example, when the second value is greater than the first value, it is considered that when the second data changes from less than or equal to x1 to greater than x1, the second latching signal TP2 has an upward jump.

[0067] It can be understood that in this embodiment, the period of the second signal to be counted CK3 is set to be less than the period of the first signal to be counted CT, that is, the minimum value of the duration of the second delay sub-signal in the second mode (i.e., the "minimum gear") can be less than the minimum value of the duration of the first delay sub-signal in the first mode (i.e., the "minimum gear"), so as to achieve the above two different "minimum gears".

[0068] In one embodiment, as Figure 1 shown, the source driver chip 10 further includes: a signal to be counted generation module 107, electrically connected to the counting module 101, for generating the second signal to be counted CK3; wherein, as Figure 6 shown, the signal to be counted generation module 107 is used to generate the second signal to be counted CK3 according to the initial signal to be counted CK1 or the first signal to be counted CT. The initial signal to be counted CK1, the first signal to be counted CT, and the second signal to be counted CK3 are all periodic signals, and the period of the initial signal to be counted CK1 is less than the period of the first signal to be counted CT.

[0069] Specifically, it can be considered that the first signal CT to be counted can be obtained by the source driver chip 10 from the outside (including but not limited to the timing control chip) for the counting module 101 to count, and the newly added second signal CK3 to be counted with a smaller period can be generated by the newly added signal generation module 107 to be counted by the counting module 101.

[0070] Specifically, taking the period of the first signal CT to be counted equal to 9UI as an example, if the period of the initial signal CK1 to be counted is greater than 9UI, there is no need to set the initial signal CK1 to be counted, and directly up-convert the first signal CT to be counted successively to obtain the second signal CK3 with a smaller period; if the period of the initial signal CK1 to be counted is less than 9UI, for example Figure 6 As shown, equal to 4UI, then up-convert the initial signal CK1 to be counted successively to obtain the second signal CK3 with a smaller period. For example, first up-convert the initial signal CK1 to be counted to obtain the second transition signal CK11 with a period equal to 2UI, and then up-convert the second transition signal CK11 to obtain CK3 with a period equal to UI.

[0071] Of course, since the period of the initial signal CK1 to be counted is also less than the period of the first signal CT to be counted, the initial signal CK1 to be counted can also be directly set as the second signal CK3 to be counted for the counting module 101 to perform counting processing. As discussed above, at this time, under the condition that other conditions are the same, the end time of the second delay sub-signal can also be earlier than the end time of the first delay sub-signal, so as to achieve a smaller "minimum gear" in the second mode M2, so as to be applicable to two source driver chips 10 corresponding to a smaller "distance difference".

[0072] In one embodiment, as Figure 7 shown, the signal generation module 107 to be counted includes a first switch unit 1071, a first switch unit 1071 and a frequency up-conversion unit 1072 connected electrically, and the frequency up-conversion unit 1072 is electrically connected to the counting module 101; wherein, the first switch unit 1071 is used to control the transmission of the initial signal CK1 to be counted or the first signal CT to be counted to the frequency up-conversion unit 1072 according to the first switch signal in the second mode M2; wherein, the frequency up-conversion unit 1072 is used to generate the second signal CK3 to be counted according to the initial signal CK1 to be counted or the first signal CT to be counted in the second mode M2. Wherein, in this embodiment, the source of the initial signal CK1 to be counted or the first signal CT to be counted required by the first switch unit 1071 is not limited, and the source of the first switch control signal is not limited either, that is, the connection mode between the first switch unit 1071 and the outside is not limited.

[0073] Specifically, the first switch unit 1071 may include a first switch transistor Q100. The gate of the first switch transistor Q100 may be loaded with a first switch signal, the source of the first switch transistor Q100 may be loaded with an initial signal to be counted CK1 or a first signal to be counted CT ( Figure 7 only taking the loading as the initial signal to be counted CK1 as an example), and the drain of the first switch transistor Q100 may be electrically connected to the frequency-up unit 1072. Among them, the first switch signal may present an effective voltage in the second mode M2 to turn on the first switch transistor Q100, so that the initial signal to be counted CK1 or the first signal to be counted CT is transmitted to the frequency-up unit 1072 through the first switch transistor Q100. Furthermore, the frequency-up unit 1072 generates a second signal to be counted CK3 with a smaller period according to the initial signal to be counted CK1 or the first signal to be counted CT with a larger period and a smaller frequency.

[0074] In one embodiment, as shown in combination with Figure 6 and Figure 7 , the frequency-up unit 1072 includes: a first delay subunit 10721, electrically connected to the first switch unit 1071, for generating a first transition signal CK2 according to one of the initial signal to be counted CK1 and the first signal to be counted CT (taking the initial signal to be counted CK1 as an example here) and a first control signal Ctrl1 in the second mode M2. The first transition signal CK2 is a signal obtained by delaying the first signal to be counted CT by a first preset duration H1, and the first preset duration H1 is not equal to 0; a first exclusive-OR subunit 10722, electrically connected to the first delay subunit 10721 and the first switch unit 1071, for generating the second signal to be counted CK3 or a second transition signal CK11 (taking the generation of the second transition signal CK11 as an example here) according to one of the initial signal to be counted CK1 and the first signal to be counted CT (taking the initial signal to be counted CK1 as an example here) and the first transition signal CK2 in the second mode M2. The second transition signal CK11 is used to generate the second signal to be counted CK3. The second signal to be counted CK3 or the second transition signal CK11 generated by the first exclusive-OR subunit 10722 is a signal obtained by performing an exclusive-OR operation on one of the initial signal to be counted CK1 and the first signal to be counted CT (taking the initial signal to be counted CK1 as an example here) and the first transition signal CK2. The period of one of the second signal to be counted CK3 and the second transition signal CK11 generated by the first exclusive-OR subunit 10722 is half of the period of one of the initial signal to be counted CK1 and the first signal to be counted CT transmitted thereto.

[0075] It can be understood that the first delay subunit 10721 in the up-conversion unit 1072 in this embodiment can delay the received initial signal to be counted CK1 or the first signal to be counted CT (here, the initial signal to be counted CK1 is taken as an example) under the action of the first control signal Ctrl1. For example, the initial signal to be counted CK1 with a period of 4UI can be delayed by 1UI to obtain a first transition signal CK2 with a period still of 4UI. Further, the first XOR subunit 10722 in the up-conversion unit 1072 can perform an XOR operation on the received initial signal to be counted CK1 and the first transition signal CK2 to obtain a second transition signal CK11 with a period of 2UI, thereby realizing the period halving process of the initial signal to be counted CK1.

[0076] Similarly, since the period of the second transition signal CK11 is also smaller than the period of the first signal to be counted CT, the second transition signal CK11 can also be directly set as the second signal to be counted CK3 for the counting module 101 to perform counting processing. As discussed above, at this time, under the condition that other conditions are the same, it is also possible to make the end time of the second delay sub-signal earlier than the end time of the first delay sub-signal, so as to have a smaller "minimum gear" in the second mode M2, thus being applicable to the two source drive chips 10 corresponding to a smaller "distance difference". Of course, the second transition signal CK11 can also be further up-converted to obtain a second signal to be counted CK3 with a smaller period.

[0077] Among them, as shown in Figure 7 and Figure 11 the first delay subunit 10721 can be a gated D latch, which can be but is not limited to a transmission-gated D latch or a logic-gated D latch. Here, the latter is taken as an example to illustrate. The first delay subunit 10721 can include a NOR gate G1, a NOR gate G2, an AND gate G3, an AND gate G4, and a NOT gate G5 electrically connected according to the connection relationship in Figure 11 . Among them, one input terminal of the AND gate G3 and one input terminal of the AND gate G4 can be respectively configured as the data input terminal D (the initial signal to be counted CK1 can be loaded) and the enable terminal E (the first control signal Ctrl1 can be loaded) of the logic-gated D latch. A NOT gate G5 can be connected between the other input terminal of the AND gate G4 and the data input terminal D. It can be considered that G1, G2, G3, G4 and their connection relationship constitute an SR latch. The output terminal of the NOR gate G2 and the output terminal of the NOR gate G1 are respectively configured as the output terminal Q (the first transition signal CK2 can be output) of the logic-gated D latch,

[0078] inverted output terminal Since the circuit will be locked in the state determined by the initial signal to be counted CK1 at the moment before the value of the first control signal Ctrl changes from 1 to 0, when the value of the first control signal Ctrl1 is 0, it can maintain the state of the logic gated D latch unchanged, enabling the storage of 1-bit binary data. And when the value of the first control signal Ctrl1 is 1, the output Q outputs the first transition signal CK2, which can change following the state of the initial signal to be counted CK1 loaded at the data input D. Therefore, the first transition signal CK2 can be obtained by delaying the initial signal to be counted CK1, and their waveforms can be the same.

[0079] Among them, as shown in combination with Figure 7 and Figure 12 , the first exclusive-OR sub-unit 10722 can be an exclusive-OR gate, and the exclusive-OR gate can include NOT gates G6, G7, G8, G9 electrically connected as shown in the connection relationship of Figure 12 . Among them, the two input terminals of the NOT gate G6 are respectively configured as the input terminal A (which can load the initial signal to be counted CK1) and the input terminal B (which can load the first transition signal CK2) of the exclusive-OR gate, and the output terminal of the NOT gate G9 can be configured as the output terminal Y (which can output the second transition signal CK11) of the exclusive-OR gate. Since the characteristic of the exclusive-OR gate is "the same is 0, the different is 1", that is, when the values of the initial signal to be counted CK1 and the first transition signal CK2 are both 0 or both 1, the value of the output second transition signal CK11 is 0, and when one of the two values is 0 and the other is 1, the value of the output second transition signal CK11 is 1.

[0080] In an embodiment, as shown in combination with Figure 6 and Figure 7 , the first exclusive-OR sub-unit 10722 is used to generate the second transition signal CK11. The frequency-up unit 1072 further includes: a second delay sub-unit 10723, electrically connected to the first exclusive-OR sub-unit 10722, and used to generate a third transition signal CK22 according to the second transition signal CK11 and the second control signal Ctrl2 in the second mode M2. The third transition signal CK22 is a signal obtained by delaying the second transition signal CK11 by a second preset duration H2, and the second preset duration H2 is not equal to 0; a second exclusive-OR sub-unit 10724, electrically connected to the second delay sub-unit 10723 and the first exclusive-OR sub-unit 10722, and used to generate the second signal to be counted CK3 according to the third transition signal CK22 and the second transition signal CK11. The second signal to be counted CK3 generated by the exclusive-OR module is a signal obtained by performing an exclusive-OR operation on the third transition signal CK22 and the second transition signal CK11. The period of the second signal to be counted CK3 generated by the second exclusive-OR sub-unit 10724 is half of the period of the second transition signal CK11.

[0081] It can be understood that in this embodiment, a second delay subunit 10723 and a second exclusive-OR subunit 10724 are further provided in the up-conversion unit 1072. The second delay subunit 10723 can delay the received second transition signal CK11 under the action of the second control signal Ctrl2. For example, the second transition signal CK11 with a period of 2UI can be delayed by (1 / 2)UI to obtain a third transition signal CK22 with a period still of 2UI. Further, the second exclusive-OR subunit 10724 can perform an exclusive-OR operation on the received third transition signal CK22 and the second transition signal CK11 to obtain a second signal to be counted CK3 with a period of 1UI, thereby realizing reducing the period of the initial signal to be counted CK1 to 1 / 4 of the original period.

[0082] At this time, the period of the second signal to be counted CK3 can be further reduced to achieve a further smaller "minimum gear" in the second mode M2, so as to be applicable to two source driver chips 10 corresponding to a smaller "distance difference".

[0083] Among them, the second delay subunit 10723 can also be a gated D latch, which can be understood by referring to the discussion of the first delay subunit 10721 above. Among them, the second transition signal CK11, the second control signal Ctrl2, and the third transition signal CK22 can be respectively understood by analogy with the above-mentioned initial signal to be counted CK1, the first control signal Ctrl1, and the first transition signal CK2.

[0084] Similarly, the second exclusive-OR subunit 10724 can also be an exclusive-OR gate, which can be understood by referring to the discussion of the first exclusive-OR subunit 10722 above. Among them, the second transition signal CK11, the third transition signal CK22, and the second signal to be counted CK3 can be respectively understood by analogy with the above-mentioned first transition signal CK2, the initial signal to be counted CK1, and the second transition signal CK11.

[0085] In one embodiment, as Figure 1As shown, the source driver chip 10 further includes: a selection module 108, electrically connected to the counting module 101, for controlling the counting module 101 to load the first signal to be counted CT to be in the first mode M1 or controlling the counting module 101 to load the second signal to be counted CK3 to be in the second mode M2 according to the input signal Input. It can be understood that, as discussed above, the counting module 101 can receive the first signal to be counted CT generated by the outside world (such as but not limited to the timing control chip), and can also receive the second signal to be counted CK3 generated by the signal to be counted generation module 107. Further, in this embodiment, the selection module 108 is further provided, which can control the counting module 101 to load the first signal to be counted CT with a larger period or the second signal to be counted CK3 with a smaller period according to the input signal Input (which can be set in advance according to the distances between the current source driver chip 10 and the previous source driver chip 10 and multiple sub-pixels), so as to achieve an appropriate "minimum gear".

[0086] Combined with the above discussion, it can be known that whether the source driver chip 10 should be in the first mode M1 or the second mode M2 currently can be set according to the current input signal Input. The input signal Input can be determined according to the debugging results of two adjacent source driver chips 10 in the display panel in advance. For example, if the distance between two adjacent source driver chips 10 in the display panel is relatively close, that is, the accuracy requirement for the "minimum gear" is relatively high. At this time, the specific value of the input signal Input may be set so that the selection module 108 determines that the source driver chip 10 should be in the second mode M2. The specific value of Input can be determined according to the results of the previous debugging (that is, the split screen phenomenon of the display panel can be eliminated).

[0087] Among them, the selection module 108 can essentially include a comparator circuit or a switch circuit. If the selection module 108 is a comparator, the two input terminals of the comparator can be respectively loaded with the input signal Input and the reference signal. The comparator can output a corresponding signal according to the magnitude relationship between the input signal Input and the reference signal to control the counting module 101 to load the first signal to be counted CT or the second signal to be counted CK3. Similarly, if the selection module 108 is a switch circuit, the input terminal of the switch circuit is loaded with the input signal Input, and the output terminal of the switch circuit can output a corresponding signal according to the magnitude of the input signal Input to control the counting module 101 to load the first signal to be counted CT or the second signal to be counted CK3.

[0088] In one embodiment, in combination with Figure 1 and Figure 7As shown, the source driver chip 10 further includes: a logic module 109, electrically connected between the counting module 101 and the latch signal generation module, for generating first judgment data according to the first data in the first mode M1, and generating second judgment data according to the second data in the second mode M2; wherein, as Figure 8 shown, the latch signal generation module includes: a second switch unit 1021, electrically connected to the logic module, for controlling the end time of the first delay sub-signal in the first latch signal TP1 according to the first judgment data in the first mode M1, and controlling the end time of the second delay sub-signal in the second latch signal TP2 according to the second judgment data in the second mode M2. Among them, the above initial signal to be counted CK1 can be generated and transmitted to the first switch unit 1071 by but not limited to the logic module.

[0089] Further, the above input signal Input can be stored in a register (whether integrated in the source driver chip 10 is not limited), and the selection module 108 can read the input signal Input (which can essentially be the value of the register, and can be 0 or 1) in this register. Further, the selection module 108 can also be integrated in the logic module 109.

[0090] It should be noted that the source driver chip 10 can be in the first mode M1 or the second mode M2 at each moment, and the counting module 101 generates the first data and the second data respectively in the two modes. Therefore, it can be considered that the data received by the logic module at each moment can be one of the first data and the second data, so as to generate the corresponding first judgment data or the corresponding second judgment data, and then apply the first judgment data or the second judgment data to the second switch unit to control the end time of the first delay sub-signal in the first latch signal TP1 or the end time of the second delay sub-signal in the second latch signal TP2, and combined with other conditions discussed above, the complete first latch signal TP1 and the second latch signal TP2 are generated respectively.

[0091] Specifically, the second switch unit may include a second switching transistor Q1. The gate of the second switching transistor is electrically connected to the logic module. The source of the second switching transistor is loaded with the operating voltage VDD. The drain of the second switching transistor is electrically connected to a resistor R and is used to output a latch signal TP. Here, taking the first mode M1 as an example, the logic module can compare the first data with a preset first threshold value at each moment. If the first data is less than or equal to the first threshold value, it can be considered that the first judgment data is equal to the first value for controlling the second switching transistor to turn off. At this time, the latch signal TP maintains its original value. If the first data is greater than the first threshold value, it can be considered that the first judgment data is equal to the second value for controlling the second switching transistor to turn off. At this time, the latch signal TP can change from its original value to be equal to the operating voltage VDD (this is also the end moment of the first delay sub-signal). It can be understood that as time goes by, the first data will gradually increase. When the first data is greater than the second threshold value (greater than the first threshold value), it can be considered that the first judgment data is equal to the first value for controlling the second switching transistor to turn off again. This is also the end moment of the first latch sub-signal.

[0092] The present invention also provides a display panel, which includes a panel body and a driving chip electrically connected to the panel body. The driving chip includes: at least two source driving chips 10 as described above, and each source driving chip 10 is used to generate a target data signal data1 according to the initial data signal and transmit the target data signal data1 to the panel body; a timing control chip, electrically connected to the source driving chip 10, for controlling the source driving chip 10 to generate the first latch signal TP1 in the first mode M1 and for controlling the source driving chip 10 to generate the second latch signal TP2 in the second mode M2.

[0093] Specifically, in combination with the above discussion on Figure 3 it can be known that the timing control chip can transmit the corresponding image signal RGB Data and the latch signal TP to each source driving chip 10. The shift register in the source driving chip 10 can process the image signal RGB Data to generate an initial data signal. The latch in the source driving chip 10 can process the initial data signal according to the latch signal TP to generate a data signal, which is converted into a corresponding plurality of analog data voltages (constituting the target data signal data1) acting on a plurality of sub-pixels in the panel body through the digital-to-analog converter 105 and the buffer 106. Among them, the first signal to be counted CT acting on the counting module 101 in the first mode M1 can be generated by the timing control chip, and the second signal to be counted CK3 acting on the counting module 101 in the second mode M2 can be generated by the counting signal generation module.

[0094] The present invention also provides a driving method for a display panel, which is used to drive the display panel as described above, such as Figure 9 shown, which may include but is not limited to the following steps, and the order of the following steps is not limited.

[0095] S1. Generate the first latch signal in the first mode. The first latch signal includes a first delay sub-signal. The end moment of the first delay sub-signal in the first latch signal is used to control the latching of the initial data signal, and latch the initial data signal according to the first latch signal.

[0096] S2. Generate the second latch signal in the second mode. The second latch signal includes a second delay sub-signal. The end moment of the second delay sub-signal in the second latch signal is used to control the latching of the initial data signal, and latch the initial data signal according to the second latch signal.

[0097] Among them, the step S1 may include the following steps:

[0098] Generate first data according to a first signal to be counted in the first mode;

[0099] Generate the first latch signal according to the first data;

[0100] Among them, the step S2 may include the following steps:

[0101] Generate second data according to a second signal to be counted in the second mode;

[0102] Generate the second latch signal according to the second data.

[0103] Specifically, the selection module 108 may obtain a first signal to be counted for generating the first latch signal according to an input signal and control the counting module 101 to load the first latch signal to be in the first mode, or obtain a second signal to be counted for generating the second latch signal and control the counting module 101 to load the second latch signal to be in the second mode. Further, the counting module 101 may generate first data or second data. Further, in combination with the function of the logic module, according to the first data or the second data, control the latch signal generation module to generate the first latch signal or the second latch signal, so as to latch the initial data signal.

[0104] That is to say, before steps S1 and S2, the following steps may be included: according to the input signal, obtain a first signal to be counted for generating the first latch signal to be in the first mode, or obtain a second signal to be counted for generating the second latch signal to be in the second mode.

[0105] Specifically, as Figure 10 shown, whether in the first mode or the second mode, the driving method of the above display panel may include but is not limited to the following steps:

[0106] S01, recognizing a first signal to be counted or a second signal to be counted;

[0107] Among them, the execution entity may be the counting module 101. It can be considered that the first signal to be counted is recognized in the first mode, and the second signal to be counted is recognized in the second mode. Specifically, it can be seen from the relevant description above;

[0108] S02, generating first data or second data;

[0109] Among them, the execution entity may be the counting module 101. It can be considered that the first data is generated according to the first signal to be counted, or the second data is generated according to the second signal to be counted. Specifically, it can be seen from the relevant description above;

[0110] S03, determining whether the current first data is greater than a first critical value, or whether the second data is greater than a third critical value;

[0111] Among them, the execution entity may be a logic module. Specifically, it can be seen from the relevant description above;

[0112] If it is greater, then execute:

[0113] S04, generating a rising edge in the latch signal;

[0114] Among them, the execution entity may be a latch signal generation module. Here, it is described by taking the amplitude of the delay sub-signal in the latch signal being less than the amplitude of the corresponding latch sub-signal as an example. It can also be understood that at this time, the end time of the delay sub-signal is reached (that is, the start time of the latch sub-signal). Specifically, it can be seen from the relevant description above;

[0115] S05, maintaining the high level state in the latch signal;

[0116] Among them, the execution entity may be a latch signal generation module. It can be understood that at this time, the latch sub-signal in the latch signal is generated and maintained. Specifically, it can be seen from the relevant description above;

[0117] S06, determining whether the current first data is greater than a second critical value, or whether the second data is greater than a fourth critical value;

[0118] Among them, the execution entity may be a logic module. It should be noted that both the first signal to be counted and the second signal to be counted are periodic signals. At every moment, the logic module is executing step S02 to generate the corresponding first data or second data at each moment, so that the first data or the second data is updated in real time. Specifically, it can be seen from the relevant description above;

[0119] If it is greater than, then execute:

[0120] S07, generate and hold the falling edge in the latch signal;

[0121] Among them, the execution entity can be a latch signal generation module. It can be understood that at this time, it reaches the end moment of the latch sub-signal and also reaches the end moment of the latch signal, and no rising edge will be generated, so it will remain as the falling edge. For specific details, refer to the relevant descriptions above.

[0122] The present invention provides a source driver chip, a display panel, and a driving method thereof. The source driver chip has a first mode and a second mode, and is used to generate first data according to a first signal to be counted in the first mode, and generate a first latch signal according to the first data, and generate second data according to a second signal to be counted in the second mode, and generate a second latch signal according to the second data; wherein, the first latch signal includes a first delay sub-signal, the second latch signal includes a second delay sub-signal, the end moment of the first delay sub-signal in the first latch signal is used to control the latching of the initial data signal, and the end moment of the second delay sub-signal in the second latch signal is used to control the latching of the initial data signal; wherein, by setting the end moment of the second delay sub-signal to be earlier than the end moment of the first delay sub-signal, the "minimum gear" is different in the two modes. For two source driver chips corresponding to a relatively small "distance difference", they can be set to work in the second mode, so that the difference between the end moments of the delay sub-signals in the two latch signals is relatively small, so that the difference in the moments when the corresponding two target data signals are output to the corresponding multiple sub-pixels is relatively small, thereby reducing the risk of the occurrence of the split screen phenomenon.

[0123] The above has introduced in detail the source driver chip, the display panel, and the driving method thereof provided by the embodiments of the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present invention; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A source driver chip, the source driver chip having a first mode and a second mode, characterized in that, the source driver chip includes: a counting module for generating first data according to a first signal to be counted in the first mode and generating second data according to a second signal to be counted in the second mode; a latch signal generation module electrically connected to the counting module for generating a first latch signal according to the first data in the first mode and generating a second latch signal according to the second data in the second mode; wherein, the first latch signal includes a first delay sub-signal, the second latch signal includes a second delay sub-signal, the end moment of the first delay sub-signal in the first latch signal is used to control the latching of an initial data signal, the end moment of the second delay sub-signal in the second latch signal is used to control the latching of the initial data signal, and the end moment of the second delay sub-signal is earlier than the end moment of the first delay sub-signal.

2. The source driver chip according to claim 1, characterized in that, both the first signal to be counted and the second signal to be counted are periodic signals, and the period of the second signal to be counted is less than the period of the first signal to be counted.

3. The source driver chip according to claim 1, characterized in that, it further includes: a signal to be counted generation module electrically connected to the counting module for generating the second signal to be counted; wherein, the signal to be counted generation module is used to generate the second signal to be counted according to an initial signal to be counted or the first signal to be counted, the initial signal to be counted, the first signal to be counted and the second signal to be counted are all periodic signals, and the period of the initial signal to be counted is less than the period of the first signal to be counted.

4. The source driver chip according to claim 3, characterized in that, the signal to be counted generation module includes a first switch unit, a first switch unit and an up-conversion unit electrically connected, and the up-conversion unit is electrically connected to the counting module; wherein, the first switch unit is used to control the transmission of the initial signal to be counted or the first signal to be counted to the up-conversion unit according to a first switch signal in the second mode; wherein, the up-conversion unit is used to generate the second signal to be counted according to the initial signal to be counted or the first signal to be counted in the second mode.

5. The source driver chip according to claim 4, characterized in that, the up-conversion unit includes: a first delay sub-unit electrically connected to the first switch unit for generating a first transition signal according to one of the initial signal to be counted and the first signal to be counted and a first control signal in the second mode, the first transition signal being a signal obtained by delaying the first signal to be counted by a first preset duration, and the first preset duration is not equal to 0; The first exclusive-OR sub-unit is electrically connected to the first delay sub-unit and the first switch unit, and is configured to generate the second signal to be counted or the second transition signal according to one of the initial signal to be counted, the first signal to be counted, and the first transition signal in the second mode. The second transition signal is used to generate the second signal to be counted. The second signal to be counted or the second transition signal generated by the exclusive-OR module is a signal obtained by performing an exclusive-OR operation on one of the initial signal to be counted, the first signal to be counted, and the first transition signal. The period of one of the second signal to be counted and the second transition signal generated by the first exclusive-OR sub-unit is half of the period of one of the initial signal to be counted and the first signal to be counted transmitted thereto.

6. The source driver chip according to claim 5, wherein, the first exclusive-OR sub-unit is configured to generate the second transition signal, and the up-conversion unit further includes: a second delay sub-unit, electrically connected to the first exclusive-OR sub-unit, and configured to generate a third transition signal according to the second transition signal and a second control signal in the second mode. The third transition signal is a signal obtained by delaying the second transition signal by a second preset duration, and the second preset duration is not equal to 0; a second exclusive-OR sub-unit, electrically connected to the second delay sub-unit and the first exclusive-OR sub-unit, and configured to generate the second signal to be counted according to the third transition signal and the second transition signal. The second signal to be counted generated by the exclusive-OR module is a signal obtained by performing an exclusive-OR operation on the third transition signal and the second transition signal. The period of the second signal to be counted generated by the second exclusive-OR sub-unit is half of the period of the second transition signal.

7. The source driver chip according to claim 3, wherein, it further includes: a selection module, electrically connected to the counting module, and configured to control the counting module to load the first signal to be counted to be in the first mode or control the counting module to load the second signal to be counted to be in the second mode according to an input signal.

8. The source driver chip according to any one of claims 2 to 7, wherein, it further includes: a logic module, electrically connected between the counting module and the latch signal generation module, and configured to generate first judgment data according to the first data in the first mode and generate second judgment data according to the second data in the second mode; wherein, the latch signal generation module includes: a second switch unit, electrically connected to the logic module, and configured to control the end time of the first delay sub-signal in the first latch signal according to the first judgment data in the first mode and control the end time of the second delay sub-signal in the second latch signal according to the second judgment data in the second mode.

9. A display panel, wherein, it includes a panel main body and a driver chip electrically connected to the panel main body. The driver chip includes: At least two source driver chips as described in any one of claims 1 to 8, each of the source driver chips being configured to generate a target data signal according to the initial data signal and transmit the target data signal to the panel body; A timing control chip, electrically connected to the source driver chip, configured to control the source driver chip to generate the first latch signal in the first mode and to control the source driver chip to generate the second latch signal in the second mode.

10. A driving method for a display panel, characterized in that, for driving the display panel as described in claim 10, comprising: generating the first latch signal in the first mode, the first latch signal including a first delay sub-signal, an end time of the first delay sub-signal in the first latch signal being configured to control latching of the initial data signal, and latching the initial data signal according to the first latch signal; generating the second latch signal in the second mode, the second latch signal including a second delay sub-signal, an end time of the second delay sub-signal in the second latch signal being configured to control latching of the initial data signal, and latching the initial data signal according to the second latch signal; wherein the step of generating the first latch signal in the first mode comprises: generating first data according to a first signal to be counted in the first mode; generating the first latch signal according to the first data; wherein the step of generating second data according to a second signal to be counted in the second mode comprises: generating second data according to a second signal to be counted in the second mode; generating the second latch signal according to the second data.

11. The driving method for a display panel as described in claim 10, characterized in that, further comprising: acquiring, according to an input signal, a first signal to be counted for generating the first latch signal to be in the first mode, or acquiring a second signal to be counted for generating the second latch signal to be in the second mode.

Images