Abnormal display processing method after LVDS signal interruption and liquid crystal display device

Abstract

The invention discloses an abnormal display processing method after LVDS signal interruption and a liquid crystal display device.The method comprises the steps that after LVDS transmission signals are interrupted, gate drive signals output by gate drive units of all rows are pulled down so as to keep the pixel voltage of a current frame scanning completed area; and after the LVDS transmission signal returns to normal, continuing to perform data writing on the row pixels of the remaining non-scanned area of the current frame by using the first clock signal and the second clock signal until all the row pixels are written. By adjusting the pulse time sequence of the first clock signal and the second clock signal, after the LVDS signal is normal, data writing is continued to be performed on the row pixels of the remaining area of the current frame, so that the situation that the pixel data of the completely scanned area of the current frame is written into the row pixels of the uncompletely scanned area of the current frame is avoided, and the scanning efficiency is improved. The problem of abnormal display caused by wrong writing of data in LVDS signals of an existing display device is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of LVDS signal interruption display anomalies of liquid crystal display screens, and particularly relates to an abnormal display processing method after LVDS signal interruption and a liquid crystal display device. Background Art

[0002] Display devices are often affected by static electricity or the surrounding environment, which can cause interruptions in the data signals transmitted from the host to the display screen driver IC. For example, during the process of the host transmitting data to the display screen driver IC through an LVDS (Low Voltage Differential Signaling) interface, it is often affected by static electricity interference or surrounding signals, and data interruptions may occur in the LVDS transmission signal line. At this time, the display screen driver IC cannot receive the correct signal. The existing method is to ground all the gate drive signals output by the GIP, that is, the Gate outputs a low level. When the data transmission is normal, the display screen is scanned again, that is, scanned from the top to the bottom of the display screen. However, since some voltages in the GIP cannot be completely released, the P point voltage of the gate output corresponding to the interruption of the LVDS transmission signal line cannot be pulled down. When the display screen is scanned from the top to the bottom again, since the CK signal is connected to the current corresponding GIP circuit, the current GIP circuit also outputs a high level. At this time, the data signal that originally did not belong to this area (which should originally belong to the top area of the display screen) is written into this area, that is, data is miswritten, resulting in disordered display data on the display screen. In addition, due to the cascaded relationship of the GIP, the misoutput Gate signal will continue to be output, that is, the mischarging will always mischarge data, and at this time, the display screen shows anomalies. Summary of the Invention

[0003] In the existing display device, after the LVDS transmission signal is interrupted, the gate drive signal is pulled low. When normal, it is scanned from the top to the bottom again, resulting in miswriting of data and abnormal display.

[0004] In view of the above problems, an abnormal display processing method after LVDS signal interruption and a liquid crystal display device are proposed. By adjusting the pulse timing of the first clock signal and the second clock signal, when an LVDS signal interruption occurs, the gate drive signal is set to a low level to prevent pixel leakage. After the LVDS signal is normal, data writing continues for the row pixels in the remaining area of the current frame, thereby avoiding writing the pixel data in the area that has been scanned in the current frame into the row pixels that have not been scanned in the current frame, and solving the problem of miswriting of data in the existing display device when the LVDS signal occurs, resulting in abnormal display.

[0005] In a first aspect, an abnormal display processing method after LVDS signal interruption includes: Step 100: After the LVDS transmission signal is interrupted, pull down the gate drive signals output by the gate drive units of all rows to maintain the pixel voltages in the scanned area of the current frame. Step 200: After the LVDS transmission signal resumes normal, continue to write data to the row pixels in the remaining unscanned area of the current frame using the first clock signal and the second clock signal until all row pixels are written. Wherein, the pulse timings of the first clock signal and the second clock signal are opposite.

[0006] Combined with the abnormal display processing method described in the first aspect of the present invention, in a first possible implementation manner, the abnormal display processing method further includes: Step 300: After writing data to the row pixels in the remaining unscanned area is completed, start the next frame of scanning using the start signal: Set the start signal to a high level to start the drive scanning of the next frame.

[0007] Combined with the first possible implementation manner of the first aspect of the present invention, in a second possible implementation manner, the step 200 includes: Step 210: Obtain the pulse level of the first clock signal in the scanned area of the current frame. Step 220: If the last pulse level of the first clock signal in the scanned area of the current frame is a high-level pulse, output the first pulse level in the remaining unscanned area of the current frame as a low level. Step 230: Continue to continuously output pulse levels until all row pixel data in the remaining unscanned area of the current frame is written.

[0008] Combined with the second possible implementation manner of the first aspect of the present invention, in a third possible implementation manner, the step 200 further includes: Step 240: Obtain the pulse level of the second clock signal in the scanned area of the current frame. Step 250: If the last pulse level of the second clock signal in the scanned area of the current frame is a low-level pulse, output the first pulse level in the remaining unscanned area of the current frame as a high level. Step 260: Continue to continuously output pulse levels until all row pixel data in the remaining unscanned area of the current frame is written.

[0009] Combined with the third possible implementation manner of the first aspect of the present invention, in a fourth possible implementation manner, the step 100 includes: Step 110: In the scanned area of the current frame, set the reset signal to a low level.

[0010] Combined with the fourth possible implementation manner of the first aspect of the present invention, in the fifth possible implementation manner, the step 200 further includes: Step 270, after the data writing of the last row of pixels in the remaining unscanned area of the current frame is completed, set the reset signal to a high level to end the driving scan of the current frame.

[0011] In a second aspect, a liquid crystal display device adopts the abnormal display processing method described in the first aspect, and includes: A first timing control unit; A second timing control unit; A control unit; The control unit is electrically connected to the first timing control unit, the second timing control unit, and the third timing control unit; The first timing control unit is configured to output a first driving timing according to the control signal of the control unit, and is used to pull down the gate driving signals output by the gate driving units of all rows after the LVDS transmission signal is interrupted, so as to maintain the pixel voltages of the scanned area of the current frame; The second timing control unit is configured to output a first pulse timing and a second pulse timing to the first clock signal line and the second clock signal line respectively according to the control signal of the control unit, and is used to continue writing data to the row pixels in the remaining unscanned area of the current frame after the LVDS transmission signal returns to normal until all row pixels are written. Wherein, the first pulse timing is opposite to the second pulse timing.

[0012] Combined with the liquid crystal display device described in the second aspect of the present invention, in the first possible implementation manner, the liquid crystal display device further includes: A third timing control unit; The third timing control unit is electrically connected to the control unit, and is used to output a second driving timing to the start signal line after the data writing of the row pixels in the remaining unscanned area is completed, and start the next frame of scan: Set the start signal to a high level to start the driving scan of the next frame.

[0013] Combined with the first possible implementation manner of the second aspect of the present invention, in the second possible implementation manner, the first pulse timing is: If the first clock signal is a high-level pulse at the last pulse level of the scanned area of the current frame, then output the first pulse level of the remaining unscanned area of the current frame as a low level, and continue to continuously output pulse levels until all row pixel data in the remaining unscanned area of the current frame are written.

[0014] Combined with the second possible implementation manner of the first aspect of the present invention, in the third possible implementation manner, the second pulse timing is as follows: If the last pulse level of the area that has been scanned in the current frame of the second clock signal is a low-level pulse, then the first pulse level of the remaining area that has not been scanned in the current frame is output as a high level, and the pulse levels are continuously output until all the row pixel data of the remaining area that has not been scanned in the current frame is written.

[0015] Implementing the abnormal display processing method and the liquid crystal display device of the present invention, by adjusting the pulse timing of the first clock signal and the second clock signal, when the LVDS signal is interrupted, the gate driving signal is set to a low level to prevent pixel leakage, and after the LVDS signal is normal, the data writing of the row pixels in the remaining area of the current frame is continued, thereby avoiding writing the pixel data of the area that has been scanned in the current frame into the row pixels that have not been scanned in the current frame, and solving the problem of incorrect data writing in the existing display device when the LVDS signal appears, resulting in abnormal display. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 is a front scan schematic diagram of a liquid crystal display device in the prior art solution; Figure 2 is a schematic circuit diagram of a gate driving circuit of a liquid crystal display device in the prior art solution; Figure 3 is a driving timing diagram of a gate driving circuit of a liquid crystal display device in the prior art solution; Figure 4 is a driving timing diagram of abnormal processing of a liquid crystal display device in the prior art solution; Figure 5 is a driving timing diagram of abnormal processing of a liquid crystal display device in the present application; Figure 6 is a schematic flowchart of a specific embodiment of an abnormal display processing method after an LVDS signal interruption in the present application; Figure 7 is Figure 6 a schematic flowchart of a specific embodiment of step 200 in; Figure 8 is Figure 7 a schematic flowchart of a specific embodiment after step 230 in; Figure 9 It is a schematic diagram of a module structure of a liquid crystal display device in the present application. Specific embodiments

[0018] The following will clearly and completely describe the technical solutions in the present invention in conjunction with the accompanying drawings in the invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the description of the present invention in this specification are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0020] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0021] It should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

[0022] In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0023] In the existing display device, after the LVDS transmission signal is interrupted, the gate drive signal is pulled low. When normal, it scans from the top to the bottom again, resulting in incorrect data writing and display anomalies. For example Figures 1-4 , Figure 1 is a schematic diagram of the normal scan of the liquid crystal display device in the prior art solution, Figure 2It is a schematic diagram of the gate driving circuit of the liquid crystal display device in the prior art solution. Figure 3 It is a driving timing diagram of the gate driving circuit of the liquid crystal display device in the prior art solution. Figure 4 It is a driving timing diagram of the abnormal handling of the liquid crystal display device in the prior art solution; in the prior art, the Gate driving signals output by all gate driving circuits (GIP) are pulled to the low level, i.e., the VGL potential, to ensure that the pixel voltages of the current screen do not leak electricity. After the data is normal, the scanning starts from the first row to the last row at the bottom again. At this time, due to the leakage of point P, the data in the area to be written is wrongly charged, and the display screen shows an abnormality. In addition, since the complete writing of the current frame of data is not completed, the display screen may also show the phenomenon of split screen display.

[0024] In view of the above problems, an abnormal display handling method and a liquid crystal display device after an LVDS signal interruption are proposed.

[0025] In the first aspect, an abnormal display handling method after an LVDS signal interruption, as Figure 6 , Figure 6 is a schematic flowchart of a specific embodiment of an abnormal display handling method after an LVDS signal interruption in the present application, including: Step 100, after the LVDS transmission signal is interrupted, pull down the gate driving signals output by the gate driving units of all rows to maintain the pixel voltages of the scanned areas of the current frame; Step 200, after the LVDS transmission signal returns to normal, continue to write data to the row pixels of the remaining unscanned areas of the current frame by using the first clock signal (CK1) and the second clock signal (CK2) until all row pixels are written; wherein, the pulse timings of the first clock signal (CK1) and the second clock signal (CK2) are opposite. By adjusting the pulse timings of the first clock signal (CK1) and the second clock signal (CK2), when an LVDS signal interruption occurs, the gate driving signal is set to the low level to prevent pixel leakage, and after the LVDS signal is normal, continue to write data to the row pixels of the remaining areas of the current frame, thereby avoiding writing the pixel data of the scanned areas of the current frame to the row pixels of the unscanned areas of the current frame, and solving the problem of abnormal display caused by wrong data writing in the existing display device when an LVDS signal appears.

[0026] In a preferred embodiment, the abnormal display handling method further includes: Step 300, after the data writing to the row pixels of the remaining unscanned areas is completed, use the start signal (STV) to start the next frame of scanning and set the start signal (STV) to the high level to start the driving scan of the next frame. After the current frame of scanning is completed, the start signal (STV) outputs a high level to start the driving scan of the next frame.

[0027] In a preferred embodiment, as Figure 7 , Figure 7 is Figure 6 a schematic flow diagram of a specific embodiment of step 200 in ; step 200 includes step 210, obtaining the pulse level of the first clock signal (CK1) in the scanned area of the current frame; step 220, if the last pulse level of the first clock signal (CK1) in the scanned area of the current frame is a high-level pulse, then output the first pulse level of the remaining unscanned area of the current frame as a low level; step 230, continue to continuously output pulse levels until all the row pixel data of the remaining unscanned area of the current frame is written, as Figure 5 , Figure 5 is the driving timing diagram of the abnormal handling of the liquid crystal display device in the present application.

[0028] In a preferred embodiment, as Figure 8 , Figure 8 is Figure 7 a schematic flow diagram of a specific embodiment after step 230 in ; step 200 further includes: step 240, obtaining the pulse level of the second clock signal (CK2) in the scanned area of the current frame; step 250, if the last pulse level of the second clock signal (CK2) in the scanned area of the current frame is a low-level pulse, then output the first pulse level of the remaining unscanned area of the current frame as a high level; step 260, continue to continuously output pulse levels until all the row pixel data of the remaining unscanned area of the current frame is written, as Figure 5 .

[0029] In Figure 5 , when the LVDS transmission signal is interrupted, the start signal (STV), the reset signal (RST), the first clock signal (CK1), and the second clock signal (CK2) are all at a low level. When the LVDS transmission signal is normal, the remaining rows are scanned using the first clock signal (CK1) and the second clock signal (CK2).

[0030] In a preferred embodiment, step 100 includes: step 110, setting the reset signal (RST) to a low level in the scanned area of the current frame.

[0031] In a preferred embodiment, step 200 further includes step 270, after the data of the last row of pixels in the remaining unscanned area of the current frame is written, setting the reset signal (RST) to a high level to end the driving scan of the current frame.

[0032] After the data is normal, the first n-1 still sets the reset signal (RST) to low level and continues to scan the remaining lines of the current frame. After the scanning of the remaining lines is completed, the reset signal (RST) is set to high level to end the driving scan of the current frame.

[0033] In a second aspect, a liquid crystal display device, such as Figure 9 , Figure 9 is a schematic diagram of a module structure of a liquid crystal display device in the present application. Using the abnormal display processing method of the first aspect, it includes a first timing control unit, a second timing control unit, and a control unit; the control unit is electrically connected to the first timing control unit, the second timing control unit, and the third timing control unit; the first timing control unit is used to output a first driving timing according to the control signal of the control unit, and is used to pull down the gate driving signals output by the gate driving units of all rows after the LVDS transmission signal is interrupted to maintain the pixel voltages in the scanned area of the current frame; the second timing control unit is used to output a first pulse timing and a second pulse timing to the first clock signal (CK1) line and the second clock signal (CK2) line respectively according to the control signal of the control unit, and is used to continue to write data to the row pixels in the remaining unscanned area of the current frame after the LVDS transmission signal returns to normal until all row pixels are written. Among them, the first pulse timing is opposite to the second pulse timing.

[0034] Specifically, the liquid crystal display device further includes a third timing control unit; the third timing control unit is electrically connected to the control unit and is used to output a second driving timing to the start signal (STV) line after the data writing of the row pixels in the remaining unscanned area is completed to start the scanning of the next frame: set the start signal (STV) to high level to start the driving scan of the next frame.

[0035] Specifically, the first pulse timing is: if the last pulse level of the first clock signal (CK1) in the scanned area of the current frame is a high-level pulse, then the first pulse level of the remaining unscanned area of the current frame is output as a low level, and the pulse levels are continuously output until all row pixel data in the remaining unscanned area of the current frame are written.

[0036] Specifically, the second pulse timing is: if the last pulse level of the second clock signal (CK2) in the scanned area of the current frame is a low-level pulse, then the first pulse level of the remaining unscanned area of the current frame is output as a high level, and the pulse levels are continuously output until all row pixel data in the remaining unscanned area of the current frame are written.

[0037] An abnormal display processing method and a liquid crystal display device for implementing the present invention adjust the pulse timings of a first clock signal (CK1) and a second clock signal (CK2). When an LVDS signal interruption occurs, the gate driving signal is set to a low level to prevent pixel leakage. After the LVDS signal is normal, data writing to the row pixels in the remaining area of the current frame continues, thereby avoiding writing pixel data in the scanned area of the current frame to the row pixels not yet scanned in the current frame, and solving the problem of abnormal display caused by incorrect data writing in the LVDS signal in the existing display device.

[0038] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for processing abnormal display after LVDS signal interruption, characterized in that: include: Step 100: after the LVDS transmission signal is interrupted, the gate driving signals output by the gate driving units of all rows are pulled down to maintain the pixel voltage of the area that has been scanned in the current frame; Step 200: After the LVDS transmission signal returns to normal, continue to write data to the row pixels in the remaining unscanned area of ​​the current frame using the first clock signal and the second clock signal until the writing of the remaining row pixels is completed; The pulse timing of the first clock signal is opposite to that of the second clock signal.

2. The abnormal display processing method after LVDS signal interruption according to claim 1 is characterized in that: The abnormal display processing method also includes: Step 300: After the data writing of the row pixels in the remaining unscanned area is completed, the next frame scan is started using a start signal: Set the start signal to a high level to start the drive scan for the next frame.

3. The abnormal display processing method after LVDS signal interruption according to claim 2 is characterized in that: The step 200 comprises: Step 210, obtaining the pulse level of the first clock signal in the scanned area of ​​the current frame; Step 220: If the last pulse level of the first clock signal in the scanned area of ​​the current frame is a high level pulse, the first pulse level of the remaining unscanned area of ​​the current frame is output as a low level; Step 230 , continue to output the pulse level continuously until the pixel data of all rows in the remaining unscanned area of ​​the current frame are written completely.

4. The abnormal display processing method after LVDS signal interruption according to claim 3 is characterized in that: The step 200 further includes: Step 240, obtaining the pulse level of the second clock signal in the scanned area of ​​the current frame; Step 250: If the last pulse level of the second clock signal in the scanned area of ​​the current frame is a low level pulse, the first pulse level of the remaining unscanned area of ​​the current frame is output as a high level; Step 260: Continue to output the pulse level continuously until the pixel data of all rows in the remaining unscanned area of ​​the current frame are written.

5. The abnormal display processing method after LVDS signal interruption according to claim 4 is characterized in that: The step 100 comprises: Step 110: After the scanning area of ​​the current frame is completed, the reset signal is set to a low level.

6. The abnormal display processing method after LVDS signal interruption according to claim 5 is characterized in that: The step 200 further includes: Step 270: After the data writing of the last row of pixels in the remaining unscanned area of ​​the current frame is completed, the reset signal is set to a high level to end the current frame drive scan.

7. A liquid crystal display device, using the abnormal display processing method after LVDS signal interruption according to any one of claims 1 to 6, characterized in that: include: a first timing control unit; a second timing control unit; Control unit; The control unit is electrically connected to the first timing control unit, the second timing control unit, and the third timing control unit; The first timing control unit is used to output a first driving timing according to a control signal of the control unit, and is used to pull down the gate driving signals output by the gate driving units of all rows after the LVDS transmission signal is interrupted, so as to maintain the pixel voltage of the area that has completed scanning in the current frame; The second timing control unit is used to output the first pulse timing and the second pulse timing to the first clock signal line and the second clock signal line respectively according to the control signal of the control unit, and is used to continue to write data to the row pixels of the remaining unscanned area of ​​the current frame after the LVDS transmission signal returns to normal, until all row pixels are written. Wherein, the first pulse timing is opposite to the second pulse timing.

8. The liquid crystal display device according to claim 7, characterized in that: The liquid crystal display device further comprises: A third timing control unit; The third timing control unit is electrically connected to the control unit, and is used to output a second driving timing to the start signal line to start the next frame scan after the data writing of the row pixels in the remaining unscanned area is completed: Set the start signal to a high level to start the drive scan for the next frame.

9. The liquid crystal display device according to claim 8, characterized in that: The first pulse timing is: If the last pulse level of the first clock signal in the scanned area of ​​the current frame is a high-level pulse, the first pulse level of the remaining unscanned area of ​​the current frame is output as a low level, and the pulse level is continuously output until all row pixel data of the remaining unscanned area of ​​the current frame is written.

10. The liquid crystal display device according to claim 9, characterized in that: The second pulse timing is: If the last pulse level of the second clock signal in the scanned area of ​​the current frame is a low-level pulse, the first pulse level of the remaining unscanned area of ​​the current frame is output as a high level, and the pulse level is continuously output until all row pixel data of the remaining unscanned area of ​​the current frame is written.

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