Pixel unit, display panel and display device

Abstract

The invention provides a pixel unit, a display panel and a display device.The pixel unit comprises a pixel electrode, a storage capacitor, a first switching circuit, a switching output circuit and an overturning circuit, when a previous frame is scanned line by line, the pixel unit of the current line can receive a line opening signal and a data signal, the overturning circuit can switch to output a first level signal, and the first level signal is switched to output a second level signal; at the moment, the first switching circuit and the switching output circuit are correspondingly switched, a first driving signal is output to a pixel electrode, in next frame line-by-line scanning, the overturning circuit is switched to output a second level signal, and at the moment, the first switching circuit and the switching output circuit are correspondingly switched; the pixel electrode can form driving voltage with the polarity opposite to that of a common electrode layer on the color film substrate in the front frame and the rear frame to drive a liquid crystal layer, polarity switching is achieved through switch switching, and charging and discharging power consumption of a storage capacitor is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of display panels, and particularly relates to a pixel unit, a display panel, and a display device. Background Art

[0002] Liquid crystal display panels have advantages such as high resolution, accurate color reproduction, simple structure, and high stability. Traditional liquid crystal display panels control the amount of polarized light passing through by controlling the deflection of liquid crystal molecules to achieve different gray-scale displays.

[0003] In a liquid crystal display panel, voltage is applied across the liquid crystal layer to drive the rotation of liquid crystal molecules. If a single-direction electric field is applied to the liquid crystal molecules for a long time, the liquid crystal molecules will undergo polarization. After the liquid crystal molecules are polarized, it will cause changes in the response characteristics of the liquid crystal, such as slower response speed, uneven display, etc. Therefore, polarity switching is required to avoid the polarization of liquid crystal molecules.

[0004] During polarity switching, the storage capacitor in the pixel unit needs to perform a large-scale charge and discharge operation to ensure that the liquid crystal pixel is displayed with the correct polarity. The large-scale charge and discharge operation increases the circuit power consumption. Summary of the Invention

[0005] An object of the present invention is to provide a pixel unit, aiming to solve the problem of high power consumption during polarity switching in traditional pixel units.

[0006] A first aspect of an embodiment of the present invention provides a pixel unit, including: A pixel electrode; A storage capacitor; A first switching circuit, connected to the data line and the storage capacitor respectively. The first switching circuit is used to transmit the data signal on the data line to the second end of the storage capacitor when receiving a first level signal, or transmit the data signal to the first end of the storage capacitor when receiving a second level signal, or turn off when receiving a row-off signal; A switching output circuit, connected to the common electrode terminal, the storage capacitor, and the pixel electrode respectively. The switching output circuit is used to transmit the common electrode voltage of the common electrode terminal to the first end of the storage capacitor when receiving the first level signal, or transmit the common electrode voltage to the second end of the storage capacitor and output the voltage at the first end of the storage capacitor to the pixel electrode when receiving the second level signal or the row-off signal; A flip - flop circuit, which is respectively connected to the scan line, the first switching circuit, and the switching output circuit. The flip - flop circuit is configured to output the first level signal or the second level signal when receiving the row enable signal transmitted by the scan line, and switch the polarity of the output level when receiving the row enable signal again, or output the row disable signal when receiving the row disable signal transmitted by the scan line.

[0007] Optionally, the first switching circuit includes a first transistor and a second transistor; The first end of the first transistor, the first end of the second transistor are connected to the data line. The second end of the first transistor is connected to the first end of the storage capacitor, and the second end of the second transistor is connected to the second end of the storage capacitor. The control ends of the first transistor and the second transistor are commonly connected to form the control end of the first switching circuit.

[0008] Optionally, the switching output circuit includes: A switch circuit, the input end of the switch circuit is connected to the output end of the flip - flop circuit. The switch circuit is configured to be triggered to conduct when receiving the third - level signal of the pulse control signal, or be triggered to turn off when receiving the fourth - level signal of the pulse control signal; A bias circuit, which is connected to the output end of the switch circuit. The bias circuit is configured to bias the voltage of the output end of the switch circuit to a preset potential when the switch circuit is in the off state; A second switching circuit, which is respectively connected to the common electrode terminal, the switch circuit, the bias circuit, and the storage capacitor. The second switching circuit is configured to transmit the common electrode voltage to the first end of the storage capacitor when receiving the first level signal, or transmit the common electrode voltage to the second end of the storage capacitor when receiving the preset potential; An output circuit, which is connected between the first end of the storage capacitor and the pixel electrode. The output circuit is also connected to the output end of the switch circuit. The output circuit is configured to be triggered to turn off when receiving the first level signal, or be triggered to conduct and transmit the voltage of the first end of the storage capacitor to the pixel electrode when receiving the preset potential; The period time of the pulse control signal is two - frame durations. The pulse control signal within each period time is composed of a third - level signal and a fourth - level signal. The phase of the third - level signal is the same as the phase of the row enable signal in the previous frame within the two - frame durations.

[0009] Optionally, the switch circuit includes a third transistor; The first end of the third transistor forms the input end of the switching circuit, the control end of the third transistor is used to receive the pulse control signal, and the second end of the third transistor forms the output end of the switching circuit.

[0010] Optionally, the bias circuit includes a bias resistor; The first end of the bias resistor is respectively connected to the output end of the switching circuit, the control end of the output circuit, and the control end of the second switching circuit, and the second end of the bias resistor is used to input a preset potential.

[0011] Optionally, the second switching circuit includes a fourth transistor and a fifth transistor; The first end of the fourth transistor, the first end of the fifth transistor are connected to the common electrode terminal, the second end of the fourth transistor is connected to the second end of the storage capacitor, the second end of the fifth transistor is connected to the first end of the storage capacitor, and the control ends of the fourth transistor and the fifth transistor are connected to form the control end of the second switching circuit.

[0012] Optionally, the output circuit includes a sixth transistor; The first end of the sixth transistor is connected to the first end of the storage capacitor, the second end of the sixth transistor is connected to the pixel electrode, and the control end of the sixth transistor forms the control end of the output circuit.

[0013] Optionally, the flip circuit includes a seventh transistor, an eighth transistor, and a ninth transistor; The first ends of the seventh transistor and the eighth transistor are connected to the scan line, the second ends of the seventh transistor and the ninth transistor are commonly connected to form the output end of the flip circuit, the second end of the eighth transistor is connected to the control end of the ninth transistor, the control ends of the seventh transistor and the eighth transistor are used to input pulse control signals, and the first end of the ninth transistor is used to input the first level signal.

[0014] A second aspect of the embodiments of the present invention provides a display panel, including a plurality of scan lines, a plurality of data lines, and a plurality of pixel units as described above, and the pixel units are respectively connected to one of the scan lines and one of the data lines.

[0015] A third aspect of the embodiments of the present invention provides a display device, including a driving circuit of the display panel and the display panel as described above, and the driving circuit of the display panel is connected to the display panel.

[0016] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The above pixel unit includes a pixel electrode, a storage capacitor, a first switching circuit, a switching output circuit, and a flip circuit. During the previous frame-by-frame scan, the pixel unit of the current row can receive a row enable signal and a data signal, and the flip circuit can switch and output a first-level signal. At this time, the first switching circuit and the switching output circuit correspondingly switch and output a first driving signal to the pixel electrode. And in the next frame-by-frame scan, the flip circuit switches and outputs a second-level signal. At this time, the first switching circuit and the switching output circuit correspondingly switch and output a second driving signal with the opposite polarity to the first driving signal to the pixel electrode. The pixel electrode can form driving voltages with opposite polarities with the common electrode layer on the color filter substrate in the front and back two frames to drive the liquid crystal layer. The polarity switching is realized through the switch switching, reducing the charging and discharging power consumption of the storage capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 FIG. is a schematic structural diagram of a display panel provided in Embodiment 1 and Embodiment 4 of the present invention; Figure 2 FIG. is a schematic structural diagram of a pixel unit provided in Embodiment 1 of the present invention; Figure 3 FIG. is a schematic signal timing diagram of a pixel unit provided in Embodiment 1 of the present invention; Figure 4 FIG. is a schematic structural diagram of a pixel unit provided in Embodiment 2 of the present invention; Figure 5 FIG. is a schematic signal timing diagram of a pixel unit provided in Embodiment 2 and Embodiment 3 of the present invention; Figure 6 FIG. is a schematic circuit diagram of a pixel unit provided in Embodiment 3 of the present invention; Figure 7 FIG. is a schematic structural diagram of a display device provided in Embodiment 5 of the present invention.

[0018] Among them, the reference numerals in the figures are as follows: 100, display panel; 200, driving circuit of the display panel; 210, source driving circuit; 220, gate driving circuit; 230, timing controller; 10, pixel unit, 11, pixel electrode; 12, first switching circuit; 13, switching output circuit; 14, flip circuit; 131, switching circuit; 132, bias circuit; 133, second switching circuit; 134, output circuit; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; Cst, storage capacitor; S, data line; G, scan line; t11, the first time period of the first frame; t12, the second time period of the first frame; t21, the first time period of the second frame; t22, the second time period of the second frame; Vgate, row scan signal; Vdata, data signal; Vcom, common electrode voltage; VG, row enable signal; VL, row disable signal; V1, first level signal; V2, second level signal; V3, third level signal; V4, fourth level signal; Vref, preset potential; Ctr1, output signal of the flip - flop circuit; Ctr2, pulse control signal; Vout, output signal of the output circuit. Detailed implementation manners

[0019] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0020] Among them, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more, unless otherwise specifically defined.

[0021] Embodiment 1 A first aspect of the embodiments of the present invention provides a pixel unit 10, as Figure 1 shown, the pixel units 10 are arranged in an array on the array substrate of the display panel 100. The array substrate further includes a plurality of scan lines G, a plurality of data lines S and a common electrode terminal. The common electrode terminal has a common electrode voltage Vcom1. Each pixel unit 10 is respectively connected to a data line S and a scan line G. The display panel 100 further includes a color filter substrate disposed opposite to the array substrate and a liquid crystal layer disposed between the array substrate and the color filter substrate. As Figure 2 shown, the pixel unit 10 includes a pixel electrode 11. A color filter layer and a common electrode layer are disposed on the color filter substrate. The common electrode layer has a second common electrode voltage. The plurality of scan lines G are used to input the row enable signal VG to the pixel units 10 of each row sequentially, and when the pixel units 10 of each row receive the row enable signal VG, the data line S outputs a corresponding data signal Vdata to the pixel units 10 of the corresponding row. The pixel unit 10 generates a corresponding driving signal based on the received row enable signal VG and data signal Vdata to the pixel electrode 11. The driving signal input to the pixel electrode 11 and the second common electrode voltage form a driving voltage, and drive the liquid crystal in the liquid crystal layer to deflect, and cooperate with the color filter layer to control the pixel unit 10 to display corresponding image information.

[0022] In an optional embodiment, the common electrode voltage Vcom is equal to the voltage of the second common electrode voltage, such as 5V, 8V, etc.

[0023] Wherein, opposite to the row enable signal VG is the row disable signal VL. During progressive scanning, multiple scan lines G sequentially receive the row enable signal VG according to the corresponding timing, and the other rows that are not selected for scanning receive the row disable signal VL. The row enable signal VG and the row disable signal VL constitute the row scan signal Vgate.

[0024] In order to reduce the power consumption of the pixel unit 10, in this embodiment, as Figure 2 shown, the pixel unit 10 includes: A pixel electrode 11; A storage capacitor Cst; A first switching circuit 12, which is respectively connected to the data line S and the storage capacitor Cst. The first switching circuit 12 is configured to transfer the data signal Vdata on the data line S to the second end of the storage capacitor Cst when receiving the first level signal V1, or transfer the data signal Vdata to the first end of the storage capacitor Cst when receiving the second level signal V2, or turn off when receiving the row disable signal VL. A switching output circuit 13, which is respectively connected to the common electrode terminal, the storage capacitor Cst, and the pixel electrode 11. The switching output circuit 13 is configured to transfer the common electrode voltage Vcom of the common electrode terminal to the first end of the storage capacitor Cst when receiving the first level signal V1, or transfer the common electrode voltage Vcom to the second end of the storage capacitor Cst and output the voltage at the first end of the storage capacitor Cst to the pixel electrode 11 when receiving the second level signal V2 or the row disable signal VL. An inversion circuit 14, which is respectively connected to the scan line G, the first switching circuit 12, and the switching output circuit 13. The inversion circuit 14 is configured to output the first level signal V1 or the second level signal V2 when receiving the row enable signal VG transmitted by the scan line G, and switch the polarity of the output level when receiving the row enable signal VG again, or output the row disable signal VL when receiving the row disable signal VL transmitted by the scan line G.

[0025] In this embodiment, as Figure 3 shown, the first level signal V1 and the second level signal V2 are high and low level signals with opposite polarities to each other.

[0026] For each pixel unit 10, each frame includes a first period and a second period. In the first period, the row enable signal VG is input to achieve progressive enabling, and in the second period, the row disable signal VL is input. Among them, in each frame, the first period of a single pixel unit 10 is shorter than the duration of the second period.

[0027] The first switching circuit 12 has an input terminal, a first output terminal, and a second output terminal. The input terminal of the first switching circuit 12 is connected to the data line S and is used to input a data signal Vdata. The first output terminal of the first switching circuit 12 is connected to the first end of the storage capacitor Cst, and the second output terminal of the first switching circuit 12 is connected to the second end of the storage capacitor Cst.

[0028] The switching output circuit 13 has an input terminal, a first output terminal, a second output terminal, and a third output terminal. The input terminal of the switching output circuit 13 is connected to the common electrode terminal and is used to input a common electrode voltage Vcom. The first output terminal of the switching output circuit 13 is connected to the first end of the storage capacitor Cst, the second output terminal of the switching output circuit 13 is connected to the second end of the storage capacitor Cst, and the third output terminal of the switching output circuit 13 is connected to the pixel electrode 11.

[0029] Wherein, it is assumed that in the first time period t11 of the first frame, the flip circuit 14 of the pixel unit 10 of the current row receives the row enable signal VG, and the output signal Ctr1 of the flip circuit 14 is the first level signal V1. At this time, after receiving the first level signal V1, the first switching circuit 12 is triggered to connect its input terminal and the second output terminal, and transmits the data signal Vdata to the second end of the storage capacitor Cst. After receiving the first level signal V1, the switching output circuit 13 is triggered to connect its input terminal and the first output terminal, and transmits the common electrode voltage Vcom to the first end of the storage capacitor Cst. At this time, the voltage difference between the first end and the second end of the storage capacitor Cst is: ΔV = Vcom - Vdata; In the second time period t12 of the first frame, the flip circuit 14 of the pixel unit 10 of the current row receives the row disable signal VL. At this time, the flip circuit 14 switches to output the row disable signal VL. After receiving the row disable signal VL, the first switching circuit 12 remains in the off state. After receiving the row disable signal VL, the switching output circuit 13 is triggered to connect its input terminal and the second output terminal, and connect the first end of the storage capacitor Cst and the pixel electrode 11, and transmits the common electrode voltage Vcom to the second end of the storage capacitor Cst, and outputs the voltage of the first end of the storage capacitor Cst to the pixel electrode 11. At this time, since the voltage difference between the first end and the second end of the storage capacitor Cst is Vcom - Vdata, and the voltage of the second end of the storage capacitor Cst is Vcom, therefore, the voltage of the first end of the storage capacitor Cst at this time is 2*Vcom - Vdata, that is, the output signal Vout of the switching output circuit 13 is 2*Vcom - Vdata.

[0030] The pixel electrode 11 and the common electrode layer of the color filter layer form a first driving voltage, and the first driving voltage is: VData1 = 2 * Vcom - Vdata - Vcom; That is, the first driving voltage VData1 is -(Vdata - Vcom). For example, assuming that the common electrode voltage Vcom and the second common electrode voltage of the color filter layer are 8V, and the data signal Vdata is 10V, the first driving voltage is -2V at this time.

[0031] When the current frame scan ends and switches to the second frame, in the first period t21 of the second frame, the flip circuit 14 receives another row enable signal VG, and the output signal Ctr1 of the flip circuit 14 switches to the second level signal V2 and is output to the first switching circuit 12 and the switching output circuit 13. At this time, the first switching circuit 12 switches to connect its input terminal and the first output terminal and transmits the data signal Vdata of the current frame to the first end of the storage capacitor Cst. The switching output circuit 13 switches to connect its input terminal and the second output terminal and transmits the common electrode voltage Vcom to the second end of the storage capacitor Cst, and outputs the voltage at the first end of the storage capacitor Cst to the pixel electrode 11. At this time, the voltage difference between the first end and the second end of the storage capacitor Cst is: ΔV = Vdata - Vcom; In the second period t22 of the second frame, the flip circuit 14 receives the row disable signal VL and converts it to output the row disable signal VL. The first switching circuit 12 is triggered to turn off. After receiving the row disable signal VL, the switching output circuit 13 maintains the connection between its input terminal and the second output terminal. The voltage at the first end of the storage capacitor Cst is maintained at Vdata, and after receiving the row disable signal VL, it connects the first end of the storage capacitor Cst and the pixel electrode 11, and outputs the voltage at the first end of the storage capacitor Cst to the pixel electrode 11. The output signal Vout of the switching output circuit 13 is Vdata, and the pixel electrode 11 and the common electrode layer of the color filter layer form a second driving voltage. The second driving voltage is: VData1 = Vdata - Vcom; For example, assuming that the common electrode voltage Vcom and the second common electrode voltage of the color filter layer are 8V, and the data signal Vdata is 10V, the second driving voltage is 2V at this time. The absolute values of the first driving voltage and the second driving voltage are equal, and the polarities are opposite.

[0032] And so on. In subsequent odd frames, the pixel unit 10 works according to the working timing and signal flow direction of the first frame and switches to output the first driving voltage. In subsequent even frames, the pixel unit 10 works according to the working timing and signal flow direction of the second frame and switches to output the second driving voltage with the opposite polarity.

[0033] By setting the inversion circuit 14, the first switching circuit 12, and the switching output circuit 13, it is possible to achieve a frame cycle with two adjacent frames as one frame. During the frame scanning process, the polarity on the data line S can remain unchanged, and the polarity of the driving voltage of the liquid crystal layer can be switched during the frame cycle, reducing the polarization of the liquid crystal layer and improving the working reliability of the liquid crystal layer.

[0034] Among them, the inversion circuit 14, the first switching circuit 12, and the switching output circuit 13 can adopt corresponding switching circuits 131, switching devices, etc. The inversion circuit 14 can adopt structures such as latches, flip-flops, logic gates, etc., and the specific structure is not limited.

[0035] The beneficial effects of the embodiment of the present invention compared with the prior art are as follows: The above-mentioned pixel unit 10 includes a pixel electrode 11, a storage capacitor Cst, a first switching circuit 12, a switching output circuit 13, and an inversion circuit 14. During the previous frame-by-frame scanning, the pixel unit 10 of the current row can receive the row enable signal VG and the data signal Vdata. The inversion circuit 14 can switch and output the first level signal V1. At this time, the first switching circuit 12 and the switching output circuit 13 switch correspondingly and output the first driving signal to the pixel electrode 11. In the next frame-by-frame scanning, the inversion circuit 14 switches and outputs the second level signal V2. At this time, the first switching circuit 12 and the switching output circuit 13 switch correspondingly and output the second driving signal with the opposite polarity to the first driving signal to the pixel electrode 11. The pixel electrode 11 can form driving voltages with opposite polarities with the common electrode layer on the color filter substrate in the front and back two frames to drive the liquid crystal layer. The polarity switching is realized through switch switching, reducing the charge and discharge power consumption of the storage capacitor Cst.

[0036] Embodiment 2 In an alternative embodiment, the switching output circuit 13 includes: A switching circuit 131, the input end of the switching circuit 131 is connected to the output end of the inversion circuit 14. The switching circuit 131 is used to be triggered to conduct when receiving the third level signal V3 of the pulse control signal Ctr2, or to be triggered to turn off when receiving the fourth level signal V4 of the pulse control signal Ctr2; A bias circuit 132, connected to the output end of the switching circuit 131. The bias circuit 132 is used to bias the voltage at the output end of the switching circuit 131 to the preset potential Vref when the switching circuit 131 is in the off state; A second switching circuit 133, respectively connected to the common electrode terminal, the switching circuit 131, the bias circuit 132, and the storage capacitor Cst. The second switching circuit 133 is used to transmit the common electrode voltage Vcom to the first end of the storage capacitor Cst when receiving the first level signal V1, or to transmit the common electrode voltage Vcom to the second end of the storage capacitor Cst when receiving the preset potential Vref; The output circuit 134 is connected between the first end of the storage capacitor Cst and the pixel electrode 11. The output circuit 134 is also connected to the output end of the switch circuit 131. The output circuit 134 is configured to be triggered to turn off when receiving the first-level signal V1, or to be triggered to turn on when receiving the preset potential Vref and transmit the voltage at the first end of the storage capacitor Cst to the pixel electrode 11; The period of the pulse control signal Ctr2 is two frame durations. The pulse control signal Ctr2 within each period consists of a third-level signal V3 and a fourth-level signal V4. The phase of the third-level signal V3 is the same as the phase of the row enable signal VG in the previous frame within the two frame durations.

[0037] In this embodiment, the second switching circuit 133 has an input end, a first output end, and a second output end. The input end of the first switching circuit 12 is connected to the common electrode terminal and is configured to input the common electrode voltage Vcom. The first output end of the second switching circuit 133 is connected to the first end of the storage capacitor Cst, and the second output end of the second switching circuit 133 is connected to the second end of the storage capacitor Cst.

[0038] Assume that in the first time period t11 of the first frame, the flip circuit 14 of the pixel unit 10 in the current row receives the row enable signal VG, and the output signal Ctr1 of the flip circuit 14 is the first-level signal V1. At this time, after receiving the first-level signal V1, the first switching circuit 12 is triggered to connect its input end and the second output end, and transmit the data signal Vdata to the second end of the storage capacitor Cst. When the switch circuit 131 receives the first-level signal V1, at this time the pulse control signal Ctr2 is the third-level signal V3, the switch circuit 131 is triggered to turn on, and transmit the first-level signal V1 to the second switching circuit 133 and the output circuit 134. The output circuit 134 is triggered to turn off, and the second switching circuit 133 is triggered to connect its input end and the first output end, and transmit the common electrode voltage Vcom to the first end of the storage capacitor Cst. At this time, the pressure difference between the first end and the second end of the storage capacitor Cst is: ΔV = Vcom - Vdata; In the second period t12 of the first frame, the inversion circuit 14 of the pixel unit 10 in the current row receives the row-off signal VL. At this time, the inversion circuit 14 switches to output the row-off signal VL. After receiving the row-off signal VL, the first switching circuit 12 remains in the off state. At this time, the switching circuit 131 receives the fourth-level signal V4, and the switching circuit 131 is triggered to turn off. The bias circuit 132 biases the control terminal of the second switching circuit 133 and the control terminal of the output circuit 134 to the preset potential Vref. The second switching circuit 133 is triggered to connect its input terminal and the second output terminal, and transmits the common electrode voltage Vcom to the second end of the storage capacitor Cst. The output circuit 134 connects the first end of the storage capacitor Cst and the pixel electrode 11, and outputs the voltage at the first end of the storage capacitor Cst to the pixel electrode 11. At this time, since the voltage difference between the first end and the second end of the storage capacitor Cst is Vcom - Vdata, and the voltage at the second end of the storage capacitor Cst is Vcom, therefore, the voltage at the first end of the storage capacitor Cst at this time is 2*Vcom - Vdata.

[0039] The pixel electrode 11 and the common electrode layer of the color filter layer form the first driving voltage, and the first driving voltage is: VData1 = 2*Vcom - Vdata - Vcom; That is, the first driving voltage VData1 is -(Vdata - Vcom). For example, assuming that the common electrode voltage Vcom and the second common electrode voltage of the color filter layer are 8V, and the data signal Vdata is 10V, the first driving voltage at this time is -2V.

[0040] When the current frame scan ends and switches to the second frame, in the first period t21 of the second frame, the inversion circuit 14 receives another row-on signal VG. The inversion circuit 14 switches to output the second-level signal V2 to the first switching circuit 12 and the switching output circuit 13. At this time, the first switching circuit 12 switches to connect its input terminal and the first output terminal and transmits the data signal Vdata of the current frame to the first end of the storage capacitor Cst. The switching circuit 131 continues to receive the fourth-level signal V4 and remains in the off state. At this time, the bias circuit 132 biases the control terminal of the second switching circuit 133 and the control terminal of the output circuit 134 to the preset potential Vref. The second switching circuit 133 is triggered to connect its input terminal and the second output terminal, and transmits the common electrode voltage Vcom to the second end of the storage capacitor Cst. The output circuit 134 connects the first end of the storage capacitor Cst and the pixel electrode 11, and outputs the voltage at the first end of the storage capacitor Cst to the pixel electrode 11. The voltage difference between the first end and the second end of the storage capacitor Cst is: ΔV = Vdata - Vcom; In the second time period t22 of the second frame, the inversion circuit 14 receives the row-off signal VL and converts and outputs the row-off signal VL. The first switching circuit 12 is triggered to turn off. The switching circuit 131 maintains the reception of the fourth-level signal V4 and remains in the off state. At this time, the bias circuit 132 biases the control terminal of the second switching circuit 133 and the control terminal of the output circuit 134 to the preset potential Vref. The second switching circuit 133 continues to transmit the common electrode voltage Vcom to the second end of the storage capacitor Cst. The output circuit 134 continues to connect the first end of the storage capacitor Cst and the pixel electrode 11, and outputs the voltage at the first end of the storage capacitor Cst to the pixel electrode 11. The voltage at the first end of the storage capacitor Cst is maintained at Vdata. The pixel electrode 11 and the common electrode layer of the color filter layer form a second driving voltage. The second driving voltage is: VData1 = Vdata - Vcom; For example, assume that the common electrode voltage Vcom and the second common electrode voltage of the color filter layer are 8V, and the data signal Vdata is 10V. At this time, the second driving voltage is 2V. The absolute values of the first driving voltage and the second driving voltage are equal, and the polarities are opposite.

[0041] By analogy, in subsequent odd frames, the pixel unit 10 works according to the working timing and signal flow direction of the first frame and switches to output the first driving voltage, and in subsequent even frames, the pixel unit 10 works according to the working timing and signal flow direction of the second frame and switches to output the second driving voltage with the opposite polarity.

[0042] By providing the inversion circuit 14, the first switching circuit 12, the second switching circuit 133, the switching circuit 131, the output circuit 134, and the bias circuit 132, it is possible to achieve that two adjacent frames form a frame cycle. During the frame scanning process, the polarity on the data line S can be kept unchanged, and the polarity of the driving voltage of the liquid crystal layer can be switched during the frame cycle, reducing the polarization of the liquid crystal layer and improving the working reliability of the liquid crystal layer.

[0043] Embodiment III In an alternative embodiment, as Figure 6 shown, the first switching circuit 12 includes a first transistor T1 and a second transistor T2; The first end of the first transistor T1, the first end of the second transistor T2 are connected to the data line S. The second end of the first transistor T1 is connected to the first end of the storage capacitor Cst. The second end of the second transistor T2 is connected to the second end of the storage capacitor Cst. The control terminals of the first transistor T1 and the second transistor T2 are commonly connected to form the control terminal of the first switching circuit 12.

[0044] The switching circuit 131 includes a third transistor T3; The first end of the third transistor T3 constitutes the input end of the switching circuit 131. The control end of the third transistor T3 is used to receive the pulse control signal Ctr2. The second end of the third transistor T3 constitutes the output end of the switching circuit 131.

[0045] The bias circuit 132 includes a bias resistor R1; The first end of the bias resistor R1 is respectively connected to the output end of the switching circuit 131, the control end of the output circuit 134, and the control end of the second switching circuit 133. The second end of the bias resistor R1 is used to input a preset potential Vref.

[0046] The second switching circuit 133 includes a fourth transistor T4 and a fifth transistor T5; The first ends of the fourth transistor T4 and the fifth transistor T5 are connected to a common electrode terminal. The second end of the fourth transistor T4 is connected to the second end of the storage capacitor Cst. The second end of the fifth transistor T5 is connected to the first end of the storage capacitor Cst. The control ends of the fourth transistor T4 and the fifth transistor T5 are connected to form the control end of the second switching circuit 133.

[0047] The output circuit 134 includes a sixth transistor T6; The first end of the sixth transistor T6 is connected to the first end of the storage capacitor Cst. The second end of the sixth transistor T6 is connected to the pixel electrode 11. The control end of the sixth transistor T6 constitutes the control end of the output circuit 134.

[0048] The flip circuit 14 includes a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9; The first ends of the seventh transistor T7 and the eighth transistor T8 are connected to the scan line G. The second end of the seventh transistor T7 and the second end of the ninth transistor T9 are commonly connected to form the output end of the flip circuit 14. The second end of the eighth transistor T8 is connected to the control end of the ninth transistor T9. The control ends of the seventh transistor T7 and the eighth transistor T8 are used to input the pulse control signal Ctr2. The first end of the ninth transistor T9 is used to input a first level signal V1.

[0049] In this embodiment, as Figure 5 shown, in order to ensure that the first transistor T1 and the second transistor T2 are triggered to turn off when receiving the row off signal VL, the voltage of the row off signal VL is zero. The first transistor T1 and the second transistor T2 both remain in the off state when receiving zero voltage, and are correspondingly switched to the on state when receiving a high level or a low level.

[0050] Among them, the first level signal V1 and the second level signal V2 are opposite level signals. For example, the first level signal V1 is a low level signal and the second level signal V2 is a high level signal. In an alternative embodiment, the row enable signal VG is the second level signal V2, and the second level signal V2 is a high level signal.

[0051] Assume that in the first time period t11 of the first frame, the flip circuit 14 of the pixel unit 10 in the current row receives the row enable signal VG, the seventh transistor T7 and the eighth transistor T8 receive the third level signal V3 of the pulse control signal Ctr2, the eighth transistor T8 is triggered to conduct, the seventh transistor T7 is triggered to turn off, the row enable signal VG is transmitted to the ninth transistor T9 through the eighth transistor T8, the ninth transistor T9 is triggered to conduct, and the first level signal V1 is transmitted to the first switching circuit 12 and the switching circuit 131.

[0052] When the first transistor T1 and the second transistor T2 receive the first level signal V1, the first transistor T1 is triggered to turn off, the second transistor T2 is triggered to conduct, the first switching circuit 12 transmits the data signal Vdata to the second end of the storage capacitor Cst. At the same time, the third transistor T3 of the switching circuit 131 is triggered to conduct when receiving the third level signal V3, and transmits the first level signal V1 to the second switching circuit 133 and the output circuit 134. At this time, the fifth transistor T5 of the second switching circuit 133 is triggered to conduct, the fourth transistor T4 is triggered to turn off, and the common electrode voltage Vcom is transmitted to the first end of the storage capacitor Cst. At this time, the pressure difference between the first end and the second end of the storage capacitor Cst is: ΔV = Vcom - Vdata; In the second time period t12 of the first frame, the inversion circuit 14 of the pixel unit 10 in the current row receives the row shutdown signal VL. At this time, the seventh transistor T7 and the eighth transistor T8 receive the fourth-level signal V4. The seventh transistor T7 is triggered to conduct, and the eighth transistor T8 is triggered to turn off. The seventh transistor T7 transmits the row shutdown signal VL to the first switching circuit 12 and the switching circuit 131. After the first transistor T1 and the second transistor T2 of the first switching circuit 12 receive the row shutdown signal VL, they switch to the off state. At this time, the third transistor T3 receives the fourth-level signal V4, and the third transistor T3 is triggered to turn off. The bias resistor R1 is biased to the preset potential Vref. The fourth transistor T4 is triggered to conduct, and the fifth transistor T5 is triggered to turn off. The common electrode voltage Vcom is transmitted to the second end of the storage capacitor Cst. The sixth transistor T6 is triggered to conduct, connecting the first end of the storage capacitor Cst and the pixel electrode 11, and outputting the voltage at the first end of the storage capacitor Cst to the pixel electrode 11. At this time, since the voltage difference between the first end and the second end of the storage capacitor Cst is Vcom - Vdata, and the voltage at the second end of the storage capacitor Cst is Vcom, the voltage at the first end of the storage capacitor Cst is 2*Vcom - Vdata at this time.

[0053] The pixel electrode 11 and the common electrode layer of the color filter layer form the first driving voltage. The first driving voltage is: VData1 = 2*Vcom - Vdata - Vcom; That is, the first driving voltage VData1 is -(Vdata - Vcom). For example, assuming that the common electrode voltage Vcom and the second common electrode voltage of the color filter layer are 8V, and the data signal Vdata is 10V, the first driving voltage is -2V at this time.

[0054] When the current frame scan ends and switches to the second frame, in the first time period t21 of the second frame, the seventh transistor T7 and the eighth transistor T8 continue to receive the fourth-level signal V4. The seventh transistor T7 maintains the on state, and the eighth transistor T8 maintains the off state. The inversion circuit 14 switches to output the row enable signal VG to the first switching circuit 12 and the switching circuit 131. At this time, the first transistor T1 is triggered to conduct, and the second transistor T2 is triggered to turn off, transmitting the data signal Vdata of the current frame to the first end of the storage capacitor Cst. The third transistor T3 continues to receive the fourth-level signal V4 and remains in the off state. At this time, the bias resistor R1 maintains the biasing function. The fourth transistor T4 maintains the on state and transmits the common electrode voltage Vcom to the second end of the storage capacitor Cst. The sixth transistor T6 maintains the on state and outputs the voltage at the first end of the storage capacitor Cst to the pixel electrode 11. The voltage difference between the first end and the second end of the storage capacitor Cst is: ΔV = Vdata - Vcom; During the second time period t22 of the second frame, the seventh transistor T7 and the eighth transistor T8 continue to receive the fourth-level signal V4. The seventh transistor T7 maintains the on state, and the eighth transistor T8 maintains the off state. The inversion circuit 14 outputs a row-off signal VL. The first transistor T1 and the second transistor T2 are triggered to turn off. The third transistor T3 continues to receive the fourth-level signal V4 and remains in the off state. At this time, the bias resistor R1 is biased to the preset potential Vref. The fourth transistor T4 continues to transfer the common electrode voltage Vcom to the second end of the storage capacitor Cst. The sixth transistor T6 outputs the voltage at the first end of the storage capacitor Cst to the pixel electrode 11. The voltage at the first end of the storage capacitor Cst is maintained at Vdata. The pixel electrode 11 and the common electrode layer of the color filter layer form a second driving voltage. The second driving voltage is: VData1 = Vdata - Vcom; For example, assume that the common electrode voltage Vcom and the second common electrode voltage of the color filter layer are 8V, and the data signal Vdata is 10V. At this time, the second driving voltage is 2V. The absolute values of the first driving voltage and the second driving voltage are equal, and the polarities are opposite.

[0055] And so on. In subsequent odd frames, the pixel unit 10 works according to the working timing and signal flow direction of the first frame and switches to output the first driving voltage. In subsequent even frames, the pixel unit 10 works according to the working timing and signal flow direction of the second frame and switches to output the second driving voltage with the opposite polarity. It is possible to achieve two adjacent frames as a frame cycle. During the frame scanning process, the polarity on the data line S can be kept unchanged, and the polarity of the driving voltage of the liquid crystal layer can be switched in the frame cycle, reducing the polarization of the liquid crystal layer and improving the working reliability of the liquid crystal layer.

[0056] Among them, the first transistor T1 and the ninth transistor T9 can be NMOS transistors, and the second transistor T2 can be a PMOS transistor.

[0057] The fourth transistor T4 and the sixth transistor T6 can be transistors of the same type. The fourth transistor T4 and the fifth transistor T5 are transistors of opposite types. The specific type is specifically set according to the input first-level signal V1 and the preset potential Vref. In an optional embodiment, the preset potential Vref is a high potential, the first-level signal V1 is a low-level signal, the fourth transistor T4 and the sixth transistor T6 are NMOS transistors, and the fifth transistor T5 is a PMOS transistor.

[0058] The third transistor T3 and the eighth transistor T8 are transistors of the same type, and the eighth transistor T8 and the seventh transistor T7 are transistors of opposite types. The specific type is determined by the specific potentials of the third-level signal V3 and the fourth-level signal V4 of the input pulse control signal Ctr2. In an alternative embodiment, the third-level signal V3 is a low-level signal, the fourth-level signal V4 is a high-level signal, the third transistor T3 and the eighth transistor T8 are PMOS transistors, and the seventh transistor T7 is an NMOS transistor.

[0059] Embodiment 4 As Figure 1 shown, a second aspect of the embodiments of the present invention provides a display panel 100, which includes multiple scan lines G, multiple data lines S, and multiple pixel units 10. The specific structure of the pixel unit 10 refers to the above embodiments. Since this display panel 100 adopts all the technical solutions of the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be elaborated here one by one. Among them, the pixel units 10 are respectively connected to a scan line G and a data line S.

[0060] The pixel units 10 are arranged in an array on the array substrate of the display panel 100. The array substrate also includes multiple scan lines G, multiple data lines S, and a common electrode terminal. The common electrode terminal has a first common electrode voltage Vcom1. Each pixel unit 10 is respectively connected to a data line S and a scan line G. The display panel 100 further includes a color filter substrate disposed opposite to the array substrate and a liquid crystal layer disposed between the array substrate and the color filter substrate. As Figure 2 shown, the pixel unit 10 includes a pixel electrode 11. A color filter layer and a common electrode layer are disposed on the color filter substrate. The common electrode layer has a second common electrode voltage. The multiple scan lines G are used to input row scan signals Vgate to the pixel units 10 of each row one by one. When the pixel units 10 of each row receive the row scan signal Vgate, the data line S outputs corresponding data signals Vdata to the pixel units 10 of the corresponding row. The pixel unit 10 generates a corresponding voltage signal to the pixel electrode 11 based on the received row scan signal Vgate and data signal Vdata. The voltage signal input to the pixel electrode 11 and the second common electrode voltage form a driving voltage, and drive the liquid crystal in the liquid crystal layer to deflect, and cooperate with the color filter layer to control the pixel unit 10 to display corresponding image information.

[0061] In an alternative embodiment, the voltage of the common electrode voltage Vcom is equal to the voltage of the second common electrode voltage, such as 5V, 8V, etc.

[0062] Embodiment 5 As Figure 7As shown in the figure, a third aspect of the embodiments of the present invention provides a display device, which includes a driving circuit 200 of a display panel and the display panel 100. The specific structure of the display panel 100 refers to the above embodiments. Since this display device adopts all the technical solutions of the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be elaborated one by one here. Among them, the driving circuit 200 of the display panel is connected to the display panel 100.

[0063] In this embodiment, the driving circuit 200 of the display panel may include a timing controller 230, a source driving circuit 210, and a gate driving circuit 220. The timing controller 230 is used to control the gate driving circuit 220 to output a row scanning signal Vgate to each row scanning line G row by row, and control the source driving circuit 210 to output a data signal Vdata to each column data line S. It can realize that two adjacent frames are used as a frame cycle, and during the frame scanning process, the polarity on the data line S can remain unchanged, and the polarity of the driving voltage of the liquid crystal layer is switched by the pixel unit 10 during the frame cycle, reducing the polarization of the liquid crystal layer and improving the working reliability of the liquid crystal layer.

[0064] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A pixel unit, characterized in that: include: Pixel electrode; Storage capacitor; a first switching circuit, connected to the data line and the storage capacitor, respectively, the first switching circuit being used to transmit the data signal on the data line to the second end of the storage capacitor when receiving a first level signal, or to transmit the data signal to the first end of the storage capacitor when receiving a second level signal, or to trigger shutdown when receiving a row closing signal; a switching output circuit, connected to the common electrode terminal, the storage capacitor and the pixel electrode, respectively, the switching output circuit being used to transmit the common electrode voltage of the common electrode terminal to the first terminal of the storage capacitor when receiving the first level signal, or to transmit the common electrode voltage to the second terminal of the storage capacitor and output the voltage of the first terminal of the storage capacitor to the pixel electrode when receiving the second level signal or the row closing signal; A flip circuit is respectively connected to the scan line, the first switching circuit and the switching output circuit. The flip circuit is used to output the first level signal or the second level signal when receiving a row start signal transmitted by the scan line, and switch the polarity of the output level when receiving the row start signal again, or output the row close signal when receiving a row close signal transmitted by the scan line.

2. The pixel unit according to claim 1, characterized in that: The first switching circuit includes a first transistor and a second transistor; The first end of the first transistor, the first end of the second transistor and the data line are connected, the second end of the first transistor is connected to the first end of the storage capacitor, the second end of the second transistor is connected to the second end of the storage capacitor, and the control end of the first transistor and the control end of the second transistor are connected together to form the control end of the first switching circuit.

3. The pixel unit according to claim 1 or 2, characterized in that: The switching output circuit comprises: a switch circuit, wherein an input end of the switch circuit is connected to an output end of the flip circuit, and the switch circuit is configured to trigger conduction upon receiving a third level signal of the pulse control signal, or trigger shutdown upon receiving a fourth level signal of the pulse control signal; A bias circuit connected to the output end of the switch circuit, the bias circuit being used to bias the voltage of the output end of the switch circuit to a preset potential when the switch circuit is in an off state; a second switching circuit, connected to the common electrode terminal, the switch circuit, the bias circuit and the storage capacitor, respectively, the second switching circuit being used to transmit the common electrode voltage to the first terminal of the storage capacitor when receiving the first level signal, or to transmit the common electrode voltage to the second terminal of the storage capacitor when receiving the preset potential; an output circuit connected between the first end of the storage capacitor and the pixel electrode, the output circuit also connected to the output end of the switch circuit, the output circuit configured to trigger off when receiving the first level signal, or trigger on when receiving the preset potential and transmit the voltage of the first end of the storage capacitor to the pixel electrode; The cycle time of the pulse control signal is two frames long. The pulse control signal in each cycle time consists of a third level signal and a fourth level signal. The phase of the third level signal is the same as the phase of the row start signal of the previous frame in the two frames long.

4. The pixel unit according to claim 3, characterized in that: The switch circuit includes a third transistor; The first end of the third transistor constitutes the input end of the switch circuit, the control end of the third transistor is used to receive the pulse control signal, and the second end of the third transistor constitutes the output end of the switch circuit.

5. The pixel unit according to claim 3, characterized in that: The bias circuit includes a bias resistor; The first end of the bias resistor is respectively connected to the output end of the switch circuit, the control end of the output circuit and the control end of the second switch circuit, and the second end of the bias resistor is used to input a preset potential.

6. The pixel unit according to claim 3, characterized in that: The second switching circuit includes a fourth transistor and a fifth transistor; The first end of the fourth transistor, the first end of the fifth transistor and the common electrode end are connected, the second end of the fourth transistor is connected to the second end of the storage capacitor, the second end of the fifth transistor is connected to the first end of the storage capacitor, and the control end of the fourth transistor and the control end of the fifth transistor are connected to form the control end of the second switching circuit.

7. The pixel unit according to claim 3, characterized in that: The output circuit includes a sixth transistor; The first end of the sixth transistor is connected to the first end of the storage capacitor, the second end of the sixth transistor is connected to the pixel electrode, and the control end of the sixth transistor constitutes the control end of the output circuit.

8. The pixel unit according to claim 3, characterized in that: The flip circuit includes a seventh transistor, an eighth transistor and a ninth transistor; The first end of the seventh transistor and the first end of the eighth transistor are connected to the scan line, the second end of the seventh transistor and the second end of the ninth transistor are connected together to form the output end of the flip circuit, the second end of the eighth transistor is connected to the control end of the ninth transistor, the control end of the seventh transistor and the control end of the eighth transistor are used to input the pulse control signal, and the first end of the ninth transistor is used to input the first level signal.

9. A display panel, characterized in that: The invention comprises a plurality of scan lines, a plurality of data lines and a plurality of pixel units as claimed in any one of claims 1 to 8, wherein the pixel units are respectively connected to one of the scan lines and one of the data lines.

10. A display device, characterized in that: The invention comprises a display panel driving circuit and the display panel as claimed in claim 9, wherein the display panel driving circuit is connected to the display panel.

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