Bridge arm multiplexing type soft switching AC-DC converter and control circuit and control method thereof

Abstract

The invention discloses a bridge arm multiplexing type soft switching AC-DC converter and a control circuit and a control method thereof, and the bridge arm multiplexing type soft switching AC-DC converter carries out bridge arm multiplexing on a primary side switching tube of a full-bridge LLC resonant converter and a rear bridge arm switching tube of a bridgeless AC-DC converter. Power factor correction and soft switching of all switching tubes can be realized, and the number of devices is reduced. The control circuit comprises an output voltage regulating circuit, an input voltage regulating circuit, an output voltage controlled phase-shift clock generating circuit, an input voltage controlled phase-shift clock generating circuit and a switching signal gating circuit. According to the invention, global soft switching, electrical isolation and wide-range voltage regulation can be realized, the number of devices is effectively reduced, and high power density, high conversion efficiency and high reliability can be realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic converters, and particularly relates to a bridge-arm multiplexing soft-switching AC-DC converter, its control circuit, and control method. Background Art

[0002] In daily life and industrial fields, electrical energy is usually taken from the AC power grid, and many electrical devices require DC power supply. Therefore, AC-DC converters are widely used in LED lighting power supplies, communication power supplies, battery chargers, new energy vehicle charging piles, and other occasions.

[0003] Common AC-DC converters include Buck PFC converters, Boost PFC converters, and Buck-Boost PFC converters. Among them, the Buck PFC converter has a dead zone in the input current and a low power factor; due to the characteristics of the boost circuit, the Boost PFC converter can only be applied to occasions with high-voltage output; the output voltage polarity of the Buck-Boost PFC converter is negative, and the voltage stress of the power switch tube is relatively high. For the four-switch Buck-Boost PFC converter, the inductor current ripple is too low when the input AC voltage passes through zero, and the ZVS (Zero Voltage Switching) of the switch tube cannot be realized. Compared with the four-switch Buck-Boost PFC converter, the bridgeless four-switch Buck-Boost AC-DC converter can achieve full-range soft switching. In some occasions that require electrical isolation and wide-range voltage variation, an isolated DC-DC module often needs to be added to the rear stage of the PFC converter, thus forming a two-stage PFC converter. The two-stage architecture can broaden the voltage regulation range and achieve electrical isolation while ensuring soft switching. However, the two-stage architecture will increase the number of devices in the converter, increasing the power density and cost. How to integrate the bridgeless PFC converter and the isolated DC-DC converter in the two-stage architecture, minimize the number of devices as much as possible, and achieve full-range soft switching and high power factor is an urgent problem to be solved. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a bridge-arm multiplexing soft-switching AC-DC converter, its control circuit, and control method for the above-mentioned deficiencies of the prior art, which can achieve full-range soft switching, high power factor, and electrical isolation.

[0005] To achieve the above technical objectives, the technical solution adopted by the present invention is as follows:

[0006] A bridge-arm multiplexing soft-switching AC-DC converter, the bridge-arm multiplexing soft-switching AC-DC converter includes a bridgeless AC-DC converter and a full-bridge LLC resonant converter;

[0007] Among them, the bridge-less AC-DC converter includes an input AC voltage source v in 、an input capacitor C inA 、an input capacitor C inB 、an inductor L a 、an inductor L b 、an intermediate bus capacitor C bus 、a switching transistor Q A1 and its anti-parallel diode D A1 and a junction capacitor C A1 、a switching transistor Q A2 and its anti-parallel diode D A2 and a junction capacitor C A2 、a switching transistor Q A3 and its anti-parallel diode D A3 and a junction capacitor C A4 、a switching transistor Q A4 and its anti-parallel diode D A4 and a junction capacitor C A4 、a switching transistor Q B1 and its anti-parallel diode D B1 and a junction capacitor C B1 、a switching transistor Q B2 and its anti-parallel diode D B2 and a junction capacitor C B2 、a switching transistor Q B3 and its anti-parallel diode D B3 and a junction capacitor C B3 、a switching transistor Q B4 and its anti-parallel diode D B4 and a junction capacitor C B4 ; Q A1 and Q A2 、Q B1 and Q B2 、Q A3 and Q A4 、Q B3 and Q B4 are respectively complementary-conducted to form bridge arms 1, 2, 3, and 4 correspondingly. C inA 、C inB 、C bus are respectively connected in series at both ends of bridge arms 1, 2, and 3. v in is connected in series between the drains of Q A1 and Q B1 . L a is connected in series between the midpoints of bridge arm 1 and bridge arm 3. L b is connected in series between the midpoints of bridge arm 2 and bridge arm 4;

[0008] The full-bridge LLC resonant converter includes a resonant inductor L r 、an exciting inductor L m 、a resonant capacitor C r 、a transformer Tr , Output filter capacitor C o , Rectifier diode D R1 , D R2 , D R3 , D R4 and load R Ld , and multiplex Q A3 and Q A4 to form leg 3 and Q B3 and Q B4 to form leg 4; L m is connected in parallel across the primary winding of T r , and one end of the primary winding of T r is connected to the midpoint of leg 3 through series-connected L r , C r , and the other end of the primary winding of T r is connected to the midpoint of leg 4; D R1 , D R2 are connected in series, D R3 , D R4 are connected in series, and the two series circuits are connected in parallel, C o , R Ld are both connected in parallel with the two series circuits, and one end of the secondary winding of T r is connected to the connection point of D R1 , D R2 , and the other end is connected to the connection point of D R3 , D R4 ;

[0009] Q A3 , Q A4 , Q B3 , Q B4 have a fixed duty cycle of 50%; and, Q A3 and Q B4 are turned on and off simultaneously, Q A4 and Q B3 are turned on and off simultaneously.

[0010] To optimize the above technical solution, the specific measures taken also include:

[0011] The drain of the above Q A1 is connected to the cathode of D A1 and one end of C A1 , the source of Q A1 is connected to the anode of D A1 and the other end of C A1 , the drain of Q A2 is connected to the cathode of D A2 and one end of C A2 , the source of Q A2 is connected to the anode of D A2 and the other end of C A2 are connected, QA3 The drain of A3 The cathode of A3 is connected to one end of A3 The source of A3 The anode of A3 is connected to the other end of A4 The drain of A4 The cathode of A4 is connected to one end of A4 The source of A4 The anode of A4 is connected to the other end of B1 The drain of B1 The cathode of B1 is connected to one end of B1 The source of B1 The anode of B1 is connected to the other end of B2 The drain of B2 The cathode of B2 is connected to one end of B2 The source of B2 The anode of B2 is connected to the other end of B3 The drain of B3 The cathode of B3 is connected to one end of B3 The source of B3 The anode of B3 is connected to the other end of B4 The drain of B4 The cathode of B4 is connected to one end of B4 The source of B4 The anode of B4 is connected to the other end.

[0012] The above-mentioned v in One end of inA One end of A1 is connected to the drain of A1 The source of A2 The drain of a is connected to one end of a The other end of A3 The source of A4 The drain of r is connected to one end of r The other end of r is connected to one end of r The other end of m One end of r is connected to one end of the primary side of A3The drain of is connected to Q B3 The drain of and C bus One end of is connected to v in The other end of is connected to C inB One end of and Q B1 The drain of is connected to Q B1 The source of and Q B2 The drain of and the inductor L b One end of the inductor L is connected to b The other end of is connected to Q B3 The source of and Q B4 The drain of and L m The other end of is connected to T r The other end of the primary side is connected to Q A2 The source of and Q B2 The source of and Q A4 The source of and Q B4 The source of and C inA The other end of is connected to C inB The other end of is connected to C bus The other end of is connected. One end of the secondary side is connected to D R1 The anode of and D R3 The cathode of is connected to D R1 The cathode of and D R2 The cathode of and C o One end of is connected to the load R Ld One end of the secondary side is connected to D R2 The anode of and D R4 The cathode of is connected to D R3 The anode of and D R4 The anode of and C o The other end of is connected to R Ld The other end of is connected.

[0013] The above-mentioned bridge-arm multiplexing soft-switching AC-DC converter includes 14 switching modes, which are respectively:

[0014] Switching mode 1 [t 0 , t 1 : At time t 0 , turn off Q A1 , the inductor current i a of L La charges the C A1 of Q A1 , and at the same time discharges the C A2 of Q A2 ; At time t 1 , the voltage of C A1 is charged to V inA , where V inA is the voltage on the input capacitor C inA , and at the same time C A2If the voltage is set to zero, then Q A2 's anti-parallel diode D A2 conducts naturally, and at this time, Q can be turned on with zero voltage A2 ; Q B2 and Q B4 conduct, and the voltage across L b is 0, and the inductor current i b of L Lb remains unchanged; L r and C r resonate, and the secondary rectifier diode D R1 and D R4 conduct, clamping the primary voltage v p of the transformer to NV o , and the primary transfers energy to the secondary. The magnetizing current i m of L Lm increases linearly;

[0015] Switching mode 2 [t 1 , t 2 : Q A2 and Q A3 conduct simultaneously, and the voltage across L a is -V bus , where V bus is the voltage across C bus , and i La decreases linearly; Q B2 and Q B4 conduct, and the voltage across L b is 0, and i Lb remains unchanged; L r and C r continue to resonate;

[0016] Switching mode 3 [t 2 , t 3 : Q A2 and Q A3 conduct simultaneously, and the voltage across L a is -V bus , and i La decreases linearly; Q B2 and Q B4 conduct, and the voltage across the inductor L b is 0, and i Lb remains unchanged; at time t 2 , the resonant current resonates to be equal to the magnetizing current i Lm , and the current of the secondary rectifier diode naturally decreases to zero, achieving zero-current turn-off; thereafter, L m , L r and C r resonate together, and the load is powered by C o ;

[0017] Switching mode 4 [t 3 , t 4 : At time t 3 , turn off Q A3 , i La charges the C A3 of Q A3 while discharging the C A4 of Q A4 ; At time t 4 , the voltage of C A3 is charged to V bus , while the voltage of C A4 is discharged to zero, then the anti-parallel diode D A4 of Q A4 naturally conducts, and at this time Q A4 can be turned on with zero voltage; Similarly, Q B3 can be turned on with zero voltage; L m , L r and C r continue to resonate, and the load is powered by C o .

[0018] Switching mode 5 [t 4 , t 5 : Q A2 and Q A4 conduct, and the voltage across L a is 0, and i La remains unchanged; Q B2 and Q B3 conduct simultaneously, and the voltage across the inductor is -V bus , and i Lb decreases linearly; L r and C r resonate, and the secondary side D R2 and D R3 conduct, clamping the primary side voltage v p to -NV o , and the primary side transfers energy to the secondary side, and the magnetizing current i Lm decreases linearly;

[0019] Switching mode 6 [t 5 , t 6 : Q A2 and Q A4 conduct, and the voltage across L a is 0, and i La remains unchanged; At time t 5 , turn off Q B2 , i Lb charges the C B2 of Q B2 whileB1 C of B1 discharges; at time t 6 , the voltage of C B2 is charged to V inB , where V inB is the voltage across C inB . At the same time, the voltage of C B1 is discharged to zero. Then, the anti-parallel diode D B1 of Q B1 naturally conducts, and at this time, Q B1 can be turned on with zero voltage; L r and C r continue to operate in resonance;

[0020] Switching mode 7 [t 6 , t 7 : Q A2 and Q A4 conduct, the voltage across L a is 0, and i La remains unchanged; Q B1 and Q B3 conduct, the voltage across L b is V inB - V bus , and i Lb decreases linearly; L r and C r continue to operate in resonance;

[0021] Switching mode 8 [t 7 , t 8 : At time t 7 , Q A2 is turned off, and i La charges the C A2 of Q A2 , and discharges the C A1 of Q A1 at the same time; at time t 8 , the voltage of C A2 is charged to V inA , and at the same time, the voltage of C A1 is discharged to zero. Then, the anti-parallel diode D A1 of Q A1 naturally conducts, and at this time, Q A1 can be turned on with zero voltage; Q B1 and Q B3 conduct, the voltage across L b is V inB - V bus , and i Lb decreases linearly; L r and C r continue to operate in resonance;

[0022] Switching mode 9[t 8 ,t 9 :Q A1 and Q A4 conduct, and the voltage across L a is V inA , i La increases linearly; Q B1 and Q B3 conduct, and the voltage across L b is V inB -V bus , i Lb decreases linearly; L r and C r continue to resonate;

[0023] Switching mode 10[t 9 ,t 10 :Q A1 and Q A4 conduct, and the voltage across L a is V inA , i La increases linearly; Q B1 and Q B3 conduct, and the voltage across L b is V inB -V bus , i Lb decreases linearly; at time t 9 , the resonant current resonates to be equal to the exciting current, and the current of the secondary rectifier diode naturally decreases to zero, realizing zero-current turn-off; thereafter, L m , L r and C r resonate together, and the load is powered by C o ;

[0024] Switching mode 11[t 10 ,t 11 :At time t 10 , turn off Q A4 , i La charges the C A4 connected to Q A4 , and at the same time discharges the C A3 connected to Q A3 ; at time t 11 , the voltage of C A4 is charged to V bus , and at the same time the voltage of C A3 is discharged to zero, then the anti-parallel diode D A3 of Q A3 naturally conducts, and at this time Q A3 can be turned on with zero voltage; similarly, Q B4 can be turned on with zero voltage; Lm , L r , and C r continue to resonate, and the load is powered by C o .

[0025] Switching mode 12[t 11 , t 12 : Q A1 and Q A3 are turned on, and the voltage across L a is V inA - V bus , i La increases linearly; Q B1 and Q B4 are turned on simultaneously, and the voltage across the inductor is V inB , i Lb increases linearly; L r and C r resonate, and the secondary rectifier diodes D R1 and D R4 are turned on, clamping the primary voltage of the transformer v p to NV o , transferring energy from the primary to the secondary, and the magnetizing current i Lm increases linearly;

[0026] Switching mode 13[t 12 , t 13 : Q A1 and Q A3 are turned on, and the voltage across L a is V inA - V bus , i La increases linearly; at t 12 , Q B1 is turned off, and i Lb charges the junction capacitance C B1 of Q B1 , and discharges the C B2 of Q B2 ; at t 13 , the voltage of C B1 is charged to V inB , and the voltage of C B2 is discharged to zero. Then the anti-parallel diode D B2 of Q B1 conducts naturally, and at this time, Q B2 can be turned on with zero voltage; L r and C r continue to resonate;

[0027] Switching mode 14[t 13 , t 14 : Q A1and Q A3 conducts, and the voltage across L a is V inA -V bus , and i La increases linearly; Q B2 and Q B4 conduct, and the voltage across L b is 0, and i Lb remains unchanged; L r and C r continue to resonate.

[0028] The control circuit of the bridge-arm multiplexed soft-switching AC-DC converter, the control circuit includes an output voltage regulation circuit, an input voltage regulation circuit, a phase-shifted clock generation circuit controlled by the output voltage, a phase-shifted clock generation circuit controlled by the input voltage, and a switching signal gating circuit;

[0029] The output voltage regulation circuit is used to sample the output voltage and compare it with a given voltage reference, stabilize the output voltage through a voltage regulator and a current regulator, and achieve power factor correction;

[0030] The input voltage regulation circuit is used to sample the input capacitor voltage and compare it with a given voltage reference, and close-loop regulate and control the input capacitor voltage through an input voltage regulator;

[0031] The phase-shifted clock generation circuit controlled by the output voltage is used to sample the valley current of the inductor current of L a or L b , after passing through an inverter, compare it with a given current reference I ZVS_ref(O) , send the obtained error value to a phase-shift regulator 1, and the signal generated by the phase-shift regulator 1 generates a phase-shift signal V θ(O) after passing through a subtractor; this phase-shift signal V θ(O) enters the phase-shift pulse generation module 1, first generates a phase-shift duty cycle D θ(O) , and finally generates two narrow pulses CLK1(O) and CLK2(O) whose phase difference is controlled by D θ(O) , CLK1(O) controls the turn-on moment of Q A4 , Q B4 , and CLK2(O) controls the turn-on moment of Q A1 , Q B1 ;

[0032] The phase-shifted clock generation circuit controlled by the input voltage is used to sample the peak current i Lb or i La of i L_max , compare it with a given current reference I ZVS_ref(I) , send the obtained error value to a phase-shift regulator 2, and the phase-shift regulator 2 generates a phase-shift signal Vθ(I) After the phase-shifted signal V θ(I) enters the phase-shift pulse generation module 2, a phase-shift duty cycle D is first generated θ(I) , and finally two narrow pulses CLK1(I) and CLK2(I) with a phase difference controlled by D are generated. CLK1(I) controls the turn-on time of Q θ(I) , Q B3 , Q A3 , and CLK2(I) controls the turn-on time of the switching transistors Q B1 , Q A1 ;

[0033] The switching signal gating circuit is used to compare the input voltage with 0 in the comparator 5 to generate the V sel signal. During the positive half-cycle of the input voltage, V sel is at a high level, and the selection switch channel 1 is turned on. During the negative half-cycle of the input voltage, V sel is at a low level, and the selection switch channel 2 is turned on at this time. Among them, the switch channel 1 is used to control Q A4 , Q A1、 Q B3 , and Q B1 , and the switch channel 2 is used to control Q B4 , Q B1 , Q A3 , and Q A1 ;

[0034] The above output voltage regulation circuit includes an output voltage regulator, a multiplier, an input current regulator, an adder, a comparator 1, and an RS flip-flop 1. The sampling signal v o of the output voltage V o_s is compared with the given voltage reference V o_ref . The obtained error signal is input to the output voltage regulator. The multiplier multiplies the output v c of the voltage regulator by the absolute value |v in_s | of the input voltage sampling signal to obtain the reference signal i g_ref of the input current. The i g_ref is compared with the sampling signal of the input current i in . The obtained error signal is input to the input current regulator. The adder adds the output v err1 of the current regulator and V θ(O) to obtain the signal v err1 ′. The v err1 ′ and the triangular wave signal v saw are sent to the comparator 1 for comparison to obtain the duty cycle signal D y(O) . The D y(O) and CLK2(O) are sent to the RS flip-flop 1, and the positive output signal of the RS flip-flop 1 is QA1 , the driving signal of Q B1 , and its inverted signal is Q A2 , the driving signal of Q B2 .

[0035] The above input voltage regulating circuit includes an input voltage regulator, an adder, a comparator 2, and an RS flip-flop 2. The sampled signal of the input capacitor voltage is compared with a given voltage reference, and the obtained error signal is input to the input voltage regulator. The adder adds the output v err2 and V θ(I) to obtain v err2 ′. Then, v err2 ′ and the triangular wave signal v saw are sent to comparator 2 for comparison to obtain signal D y(I) . D y(I) and CLK2(I) are sent to RS flip-flop 2. The positive output signal of RS flip-flop 2 is the driving signal of switch tubes Q B1 , Q A1 , and its inverted signal is the driving signal of switch tubes Q B2 , Q A2 .

[0036] The above phase-shifted clock generation circuit for output voltage control includes a phase-shifted signal generation module for output voltage control, a phase-shifted pulse generation module 1, and a switch tube drive circuit 1;

[0037] The phase-shifted signal generation module for output voltage control includes a valley current detection circuit, an inverter, a phase-shift regulator 1, and a subtractor. The valley current detection circuit samples the valley value of the inductor current of L a or L b . After passing through the inverter, it is compared with the given current reference I ZVS_ref(O) . The obtained error value is sent to the phase-shift regulator 1. The signal generated by the phase-shift regulator 1 is subtracted from 0.5V M by the subtractor to obtain the phase-shifted signal V θ(O) , where V M is the peak voltage of the triangular wave signal v saw ;

[0038] After receiving the phase-shifted signal V θ(O) , the phase-shifted pulse generation module 1 sends V θ(O) and the triangular wave signal v saw to comparator 3 for comparison and then outputs the phase-shifted duty cycle D θ(O) . The phase-shifted pulse generation module 1 finally generates two narrow pulses CLK1(O) and CLK2(O) whose phase difference is controlled by D θ(O) . Among them, CLK1(O) is used to control switch tubes Q A4 , QB4 At the turn-on moment, CLK2(O) is used to control the switching transistors Q A1 and Q B1 at their turn-on moments;

[0039] The switching transistor driving circuit 1 includes a delay module 1 and an RS flip-flop 3. The delay module 1 delays the CLK1(O) pulse signal by half a switching cycle and then sends it together with CLK1(O) to the RS flip-flop 3, which is used to generate a turn-off signal for half a switching cycle. The positive output signal of the RS flip-flop 3 is the driving signal for the switching transistors Q A4 and Q B4 ; its inverted signal is the driving signal for the switching transistors Q A3 and Q B3 .

[0040] The above-mentioned phase-shifted clock generation circuit controlled by the input voltage includes a phase-shifted signal generation module controlled by the input voltage, a phase-shifted pulse generation module 2, and a switching transistor driving circuit 2;

[0041] The phase-shifted generation module controlled by the input voltage includes a peak current detection circuit and a phase-shift regulator 2. The peak current detection circuit samples the peak value of the inductor current of L a or L b , compares it with the given current reference I ZVS_ref(I) , and sends the obtained error value to the phase-shift regulator 2, which generates a phase-shifted signal V θ(I) ;

[0042] After receiving the phase-shifted signal V θ(I) , the phase-shifted pulse generation module 2 sends V θ(I) and the triangular wave signal v saw to the comparator 3 for comparison, and then outputs a phase-shifted duty cycle D θ(I) . The phase-shifted pulse generation module 2 finally generates two narrow pulses CLK1(I) and CLK2(I) whose phase difference is controlled by D θ(I) . Among them, CLK1(I) is used to control the turn-on moments of the switching transistors Q B3 and Q A3 ), and CLK2(I) is used to control the turn-on moments of the switching transistors Q B1 and Q A1 ;

[0043] The switching transistor driving circuit 2 includes a delay module 2 and an RS flip-flop 4. The delay module 2 delays the CLK1(I) pulse signal by half a switching cycle and then sends it together with CLK1(I) to the RS flip-flop 4, which is used to generate a turn-off signal for half a switching cycle. The positive output signal of the RS flip-flop 4 is the driving signal for the switching transistors Q B3 and Q A3 ; its inverted signal is the driving signal for the switching transistors QB4 , Q A4 's drive signal.

[0044] A control method for a bridge-arm multiplexed soft-switching AC-DC converter, the control method comprising: comparing an input voltage with 0 in a comparator 5 to generate a V sel signal, during the positive half-cycle of the input voltage, V sel is at a high level, at this time the switch channel 1 is selected to be turned on, the output voltage sampling signal passes through a voltage regulator and then through a multiplier and a current regulator to achieve power factor correction and generate a duty cycle D A1 of Q y1(O) , whose inverted signal is used to control Q A2 , L a 's inductor current valley value is output as a phase-shifted duty cycle D θ(O) after passing through an inverter, a phase-shift regulator, and a subtractor, and two narrow pulses CLK1(O) and CLK2(O) are generated by a phase-shift pulse signal generation module 1 to respectively control the turn-on moments of Q A4 and Q A1 , where CLK1(O) generates a turn-off signal for Q A4 after a half-switching cycle delay; the voltage sampling signal of C inB generates a duty cycle D B1 of the switch tube Q y1(I) , whose inverted signal is used to control Q B2 ; L b 's inductor current peak value is output as a phase-shifted duty cycle D θ(I) after passing through a phase-shift regulator, and two narrow pulses CLK1(I) and CLK2(I) are generated by a phase-shift pulse signal generation module 2 to respectively control the turn-on moments of Q B3 and Q B1 , where CLK1(I) generates a turn-off signal for Q B3 after a half-switching cycle delay;

[0045] During the negative half-cycle of the input voltage, V sel is at a low level, the switch channel 2 is selected to be turned on, the output voltage sampling signal passes through a voltage regulator and then through a multiplier and a current regulator to achieve power factor correction and generate a duty cycle D B1 of the switch tube Q y1(O) , whose inverted signal is used to control Q B2 , L b 's inductor current valley value is output as a phase-shifted duty cycle D θ(O) after passing through an inverter, a phase-shift regulator, and a subtractor, and two narrow pulses CLK1(O) and CLK2(O) are generated by a phase-shift pulse signal generation module 1 to respectively control the turn-on moments of Q B4 and Q B1The turn-on moment, where Q is generated after CLK1(O) is delayed by half a switching period B4 's turn-off signal; C inA The voltage sampling signal of is fed through a voltage regulator to generate the switching transistor Q A1 's duty cycle D y1(I) , whose inverted signal is used to control Q A2 ; L a The peak inductor current of is output as the phase-shifted duty cycle D θ(I) through a phase-shift regulator, and two narrow pulses CLK1(I) and CLK2(I) are generated by the phase-shift pulse signal generation module 2 to control Q A3 and Q A1 's turn-on moment, where Q is generated after CLK1(I) is delayed by half a switching period A3 's turn-off signal.

[0046] The present invention has the following beneficial effects:

[0047] Based on a bridgeless AC-DC converter and a full-bridge LLC resonant converter, the present invention innovates the circuit topology by multiplexing the primary switching transistors of the full-bridge LLC resonant converter and the rear-leg switching transistors of the bridgeless AC-DC converter. Compared with traditional AC-DC converters, the bridgeless soft-switching AC-DC converter of the present invention can achieve power factor correction, soft-switching of all switching transistors, and effectively reduce the number of devices.

[0048] The present invention can also electrically isolate the input voltage from the output voltage, better protect the subsequent electrical equipment, can achieve wide-range voltage regulation, and has high power density, high conversion efficiency, and high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 is the circuit structure diagram of the bridgeless soft-switching AC-DC converter.

[0050] Figure 2 is the control circuit diagram of the bridgeless soft-switching AC-DC converter.

[0051] Figure 3 is the working waveform diagram of the bridgeless soft-switching AC-DC converter.

[0052] Figure 4a is the equivalent circuit diagram of switching mode 1 of the bridgeless soft-switching AC-DC converter.

[0053] Figure 4b is the equivalent circuit diagram of switching mode 2 of the bridgeless soft-switching AC-DC converter.

[0054] Figure 4cIt is the equivalent circuit diagram of switching mode 3 of the arm - multiplexed soft - switched AC - DC converter.

[0055] Figure 4d It is the equivalent circuit diagram of switching mode 4 of the arm - multiplexed soft - switched AC - DC converter.

[0056] Figure 4e It is the equivalent circuit diagram of switching mode 5 of the arm - multiplexed soft - switched AC - DC converter.

[0057] Figure 4f It is the equivalent circuit diagram of switching mode 6 of the arm - multiplexed soft - switched AC - DC converter.

[0058] Figure 4g It is the equivalent circuit diagram of switching mode 7 of the arm - multiplexed soft - switched AC - DC converter.

[0059] Figure 4h It is the equivalent circuit diagram of switching mode 8 of the arm - multiplexed soft - switched AC - DC converter.

[0060] Figure 4i It is the equivalent circuit diagram of switching mode 9 of the arm - multiplexed soft - switched AC - DC converter.

[0061] Figure 4j It is the equivalent circuit diagram of switching mode 10 of the arm - multiplexed soft - switched AC - DC converter.

[0062] Figure 4k It is the equivalent circuit diagram of switching mode 11 of the arm - multiplexed soft - switched AC - DC converter.

[0063] Figure 4l It is the equivalent circuit diagram of switching mode 12 of the arm - multiplexed soft - switched AC - DC converter.

[0064] Figure 4m It is the equivalent circuit diagram of switching mode 13 of the arm - multiplexed soft - switched AC - DC converter.

[0065] Figure 4n It is the equivalent circuit diagram of switching mode 14 of the arm - multiplexed soft - switched AC - DC converter.

[0066] Figure 5 It is the PFC simulation waveform diagram of the arm - multiplexed soft - switched AC - DC converter.

[0067] Figure 6 It is the simulation waveform diagram of the FSBB A module of the arm - multiplexed soft - switched AC - DC converter.

[0068] Figure 7 It is the simulation waveform diagram of the FSBB B module of the arm - multiplexed soft - switched AC - DC converter.

[0069] Figure 8 It is the simulation waveform diagram of the LLC module of the bridge-arm multiplexing soft-switching AC-DC converter. Specific embodiments

[0070] The following further describes the embodiments of the present invention in detail with reference to the accompanying drawings.

[0071] The circuit structure of the bridge-arm multiplexing soft-switching AC-DC converter of the present invention is as Figure 1 shown. The bridge-arm multiplexing soft-switching AC-DC converter includes an input AC voltage source v in , an input capacitor C inA , an input capacitor C inB , an inductor L a , an inductor L b , an intermediate bus capacitor C bus , a resonant inductor L r , an exciting inductor L m , a resonant capacitor C r , a transformer T r , an output filter capacitor C o , a switching transistor Q A1 and its anti-parallel diode D A1 and junction capacitance C A1 , a switching transistor Q A2 and its anti-parallel diode D A2 and junction capacitance C A2 , a switching transistor Q A3 and its anti-parallel diode D A3 and junction capacitance C A4 , a switching transistor Q A4 and its anti-parallel diode D A4 and junction capacitance C A4 , a switching transistor Q B1 and its anti-parallel diode D B1 and junction capacitance C B1 , a switching transistor Q B2 and its anti-parallel diode D B2 and junction capacitance C B2 , a switching transistor Q B3 and its anti-parallel diode D B3 and junction capacitance C B3 , a switching transistor Q B4 and its anti-parallel diode D B4 and junction capacitance C B4 , a rectifying diode D R1 , a rectifying diode D R2 , a rectifying diode D R3 , a rectifying diode D R4 , a load R Ld . In the bridge-arm multiplexing soft-switching AC-DC converter, the switching transistor QA1 and Q A2 、Q B1 and Q B2 、Q A3 and Q A4 、Q B3 and Q B4 are complementarily turned on respectively, and the duty cycle of the switching transistor Q A3 、Q A4 、Q B3 、Q B4 is fixed at 50%; and, the switching transistors Q A3 and the switching transistor Q B4 are turned on and off simultaneously, and the switching transistor Q A4 and the switching transistor Q B3 are turned on and off simultaneously.

[0072] The present invention is based on a bridgeless AC-DC converter and a full-bridge LLC resonant converter, innovates the circuit topology, and multiplexes the primary switching transistors of the full-bridge LLC resonant converter and the rear-leg switching transistors of the bridgeless AC-DC converter, so as to achieve power factor correction, soft switching of all switching transistors and reduce the number of devices.

[0073] The bridge-leg multiplexing type soft-switching AC-DC converter includes a bridgeless AC-DC converter and a full-bridge LLC resonant converter;

[0074] Among them, the bridgeless AC-DC converter includes an input AC voltage source v in 、input capacitor C inA 、input capacitor C inB 、inductor L a 、inductor L b 、intermediate bus capacitor C bus 、switching transistor Q A1 and its anti-parallel diode D A1 and junction capacitor C A1 、switching transistor Q A2 and its anti-parallel diode D A2 and junction capacitor C A2 、switching transistor Q A3 and its anti-parallel diode D A3 and junction capacitor C A4 、switching transistor Q A4 and its anti-parallel diode D A4 and junction capacitor C A4 、switching transistor Q B1 and its anti-parallel diode D B1 and junction capacitor C B1 、switching transistor Q B2 and its anti-parallel diode D B2 and junction capacitor C B2 、switching transistor Q B3and its anti-parallel diode D B3 and junction capacitance C B3 、switching transistor Q B4 and its anti-parallel diode D B4 and junction capacitance C B4 ; Q A1 and Q A2 、Q B1 and Q B2 、Q A3 and Q A4 、Q B3 and Q B4 complementary conduct respectively, corresponding to form bridge arms 1, 2, 3, 4, C inA 、C inB 、C bus are respectively connected in series at both ends of bridge arms 1, 2, 3, v in is connected in series between the drain of Q A1 and the drain of Q B1 ; L a is connected in series between the midpoint of bridge arm 1 and the midpoint of bridge arm 3, L b is connected in series between the midpoint of bridge arm 2 and the midpoint of bridge arm 4;

[0075] The full-bridge LLC resonant converter includes resonant inductor L r 、excitation inductor L m 、resonant capacitor C r 、transformer T r 、output filter capacitor C o 、rectifier diode D R1 、D R2 、D R3 、D R4 and load R Ld , and reuse the bridge arm 3 formed by Q A3 and Q A4 and the bridge arm 4 formed by Q B3 and Q B4 ; L m is connected in parallel at both ends of the primary side of T r , and one end of the primary side of T r is connected to the midpoint of bridge arm 3 through the series-connected L r 、C r , the other end of the primary side of T r is connected to the midpoint of bridge arm 4; D R1 、D R2 are connected in series, D R3 、D R4 are connected in series, and the two series circuits are connected in parallel, C o 、R Ld are both connected in parallel with the two series circuits, one end of the secondary side of T r is connected to D R1 、D R2The connection point, with the other end connected to D R3 , D R4 's connection point;

[0076] In the arm - multiplexed AC - DC converter of the present invention, the switching transistors in the same arm conduct complementarily, and the multiplexed arm switching transistors Q A3 , Q A4 , Q B3 , Q B4 's duty cycle is fixed at 50%; and, the switching transistor Q A3 and the switching transistor Q B4 are turned on and off simultaneously, and the switching transistor Q A4 and the switching transistor Q B3 are turned on and off simultaneously.

[0077] The control circuit of the arm - multiplexed soft - switching AC - DC converter of the present invention is as Figure 2 shown. The control circuit of the arm - multiplexed soft - switching AC - DC converter includes:

[0078] An output voltage regulation circuit that samples the output voltage and compares it with a given voltage reference, and closes the loop through a voltage outer - loop regulator and a current inner - loop regulator to regulate and stabilize the output voltage, and achieve power - factor correction.

[0079] An input voltage regulation circuit that samples the input - capacitor voltage and compares it with a given voltage reference, and closes the loop through a voltage regulator to control the input - capacitor voltage.

[0080] A phase - shifted clock generation circuit for output - voltage control that samples the valley current i La (i Lb ) of i L_min , which becomes - i L_min after passing through an inverter, and compares it with a given current reference I ZVS_ref(O) . The error value is sent to a phase - shift regulator 1. The signal generated by the phase - shift regulator 1 passes through a subtractor to generate a phase - shifted signal V A4 (Q B4 ) between the turn - on times of Q A1 (Q B1 ) and Q θ(O) . After the phase - shifted signal V θ(O) enters the phase - shifted pulse generation module, it first generates a phase - shifted duty cycle D θ(O) , and finally generates two narrow pulses CLK1(O) and CLK2(O) whose phase difference is controlled by D θ(O) , respectively controlling the turn - on times of the switching transistors Q A4 (Q B4 ) and Q A1 (Q B1 ).

[0081] Input voltage controlled phase-shifted clock generation circuit, sampling i Lb (i La ) peak current i L_max is compared with a given current reference I ZVS_ref(I) . The error value is sent to the phase-shift regulator 2, and the phase-shift regulator 2 generates the conduction time between the switching transistors Q B3 (Q A3 ) and Q B1 (Q A1 ) phase-shift signal V θ(I) . After the phase-shift signal V θ(I) enters the phase-shift pulse generation module, it first generates a phase-shift duty cycle D θ(I) , and finally generates two narrow pulses CLK1(I) and CLK2(I) with a phase difference controlled by D θ(I) , which respectively control the conduction times of the switching transistors Q B3 (Q A3 ) and Q B1 (Q A1 ).

[0082] Switch signal gating circuit. During the positive half-cycle of the input AC voltage, V sel is at a high level, and at this time, the switch channel 1 is selected to conduct. During the negative half-cycle of the input AC voltage, V sel is at a low level, and at this time, the switch channel 2 is selected to conduct.

[0083] Such as Figure 1 , in a bridge-arm multiplexed soft-switching AC-DC converter, the drain of the switching transistor Q A1 is connected to the cathode of the diode D A1 and one end of the junction capacitor C A1 . The source of the switching transistor Q A1 is connected to the anode of the diode D A1 and the other end of the junction capacitor C A1 . The drain of the switching transistor Q A2 is connected to the cathode of the diode D A2 and one end of the junction capacitor C A2 . The source of the switching transistor Q A2 is connected to the anode of the diode D A2 and the other end of the junction capacitor C A2 . The drain of the switching transistor Q A3 is connected to the cathode of the diode D A3 and one end of the junction capacitor C A3 . The source of the switching transistor Q A3 is connected to the anode of the diode D A3 and the other end of the junction capacitor C A3 . The drain of the switching transistor Q A4 is connected to the cathode of the diode D A4 and the junction capacitor CA4 is connected to one end of the switching transistor Q A4 's source electrode and the diode D A4 's anode and the junction capacitance C A4 is connected to the other end of the switching transistor Q B1 's drain electrode and the diode D B1 's cathode and the junction capacitance C B1 is connected to one end of the switching transistor Q B1 's source electrode and the diode D B1 's anode and the junction capacitance C B1 is connected to the other end of the switching transistor Q B2 's drain electrode and the diode D B2 's cathode and the junction capacitance C B2 is connected to one end of the switching transistor Q B2 's source electrode and the diode D B2 's anode and the junction capacitance C B2 is connected to the other end of the switching transistor Q B3 's drain electrode and the diode D B3 's cathode and the junction capacitance C B3 is connected to one end of the switching transistor Q B3 's source electrode and the diode D B3 's anode and the junction capacitance C B3 is connected to the other end of the switching transistor Q B4 's drain electrode and the diode D B4 's cathode and the junction capacitance C B4 is connected to one end of the switching transistor Q B4 's source electrode and the diode D B4 's anode and the junction capacitance C B4 is connected to the other end;

[0084] The input AC voltage source v in 's one end is connected to the input capacitance C inA 's one end and the switching transistor Q A1 's drain electrode, the switching transistor Q A1 's source electrode and the switching transistor Q A2 's drain electrode and the inductor L a 's one end, the inductor L a 's other end is connected to the switching transistor Q A3 's source electrode and the switching transistor Q A4 's drain electrode and the resonant capacitance C r 's one end, the resonant capacitance C r 's other end and the resonant inductor L r 's one end, the resonant inductor L r 's other end is connected to the exciting inductor L m 's one end and the transformer T r 's one end of the primary side, the switching transistor Q A3 's drain electrode is connected to the switching transistor QB3 The drain of and the intermediate bus capacitor C bus are connected at one end, and the input AC voltage source v in is connected to the other end of the input capacitor C inB at one end and the switching transistor Q B1 at the drain. The source of the switching transistor Q B1 and the drain of the switching transistor Q B2 are connected to one end of the inductor L b The other end of the inductor L b is connected to the source of the switching transistor Q B3 and the drain of the switching transistor Q B4 are connected to one end of the exciting inductor L m The other end and the transformer T r are connected to the other end of the primary side. The source of the switching transistor Q A2 and the source of the switching transistor Q B2 and the source of the switching transistor Q A4 and the source of the switching transistor Q B4 and the source of the input capacitor C inA The other end and the input capacitor C inB The other end and the intermediate bus capacitor C bus The other end is connected. One end of the secondary side of the transformer and the rectifier diode D R1 The anode and the rectifier diode D R3 The cathode is connected. The cathode of the rectifier diode D R1 The cathode and the rectifier diode D R2 The cathode and the output filter capacitor C o One end and the load R Ld One end is connected. The other end of the secondary side of the transformer and the rectifier diode D R2 The anode and the rectifier diode D R4 The cathode is connected. The rectifier diode D R3 The anode and the rectifier diode D R4 The anode and the output filter capacitor C o The other end and the load R Ld The other end is connected.

[0085] The bridge-arm multiplexing soft-switching AC-DC converter of the present invention includes 14 switching modes. Figure 3 is the working waveform diagram of the bridge-arm multiplexing soft-switching AC-DC converter. Fig. 4 is the equivalent circuit diagram of the bridge-arm multiplexing soft-switching AC-DC converter under different switching modes. The 14 switching modes are respectively:

[0086] Such as Figure 4a , switching mode 1 [t 0 , t 1 : At time t 0 , turn off Q A1 , the inductor current iLa Charge Q A1 's junction capacitance C A1 and discharge the junction capacitance C A2 of Q A2 At time t 1 , the voltage of C A1 is charged to V inA , where V inA is the voltage on the input capacitance C inA . At the same time, the voltage of C A2 is discharged to zero. Then the anti-parallel diode D A2 of Q A2 naturally conducts, and at this time Q A2 can be turned on at zero voltage; Q B2 and Q B4 conduct, and the voltage across the inductor L b is 0, and the inductor current i Lb remains unchanged; L r and C r resonate. The secondary rectifier diodes D R1 and D R4 conduct, clamping the primary voltage v p of the transformer to NV o , transferring energy from the primary side to the secondary side, and the magnetizing current i Lm increases linearly.

[0087] As Figure 4b , switching mode 2 [t 1 , t 2 : Q A2 and Q A3 conduct simultaneously, and the voltage across the inductor L a is -V bus , where V bus is the voltage on the intermediate bus capacitance C bus . The inductor current i La decreases linearly; Q B2 and Q B4 conduct, and the voltage across the inductor L b is 0, and the inductor current i Lb remains unchanged; L r and C r continue to resonate.

[0088] As Figure 4c , switching mode 3 [t 2 , t 3 : Q A2 and Q A3 conduct simultaneously, and the voltage across the inductor L a is -V bus , and the inductor current i La decreases linearly; QB2 and Q B4 conducts, and the voltage across the inductor L b is 0, and the inductor current i Lb remains unchanged; at time t 2 , the resonant current resonates to be equal to the exciting current, and the current of the secondary rectifier diode naturally decreases to zero, achieving zero-current turn-off. After that, L m , L r and C r resonate together, and the load is powered by the output capacitor C o .

[0089] As Figure 4d , switching mode 4 [t 3 , t 4 : At time t 3 , turn off Q A3 , and the inductor current i La charges the junction capacitance C A3 of Q A3 , and at the same time discharges the junction capacitance C A4 of Q A4 . At time t 4 , the voltage of C A3 is charged to V bus , and at the same time the voltage of C A4 is discharged to zero. Then the anti-parallel diode D A4 of Q A4 naturally conducts, and at this time Q A4 can be turned on with zero voltage; similarly, Q B3 can be turned on with zero voltage; L m , L r and C r continue to resonate, and the load is powered by the output capacitor C o .

[0090] As Figure 4e , switching mode 5 [t 4 , t 5 : Q A2 and Q A4 conduct, and the voltage across the inductor L a is 0, and the inductor current i La remains unchanged; Q B2 and Q B3 conduct simultaneously, and the voltage across the inductor is -V bus , and the inductor current i Lb decreases linearly; L r and C r resonate, and the secondary rectifier diodes D R2 and D R3 conduct, and the primary voltage of the transformer v pClamped to -NV o , the primary side transfers energy to the secondary side, and the exciting current i Lm decreases linearly.

[0091] As Figure 4f , switching mode 6 [t 5 , t 6 : Q A2 and Q A4 conduct, the voltage across the inductor L a is 0, and the inductor current i La remains unchanged; at t 5 moment, turn off Q B2 , the inductor current i Lb charges the junction capacitance C B2 of Q B2 , and at the same time discharges the junction capacitance C B1 of Q B1 . At t 6 moment, the voltage of C B2 is charged to V inB , where V inB is the voltage across the input capacitance C inB , and at the same time the voltage of C B1 is discharged to zero, then the anti-parallel diode D B1 of Q B1 naturally conducts, and at this time Q B1 can be turned on with zero voltage; L r and C r continue to resonate.

[0092] As Figure 4g , switching mode 7 [t 6 , t 7 : Q A2 and Q A4 conduct, the voltage across the inductor L a is 0, and the inductor current i La remains unchanged; Q B1 and Q B3 conduct, the voltage across the inductor L b is V inB - V bus , and the inductor current i Lb decreases linearly; L r and C r continue to resonate.

[0093] As Figure 4h , switching mode 8 [t 7 , t 8 : At t 7 moment, turn off Q A2 , the inductor current i La charges Q A2The junction capacitance C A2 is charged, and at the same time Q A1 's junction capacitance C A1 is discharged. At time t 8 , the voltage of C A2 is charged to V inA , and at the same time the voltage of C A1 is discharged to zero. Then the anti-parallel diode D A1 of Q A1 naturally conducts, and at this time Q A1 can be turned on at zero voltage; Q B1 and Q B3 conduct, and the voltage across the inductor L b is V inB -V bus , and the inductor current i Lb decreases linearly; L r and C r continue to resonate.

[0094] As Figure 4i , switching mode 9 [t 8 , t 9 : Q A1 and Q A4 conduct, and the voltage across the inductor L a is V inA , and the inductor current i La increases linearly; Q B1 and Q B3 conduct, and the voltage across the inductor L b is V inB -V bus , and the inductor current i Lb decreases linearly; L r and C r continue to resonate.

[0095] As Figure 4j , switching mode 10 [t 9 , t 10 : Q A1 and Q A4 conduct, and the voltage across the inductor L a is V inA , and the inductor current i La increases linearly; Q B1 and Q B3 conduct, and the voltage across the inductor L b is V inB -V bus , and the inductor current i Lb decreases linearly; at t 9At this moment, the resonant current resonates to be equal to the exciting current, and the current of the secondary rectifying diode naturally decreases to zero, achieving zero-current turn-off. After that, L m , L r and C r resonate together, and the load is powered by the output capacitor C o .

[0096] For example Figure 4k , switching mode 11[t 10 , t 11 : At time t 10 , turn off Q A4 , and the inductor current i La charges the junction capacitance C A4 of Q A4 , and discharges the junction capacitance C A3 of Q A3 . At time t 11 , the voltage of C A4 is charged to V bus , and the voltage of C A3 is discharged to zero. Then the anti-parallel diode D A3 of Q A3 conducts naturally, and at this time Q A3 can be turned on with zero voltage; similarly, Q B4 can be turned on with zero voltage; L m , L r and C r continue to resonate, and the load is powered by the output capacitor C o .

[0097] For example Figure 4l , switching mode 12[t 11 , t 12 : Q A1 and Q A3 are conducting, and the voltage across the inductor L a is V inA - V bus , and the inductor current i La increases linearly; Q B1 and Q B4 are conducting simultaneously, and the voltage across the inductor is V inB , and the inductor current i Lb increases linearly; L r and C r resonate, and the secondary rectifying diodes D R1 and D R4 are conducting, clamping the primary voltage v p of the transformer to NV o , and the primary transfers energy to the secondary, and the exciting current i Lm increases linearly.

[0098] As Figure 4m , switching mode 13 [t 12 , t 13 : Q A1 and Q A3 conduct, and the voltage applied across the inductor L a is V inA -V bus , and the inductor current i La increases linearly; at the moment of t 12 , turn off Q B1 , and the inductor current i Lb charges the junction capacitance C B1 of Q B1 , and at the same time discharges the junction capacitance C B2 of Q B2 . At the moment of t 13 , the voltage of C B1 is charged to V inB , and at the same time the voltage of C B2 is discharged to zero, then the anti-parallel diode D B2 of Q B1 naturally conducts, and at this time Q B2 can be turned on with zero voltage; L r and C r continue to resonate.

[0099] As Figure 4n , switching mode 14 [t 13 , t 14 : Q A1 and Q A3 conduct, and the voltage applied across the inductor L a is V inA -V bus , and the inductor current i La increases linearly; Q B2 and Q B4 conduct, and the voltage applied across the inductor L b is 0, and the inductor current i Lb remains unchanged; L r and C r continue to resonate.

[0100] As Figure 2 in circuit A, the output voltage regulating circuit includes an output voltage regulator, a multiplier, an input current regulator, an adder, a comparator 1 and an RS flip-flop 1. Compare the sampling signal v o of the output voltage V o_s with the given voltage reference V o_ref . Input its error signal into the output voltage regulator, and compare the output v c of the voltage regulator with the absolute value |v of the input voltage sampling signalin_s Multiply to obtain the reference signal i of the input current g_ref , sample the input current i in to get the sampling signal i ina_s (i inb_s ) and compare it with the input current reference signal i g_ref . Input the error signal into the current regulator, and add the output v err1 of the current regulator and V θ(O) to obtain the signal v err1 '. Send v err1 ' and the triangular wave v saw to comparator 1 for comparison to obtain the duty cycle signal D y(O) . D y(O) is the sum of the duty cycle D A1 (Q B1 ) of the switching transistor Q y1(O) and the duty cycle D A4 (Q B4 ) of the switching transistor Q A1 (Q B1 ) corresponding to the conduction time prior to Q θ(O) . Send the signal D y(O) and CLK2(O) to RS flip-flop 1. The positive output signal of RS flip-flop 1 is the drive signal of the switching transistor Q A1 (Q B1 ), and its inverted signal is the drive signal of the switching transistor Q A2 (Q B2 ).

[0101] For example, in circuit B Figure 2 , the input voltage circuit includes an input voltage regulator, an adder, a comparator 2, and an RS flip-flop 2. Compare the sampling signal v inB_s (v inA_s ) of the input capacitor voltage with the given voltage reference V in_refB (V in_refA ). Input the error signal into the input voltage regulator, and add the output v err2 of the voltage regulator and V θ(I) to obtain v err2 '. Send v err2 ' and the triangular wave v saw to comparator 2 for comparison to obtain the signal D y(I) . D y(I) is the sum of the duty cycle D B1 (Q A1 ) of the switching transistor Q y1(I) and the duty cycle D B3 (Q A3 ) of the switching transistor Q B1 (Q A1The duty cycle D corresponding to the conduction time θ(I) The sum of which, D y(I) and CLK2(I) are sent to the RS flip-flop 2, and the positive output signal of the RS flip-flop 2 is the driving signal of the switching transistor Q B1 (Q A1 ) and its inverted signal is the driving signal of the switching transistor Q B2 (Q A2 ).

[0102] Such as Figure 2 in the C circuit, the phase-shifted clock generation circuit controlled by the output voltage includes a phase-shifted signal generation module controlled by the output voltage, a phase-shifted pulse generation module 1, and the switching transistors Q A3 (Q B3 ) and Q A4 (Q B4 ) driving circuit (switching transistor driving circuit 1). Among them, the phase-shifted signal generation module controlled by the output voltage includes a valley current detection circuit, an inverter, a phase-shift regulator 1, and a subtractor. The valley current detection circuit samples and obtains the valley value i La (i Lb ) of the inductor current, which becomes -i L_min after passing through the inverter, and is compared with the given current reference I L_min . The error value is sent to the phase-shift regulator 1, and the phase-shift regulator 1 generates the phase-shifted signal v ZVS_ref(O) between the turn-on times of the switching transistors Q A1 (Q B1 ) and Q A3 (Q B3 ). The phase-shifted signal v err3 is subtracted from 0.5V eror3 through the subtractor to obtain the phase-shifted signal V M between the turn-on times of the switching transistors Q A4 (Q B4 ) and Q A1 (Q B1 ), where V θ(O) is the peak voltage of the triangular wave v M ; saw

[0103] After the phase-shifted pulse generation module 1 receives the phase-shifted signal V θ(O) , V θ(O) and the triangular wave v saw are sent to the comparator 3 for comparison, and then the phase-shifted duty cycle D θ(O) is output. The phase-shifted pulse generation module finally generates two narrow pulses CLK1(O) and CLK2(O) whose phase difference is controlled by D θ(O) . Among them, CLK1(O) is used to control the switching transistor Q A4 (Q B4 ​) turn-on moment, CLK2(O) is used to control the switching transistor Q A1 (Q B1 ) turn-on moment;

[0104] The switching transistor Q A3 (Q B3 ) and Q A4 (Q B4 ) drive circuit, including a delay module 1 and an RS flip-flop 3. The CLK1(O) pulse signal is delayed by T s / 2 and then sent to the RS flip-flop 3 together with CLK1(O) to generate a turn-off signal for half of the switching period. The positive output signal of the RS flip-flop 3 is the drive signal for the switching transistor Q A4 (Q B4 ), and its inverted signal is the drive signal for the switching transistor Q A3 (Q B3 ).

[0105] Such as Figure 2 in the D circuit, the input voltage controlled phase-shifted clock generation circuit includes an input voltage controlled phase-shifted signal generation module, a phase-shifted pulse generation module 2, and the switching transistors Q B3 (Q A3 ) and Q B4 (Q A4 ) drive circuit (switching transistor drive circuit 2). Among them, the input voltage controlled phase-shifted generation module includes a peak current detection circuit and a phase-shift regulator 2. The peak current detection circuit samples the peak value i Lb (i La ) of the inductor current i L_max , compares it with the given current reference I ZVS_ref(I) , and sends the error value to the phase-shift regulator 2. The phase-shift regulator 2 generates a phase-shifted signal V B3 (Q A3 ) and Q B1 (Q A1 ) between the turn-on moments; θ(I) ;

[0106] After the phase-shifted pulse generation module 2 receives the phase-shifted signal V θ(I) , it sends V θ(I) and the triangular wave v saw to the comparator 3 for comparison, and then outputs the phase-shifted duty cycle D θ(I) . The phase-shifted pulse generation module finally generates two narrow pulses CLK1(I) and CLK2(I) whose phase difference is controlled by D θ(I) . Among them, CLK1(I) is used to control the turn-on moment of the switching transistor Q B3 (Q A3 ), and CLK2(I) is used to control the turn-on moment of the switching transistor Q B1 (QA1 ) turn-on time;

[0107] The switching transistor Q B3 (Q A3 ) and Q B4 (Q A4 ) drive circuit, including a delay module 2 and an RS flip-flop 4. The CLK1(I) pulse signal is delayed by T s / 2 and then sent to the RS flip-flop 4 together with CLK1(I) to generate a turn-off signal for half of the switching period. The positive output signal of the RS flip-flop 4 is the drive signal for the switching transistor Q B3 (Q A3 ), and its inverted signal is the drive signal for the switching transistor Q B4 (Q A4 ).

[0108] Such as Figure 2 the E circuit in. The switching signal gating circuit includes a comparator 5 and a switching signal gating module. The input voltage and 0 are sent to the comparator 5 for comparison to generate a V sel signal. In the positive half-cycle of the input voltage, V sel is high level, and at this time, the selection switch channel 1 is turned on. In the negative half-cycle of the input voltage, V sel is low level, and at this time, the selection switch channel 2 is turned on.

[0109] The present invention also proposes a control method for a bridge-arm multiplexing soft-switching AC-DC converter. The specific control method is as follows:

[0110] In the positive half-cycle of the input voltage, V sel is high level. At this time, the selection switch channel 1 is turned on. The output voltage sampling signal is subjected to power factor correction through a voltage regulator, a multiplier, and a current regulator, and then a duty cycle D A1 of the switching transistor Q y1(O) is generated. Its inverted signal is used to control Q A2 , and the valley value of the inductor current of the inductor L a is output as a phase-shifted duty cycle D θ(O) after passing through an inverter, a phase-shift regulator, and a subtractor. Two narrow pulses CLK1(O) and CLK2(O) are generated through a phase-shift pulse signal generation module 1 to respectively control the turn-on times of Q A4 and Q A1 . Among them, CLK1(O) generates a turn-off signal for Q A4 after being delayed by half of the switching period; the voltage sampling signal of the input capacitor C inB generates a duty cycle D B1 of the switching transistor Q y1(I) . Its inverted signal is used to control Q B2 ; the inductor L bThe peak value of the inductor current outputs a phase-shifted duty cycle D after passing through the phase-shifting regulator. θ(I) , two narrow pulses CLK1(I) and CLK2(I) are generated by the phase-shifting pulse signal generation module 2 to respectively control Q B3 and Q B1 's turn-on moment, where the turn-off signal of Q B3 is generated after CLK1(I) is delayed by half a switching cycle.

[0111] During the negative half-cycle of the input voltage, V sel is at a low level, the switch channel 2 is selected to turn on, the output voltage sampling signal passes through the voltage regulator, then through the multiplier and the current regulator to achieve power factor correction and generate the duty cycle D B1 of the switching transistor Q y1(O) , and its inverted signal is used to control Q B2 , the valley value of the inductor current of the inductor L b outputs a phase-shifted duty cycle D after passing through the inverter, the phase-shifting regulator and the subtractor, and two narrow pulses CLK1(O) and CLK2(O) are generated by the phase-shifting pulse signal generation module 1 to respectively control Q θ(O) and Q B4 's turn-on moment, where the turn-off signal of Q B1 is generated after CLK1(O) is delayed by half a switching cycle; the voltage sampling signal of the input capacitor C B4 generates the duty cycle D inA of the switching transistor Q A1 , and its inverted signal is used to control Q y1(I) ; the peak value of the inductor current of the inductor L A2 outputs a phase-shifted duty cycle D after passing through the phase-shifting regulator, and two narrow pulses CLK1(I) and CLK2(I) are generated by the phase-shifting pulse signal generation module 2 to respectively control Q a and Q θ(I) 's turn-on moment, where the turn-off signal of Q A3 is generated after CLK1(I) is delayed by half a switching cycle. A1 A3

[0112] The present invention can achieve full-range soft switching, electrical isolation and wide-range voltage regulation, effectively reduce the number of devices, and can achieve high power density, high conversion efficiency and high reliability.

[0113] To further illustrate the superiority of the circuit topology and its control strategy of the present invention, a simulation example of the present invention is given below.

[0114] According to the main parameters of the 500W bridge-arm multiplexing soft-switching AC-DC converter given in Table 1, a simulation circuit is built with Saber simulation software.

[0115] Table 1 Main parameters of the arm multiplexing soft-switching AC-DC converter

[0116] Parameter Symbol Value Parameter Symbol Value Input voltage <![CDATA[V in > 220V / 50Hz Field inductance <![CDATA[L m > 483 μH Output voltage <![CDATA[V o > 24V Resonant inductance <![CDATA[L r > 22.8 μH Output power <![CDATA[P o > 500W Resonant capacitor <![CDATA[C r > 91.8 nF Switching frequency <![CDATA[f s > 100 kHz Transformer turns ratio N 15:1 Input capacitor <![CDATA[C in , C in2 > 2 μF Intermediate bus capacitor <![CDATA[C bus > 1 mF Inductor <![CDATA[L a , L b > 75 μH Output capacitor <![CDATA[C o > 5 mF

[0117] Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 The simulation waveform diagram of the 500W arm multiplexing soft-switching AC-DC converter is given. It can be seen from Figure 5 that v in and i in are the input AC voltage and input AC current respectively, V o is the output voltage, i La and i Lb are the inductor currents of L a and L b respectively. i in can track the v in waveform well, realizing high power factor correction. It can be seen from Figure 6 that under the switching period, the inductor current i a of L La is modulated into a quadrilateral, which can realize the ZVS (Zero Voltage Switching) turn-on of the switching tube. It can be seen from Figure 7 that under the switching period, the inductor current i b of L Lb is modulated into a quadrilateral, which can realize the ZVS turn-on of the switching tube. It can be seen from Figure 8 that the secondary rectifier diode also realizes ZCS (Zero Current Shutdown).

[0118] The above is only the preferred embodiment of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the idea of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, several improvements and refinements made without departing from the principle of the present invention should be regarded as within the protection scope of the present invention.

Claims

1. A bridge arm multiplexing soft switching AC-DC converter, characterized in that: The bridge arm multiplexing soft-switching AC-DC converter includes a bridgeless AC-DC converter and a full-bridge LLC resonant converter; The bridgeless AC-DC converter includes an input AC voltage source v in , input capacitor C inA , input capacitor C inB 、Inductance L a 、Inductance L b 、Intermediate bus capacitor C bus , switch tube Q A1 Its anti-parallel diode D A1 and junction capacitance C A1 , switch tube Q A2 Its anti-parallel diode D A2 and junction capacitance C A2 , switch tube Q A3 Its anti-parallel diode D A3 and junction capacitance C A4 , switch tube Q A4 Its anti-parallel diode D A4 and junction capacitance C A4 , switch tube Q B1 Its anti-parallel diode D B1 and junction capacitance C B1 , switch tube Q B2 Its anti-parallel diode D B2 and junction capacitance C B2 , switch tube Q B3 Its anti-parallel diode D B3 and junction capacitance C B3 , switch tube Q B4 Its anti-parallel diode D B4 and junction capacitance C B4 ;Q A1 and Q A2 , Q B1 and Q B2 , Q A3 and Q A4 , Q B3 and Q B4 They are complementary and conduct respectively, forming bridge arms 1, 2, 3, and 4, respectively. inA , C inB , C bus Connected in series at both ends of bridge arms 1, 2, and 3, respectively, v in Connected in Q A1 Drain and Q B1 Between drain, L a Connected in series between the midpoint of bridge arm 1 and the midpoint of bridge arm 3, L b Connected in series between the midpoint of bridge arm 2 and the midpoint of bridge arm 4; The full-bridge LLC resonant converter includes a resonant inductor L r , Excitation inductance L m , resonant capacitor C r 、Transformer T r , output filter capacitor C o , rectifier diode D R1 , D R2 , D R3 , D R4 and load R Ld , and reuse Q A3 and Q A4 The bridge arm 3 and Q B3 and Q B4 The bridge arm 4 is formed; L m In parallel with T r The two ends of the original side, and T r One end of the primary side is connected in series with L r , C r Connect the midpoint of bridge arm 3, T r The other end of the primary side is connected to the midpoint of bridge arm 4; D R1 , D R2 Series, D R3 , D R4 Series, and two series circuits in parallel, C o , R Ld Both are connected in parallel with the two series circuits, T r One end of the secondary side is connected to D R1 , D R2 The other end is connected to D R3 , D R4 The connection point; Q A3 , Q A4 , Q B3 , Q B4 The duty cycle of Q A3 and Q B4 At the same time, Q A4 and Q B3 On and off at the same time.

2. The bridge arm multiplexing soft-switching AC-DC converter according to claim 1, characterized in that: Q A1 The drain and D A1 The cathode and C A1 One end is connected to Q A1 The source and D A1 The anode and C A1 The other end is connected to Q A2 The drain and D A2 The cathode and C A2 One end is connected to Q A2 The source and D A2 The anode and C A2 The other end is connected to Q A3 The drain and D A3 The cathode and C A3 One end of Q A3 The source and D A3 The anode and C A3 The other end is connected to Q A4 The drain and D A4 The cathode and C A4 One end is connected to Q A4 The source and D A4 The anode and C A4 The other end is connected to Q B1 The drain and D B1 The cathode and C B1 One end is connected to Q B1 The source and D B1 The anode and C B1 The other end is connected to Q B2 The drain and D B2 The cathode and C B2 One end is connected to Q B2 The source and D B2 The anode and C B2 The other end is connected to Q B3 The drain and D B3 The cathode and C B3 One end of Q B3 The source and D B3 The anode and C B3 The other end is connected to Q B4 The drain and D B4 The cathode and C B4 One end is connected to Q B4 The source and D B4 The anode and C B4 The other end is connected.

3. The bridge arm multiplexing soft-switching AC-DC converter according to claim 1, characterized in that: v in One end of C inA One end and Q A1 The drain of A1 the source and Q A2 The drain and L a One end is connected to L a The other end of the Q A3 the source and Q A4 The drain and C r One end of C r The other end and L r One end is connected to L r The other end of L m One end and T r One end of the original side is connected, Q A3 The drain and Q B3 The drain and C bus One end is connected to v in The other end of the inB One end and Q B1 The drain of B1 the source and Q B2 The drain and inductance L b One end of the inductor is connected to b The other end of the Q B3 the source and Q B4 The drain and L m The other end and T r The other end of the original side is connected, Q A2 the source and Q B2 the source and Q A4 the source and Q B4 The source and C inA The other end and C inB The other end and C bus The other end of the secondary side is connected to D R1 The anode and D R3 The cathode of R1 The cathode and D R2 The cathode and C o One end and the load R Ld One end of the secondary side is connected to D R2 The anode and D R4 The cathode of R3 The anode and D R4 The anode and C o The other end and R Ld The other end is connected.

4. The bridge arm multiplexing soft-switching AC-DC converter according to claim 1, characterized in that: The bridge arm multiplexing soft-switching AC-DC converter includes 14 switching modes, which are: Switching mode 1 [t0, t1]: At t0, turn off Q A1 , L a The inductor current i La Give Q A1 C A1 Charging and Q A2 C A2 Discharge; at time t1, C A1 The voltage is charged to V inA , where V inA is the input capacitance C inA On voltage, C A2 The voltage is reduced to zero, then Q A2 The anti-parallel diode D A2 Natural conduction, at this time, Q can be turned on with zero voltage A2 ;Q B2 and Q B4 conduction, add to L b The voltage across the two ends is 0, L b The inductor current i Lb Remain unchanged; L r and C r Resonant operation, secondary rectifier diode D R1 and D R4 conduction, the transformer primary voltage v p Clamp to NV o , the primary side transfers energy to the secondary side, L m The excitation current i Lm Linear increase, where N is the turn side of the transformer primary and secondary, V o is the output voltage; Switching mode 2[t1,t2]:Q A2 and Q A3 At the same time, add L a The voltage across the two ends is -V bus , where V bus C bus Upper voltage, i La Linear decrease; Q B2 and Q B4 conduction, add to L b The voltage across the two ends is 0, i Lb Remain unchanged; L r and C r Continue to work in resonance; Switching mode 3[t2,t3]:Q A2 and Q A3 At the same time, add L a The voltage across the two ends is -V bus ,i La Linear decrease; Q B2 and Q B4 On, inductance L b The voltage across the two ends is 0, i Lb remains unchanged; at time t2, the resonant current i Lr Resonance to the excitation current i Lm equal, the secondary rectifier diode current naturally decreases to zero, achieving zero current shutdown; thereafter, L m , L r and C r The three work in resonance, and the load is C o powered by; Switching mode 4 [t3, t4]: At t3, turn off Q A3 ,i La Give Q A3 C A3 Charging and Q A4 C A4 Discharge; at t4, C A3 The voltage is charged to V bus , while C A4 The voltage is reduced to zero, then Q A4 The anti-parallel diode D A4 Natural conduction, at this time, Q can be turned on with zero voltage A4 ; Similarly, Q can be turned on at zero voltage B3 ; L m , L r and C r The three continue to work in resonance, and the load is C o powered by; Switching mode 5[t4,t5]: Q A2 and Q A4 conduction, add to L a The voltage across the two ends is 0, i La Remain unchanged; Q B2 and Q B3 At the same time, the inductor L a The voltage across the two ends is -V bus ,i Lb Linear decrease; L r and C r Resonant operation, secondary side D R2 and D R3 conduction, the transformer primary voltage v p Clamp to -NV o , the primary side transfers energy to the secondary side, and the excitation current i Lm Linear decline; Switching mode 6[t5,t6]:Q A2 and Q A4 conduction, add to L a The voltage across the two ends is 0, i La Remain unchanged; at t5, turn off Q B2 ,i Lb Give Q B2 C B2 Charging and Q B1 C B1 Discharge; at t6, C B2 The voltage is charged to V inB , where V inB C inB On voltage, C B1 The voltage is reduced to zero, then Q B1 The anti-parallel diode D B1 Natural conduction, at this time, Q can be turned on with zero voltage B1 ; L r and C r Continue to work in resonance; Switching mode 7[t6,t7]: Q A2 and Q A4 conduction, add to L a The voltage across the two ends is 0, i La Remain unchanged; Q B1 and Q B3 conduction, add to L b The voltage across the terminals is V inB -V bus ,i Lb Linear decrease; L r and C r Continue to work in resonance; Switching mode 8 [t7, t8]: At t7, turn off Q A2 ,i La Give Q A2 C A2 Charging and Q A1 C A1 Discharge; at t8, C A2 The voltage is charged to V inA , while C A1 The voltage is reduced to zero, then Q A1 The anti-parallel diode D A1 Natural conduction, at this time, Q can be turned on with zero voltage A1 ;Q B1 and Q B3 conduction, add to L b The voltage across the terminals is V inB -V bus ,i Lb Linear decrease; L r and C r Continue to work in resonance; Switching mode 9[t8,t9]: Q A1 and Q A4 conduction, add to L a The voltage across the terminals is V inA ,i La Linear increase; Q B1 and Q B3 conduction, add to L b The voltage across the terminals is V inB -V bus ,i Lb Linear decrease; L r and C r Continue to work in resonance; Switching mode 10[t9,t 10 ]:Q A1 and Q A4 conduction, add to L a The voltage across the terminals is V inA ,i La Linear increase; Q B1 and Q B3 conduction, add to L b The voltage across the terminals is V inB -V bus ,i Lb Linear decrease; at t9, the resonant current i Lr When the resonant current is equal to the excitation current, the secondary rectifier diode current naturally decreases to zero, achieving zero current shutdown; thereafter, L m , L r and C r The three work in resonance, and the load is C o powered by; Switching mode 11[t 10 ,t 11 ]:In t 10 At this moment, turn off Q A4 ,i La Give Q A4 C A4 Charging and Q A3 C A3 Discharge; at t 11 Moment, C A4 The voltage is charged to V bus , while C A3 The voltage is reduced to zero, then Q A3 The anti-parallel diode D A3 Natural conduction, at this time, Q can be turned on with zero voltage A3 Similarly, Q can be turned on at zero voltage B4 ; L m , L r and C r The three continue to work in resonance, and the load is C o powered by; Switching mode 12[t 11 ,t 12 ]:Q A1 and Q A3 conduction, add to L a The voltage across the terminals is V inA -V bus ,i La Linear increase; Q B1 and Q B4 At the same time, the inductor L a The voltage across the terminals is V inB ,i Lb Linear increase; L r and C r Resonant operation, secondary rectifier diode D R1 and D R4 conduction, the transformer primary voltage v p Clamp to NV o , the primary side transfers energy to the secondary side, and the excitation current i Lm Linear increase; Switching mode 13[t 12 ,t 13 ]:Q A1 and Q A3 conduction, add to L a The voltage across the terminals is V inA -V bus ,i La Linear increase; at t 12 At this moment, turn off Q B1 ,i Lb Give Q B1 The junction capacitance C B1 Charging and Q B2 C B2 Discharge; at t 13 Moment, C B1 The voltage is charged to V inB , while C B2 The voltage is reduced to zero, then Q B2 The anti-parallel diode D B1 Natural conduction, at this time, Q can be turned on with zero voltage B2 ; L r and C r Continue to work in resonance; Switch mode 14[t 13 ,t 14 ]:Q A1 and Q A3 conduction, add to L a The voltage across the terminals is V inA -V bus ,i La Linear increase; Q B2 and Q B4 conduction, add to L b The voltage across the two ends is 0, i Lb Remain unchanged; L r and C r Continue to work in resonance.

5. A control circuit for a bridge arm multiplexing soft-switching AC-DC converter according to any one of claims 1 to 4, characterized in that: The control circuit includes an output voltage regulating circuit, an input voltage regulating circuit, an output voltage controlled phase shift clock generating circuit, an input voltage controlled phase shift clock generating circuit, and a switch signal gating circuit; The output voltage regulating circuit is used to sample the output voltage and compare it with a given voltage reference, stabilize the output voltage through a voltage regulator and a current regulator, and realize power factor correction; The input voltage regulating circuit is used to sample the input capacitor voltage and compare it with a given voltage reference, and to control the input capacitor voltage through closed-loop regulation of the input voltage regulator; The output voltage controlled phase shift clock generating circuit is used to sample L a or L b The valley current of the inductor current is converted to the given current reference I after passing through the inverter. ZVS_ref(O) The error value obtained by comparison is sent to the phase shift regulator 1. The signal generated by the phase shift regulator 1 is passed through the subtractor to generate a phase shift signal V θ(O) ; The phase shift signal V θ(O) After entering the phase shift pulse generation module 1, the phase shift duty ratio D is first generated θ(O) , and finally generate two phase differences affected by D θ(O) Controlled narrow pulses CLK1(O) and CLK2(O), CLK1(O) controls Q A4 , Q B4 At the turn-on time, CLK2(O) controls Q A1 , Q B1 The opening time of The input voltage controlled phase shift clock generating circuit is used to sample i Lb or La The peak current i L_max , with a given current reference I ZVS_ref(I) The error value obtained by comparison is sent to the phase shift regulator 2, and the phase shift regulator 2 generates a phase shift signal V θ(I) , the phase shift signal V θ(I) After entering the phase shift pulse generation module 2, the phase shift duty ratio D is first generated θ(I) , and finally generate two phase differences affected by D θ(I) The narrow pulses CLK1(I) and CLK2(I) are controlled. CLK1(I) controls Q B3 , Q A3 At the turn-on time, CLK2(I) controls the switch tube Q B1 , Q A1 The opening time of The switch signal selection circuit is used to send the input voltage and 0 to the comparator 5 for comparison and then generate V sel signal, in the positive half cycle of the input voltage, V sel is high, this selection switch channel 1 is turned on, and in the negative half cycle of the input voltage, V sel It is a low level, and switch channel 2 is selected to be turned on.

6. The control circuit according to claim 5, characterized in that: The output voltage regulation circuit includes an output voltage regulator, a multiplier, an input current regulator, an adder, a comparator 1 and an RS trigger 1. The output voltage V o The sampled signal v o_s With a given voltage reference V o_ref The error signal is compared and input to the output voltage regulator. The multiplier converts the output of the voltage regulator v c The absolute value of the input voltage sampling signal |v in_s |Multiply to get the reference signal i of the input current g_ref , change i g_ref With input current i in The sampled signal is compared with the error signal obtained by comparison, and the error signal is input into the current regulator. The adder converts the output v of the current regulator into err1 and V θ(O) After adding, we get the signal v err1 ′,v err1 ′ and triangle wave signal v saw It is sent to comparator 1 for comparison to obtain the duty cycle signal D y(O) , D y(O) and CLK2(O) are sent to RS flip-flop 1, and the positive output signal of RS flip-flop 1 is Q A1 , Q B1 The driving signal, its inverted signal is Q A2 , Q B2 The driving signal.

7. The control circuit according to claim 5, characterized in that: The input voltage regulation circuit includes an input voltage regulator, an adder, a comparator 2 and an RS trigger 2. The sampling signal of the input capacitor voltage is compared with a given voltage reference, and the error signal obtained by the comparison is input to the input voltage regulator. The adder converts the output v err2 and V θ(I) After adding, we get v err2 ′, v err2 ′ and the triangle wave signal v saw It is sent to comparator 2 for comparison and the signal D is obtained. y(I) , D y(I) and CLK2(I) are sent to RS trigger 2. The positive output signal of RS trigger 2 is the switch tube Q B1 , Q A1 The driving signal of the switch tube Q B2 , Q A2 The driving signal.

8. The control circuit according to claim 5, characterized in that: The output voltage controlled phase shift clock generating circuit comprises an output voltage controlled phase shift signal generating module, a phase shift pulse generating module 1 and a switch tube driving circuit 1; The output voltage controlled phase shift signal generating module comprises a valley current detection circuit, an inverter, a phase shift regulator 1 and a subtractor; The valley current detection circuit samples the L a or L b The valley value of the inductor current is converted to the given current reference I after passing through the inverter. ZVS_ref(O) The error value obtained by comparison is sent to the phase shift regulator 1. The signal generated by the phase shift regulator 1 is subtracted from the 0.5V M Subtract the phase shift signal V θ(O) , where V M is the triangle wave signal v saw The peak voltage of The phase-shift pulse generating module 1 receives the phase-shift signal V θ(O) After that, V θ(O) With the triangle wave signal v saw After being sent to comparator 3 for comparison, the output phase shift duty ratio D θ(O) The phase shift pulse generating module 1 finally generates two phase difference pulses D θ(O) The narrow pulses CLK1(O) and CLK2(O) are used to control the switch tube Q. A4 , Q B4 The opening moment of the switch tube Q is controlled by CLK2(O). A1 , Q B1 The opening time of The switch tube driving circuit 1 includes a delay module 1 and an RS trigger 3. The delay module 1 delays the CLK1(O) pulse signal by half of the switching cycle and then sends it to the RS trigger 3 together with CLK1(O) to generate a turn-off signal of half the switching cycle. The positive output signal of the RS trigger 3 is the switch tube Q A4 , Q B4 The driving signal of the switch tube Q A3 , Q B3 The driving signal.

9. The control circuit according to claim 5, characterized in that: The input voltage controlled phase shift clock generating circuit comprises an input voltage controlled phase shift signal generating module, a phase shift pulse generating module 2 and a switch tube driving circuit 2; The input voltage controlled phase shift generation module comprises a peak current detection circuit and a phase shift regulator 2; the peak current detection circuit samples and obtains L a or L b The peak value of the inductor current is compared with the given current reference I ZVS_ref(I) The error value obtained by comparison is sent to the phase shift regulator 2, and the phase shift regulator 2 generates a phase shift signal V θ(I) ; The phase-shift pulse generating module 2 receives the phase-shift signal V θ(I) After that, V θ(I) With the triangle wave signal v saw After being sent to comparator 3 for comparison, the output phase shift duty ratio D θ(I) The phase shift pulse generating module 2 finally generates two phase difference pulses D θ(I) The narrow pulses CLK1(I) and CLK2(I) are used to control the switch tube Q. B3 , Q A3 ) is turned on, CLK2(I) is used to control the switch tube Q B1 , Q A1 The opening time of The switch tube driving circuit 2 includes a delay module 2 and an RS trigger 4. The delay module 2 delays the CLK1(I) pulse signal by half of the switching cycle and then sends it to the RS trigger 4 together with CLK1(I) to generate a turn-off signal of half the switching cycle. The positive output signal of the RS trigger 4 is the switch tube Q B3 , Q A3 The driving signal of the switch tube Q B4 , Q A4 The driving signal.

10. A control method for a bridge arm multiplexing soft-switching AC-DC converter implemented by a control circuit according to any one of claims 5 to 9, characterized in that: The control method comprises: sending the input voltage and 0 to the comparator 5 for comparison and then generating V sel signal, in the positive half cycle of the input voltage, V sel The output voltage sampling signal is passed through the voltage regulator, the multiplier and the current regulator to realize power factor correction and generate Q A1 Duty cycle D y1(O) , whose inverted signal is used to control Q A2 , L a The inductor current valley value is output as phase shift duty ratio D after passing through inverter, phase shift regulator and subtractor. θ(O) , two narrow pulses CLK1(O) and CLK2(O) are generated by the phase-shift pulse signal generating module 1 to control Q A4 and Q A1 The turn-on moment, where CLK1(O) is delayed by half a switching cycle to generate Q A4 The shutdown signal of C inB The voltage sampling signal is passed through the voltage regulator to generate the switch tube Q B1 Duty cycle D y1(I) , whose inverted signal is used to control Q B2 ; L b The peak value of the inductor current is output through the phase shift regulator to achieve a phase shift duty ratio D θ(I) , two narrow pulses CLK1(I) and CLK2(I) are generated by the phase-shift pulse signal generating module 2 to control Q B3 and Q B1 The turn-on moment, where CLK1(I) is delayed by half a switching cycle to generate Q B3 The shutdown signal; During the negative half cycle of the input voltage, V sel When the voltage is low, switch channel 2 is selected to be turned on. The output voltage sampling signal passes through the voltage regulator, the multiplier and the current regulator to achieve power factor correction and generate the switch tube Q B1 Duty cycle D y1(O) , whose inverted signal is used to control Q B2 , L b The inductor current valley value is output as phase shift duty ratio D after passing through inverter, phase shift regulator and subtractor. θ(O) , two narrow pulses CLK1(O) and CLK2(O) are generated by the phase-shift pulse signal generating module 1 to control Q B4 and Q B1 The turn-on moment, where CLK1(O) is delayed by half a switching cycle to generate Q B4 The shutdown signal of C inA The voltage sampling signal is passed through the voltage regulator to generate the switch tube Q A1 Duty cycle D y1(I) , whose inverted signal is used to control Q A2 ; L a The peak value of the inductor current is output through the phase shift regulator to achieve a phase shift duty ratio D θ(I) , two narrow pulses CLK1(I) and CLK2(I) are generated by the phase-shift pulse signal generating module 2 to control Q A3 and Q A1 The turn-on moment, where CLK1(I) is delayed by half a switching cycle to generate Q A3 The shutdown signal.

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