Digital signal interpolation filtering method and device, electronic equipment and storage medium

Abstract

The invention discloses a digital signal interpolation filtering method and device, electronic equipment and a storage medium. The method comprises the following steps: determining a first signal after interpolation and before filtering, and a signal path number and an interpolation multiple corresponding to the first signal, and determining an impact response and a corresponding order of a filter, the impact response of the filter having symmetry; performing convolution operation on the first signal and the impact response to obtain a first expression corresponding to the output signal; decomposing the convolution operation in the first expression into a plurality of convolution sub-operations by adopting a multi-phase decomposition technology to obtain a second expression corresponding to the output signal; the second expression is simplified, an output signal is determined according to the simplified second expression, and the simplification operation is used for reducing the operation amount of multiplication and addition in convolution sub-operation by using the symmetry of the filter. According to the invention, the technical problems of large operand and insufficient stop-band suppression during digital signal interpolation filtering in the prior art are solved.

Description

Technical Field

[0001] The present application relates to the technical field of baseband digital signal processing, and in particular, to a digital signal interpolation filtering method, apparatus, electronic device, and storage medium. Background Art

[0002] Signal interpolation technology is to restore a low-rate baseband signal into a high-rate signal and convert the signal into a high-rate analog signal through a DAC (Digital-to-Analog Converter). Considering ensuring that the signal itself is not distorted, interpolation filters usually adopt linear-phase filters, commonly including FIR filters, CIC (Cascaded Integrator-Comb) filters, etc. The CIC filter can complete the filtering operation through simple addition, but its transition band is relatively wide and the stopband suppression is insufficient, which is not applicable in some scenarios with strict requirements for signal bandwidth. The passband and stopband of the FIR (Finite Impulse Response) filter are relatively flexible in design and can be applied to the interpolation filtering of various signals. However, its filter coefficients are usually not 0 or 1 and need to be expressed by variables with a certain precision. Therefore, more multiplications and additions are required during its filtering calculation. Especially when processing ultra-wideband signals in an FPGA (Field-Programmable Gate Array), it not only brings great pressure on computing resources but also brings high power consumption.

[0003] In the related art, the symmetry of the FIR filter is mainly applied in the decimation filter, and the calculation amount can also be reduced. However, there is a lack of a scheme for utilizing the symmetry of the FIR filter in the interpolation filter, and there is also a lack of a general calculation method for different numbers of input signal paths, filter orders, and interpolation multiples.

[0004] To address the above problems, no effective solution has been proposed yet. Summary of the Invention

[0005] Embodiments of the present application provide a digital signal interpolation filtering method, apparatus, electronic device, and storage medium to at least solve the technical problems of large computing amount and insufficient stopband suppression during digital signal interpolation filtering in the related art.

[0006] According to one aspect of the embodiments of the present application, a digital signal interpolation filtering method is provided, including: determining a first signal after interpolation and before filtering, the number of signal paths corresponding to the first signal, and the interpolation multiple, and determining the impulse response of the filter and the corresponding order, wherein the impulse response of the filter has symmetry; performing a convolution operation on the first signal and the impulse response to obtain a first expression corresponding to the output signal; using the polyphase decomposition technique to decompose the convolution operation in the first expression into multiple convolution sub-operations to obtain a second expression corresponding to the output signal; performing a simplification operation on the second expression, and determining the output signal according to the simplified second expression, wherein the simplification operation is used to utilize the symmetry of the filter to reduce the amount of multiplication and addition operations in the convolution sub-operations.

[0007] Optionally, determining the first signal after interpolation and before filtering, the number of signal paths corresponding to the first signal, and the interpolation multiple includes: defining the first signal as x(n), the number of signal paths as D, and the difference multiple as Q; determining the impulse response of the filter and the corresponding order includes: determining the impulse response as h t (n), the order as N - 1, where N is an integer power of 2, and for any index m, h(m) = h(N - 1 - m) is satisfied; determining the first expression corresponding to the output signal, where the first expression is as shown in the following formula: Decomposing the convolution operation in the first expression into multiple convolution sub-operations to obtain a second expression corresponding to the output signal includes: letting n = mD + p, where p is the phase index, p = 0, 1, 2... D - 1; representing y(n) as y′(m, p) to obtain the second expression, as shown in the following formula: y′(m, p) = ∑ k N ＝-0 1 h t (k) × x(mD + p - k).

[0008] Optionally, performing a simplification operation on the second expression includes: transforming the second expression into the following representation form: y′(m, p) = g(m, p) - f(m, p); where floor() represents rounding down, % represents taking the remainder, g(m, p) and f(m, p) respectively represent two different calculation parts, and the corresponding calculation formulas are as shown below:

[0009]

[0010] Optionally, since x(n) is the signal after Q-fold interpolation, when k - p ≠ Qi, x(mD - (k - p)) = 0, then the second expression can be simplified to the following first formula: Among them, ceil represents rounding up, floor represents rounding down, and the first formula satisfies: Then the first formula can be further expressed as the second formula shown below: Let Then The second formula can be expressed as the third formula shown below:

[0011] Substitute it into floor in the third formula. p Q / , the following fourth formula can be obtained: Based on the third formula and the fourth formula, the following fifth formula can be determined:

[0012] Optionally, express the third formula as the sixth formula shown below:

[0013] Express the fifth formula as the seventh formula shown below:

[0014] Let:

[0015] Then the sixth formula and the seventh formula can be expressed as: y′(m,p) = g(m,p) - f(m,p);

[0016]

[0017] Optionally, since the filter is symmetrically designed, therefore: is centrosymmetric, is centrosymmetric negatively; thus, g(m,p) can be expressed in the form of the following eighth formula:

[0018]

[0019] f(m,p) can be expressed in the form of the following ninth formula:

[0020]

[0021]

[0022] According to another aspect of the embodiments of the present application, there is also provided a digital signal interpolation filtering device, including: a parameter determination module, configured to determine a first signal before filtering after interpolation, the number of signal paths corresponding to the first signal, and an interpolation multiple, and determine the impulse response of the filter and the corresponding order, wherein the impulse response of the filter has symmetry; a convolution operation module, configured to perform a convolution operation on the first signal and the impulse response to obtain a first expression corresponding to the output signal; a polyphase decomposition module, configured to use polyphase decomposition technology to decompose the convolution operation in the first expression into multiple convolution sub-operations to obtain a second expression corresponding to the output signal; an operation simplification module, configured to perform a simplification operation on the second expression and determine the output signal according to the simplified second expression, wherein the simplification operation is used to utilize the symmetry of the filter to reduce the amount of multiplication and addition operations in the convolution sub-operations.

[0023] According to yet another aspect of the embodiments of the present application, there is also provided an electronic device, including: a memory and a processor, where the processor is configured to run a program stored in the memory, and when the program runs, it executes the digital signal interpolation filtering method.

[0024] According to still another aspect of the embodiments of the present application, there is also provided a non-volatile storage medium, the non-volatile storage medium including a stored computer program, where the device where the non-volatile storage medium is located executes the digital signal interpolation filtering method by running the computer program.

[0025] According to still another aspect of the embodiments of the present application, there is also provided a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the steps of the digital signal interpolation filtering method.

[0026] In the embodiments of the present application, by determining the first signal before filtering after interpolation, the number of signal paths corresponding to the first signal, and the interpolation multiple, and determining the impulse response of the filter and the corresponding order, wherein the impulse response of the filter has symmetry; performing a convolution operation on the first signal and the impulse response to obtain a first expression corresponding to the output signal; using polyphase decomposition technology to decompose the convolution operation in the first expression into multiple convolution sub-operations to obtain a second expression corresponding to the output signal; performing a simplification operation on the second expression and determining the output signal according to the simplified second expression, wherein the simplification operation is used to utilize the symmetry of the filter to reduce the amount of multiplication and addition operations in the convolution sub-operations, a digital signal interpolation filtering method based on FPGA and FIR filter is provided, achieving the purpose of significantly reducing the amount of operations when using a better-performance FIR interpolation filter, and further solving the technical problems of large amount of operations and insufficient stopband suppression in the related technology during digital signal interpolation filtering. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0028] Figure 1 is a hardware structure block diagram of a computer terminal (or electronic device) for implementing a method for digital signal interpolation filtering according to an embodiment of the present application;

[0029] Figure 2 is a schematic diagram of a method flow for digital signal interpolation filtering according to an embodiment of the present application;

[0030] Figure 3 is a schematic structural diagram of a digital signal interpolation filtering device according to an embodiment of the present application. Detailed implementation manners

[0031] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0032] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above accompanying drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0033] In the related art, there is a lack of a solution to utilize the symmetry of the FIR filter in the interpolation filter, and there is no general calculation method for different numbers of input signal paths, filter orders, and interpolation multiples, resulting in problems such as large computational amounts and insufficient stopband suppression.

[0034] To solve the above problems, relevant solutions are provided in the embodiments of the present application, which are described in detail below.

[0035] According to an embodiment of the present application, an embodiment of a method for digital signal interpolation filtering is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0036] The method embodiment provided by the embodiment of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Figure 1 The hardware structure block diagram of a computer terminal (or electronic device) for implementing the digital signal interpolation filtering method is shown. As Figure 1 shown, the computer terminal 10 (or electronic device) may include one or more (shown as 102a, 102b,..., 102n in the figure) processors 102 (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory 104 for storing data, and a transmission device 106 for communication functions. In addition, it may further include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of the BUS bus), a network interface, a power supply, and / or a camera. Those of ordinary skill in the art can understand that Figure 1 the structure shown is only schematic and does not limit the structure of the above-mentioned electronic device. For example, the computer terminal 10 may further include more or fewer components than Figure 1 shown, or have a different configuration from Figure 1 shown.

[0037] It should be noted that the above one or more processors 102 and / or other data processing circuits are generally referred to as "data processing circuits" in this article. The data processing circuit can be embodied as software, hardware, firmware, or any combination thereof, in whole or in part. In addition, the data processing circuit can be a single independent processing module, or be incorporated in whole or in part into any one of the other elements in the computer terminal 10 (or electronic device). As involved in the embodiment of the present application, the data processing circuit is used for processor control (such as the selection of a variable resistor terminal path connected to an interface).

[0038] The memory 104 can be used to store software programs and modules of application software, such as the program instructions / data storage device corresponding to the digital signal interpolation filtering method in the embodiments of the present application. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, implements the above digital signal interpolation filtering method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some instances, the memory 104 may further include a memory remotely disposed relative to the processor 102, and these remote memories can be connected to the computer terminal 10 through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0039] The transmission device 106 is used to receive or send data via a network. Specific examples of the above network may include a wireless network provided by a communication provider of the computer terminal 10. In one instance, the transmission device 106 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station and thus can communicate with the Internet. In one instance, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0040] The display can be, for example, a touch-screen liquid crystal display (LCD), and the liquid crystal display enables a user to interact with the user interface of the computer terminal 10 (or electronic device).

[0041] Under the above operating environment, the embodiments of the present application provide a digital signal interpolation filtering method. Figure 2 It is a schematic diagram of the method flow of digital signal interpolation filtering provided according to the embodiments of the present application, as Figure 2 shown. The method includes the following steps:

[0042] Step S202, determine the first signal after interpolation and before filtering, the number of signal paths and the interpolation multiple corresponding to the first signal, and determine the impulse response of the filter and the corresponding order, wherein the impulse response of the filter has symmetry;

[0043] Step S204, perform a convolution operation on the first signal and the impulse response to obtain a first expression corresponding to the output signal;

[0044] Step S206, adopt the polyphase decomposition technique to decompose the convolution operation in the first expression into multiple convolution sub-operations to obtain a second expression corresponding to the output signal;

[0045] Step S208, simplify the second expression, and determine the output signal according to the simplified second expression, where the simplification operation is used to reduce the amount of multiplication and addition operations in the convolution sub-operations by using the symmetry of the filter.

[0046] Through the above steps, by providing a digital signal interpolation filtering method based on FPGA and FIR filter, the purpose of significantly reducing the amount of operations is achieved when using a better-performance FIR interpolation filter, thereby solving the technical problems of large amount of operations and insufficient stopband suppression in the related technology during digital signal interpolation filtering.

[0047] Next, the digital signal interpolation filtering method in steps S202 to S208 of the embodiment of the present application will be further introduced.

[0048] In some embodiments of the present application, determining the first signal before interpolation and filtering, as well as the number of signal paths and the interpolation multiple corresponding to the first signal includes: defining the first signal as x(n), the number of signal paths as D, and the difference multiple as Q; determining the impulse response of the filter and the corresponding order includes: determining the impulse response as h t (n) and the order as N - 1, where N is an integer power of 2, and for any index m, h(m) = h(N - 1 - m) is satisfied; determining the first expression corresponding to the output signal, where the first expression is shown as follows: Decomposing the convolution operation in the first expression into multiple convolution sub-operations to obtain the second expression corresponding to the output signal includes: letting n = mD + p, where p is the phase index, p = 0, 1, 2... D - 1; representing y(n) as y′(m, p), and obtaining the second expression, as shown in the following formula: The operation of simplifying the second expression includes: transforming the second expression into the following representation form: where floor() represents rounding down, % represents taking the remainder, g(m, p) and f(m, p) respectively represent two different calculation parts, and the corresponding calculation formulas are shown as follows:

[0049]

[0050] Through the above steps, aiming at the problem of large multiplication operation amount when using an FIR filter for interpolation filtering, by using the symmetry of the FIR filter, the pressure on computing resources is reduced. Next, the specific steps and derivation process of using the symmetry of the FIR filter to reduce the computing pressure during interpolation filtering will be described in detail.

[0051] Let the first signal before filtering after interpolation (inserting 0) be x(n), the number of signal channels be D (in an FPGA, signals are usually represented as multi-channel / phase signals to reduce the processing rate), and the interpolation factor be Q;

[0052] Let the impulse response of the filter be h t (n), its order be N - 1, N is usually an integer power of 2. Since the filter requires a linear phase, for any index m, it satisfies:

[0053] h t (m) = h t (N - 1 - m) (1)

[0054] The first signal x(n) after interpolation is convolved with h t (n) to obtain the output:

[0055]

[0056] Express the above equation in a polyphase form. Let n = mD + p, then y(n) can be represented by y′(m, p):

[0057]

[0058] Since x(n) is the signal after Q-fold interpolation, when k - p ≠ Qi, x(mD - (k - p)) = 0, then Equation (3) can be simplified to the following first formula:

[0059]

[0060] In Equation (4), ceil represents rounding up, floor represents rounding down, and it satisfies:

[0061]

[0062] Then Equation (4) can be represented as the following second formula:

[0063]

[0064] Let Then Equation (6) can be written as the following third formula:

[0065]

[0066] Let Substitute it into The following fourth formula can be obtained:

[0067]

[0068] According to equations (8) and (9), the following fifth formula can be obtained:

[0069]

[0070] Equations (8) and (11) can be expressed as the following sixth and seventh formulas:

[0071]

[0072] Let:

[0073]

[0074] Then, equations (12) and (13) can be expressed as:

[0075] y t ′(m,p) = g(m,p) - f(m,p) (16)

[0076]

[0077] Since the filter is symmetrically designed, then:

[0078]

[0079] Since Substituting the above into the equation gives:

[0080]

[0081] From equation (21), it can be seen that is centrosymmetric. Since the filter is symmetrically designed, then:

[0082]

[0083] Since Substituting the above into the equation gives:

[0084]

[0085] From equation (25), it can be seen that is centro-negatively symmetric. For g(m,p):

[0086]

[0087] Let The above equation (27) can be expressed as:

[0088]

[0089] According to equation (29), g(m,p) can be expressed in the form of the following eighth formula:

[0090]

[0091] Similarly, for f(m, p):

[0092]

[0093]

[0094] Let The above f(m, p) can be expressed as:

[0095]

[0096] According to Equation (34), f(m, p) can be expressed in the form of the ninth formula as follows:

[0097]

[0098] Finally, we get:

[0099] y′(m, p) = g(m, p) - f(m, p);

[0100]

[0101] According to the above results, it can be found that after using the symmetric property of the filter, the number of multiplication calculations is:

[0102] For the expression in the related art that does not utilize symmetry:

[0103]

[0104] The number of its multiplication calculations is: According to the above results, it can be found that the multiplication calculation amount in the embodiment of the present application is reduced by half compared with the calculation method in the related art.

[0105] The solution of the present application aims at the problem of large multiplication operation amount when using FIR filters for interpolation filtering. By utilizing the symmetry of FIR filters, the multiplication operation amount can be reduced by half, significantly reducing the pressure on computing resources and also significantly reducing power consumption without sacrificing any filter performance. At the same time, the solution of the present application is applicable to various interpolation multiples and gives a general expression, having good universality.

[0106] According to the embodiment of the present application, an embodiment of a digital signal interpolation filtering device is also provided. Figure 3 It is a schematic structural diagram of a digital signal interpolation filtering device provided according to the embodiment of the present application. As Figure 3 shown, the device includes:

[0107] The parameter determination module 30 determines the first signal before interpolation and before filtering, the number of signal paths corresponding to the first signal, and the interpolation multiple, and determines the impulse response of the filter and the corresponding order, where the impulse response of the filter has symmetry;

[0108] The convolution operation module 32 performs a convolution operation on the first signal and the impulse response to obtain a first expression corresponding to the output signal;

[0109] The polyphase decomposition module 34 uses polyphase decomposition technology to decompose the convolution operation in the first expression into multiple convolution sub-operations to obtain a second expression corresponding to the output signal;

[0110] The operation simplification module 36 performs a simplification operation on the second expression and determines the output signal according to the simplified second expression, where the simplification operation is used to utilize the symmetry of the filter to reduce the amount of multiplication and addition operations in the convolution sub-operations.

[0111] Optionally, determining the first signal before interpolation and before filtering, and the number of signal paths and the interpolation multiple corresponding to the first signal includes: defining the first signal as x(n), the number of signal paths as D, and the interpolation multiple as Q; determining the impulse response of the filter and the corresponding order includes: determining the impulse response as h t (n) and the order as N - 1, where N is an integer power of 2, and for any index m, h(m) = h(N - 1 - m) is satisfied; determining the first expression corresponding to the output signal, where the first expression is shown as follows: Decomposing the convolution operation in the first expression into multiple convolution sub-operations to obtain a second expression corresponding to the output signal includes: letting n = mD + p, where p is the phase index, p = 0, 1, 2... D - 1; representing y(n) as y′(m, p) to obtain the second expression, as shown in the following formula:

[0112] Optionally, performing a simplification operation on the second expression includes: transforming the second expression into the following representation form: y′(m, p) = g(m, p) - f(m, p); where, floor() represents rounding down, % represents taking the remainder, g(m, p) and f(m, p) respectively represent two different calculation parts, and the corresponding calculation formulas are shown as follows:

[0113]

[0114] Optionally, since x(n) is the signal after Q-fold interpolation, when k - p ≠ Qi, x(mD - (k - p)) = 0, then the second expression It can be simplified to the first formula as shown below: where ceil represents rounding up, floor represents rounding down, and the first formula satisfies: Then the first formula can be further expressed as the second formula as shown below: Let Then The second formula can be expressed as the third formula as shown below:

[0115] Let Substitute it into in the third formula, and the following fourth formula can be obtained: Based on the third formula and the fourth formula, the following fifth formula can be determined:

[0116] Optionally, the third formula is expressed as the sixth formula as shown below:

[0117] The fifth formula is expressed as the seventh formula as shown below:

[0118] Let:

[0119] Then the sixth formula and the seventh formula can be expressed as: y′(m, p) = g(m, p) - f(m, p);

[0120]

[0121] Optionally, since the filter is symmetrically designed, therefore: is centrosymmetric, is centrally negatively symmetric; thus, g(m, p) can be expressed in the form of the following eighth formula:

[0122]

[0123] f(m, p) can be expressed in the form of the following ninth formula:

[0124]

[0125] It should be noted that each module in the above digital signal interpolation filtering device can be a program module (for example, a set of program instructions for implementing a specific function), or a hardware module. For the latter, it can be presented in the following forms, but not limited to this: the manifestation of each of the above modules is a processor, or the functions of each of the above modules are implemented by a processor.

[0126] It should be noted that the digital signal interpolation filtering device provided in this embodiment can be used to execute Figure 2 the digital signal interpolation filtering method shown. Therefore, the relevant explanations of the above digital signal interpolation filtering method also apply to the embodiments of this application, and will not be elaborated here.

[0127] The embodiments of this application also provide a non-volatile storage medium. The non-volatile storage medium includes a stored computer program. Among them, the device where the non-volatile storage medium is located executes the following digital signal interpolation filtering method by running the computer program: determining a first signal before filtering after interpolation, as well as the number of signal paths and interpolation multiple corresponding to the first signal, and determining the impulse response of the filter and the corresponding order, where the impulse response of the filter has symmetry; performing a convolution operation on the first signal and the impulse response to obtain a first expression corresponding to the output signal; using the polyphase decomposition technique to decompose the convolution operation in the first expression into multiple convolution sub-operations to obtain a second expression corresponding to the output signal; performing a simplification operation on the second expression, and determining the output signal according to the simplified second expression, where the simplification operation is used to utilize the symmetry of the filter to reduce the amount of multiplication and addition operations in the convolution sub-operations.

[0128] The embodiments of this application also provide a computer program product, including a computer program. When the computer program is executed by a processor, it implements the steps of the digital signal interpolation filtering method described in each embodiment of this application: determining a first signal before filtering after interpolation, as well as the number of signal paths and interpolation multiple corresponding to the first signal, and determining the impulse response of the filter and the corresponding order, where the impulse response of the filter has symmetry; performing a convolution operation on the first signal and the impulse response to obtain a first expression corresponding to the output signal; using the polyphase decomposition technique to decompose the convolution operation in the first expression into multiple convolution sub-operations to obtain a second expression corresponding to the output signal; performing a simplification operation on the second expression, and determining the output signal according to the simplified second expression, where the simplification operation is used to utilize the symmetry of the filter to reduce the amount of multiplication and addition operations in the convolution sub-operations.

[0129] The serial numbers of the above embodiments of this application are only for description and do not represent the advantages and disadvantages of the embodiments.

[0130] In the above embodiments of the present application, the descriptions of the respective embodiments have their own focuses. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0131] In several embodiments provided by the present application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are merely illustrative. For example, the division of the units can be a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of units or modules can be in an electrical or other form.

[0132] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0133] In addition, the functional units in the various embodiments of the present application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0134] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The foregoing storage medium includes: USB flash drives, read-only memories (ROMs), random access memories (RAMs), mobile hard disks, magnetic disks, or optical disks, and other media that can store program codes.

[0135] The above is only the preferred embodiment of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present application.

Claims

1. A digital signal interpolation filtering method, characterized in that: include: Determine the first signal after interpolation and before filtering, as well as the number of signal paths and interpolation multiples corresponding to the first signal, and determine the impulse response of the filter and the corresponding order, wherein the impulse response of the filter has symmetry; Performing a convolution operation on the first signal and the impulse response to obtain a first expression corresponding to an output signal; Using a polyphase decomposition technique, the convolution operation in the first expression is decomposed into a plurality of convolution sub-operations to obtain a second expression corresponding to the output signal; The second expression is simplified, and the output signal is determined based on the simplified second expression, wherein the simplification operation is used to utilize the symmetry of the filter to reduce the amount of multiplication and addition operations in the convolution sub-operation.

2. The digital signal interpolation filtering method according to claim 1, characterized in that: Determining the first signal before interpolation and filtering, and the number of signal paths and interpolation multiples corresponding to the first signal includes: defining the first signal as x(n), the number of signal paths as D, and the difference multiple as Q; Determining the impulse response of the filter and the corresponding order includes: determining the impulse response as h t (n), the order is N-1, where N is an integer power of 2, and for any index m, h(m)=h(N-1-m); Determine the first expression corresponding to the output signal, wherein the first expression is as follows: Decomposing the convolution operation in the first expression into a plurality of convolution sub-operations to obtain a second expression corresponding to the output signal includes: setting n=mD+p, where p is a phase index, p=0, 1, 2…D-1; expressing y(n) by y′(m, p), to obtain the second expression, as shown in the following formula:

3. The digital signal interpolation filtering method according to claim 2, characterized in that: The simplification operation on the second expression includes: The second expression Converted into the following representation: y′(m,p)=g(m,p)-f(m,p); Among them, floor() means rounding down, % means taking the remainder, g(m,p) and f(m,p) represent two different calculation parts, and the corresponding calculation formulas are as follows:

4. The digital signal interpolation filtering method according to claim 3, characterized in that: Since x(n) is the Q-times interpolated signal, when kp≠Qi, x(mD-(kp))=0, then the second expression is It can be simplified into the first formula as shown below: Wherein, ceil means rounding up, floor means rounding down, and the first formula satisfies: Then the first formula can be further expressed as the second formula shown below: make but The second formula can be expressed as the third formula shown below: make Substituting this into the third formula The fourth formula is as follows: According to the third formula and the fourth formula, a fifth formula as shown below can be determined:

5. The digital signal interpolation filtering method according to claim 4, characterized in that: The third formula is expressed as the sixth formula shown below: The fifth formula is expressed as the seventh formula shown below: make: Then the sixth formula and the seventh formula can be expressed as: y′(m,p)=g(m,p)-f(m,p); 6. The digital signal interpolation filtering method according to claim 5, characterized in that: Since the filter is a symmetrical design, therefore: is centrally symmetrical, It is centrally negatively symmetric; Therefore, g(m,p) can be expressed in the form of the eighth formula shown below: f(m,p) can be expressed in the form of the ninth formula shown below:

7. A digital signal interpolation filtering device, characterized in that: include: A parameter determination module, used to determine the first signal after interpolation and before filtering, as well as the number of signal paths and interpolation multiples corresponding to the first signal, and determine the impulse response of the filter and the corresponding order, wherein the impulse response of the filter has symmetry; A convolution operation module, used for performing a convolution operation on the first signal and the impulse response to obtain a first expression corresponding to an output signal; A multi-phase decomposition module, used for decomposing the convolution operation in the first expression into a plurality of convolution sub-operations by using a multi-phase decomposition technique, to obtain a second expression corresponding to the output signal; An operation simplification module is used to simplify the second expression and determine the output signal based on the simplified second expression, wherein the simplification operation is used to utilize the symmetry of the filter to reduce the amount of multiplication and addition operations in the convolution sub-operation.

8. An electronic device, characterized in that: include: A memory and a processor, wherein the processor is used to run a program stored in the memory, wherein the digital signal interpolation filtering method according to any one of claims 1 to 6 is executed when the program is run.

9. A non-volatile storage medium, characterized in that: The non-volatile storage medium includes a stored computer program, wherein the device where the non-volatile storage medium is located executes the digital signal interpolation filtering method according to any one of claims 1 to 6 by running the computer program.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the digital signal interpolation filtering method according to any one of claims 1 to 6 are implemented.

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