A Data Stream-Based RS Code Compilation Method and System

Abstract

This invention discloses a data stream-based RS code compilation method and system, relating to the field of encoding and decoding technology. The method includes: acquiring k target data packets and corresponding m×k target matrices; converting the target matrices into coefficient matrices and the data packets into byte vectors; and performing matrix-vector multiplication based on the preprocessed target matrix and data packets to obtain target data. This solution improves upon existing encoding and decoding technologies in terms of method and structure. It converts the target matrix into a coefficient matrix, converts the data packets into byte vectors, and performs matrix-vector multiplication based on the coefficient matrix and byte vectors to obtain target data. It supports arbitrarily defined generator matrices and primitive polynomials, is compatible with various known or future RS code algorithms, and implements in-path processing of encoding and decoding based on a data stream-based data processing mechanism.

Description

Technical Field

[0001] This invention relates to the field of encoding and decoding technology, specifically to a method and system for compiling RS codes based on data streams. Background Technology

[0002] Due to the diversity of RS code algorithms, including RS codes of different lengths and redundancy levels, as well as the different primitive and generator polynomials that may be used, compilers need to be able to adapt to these different parameter configurations to ensure the correct implementation of the algorithm. Existing compilers may not be compatible with various RS code algorithms, which limits the applicability of compilers in different application scenarios. Furthermore, existing compilers have difficulty processing data streams in real time or near real time during data transmission, which is crucial for ensuring system response time and reducing latency. Summary of the Invention

[0003] The technical problem this invention aims to solve is that existing compilers may not be compatible with various RS code algorithms, and it is difficult to achieve real-time or near real-time data stream processing during data transmission. This limits the applicability of compilers in different application scenarios and also affects the system's response time and latency. The purpose of this invention is to provide an RS code compilation method and system based on data stream processing. Based on existing encoding and decoding technologies, this invention improves the method and structure. This scheme transforms the target matrix into a coefficient matrix, converts data packets into byte vectors, and performs matrix-vector multiplication based on the coefficient matrix and byte vectors to obtain the target data. It supports arbitrarily customized generator matrices and primitive polynomials, is compatible with various known or future RS code algorithms, and achieves in-path processing of encoding and decoding based on a data stream processing mechanism.

[0004] This invention is achieved through the following technical solution:

[0005] This solution provides a data stream-based RS code compilation method, including:

[0006] Obtain k target data packets and their corresponding target matrices; the dimensions of the target matrices are m×k.

[0007] Preprocess the target matrix and target data packets: convert the target matrix into a coefficient matrix and the data packets into byte vectors;

[0008] Target data is obtained by performing matrix-vector multiplication on the preprocessed target matrix and data packets. The target data includes encoded data or decoded data.

[0009] Wherein, when the target data packet is an information packet to be encoded, the target matrix is ​​the generator matrix in the encoding process, and the target data is the encoded data; when the target data packet is an information packet to be decoded, the target matrix is ​​the decoder matrix in the decoding process, and the target data is the decoded data.

[0010] The working principle of this scheme is as follows: This scheme provides a data stream-based RS code compilation method. Based on existing encoding and decoding technologies, it improves the method and structure. This scheme transforms the target matrix into a coefficient matrix, converts data packets into byte vectors, and performs matrix-vector multiplication based on the coefficient matrix and byte vectors to obtain the target data. It supports arbitrary custom generator matrices and primitive polynomials, is compatible with various known or future RS code algorithms, and realizes in-path processing of encoding and decoding based on the data stream-based data processing mechanism.

[0011] A further optimization scheme is that the preprocessing of the target matrix and target data packets includes the following methods:

[0012] Represent each of the m×k elements in the target matrix using an 8×8 bit matrix to obtain an 8m×8k target bit matrix. Transpose the target bit matrix to obtain the coefficient matrix.

[0013] Each target data packet is converted into 8-byte elements, resulting in a column vector of 8,000 bytes, where each element is configured to have a stride of bytes.

[0014] A further optimized solution is that the method for obtaining the coefficient matrix includes:

[0015] The element c in the i-th row and j-th column of the coefficient matrix is ​​calculated using the following formula. i，j :

[0016] c i，j =[a j，i / 8 <<(i%8)]%P;

[0017] 0 ≤ i < 8k;

[0018] 0≤j <m;

[0019] Where (#) / (*) represents integer division of (#) and (*); (#)%(*) represents XOR operation of (#) and (*); P represents primitive polynomial; (#)<<(*) represents left shift of (#) times; a j，i / 8 This represents the element in the j-th row and i / 8-th position of the target matrix.

[0020] A further optimized solution involves converting each target data packet into 8-byte elements to obtain a column vector consisting of 8,000 bytes, including the following method:

[0021] Obtain the fixed bit width w in the matrix-vector multiplication operation;

[0022] Configure the stride of each element in the column vector;

[0023] When the bit width stride is not an integer multiple of the fixed bit width w, the element corresponding to the last data packet in the column vector is padded with 0.

[0024] A further optimized solution is that the method for obtaining the decoding matrix includes:

[0025] Obtain the corresponding m of the decoding matrix A ×k A Encoding of dimension-1 A, k A 3D data packet column vector B, encoded m A dimensional redundant package column vectors C and k A +m A The number of invalid data packets in the data packets is Q; where Q < k. A +m A ;

[0026] Based on the encoding generation matrix A, the data packet column vector B, and the redundant packet vector C, construct the matrix-vector multiplication equation: A×B=H×C; where H represents the transformation matrix.

[0027] Reconstruct the matrix-vector multiplication equation based on the failed data packet;

[0028] Multiply both sides of the recombined matrix-vector multiplication equation by the inverse matrix N, which is the inverse of the Q×Q dimension coefficient matrix V, to obtain the decoding matrix calculation model.

[0029] The decoding matrix is ​​solved based on the Gaussian elimination method and the code matrix calculation model.

[0030] A further optimized solution is that the method for reconstructing the matrix-vector multiplication equation based on the failed data packet includes:

[0031] Reorganize the encoding generation matrix A in the matrix-vector multiplication equation: delete the elements in the encoding generation matrix A that are coefficients of invalid data packets, and fill them with the elements in the transformation matrix H by shifting;

[0032] Reorganize the data packet column vector B in the matrix-vector multiplication equation: delete the invalid data packets in the data packet column vector B and fill it with the elements in the redundant packet column vector C by shifting;

[0033] Reorganize the redundant packet column vector C in the matrix-vector multiplication equation by replacing the elements in the redundant packet column vector C with invalid data packets;

[0034] Reorganize the coefficient matrix H in the matrix-vector multiplication equation: replace the elements in the coefficient matrix H with the elements in the encoding generation matrix A that are the coefficients of the failed data packets;

[0035] The shift filling refers to filling the empty spaces after deleting an element from the matrix to be filled by the elements of the following column in sequence, and then filling the newly generated empty spaces.

[0036] A further optimization scheme is that the coefficient matrix V is composed of elements in the encoding generation matrix A that serve as coefficients for failed data packets.

[0037] This solution also provides a data-stream-based RS code compilation system for implementing the aforementioned data-stream RS code compilation method; the system includes:

[0038] The data input module is used to acquire k target data packets and their corresponding target matrices; the target matrices have a dimension of m×k; the data input module is also used to convert the data packets into byte vectors;

[0039] The coefficient matrix module is used to convert the target matrix into a coefficient matrix;

[0040] The computation array module is used to perform matrix-vector multiplication operations based on the preprocessed target matrix and data packets to obtain the target data.

[0041] Wherein, when the target data packet is an information packet to be encoded, the target matrix is ​​the generator matrix in the encoding process, and the target data is the encoded data; when the target data packet is an information packet to be decoded, the target matrix is ​​the decoder matrix in the decoding process, and the target data is the decoded data.

[0042] A further optimization scheme includes a PCIe module. The data input module uses a DMA engine to batch transfer k target data packets from the host machine via the PCIe module. The data input module is also used to configure the stride of each element in the column vector, and when the stride is not an integer multiple of the fixed stride w during the matrix-vector multiplication operation, the element corresponding to the last data packet in the column vector is padded with 0.

[0043] A further optimization scheme includes a computation buffer module, which is used to temporarily store some of the accumulated data during matrix-vector multiplication. The computation buffer module and the computation array module form a ring data flow channel.

[0044] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0045] The RS code compilation method and system based on data stream provided by this invention improves the method and structure on the basis of existing encoding and decoding technologies. This scheme transforms the target matrix into a coefficient matrix, converts the data packet into a byte vector, and obtains the target data by performing matrix-vector multiplication based on the coefficient matrix and the byte vector. It supports arbitrarily customized generator matrices and primitive polynomials, is compatible with various known or future RS code algorithms, and realizes in-path processing of encoding and decoding based on the data stream data processing mechanism. Attached Figure Description

[0046] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings:

[0047] Figure 1 This is a schematic diagram of the RS code compilation method based on data stream.

[0048] Figure 2 This is a schematic diagram illustrating the reasoning process of element-wise multiplication from vector multiplication to matrix-vector multiplication.

[0049] Figure 3 A schematic diagram of the RS code encoding process for generating matrix representation;

[0050] Figure 4 A schematic diagram of the encoding operation process for generating a matrix representation of bits;

[0051] Figure 5 This is a schematic diagram illustrating the generation process of the coefficient matrix;

[0052] Figure 6 This is a schematic diagram illustrating the generation process of the decoding matrix D;

[0053] Figure 7 This is a schematic diagram of the RS code compilation system architecture based on data stream;

[0054] Figure 8 This is a schematic diagram illustrating the working principle of a data stream-based RS code compilation system.

[0055] Figure 9 This is a schematic diagram illustrating how a single data packet is stored in memory.

[0056] Figure 10 A schematic diagram of the microarchitecture of the data input module;

[0057] Figure 11 This is a schematic diagram of the microarchitecture of the input buffer module;

[0058] Figure 12 This is a schematic diagram of the microarchitecture of the coefficient matrix module;

[0059] Figure 13 This is a schematic diagram of the microarchitecture of the compute buffer module;

[0060] Figure 14 This is a schematic diagram of the microarchitecture of the data output module. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0062] Existing compilers may not be compatible with various RS code algorithms, and it is difficult to process data streams in real time or near real time during data transmission. This limits the applicability of compilers in different application scenarios and also affects the system's response time and latency. In view of this, the present invention provides the following embodiments to solve the above-mentioned technical problems.

[0063] Example 1

[0064] This embodiment provides a data stream-based RS code compilation method, such as... Figure 1 As shown, it includes:

[0065] Step 1: Obtain k target data packets and their corresponding target matrices; the dimensions of the target matrices are m×k.

[0066] Step two involves preprocessing the target matrix and target data packets: converting the target matrix into a coefficient matrix and the data packets into byte vectors; this step specifically includes the following methods:

[0067] Represent each of the m×k elements in the target matrix using an 8×8 bit matrix to obtain an 8m×8k target bit matrix. Transpose the target bit matrix to obtain the coefficient matrix.

[0068] Each target data packet is converted into 8-byte elements, resulting in a column vector of 8,000 bytes, where each element is configured to have a stride of bytes. Specifically:

[0069] S01, obtain the fixed bit width w in the matrix-vector multiplication operation;

[0070] S02, configure the stride of each element in the column vector;

[0071] S03, when the bit width stride is not an integer multiple of the fixed bit width w, fill the element corresponding to the last data packet in the column vector with 0.

[0072] In applications such as storage, RS codes need to process large amounts of data in batches. In order to improve efficiency, the encoding cannot be done in units of bytes. This scheme treats each data packet as a fixed 8 elements. The size of each element changes with the size of the data packet. The size of a single element is denoted as stride bytes.

[0073] The encoding and decoding process of RS code involves element-wise operations defined in the finite field GF(2). 8 The matrix-vector multiplication process within a finite field requires feedback modulo calculation for multiplication operations. To eliminate the differences caused by primitive polynomials of different finite fields, this scheme transforms the representation of finite field elements and multiplication operations, improving computational parallelism and facilitating hardware acceleration.

[0074] Elements in a finite field can be represented in two ways: vector representation and matrix representation. For any two elements A and B in the finite field, their vector representations are {a7, a6, a5, a4, a3, a2, a1, a0} and {b7, b6, b5, b4, b3, b2, b1, b0}, respectively, where a... i and b i Each bit is a single bit, with a value of 0 or 1. The operation C = A × B can be represented as vector multiplication, matrix-vector multiplication, and matrix multiplication, yielding vector and matrix representations of C, respectively. This scheme represents the M × K elements in the generator matrix G during the encoding process and the decoder matrix D during the decoding process of the RS code using an 8 × 8 bit matrix, expanding it to an 8M × 8K bit matrix as the coefficient matrix. Data packets are directly represented as vectors, and the encoding and decoding operations are completed using matrix-vector multiplication. The reasoning process for element-wise multiplication from vector multiplication to matrix-vector multiplication is as follows: Figure 2 As shown, the bit multiplication and addition operations in the figure are defined in GF(2), that is, addition is an XOR operation and multiplication is an AND operation:

[0075] Equation ① in the figure is vector multiplication: after aligning vector A according to the weights of the coefficients in vector B, a bitwise XOR operation is performed, and a polynomial P is generated based on the modulus of the final result;

[0076] In Equation ②, each row of the shaded vector A can be XORed with the primitive polynomial P in advance, so that the subsequent operation is independent of P. That is, vector A is shifted left by one bit each time, and the low bits are filled with 0. If the highest bit shifted out is 1, the result is XORed with the lower 8 bits of P.

[0077] In equation ③, vector A is shifted 7 times and modulo P to obtain 8 column vectors;

[0078] In equation ④, the multiplication can be represented as the multiplication of the bit matrix representation of A, which is a combination of 8 column vectors, with the column vector B.

[0079] During the encoding and decoding process, the coefficient matrix is ​​related to the encoding and decoding mode. It can be determined and converted into a bit matrix representation before the operation begins. That is, A corresponds to the elements in the generator matrix or decoder matrix, and B corresponds to the elements in the data packet. The matrix representation of A is handled by the software. The encoding and decoding calculation of the hardware accelerator is independent of the primitive polynomial P.

[0080] like Figure 3 As shown, the generator matrix G of the RS code in this embodiment has M rows and K columns, and the elements are defined in GF(2... 8 In this context, the encoding process involving the bit matrix is ​​described in [reference needed]. Figure 4 ,and Figure 3 In contrast, by transforming each element of the generator matrix G into an 8×8 bit matrix, the M×K generator matrix G is transformed into an 8M×8K target bit matrix, and the K data packets are transformed into a class vector with 8K elements, each element having stride bytes. Because the hardware accelerator processes data along-path and does not store the input data packets, the coefficient matrix participates in the calculation column by column. The elements of each data packet (i.e., stride bytes) are XORed and accumulated under the bit control of the 8M column vectors, as shown in the pseudocode below:

[0081] for(j=0;j<8*K;j++)

[0082] for(i=0;i<8*M;i++)

[0083] Sum[i] += Data[j] * G[i][j]; / / Sum[i] and Data[j] are both stride byte vectors.

[0084] / / G[i][j] represents a single ratio.

[0085] As can be seen from the pseudocode representation of the operation process, the K data packets (Data) only need to be read once, and the summation is performed column-wise according to the generated matrix after each stride of bytes is obtained, without needing to store the input data. However, the generated matrix G is used bit-by-bit column-wise; therefore, the extended bit-generating matrix needs to be transposed into a coefficient matrix used by the subsequent accelerator calculations. This process is as follows: Figure 5 As shown:

[0086] Figure 5 Equation ① is to divide each GF(2) in G. 8 element a in ) i，j Expanded to an 8×8 bit matrix, for example, the shaded element g 0，0 to g 7，7 The 8×8 bit matrix is ​​a 0，0 The bit matrix representation;

[0087] Figure 5 Equation ② derives the matrix column by column, with every 7 column bits forming a byte. For example, the two dashed boxes in the figure each have 8 bits, corresponding to element c. 0，0 and element c 1，0 ;

[0088] Figure 5 Equation ③ represents the transformation relationship between the elements of the coefficient matrix and the elements of the generator matrix, obtained by considering the above:

[0089] The element c in the i-th row and j-th column of the coefficient matrix is ​​obtained according to the following formula. i，j :

[0090] c i，j =[a j，i / 8 <<(i%8)]%P;

[0091] 0 ≤ i < 8k;

[0092] 0≤j <m;

[0093] Where (#) / (*) represents integer division of (#) and (*); (#)%(*) represents XOR operation of (#) and (*); P represents primitive polynomial; (#)<<(*) represents left shift of (#) times; a j，i / 8 This represents the element in the j-th row and i / 8-th position of the target matrix.

[0094] Step 3: Perform matrix-vector multiplication on the preprocessed target matrix and the data packet to obtain the target data, which includes encoded data or decoded data; wherein, when the target data packet is an information packet to be encoded, the target matrix is ​​the generator matrix in the encoding process, and the target data is the encoded data; when the target data packet is an information packet to be decoded, the target matrix is ​​the decoder matrix in the decoding process, and the target data is the decoded data.

[0095] Methods for obtaining the decoding matrix include:

[0096] Obtain the corresponding m of the decoding matrix A ×k A Encoding generation matrix A, k of dimension A 3D data packet column vector B, encoded m A dimensional redundant package column vectors C and k A +m A The number of invalid data packets in the data packets is Q; where Q < k. A +m A ;

[0097] S11, construct the matrix-vector multiplication equation based on the encoding generation matrix A, the data packet column vector B, and the redundant packet vector C: A×B=H×C; where H represents the transformation matrix;

[0098] S12, Reconstruct the matrix-vector multiplication equation based on the failed data packet; this step specifically includes the following methods:

[0099] Reorganize the encoding generation matrix A in the matrix-vector multiplication equation: delete the elements in the encoding generation matrix A that are coefficients of invalid data packets, and fill them with the elements in the transformation matrix H by shifting;

[0100] Reorganize the data packet column vector B in the matrix-vector multiplication equation: delete the invalid data packets in the data packet column vector B and fill it with the elements in the redundant packet column vector C by shifting;

[0101] Reorganize the redundant packet column vector C in the matrix-vector multiplication equation by replacing the elements in the redundant packet column vector C with invalid data packets;

[0102] Reorganize the coefficient matrix H in the matrix-vector multiplication equation: replace the elements in the coefficient matrix H with the elements in the encoding generation matrix A that are the coefficients of the failed data packets;

[0103] The shift filling refers to filling the empty spaces after deleting an element from the matrix to be filled by the elements of the following column in sequence, and then filling the newly generated empty spaces.

[0104] S13, multiply both sides of the recombined matrix-vector multiplication equation by the inverse matrix N, which is the inverse of the Q×Q dimension coefficient matrix V, to obtain the decoding matrix calculation model; the coefficient matrix V is composed of the elements in the encoding generation matrix A that serve as the coefficients of the failed data packets.

[0105] S14, the decoding matrix is ​​solved based on the Gaussian elimination method and the summation code matrix calculation model.

[0106] In this scheme, the difference between RS decoding and encoding lies in the different coefficient matrices calculated by the software. Matrix-vector multiplication does not distinguish between encoding and decoding. The calculation of the decoding matrix D depends on the encoding generation matrix A and the primitive polynomial P, as well as the packet loss or corruption mode. It is required that the number of failed data packets Q (in this embodiment, failed data packets mainly include lost or corrupted data packets) is no greater than m. A Solving for the inverse matrix with k A =4,m A Let's take Q=2 as an example. Figure 6 As shown:

[0107] Figure 6Equation ① is the constructed matrix-vector multiplication equation, where A is the encoding generation matrix, B is the data packet column vector composed of 4 information packets, and C is the redundant packet column vector composed of 2 redundant packets obtained by encoding. A total of 6 data packets (b0, b1, b2, b3, c0, c1) are stored or transmitted. Each data packet corresponds to a coefficient column. The columns of the information packets come from the encoding matrix, and the columns of the redundant packets are one-hot encoded. The i-th row of the coefficient column of the i-th redundant packet is 1.

[0108] Figure 6 Equation ② is a matrix-vector multiplication equation based on the reconstructed invalid data packets, where data packets b1 and b2 were damaged or lost. In a finite field, addition is an XOR operation, which yields this equation. The left-hand matrix is ​​obtained by reconstructing the coefficient columns of the received or error-free data packets, and the right-hand matrix is ​​obtained by reconstructing the coefficient columns of the lost or erroneous data packets.

[0109] Figure 6 Equation ③ is the formula for calculating the decoding matrix D by multiplying both sides of equation ② by the inverse matrix N. The decoding matrix D is obtained by multiplying the inverse matrix N by the recombined encoded generation matrix A.

[0110] Example 2

[0111] This embodiment provides a data-stream-based RS code compilation system for implementing the data-stream-based RS code compilation method described in Embodiment 1; such as Figure 7 and Figure 8 As shown, the system includes:

[0112] The data input module is used to acquire k target data packets and their corresponding target matrices; the target matrices have a dimension of m×k; the data input module is also used to convert the data packets into byte vectors;

[0113] The coefficient matrix module is used to convert the target matrix into a coefficient matrix;

[0114] The computation array module is used to perform matrix-vector multiplication operations based on the preprocessed target matrix and data packets to obtain the target data.

[0115] Wherein, when the target data packet is an information packet to be encoded, the target matrix is ​​the generator matrix in the encoding process, and the target data is the encoded data; when the target data packet is an information packet to be decoded, the target matrix is ​​the decoder matrix in the decoding process, and the target data is the decoded data.

[0116] It also includes a PCIe module. The data input module uses a DMA engine to batch transfer k target data packets from the host machine through the PCIe module. The data input module is also used to configure the stride of each element in the column vector, and when the stride is not an integer multiple of the fixed stride w during the matrix-vector multiplication operation, the element corresponding to the last data packet in the column vector is padded with 0.

[0117] It also includes a computation buffer module, which is used to temporarily store some of the accumulated data during matrix-vector multiplication. The computation buffer module and the computation array module form a ring data flow channel.

[0118] In this embodiment, the main hardware of the entire system is an accelerator, which connects to the host machine in the form of a PCIe accelerator card to complete the main computational tasks of encoding and decoding. Figure 8 In this accelerator card, the core is the FPGA chip, which internally comprises two main parts: a PCIe module and a computing engine. The PCIe module implements a PCIe Endpoint device, and the application layer implements a DMA engine, using the AXI Lite interface for PIO read / write and the AXI Stream interface for DMA read / write. The computing engine includes a data input module, a computing array module, a coefficient matrix module, a computing buffer module, and a data output module, implementing data-stream RS code encoding / decoding acceleration. When the data input module, coefficient matrix module, and computing buffer module can all provide the relevant data or coefficients to start the computation, the computation is executed pipelined in the computing array module without requiring additional start control or synchronization signals. Generally, the computation is driven by the data provided by the data input module. After the computation task is completed, the data output module retrieves the results from the computing buffer module and writes them back to the host machine. The data input and data output modules exchange data with the host machine via DMA, while the configuration registers of the coefficient matrix module and the computing engine accept configurations from the host machine via PIO. The bit width of the computing engine is defined by the width w bytes of the XOR operation in the computing array module.

[0119] The data input module receives data packets transferred from the host machine to the board via the AXI Stream interface, organizes the data, and then hands it over to the computing array module to drive the data stream computing. A single codec computation task can contain multiple batches of computation data. Each batch consists of K data packets, each data packet consists of 8 computation stripes, and each computation stripe contains stride bytes. The storage method of a single data packet in memory is as follows: Figure 9As shown, DMA moves data to the board as a byte stream and hands it over to the data input module. Stride, as an encoding parameter, is configurable, while the bit width w of the computing engine is fixed. When Stride is not an integer multiple of w, the data input module needs to pad the data in the last cycle.

[0120] The microarchitecture of the data input module is as follows Figure 10 As shown, the data input module receives data from the host machine via the DMA read channel. The data width dw of the DMA AXI Stream interface is a multiple of the bit width w of the computing engine. Because the data packets are stored contiguously in memory, the data acquired by the DMA in each cycle may contain data from two adjacent strides. However, the computing engine must input w bits of data per cycle, which must belong to the same stripe. The byte slipbuffer module is responsible for performing byte alignment operations, cutting and splicing data that do not belong to the same stripe, and padding with zeros if the data is less than w bits. The input buffer has a width of w bits, is at the same frequency and width as the computing array module, and belongs to the same clock domain. Because each stripe needs to be XORed with 8*K buffered stripes under the control of 8*K coefficients, the reuse buffer buffers multi-cycle data of a single stripe. When the last coefficient of the previous stripe is calculated, the new stripe enters the reuse buffer from the data buffer, and then loads the data from the input to the input port in a circular buffer mode, reusing 8*K cycles. The Reuse Counter state machine controls the scheduling and use of data in the databuffer and reuse buffer.

[0121] The computation array performs the XOR operation of the core encoding and decoding computation. Under the control of the coefficient bits provided by the coefficient matrix module, it performs an XOR operation between the input data provided by the input buffer module and the accumulated sum provided by the computation buffer module, and writes the result back to the computation buffer module. Figure 11 As shown. The output is only valid when the input data, calculated coefficients, and accumulated sum are all valid, and the calculation buffer module has space. The valid signal is then fed back to the modules in four directions. Signals such as data_in, sum_out, and sum_in are w bits wide, while the rest are single bits wide.

[0122] The coefficient matrix module is responsible for storing and reusing the encoded and decoded coefficients, and controlling the execution of XOR operations in the computation array, such as... Figure 12As shown. The coefficient buffer is a single byte wide and 128KB deep, i.e., has a capacity of 128KB, which can support the encoding and decoding of RS codes of any dimension within GF(2^8). The coefficient buffer is a circular buffer that reuses the coefficient matrix, allowing for the computation of multiple batches of data in a single task. The coefficient matrix only needs to be reinitialized when the configuration of the computation task's encoding and decoding changes. The coe_rd signal is equivalent to the coe_in_rdy of the computation array module. Each time a cycle of computation is completed, the reuse counter is incremented by 1, and each coefficient is reused. Next, when the reuse counter overflows, the rotate counter is incremented by 1, and the next bit in the byte is selected to produce the coefficient output. When the rotate counter reaches 8, the byte is shifted out, removed from the coefficient buffer, and rewritten to the end of the buffer. During the initialization phase of the computation task, the coefficient buffer receives the coefficient matrix configured by the software from the PIO channel.

[0123] The computation buffer module is used to temporarily store some of the accumulated redundant packet data during the encoding and decoding process, totaling M*8*stride bytes, such as... Figure 13 As shown. During encoding and decoding calculations, the computation buffer and the computation array module form a circular data stream. The data in the computation buffer is XORed with the computation array's `sum_in` and `data_in` under the control of `coe_in`. The result is written back to the computation buffer module as the computation array's `sum_out`. During initialization, the computation buffer can load a partial sum of all zeros equal to the size of the redundant packet, or it can load the previously calculated partial sum or a specific initial vector from the data input module. During the final stage, the data in the computation buffer can be exported to the data output module.

[0124] It also includes, such as Figure 14 The data output module shown retrieves the calculation results from the calculation buffer module, organizes them, and then passes them to the DMA engine for write operations to send back to the host machine's main memory. The byte slipbuffer module is responsible for removing padding zeros from the results and merging the strides into a continuous byte stream for DMA transfer.

[0125] This solution supports various RS code encoding and decoding algorithms, including those based on Vandermonde and Cauchy matrices. The system completes computational tasks through a hardware-software co-processing approach. The software configures the hardware accelerator's operating mode and schedules the execution of multiple computational tasks, while the hardware uses DMA to read and write data via PCIe. The system performs encoding and decoding operations on large amounts of data within a given timeframe, completing each computational task sequentially, according to the software-configured operating mode. Compared to existing RS code encoders and decoders, this solution offers the following advantages:

[0126] Compared with software codecs, the computing core of this solution is implemented in hardware, which has strong computing power and high energy efficiency. The hardware implementation has the same overhead and performance for both encoding and decoding.

[0127] Compared with various dedicated RS code hardware accelerators, this solution supports arbitrarily customized generator matrices and primitive polynomials, and is compatible with various known or future RS code algorithms.

[0128] This solution is based on a streaming data processing mechanism, enabling in-path encoding and decoding. The system requires no additional storage overhead, such as board-level memory, meets real-time performance metrics with low latency, and is not limited by data supply patterns or bandwidth.

[0129] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A data stream-based RS code compilation method, characterized in that, include: Obtain k target data packets and their corresponding target matrices; The dimension of the target matrix is ​​m×k; Preprocessing of the target matrix and target data packets: converting the target matrix into a coefficient matrix and the data packets into byte vectors; the preprocessing of the target matrix and target data packets includes the following methods: Represent each of the m×k elements in the target matrix using an 8×8 bit matrix to obtain an 8m×8k target bit matrix. Transpose the target bit matrix to obtain the coefficient matrix. The method for obtaining the coefficient matrix includes: The element c in the i-th row and j-th column of the coefficient matrix is ​​calculated using the following formula. i，j : c i，j =[ a j，i / 8 <<(i%8)] %P; 0 ≤ i < 8k; 0≤ j <m; Where (#) / (*) represents integer division of (#) and (*); (#)%(*) represents XOR operation of (#) and (*); P represents primitive polynomial; (#)<<(*) represents left shift of (#) times; a j，i / 8 This represents the element in the j-th row and i / 8-th position of the target matrix; Each target data packet is converted into 8-byte elements, resulting in a byte column vector consisting of 8,000 bytes, where each element is configured with a stride of bytes. Target data is obtained by performing matrix-vector multiplication on the preprocessed target matrix and data packets. The target data includes encoded data or decoded data. Wherein, when the target data packet is an information packet to be encoded, the target matrix is ​​the generator matrix in the encoding process, and the target data is the encoded data; when the target data packet is an information packet to be decoded, the target matrix is ​​the decoder matrix in the decoding process, and the target data is the decoded data; The method for obtaining the decoding matrix includes: Obtain the corresponding m of the decoding matrix A ×k A Encoding generation matrix A, k of dimension A 3D data packet column vector B, encoded m A dimensional redundant package column vectors C and k A +m A The number of invalid data packets in the data packets is Q; where Q < k. A +m A ; Based on the encoding generation matrix A, the data packet column vector B, and the redundant packet vector C, construct the matrix-vector multiplication equation: A×B=H×C; where H represents the transformation matrix. Reconstruct the matrix-vector multiplication equation based on the failed data packet; Multiply both sides of the recombined matrix-vector multiplication equation by the inverse matrix N, which is the inverse of the Q×Q dimension coefficient matrix V, to obtain the decoding matrix calculation model. The decoding matrix is ​​solved based on the Gaussian elimination method and the code matrix calculation model.

2. The RS code compilation method based on data stream according to claim 1, characterized in that, The method for converting each target data packet into 8-byte elements to obtain a column vector consisting of 8,000 bytes includes: Obtain the fixed bit width w in the matrix-vector multiplication operation; Configure the stride of each element in the column vector; When the bit width stride is not an integer multiple of the fixed bit width w, the element corresponding to the last data packet in the column vector is padded with 0.

3. The RS code compilation method based on data stream according to claim 1, characterized in that, The method for reconstructing the matrix-vector multiplication equation based on the failed data packet includes: Reorganize the encoding generation matrix A in the matrix-vector multiplication equation: delete the elements in the encoding generation matrix A that are coefficients of invalid data packets, and fill them with the elements in the transformation matrix H by shifting; Reorganize the data packet column vector B in the matrix-vector multiplication equation: delete the invalid data packets in the data packet column vector B and fill it with the elements in the redundant packet column vector C by shifting; Reorganize the redundant packet column vector C in the matrix-vector multiplication equation by replacing the elements in the redundant packet column vector C with invalid data packets; Reorganize the coefficient matrix H in the matrix-vector multiplication equation: replace the elements in the coefficient matrix H with the elements in the encoding generation matrix A that are the coefficients of the failed data packets; The shift filling refers to filling the empty spaces after deleting an element from the matrix to be filled by the elements of the following column in sequence, and then filling the newly generated empty spaces.

4. The RS code compilation method based on data stream according to claim 1, characterized in that, The coefficient matrix V is composed of elements in the encoding generation matrix A that serve as coefficients for failed data packets.

5. A data-stream-based RS code compilation system, characterized in that, The system is used to implement the data stream-based RS code compilation method according to any one of claims 1-4; the system comprises: The data input module is used to acquire k target data packets and their corresponding target matrices; the target matrices have a dimension of m×k; the data input module is also used to convert the data packets into byte vectors; The coefficient matrix module is used to convert the target matrix into a coefficient matrix; The computation array module is used to perform matrix-vector multiplication operations based on the preprocessed target matrix and data packets to obtain the target data. Wherein, when the target data packet is an information packet to be encoded, the target matrix is ​​the generator matrix in the encoding process, and the target data is the encoded data; when the target data packet is an information packet to be decoded, the target matrix is ​​the decoder matrix in the decoding process, and the target data is the decoded data.

6. The RS code compilation system based on data stream according to claim 5, characterized in that, It also includes a PCIe module. The data input module uses a DMA engine to batch transfer k target data packets from the host machine through the PCIe module. The data input module is also used to configure the stride of each element in the column vector, and when the stride is not an integer multiple of the fixed stride w during the matrix-vector multiplication operation, the element corresponding to the last data packet in the column vector is padded with 0.

7. The RS code compilation system based on data stream according to claim 5, characterized in that, It also includes a computation buffer module, which is used to temporarily store some of the accumulated data during matrix-vector multiplication. The computation buffer module and the computation array module form a ring data flow channel.

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