Coding method, decoding method and related products

Abstract

The invention discloses a coding method, a decoding method and a related product, the method can be applied to a low power consumption scene, the method comprises the following steps: performing CRC coding on K1 information bits to obtain a first bit sequence, the first bit sequence comprising L CRC bits, K1 being a positive integer, and L being a positive integer less than 24; interleaving the first bit sequence using a first distributed CRC interleaver; the first distributed CRC interleaver comprises (K2 + L) elements, and the values of the (K2 + L-S) th element to the (K2 + L) th element of the first distributed CRC interleaver are (K2 + L-1-S) to (K2 + L-1) in sequence; or the first distributed CRC interleaver comprises (K2 + L) natural numbers from 0 to (K2 + L-1), P in the first distributed CRC interleaver is before Q, both P and Q are integers greater than or equal to K2, and P is greater than Q; the decoding power consumption can be reduced.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to encoding methods, decoding methods, and related products. Background Art

[0002] During wireless transmission, channel coding is usually used to encode and decode data, so as to improve the reliability of information transmission and reduce the error probability during transmission.

[0003] In a new radio (NR) system, a channel coding method is as follows: for the K bits (i.e., payload bits) to be transmitted on the downlink control channel, cyclic redundancy check (CRC) encoding is first performed to obtain 24 cyclic redundancy check bits; these 24 cyclic redundancy check bits are concatenated to the end of the K bits to obtain a message sequence concatenated with 24 cyclic redundancy check bits; the message sequence is interleaved through an interleaver to obtain an interleaved sequence; finally, polar encoding is performed on the interleaved sequence. In this scheme, the size K of the payload (i.e., payload bits) is less than or equal to 140, and the maximum length after concatenating 24 cyclic redundancy check bits is 164. Therefore, the length of the interleaver is 164.

[0004] However, this channel coding scheme has problems of relatively high decoding power consumption and large resource overhead in scenarios such as low power consumption and downlink control information (DCI). Summary of the Invention

[0005] Embodiments of this application disclose encoding methods, decoding methods, and related products, aiming to reduce decoding power consumption and resource overhead.

[0006] In a first aspect, an embodiment of the present application provides an encoding method, which includes: performing cyclic redundancy check (CRC) encoding on K1 information bits to obtain a first bit sequence, where the first bit sequence includes the K1 information bits and L CRC bits, K1 is a positive integer, and L is a positive integer less than 24; using a first distributed CRC interleaver to interleave the first bit sequence to obtain a second bit sequence; where the first distributed CRC interleaver includes (K2 + L) elements, and the values of the (K2 + L - S)-th element to the (K2 + L)-th element of the first distributed CRC interleaver are sequentially (K2 + L - 1 - S) to (K2 + L - 1), S is an integer greater than or equal to 0 and less than or equal to L, and K2 is an integer greater than or equal to K1; alternatively, the first distributed CRC interleaver includes a total of (K2 + L) natural numbers from 0 to (K2 + L - 1), P is before Q in the first distributed CRC interleaver, both P and Q are integers greater than or equal to K2, and P is greater than Q. The statement that the values of the (K2 + L - S)-th element to the (K2 + L)-th element of the first distributed CRC interleaver are sequentially (K2 + L - 1 - S) to (K2 + L - 1) can be replaced with: the first distributed CRC interleaver includes L natural numbers that are sorted in ascending order and are greater than or equal to K2.

[0007] In an embodiment of the present application, cyclic redundancy check (CRC) encoding is performed on K1 information bits to obtain a first bit sequence, and the number of CRC check bits is less than 24. The first bit sequence is interleaved using a first distributed CRC interleaver. The first distributed CRC interleaver supports DCRC encoding for shorter payloads. The receiver decodes through a deinterleaver corresponding to the first distributed CRC interleaver, which can reduce decoding power consumption and resource overhead.

[0008] In a possible implementation, L is equal to 6, 11, or 16.

[0009] In a possible implementation, K2 is equal to 32, 40, 48, 54, 64, 70, or 100.

[0010] In a possible implementation, the first distributed CRC interleaver is obtained by arranging L element sequences in order. Any two of the L element sequences are a first element sequence and a second element sequence. The elements included in the first element sequence are obtained based on the positions of the information bits associated with the first check column. The elements included in the second element sequence are obtained based on the positions of the information bits associated with the second check column. The first check column and the second check column are any two columns in the check matrix obtained based on the CRC generating polynomial of length L. When the largest element representing the position of the information bits associated with the first check column in the first element sequence is greater than the largest element representing the position of the information bits associated with the second check column in the second element sequence, the sorting of the first element sequence in the first distributed CRC interleaver is after the second element sequence.

[0011] In this implementation, when the largest element representing the position of the information bits associated with the first check column in the first element sequence is greater than the largest element representing the position of the information bits associated with the second check column in the second element sequence, the sorting of the first element sequence in the first distributed CRC interleaver is after the second element sequence, so that the receiving end can detect the CRC check failure earlier during decoding, thereby saving decoding power consumption.

[0012] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence. L is equal to 6, K2 is equal to 70, the CRC generating polynomial is D^6 + D^5 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 2 3 4 5 6 7 13 18 19 23 25 28 29 30 31 33 37 38 39 42 45 47 48 50 51 52 54 55 58 59 61 63 65 66 67 68 69 70 1 8 14 20 24 26 32 34 40 43 46 49 53 56 60 62 64 71 9 15 21 27 35 41 44 57 72 10 16 22 36 73 11 17 74 12 75.

[0013] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generating polynomial is D^6 + D^5 + D^4 + D^3 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 1 4 5 6 9 10 16 19 20 21 24 25 31 34 35 36 39 40 46 49 50 51 54 55 61 64 65 66 69 70 2 7 11 17 22 26 32 37 41 47 52 56 62 67 71 3 8 12 18 23 27 33 38 42 48 53 57 63 68 72 13 28 43 58 73 14 29 44 59 74 0 15 30 45 60 75.

[0014] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generating polynomial is D^6 + D^4 + D^3 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 1 2 3 4 5 7 13 14 15 20 23 27 28 30 31 34 36 37 39 41 42 43 45 46 47 48 51 52 56 58 60 63 64 65 66 67 68 70 6 8 16 21 24 29 32 35 38 40 44 49 53 57 59 61 69 71 9 17 22 25 33 50 54 62 72 10 18 26 55 73 11 19 74 12 75.

[0015] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generating polynomial is D^6 + D^3 + D^2 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 1 2 5 6 7 10 16 17 20 21 22 25 31 32 35 36 37 40 46 47 50 51 52 55 61 62 65 66 67 70 3 8 11 18 23 26 33 38 41 48 53 56 63 68 71 4 9 12 19 24 27 34 39 42 49 54 57 64 69 72 13 28 43 58 73 14 29 44 59 74 0 15 30 45 60 75.

[0016] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generating polynomial is D^6 + D^5 + D^2 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 1 2 4 5 6 7 13 15 17 18 21 22 23 25 26 27 28 34 36 38 39 42 43 44 46 47 48 49 55 57 59 60 63 64 65 67 68 69 70 3 8 14 16 19 24 29 35 37 40 45 50 56 58 61 66 71 9 20 30 41 51 62 72 10 31 52 73 11 32 53 74 12 33 54 75.

[0017] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generating polynomial is D^6 + D^5 + D^4 + D^2 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 80 1 4 6 7 13 15 18 21 22 25 27 28 34 36 39 42 43 46 48 49 55 57 60 63 64 67 69 70 2 5 8 14 16 19 23 26 29 35 37 40 44 47 50 56 58 61 65 68 71 3 9 17 20 24 30 38 41 45 51 59 62 66 72 10 31 52 73 11 32 53 74 12 33 54 75.

[0018] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generating polynomial is D^6 + D^3 + D^2 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 4 5 8 14 16 17 18 20 21 23 25 28 29 30 31 35 36 39 45 47 48 49 51 52 54 56 59 60 61 62 66 67 70 1 6 9 15 19 22 24 26 32 37 40 46 50 53 55 57 63 68 71 2 7 10 27 33 38 41 58 64 69 72 3 11 34 42 65 73 12 43 74 13 44 75.

[0019] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generating polynomial is D^6 + D^5 + D^3 + D^2 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 5 6 7 13 15 16 17 18 19 20 23 25 27 31 32 35 36 37 38 40 41 42 44 46 47 49 52 53 55 56 60 63 68 69 70 1 8 14 21 24 26 28 33 39 43 45 48 50 54 57 61 64 71 2 9 22 29 34 51 58 62 65 72 3 10 30 59 66 73 4 11 67 74 12 75.

[0020] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generating polynomial is D^6 + D^5 + D^4 + D^3 + D^2 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 2 5 9 10 16 18 19 21 22 23 26 27 28 29 30 32 35 39 40 46 48 49 51 52 53 56 57 58 59 60 62 65 69 70 1 3 6 11 17 20 24 31 33 36 41 47 50 54 61 63 66 71 4 7 12 25 34 37 42 55 64 67 72 8 13 38 43 68 73 14 44 74 15 45 75.

[0021] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generating polynomial is D^6 + D^5 + D^4 + D^3 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 1 2 4 7 8 14 15 16 19 23 25 27 28 29 30 32 33 35 38 39 45 46 47 50 54 56 58 59 60 61 63 64 66 69 70 0 3 5 9 17 20 24 26 31 34 36 40 48 51 55 57 62 65 67 71 6 10 18 21 37 41 49 52 68 72 11 22 42 53 73 12 43 74 13 44 75.

[0022] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generating polynomial is D^6 + D^4 + D^2 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 2 5 7 13 14 16 19 20 23 26 28 34 35 37 40 41 44 47 49 55 56 58 61 62 65 68 70 0 3 6 8 15 17 21 24 27 29 36 38 42 45 48 50 57 59 63 66 69 71 1 4 9 18 22 25 30 39 43 46 51 60 64 67 72 10 31 52 73 11 32 53 74 12 33 54 75.

[0023] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generating polynomial is D^11 + D^10 + D^9 + D^5 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 1 2 3 4 6 7 10 13 15 19 21 22 23 24 25 27 30 33 34 35 37 41 44 46 47 48 49 50 55 57 58 59 60 61 62 63 66 67 69 70 5 8 11 14 16 20 26 28 31 36 38 42 45 51 56 64 68 71 9 12 17 29 32 39 43 52 65 72 18 40 53 73 54 74 75 76 77 78 79 80.

[0024] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generating polynomial is D^11 + D^7 + D^6 + D^2 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 1 5 11 13 15 16 19 20 23 24 29 30 31 32 33 35 37 39 41 43 47 52 53 54 55 56 57 58 59 60 61 62 65 66 70 2 6 12 14 17 21 25 34 36 38 40 42 44 48 63 67 71 3 7 18 22 26 45 49 64 68 72 0 4 8 27 46 50 69 73 9 28 51 74 10 75 76 77 78 79 80.

[0025] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generating polynomial is D^11 + D^10 + D^9 + D^6 + D^4 + D^2 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 1 5 6 9 10 12 13 14 16 19 21 22 23 24 25 26 29 34 36 37 38 41 43 47 49 50 51 52 54 61 63 64 65 66 67 69 70 2 7 11 15 17 20 27 30 35 39 42 44 48 53 55 62 68 71 3 8 18 28 31 40 45 56 72 4 32 46 57 73 33 58 74 59 75 60 76 77 78 79 80.

[0026] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generating polynomial is D^11 + D^10 + D^9 + D^7 + D^5 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 5 7 8 11 12 16 18 19 21 22 24 25 27 30 34 38 39 46 50 53 54 55 58 59 63 64 67 69 70 1 6 9 13 17 20 23 26 28 31 35 40 47 51 56 60 65 68 71 2 10 14 29 32 36 41 48 52 57 61 66 72 3 15 33 37 42 49 62 73 4 43 74 44 75 45 76 77 78 79 80.

[0027] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generating polynomial is D^11 + D^9 + D^8 + D^6 + D^5 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 10 15 18 20 21 22 23 24 27 29 31 32 35 36 38 41 42 44 46 47 49 53 54 55 58 59 63 64 65 66 67 68 70 1 11 16 19 25 28 30 33 37 39 43 45 48 50 56 60 69 71 2 12 17 26 34 40 51 57 61 72 3 13 52 62 73 4 14 74 5 75 6 76 7 77 8 78 9 79 80.

[0028] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generating polynomial is D^11 + D^10 + D^9 + D^8 + D^7 + D^5 + D^4 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 1 2 4 5 8 9 11 13 17 18 20 24 27 28 30 32 33 36 39 40 41 42 43 44 47 49 52 53 54 55 61 62 63 65 69 70 3 6 10 12 14 19 21 25 29 31 34 37 45 48 50 56 64 66 71 7 15 22 26 35 38 46 51 57 67 72 0 16 23 58 68 73 59 74 60 75 76 77 78 79 80.

[0029] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generating polynomial is D^11 + D^10 + D^3 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 2 3 4 5 9 16 17 18 19 20 22 25 28 29 30 31 32 33 38 39 40 42 44 47 50 52 53 56 58 60 61 63 64 65 66 67 68 69 70 0 6 10 21 23 26 34 41 43 45 48 51 54 57 59 62 71 1 7 11 24 27 35 46 49 55 72 8 12 36 73 13 37 74 14 75 15 76 77 78 79 80.

[0030] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generating polynomial is D^11 + D^5 + D^3 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 2 5 13 14 15 16 20 23 27 30 32 34 35 36 37 38 39 40 43 47 48 52 54 58 59 60 62 64 70 0 3 6 17 21 24 28 31 33 41 44 49 53 55 61 63 65 71 1 4 7 18 22 25 29 42 45 50 56 66 72 8 19 26 46 51 57 67 73 9 68 74 10 69 75 11 76 12 77 78 79 80.

[0031] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generating polynomial is D^11 + D^10 + D^9 + D^8 + D^6 + D^5 + D^3 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 1 3 4 5 8 9 10 13 22 24 28 33 34 39 41 46 47 49 53 54 56 57 60 61 62 63 64 66 69 70 2 6 11 14 23 25 29 35 40 42 48 50 55 58 65 67 71 7 12 15 26 30 36 43 51 59 68 72 16 27 31 37 44 52 73 17 32 38 45 74 18 75 19 76 20 77 21 78 79 80.

[0032] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generating polynomial is D^11 + D^10 + D^8 + D^7 + D^6 + D^5 + D^3 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 3 5 6 7 8 11 13 15 17 19 21 22 26 27 30 31 32 33 35 36 41 42 43 47 49 53 61 62 65 68 69 70 1 4 9 12 14 16 18 20 23 28 34 37 44 48 50 54 63 66 71 2 10 24 29 38 45 51 55 64 67 72 25 39 46 52 56 73 40 57 74 58 75 59 76 60 77 78 79 80.

[0033] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generating polynomial is D^11 + D^9 + D^7 + D^6 + D^5 + D^4 + D^3 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 1 4 6 9 12 14 15 16 23 28 30 34 35 37 38 39 41 42 43 45 46 47 48 51 52 53 56 60 61 63 65 68 70 2 5 7 10 13 17 24 29 31 36 40 44 49 54 57 62 64 66 69 71 0 3 8 11 18 25 32 50 55 58 67 72 19 26 33 59 73 20 27 74 21 75 22 76 77 78 79 80.

[0034] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generating polynomial is D^11 + D^10 + D^9 + D^7 + D^6 + D^3 + D^2 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 2 3 6 8 9 11 12 13 14 21 24 26 27 28 29 30 31 32 34 36 37 38 39 40 41 47 48 49 53 54 57 61 65 67 69 70 0 4 7 10 15 22 25 33 35 42 50 55 58 62 66 68 71 1 5 16 23 43 51 56 59 63 72 17 44 52 60 64 73 18 45 74 19 46 75 20 76 77 78 79 80.

[0035] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generating polynomial is D^11 + D^8 + D^6 + D^5 + D^4 + D^3 + D^2 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 2 3 4 5 6 7 12 14 16 20 22 23 26 31 34 37 39 40 41 44 46 49 51 52 53 54 58 62 63 65 67 70 0 8 13 15 17 21 24 27 32 35 38 42 45 47 50 55 59 64 66 68 71 1 9 18 25 28 33 36 43 48 56 60 69 72 10 19 29 57 61 73 11 30 74 75 76 77 78 79 80.

[0036] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 16, K2 is equal to 100, the CRC generating polynomial is D^16 + D^12 + D^5 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 2 4 5 12 14 16 18 19 20 23 25 26 28 30 33 34 35 36 37 42 44 45 48 49 51 52 58 65 67 68 72 73 74 78 80 81 88 89 92 96 100 3 6 13 15 17 21 24 27 29 31 38 43 46 50 53 59 66 69 75 79 82 90 93 97 101 7 22 32 39 47 54 60 70 76 83 91 94 98 102 8 40 55 61 71 77 84 95 99 103 0 9 41 56 62 85 104 1 10 57 63 86 105 11 64 87 106 107 108 109 110 111 112 113 114 115.

[0037] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 6, K2 is equal to 70, the CRC generating polynomial is D^6 + D^5 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 1 2 8 13 14 18 20 23 24 25 26 28 32 33 34 37 40 42 43 45 46 47 49 50 53 54 56 58 60 61 62 63 64 65 71 3 9 15 19 21 27 29 35 38 41 44 48 51 55 57 59 66 72 4 10 16 22 30 36 39 52 67 73 5 11 17 31 68 74 6 7 69 70 12 75.

[0038] In a possible implementation, the cyclic redundancy check (CRC) encoding of the K1 information bits to obtain the first bit sequence includes: performing CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L is equal to 11, K2 is equal to 70, the CRC generating polynomial is D^11 + D^10 + D^9 + D^5 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 1 2 5 8 10 14 16 17 18 19 20 22 25 28 29 30 32 36 39 41 42 43 44 45 50 52 53 54 55 56 57 58 61 62 64 65 76 0 3 49 11 12 13 23 24 31 33 35 38 48 49 59 60 63 66 72 6 15 21 26 37 40 46 51 77 34 67 73 7 27 47 78 68 74 79 69 70 71 75 80.

[0039] Second aspect, embodiments of the present application provide a decoding method, which includes: obtaining a sequence to be decoded; performing a check on the sequence to be decoded based on a first CRC generating polynomial, where the sequence to be decoded is obtained based on a second bit sequence obtained by interleaving a first bit sequence, the first bit sequence includes K1 information bits and L CRC bits, K1 is a positive integer, and L is a positive integer less than 24; when the sequence to be decoded passes the check, using a first distributed CRC deinterleaver to deinterleave the second bit sequence to obtain the K1 information bits; where the first distributed CRC deinterleaver corresponds to a first distributed interleaver, the first distributed CRC interleaver includes (K2 + L) elements, and the values of the (K2 + L - S)-th element to the (K2 + L)-th element of the first distributed CRC interleaver are sequentially (K2 + L - 1 - S) to (K2 + L - 1), S is an integer greater than or equal to 0 and less than or equal to L, and K2 is an integer greater than or equal to K1.

[0040] In embodiments of the present application, when the sequence to be decoded passes the check, a first distributed CRC deinterleaver is used to deinterleave the second bit sequence to obtain K1 information bits. The first distributed CRC deinterleaver supports DCRC encoding with shorter payloads, which can reduce decoding power consumption and resource overhead.

[0041] In a possible implementation, the first distributed CRC interleaver is obtained by arranging L element sequences in order. For any two element sequences among the L element sequences, which are a first element sequence and a second element sequence, the elements included in the first element sequence are obtained based on the positions of the information bits associated with a first check column, and the elements included in the second element sequence are obtained based on the positions of the information bits associated with a second check column. The first check column and the second check column are any two columns in a check matrix obtained based on an L-length CRC generating polynomial. When the largest element representing the position of the information bit associated with the first check column in the first element sequence is greater than the largest element representing the position of the information bit associated with the second check column in the second element sequence, the sorting of the first element sequence in the first distributed CRC interleaver is after the second element sequence.

[0042] For various possible implementation manners of the second aspect, reference may be made to various possible implementation manners of the first aspect.

[0043] Regarding the technical effects brought by various possible implementation manners of the second aspect, reference may be made to the introduction of the technical effects of various possible implementation manners of the first aspect.

[0044] In a third aspect, an embodiment of the present application provides a communication device, which has the function of implementing the actions in the method embodiment of the first aspect above. The communication device may be a network device, a component of a network device (such as a processor, a chip, or a chip system, etc.), or a logic module or software that can implement all or part of the functions of the network device. Alternatively, the communication device may be a terminal device, a component of a terminal device (such as a processor, a chip, or a chip system, etc.), or a logic module or software that can implement all or part of the functions of the terminal device. The function of the communication device may be implemented by hardware or by hardware executing corresponding software, and the hardware or software includes one or more modules or units corresponding to the above functions. In a possible implementation manner, the communication device includes a processing module, where: the processing module is configured to perform (cyclic redundancy check, CRC) encoding on K1 information bits to obtain a first bit sequence, the first bit sequence includes the K1 information bits and L CRC bits, K1 is a positive integer, and L is a positive integer less than 24; use a first distributed CRC interleaver to interleave the first bit sequence to obtain a second bit sequence; where the first distributed CRC interleaver includes (K2 + L) elements, and the values of the (K2 + L - S)-th element to the (K2 + L)-th element of the first distributed CRC interleaver are sequentially (K2 + L - 1 - S) to (K2 + L - 1), S is an integer greater than or equal to 0 and less than or equal to L, and K2 is an integer greater than or equal to K1; or the first distributed CRC interleaver includes a total of (K2 + L) natural numbers from 0 to (K2 + L - 1), P is before Q in the first distributed CRC interleaver, both P and Q are integers greater than or equal to K2, and P is greater than Q. Optionally, the communication device further includes a transceiver module, and the transceiver module is configured to send a signal carrying a sequence to be decoded obtained based on the second bit sequence.

[0045] For possible implementation manners of the communication device in the third aspect, reference may be made to various possible implementation manners of the first aspect.

[0046] Regarding the technical effects brought by various possible implementation manners of the third aspect, reference may be made to the introduction of the technical effects of various possible implementation manners of the first aspect.

[0047] Fourthly, an embodiment of the present application provides a communication device, which has a function of implementing the actions in the method embodiment of the second aspect above. The communication device may be a network device, a component of a network device (such as a processor, a chip, or a chip system, etc.), or a logical module or software that can implement all or part of the functions of the network device. Alternatively, the communication device may be a terminal device, a component of a terminal device (such as a processor, a chip, or a chip system, etc.), or a logical module or software that can implement all or part of the functions of the terminal device. The function of the communication device may be implemented by hardware or by hardware executing corresponding software, and the hardware or software includes one or more modules or units corresponding to the above functions. In a possible implementation manner, the communication device includes a processing module, where: the processing module is configured to obtain a sequence to be decoded; perform a check on the sequence to be decoded based on a first CRC generation polynomial, the sequence to be decoded is obtained based on a second bit sequence obtained by interleaving a first bit sequence, the first bit sequence includes K1 information bits and L CRC bits, K1 is a positive integer, and L is a positive integer less than 24; when the sequence to be decoded passes the check, use a first distributed CRC deinterleaver to deinterleave the second bit sequence to obtain the K1 information bits; where the first distributed CRC deinterleaver corresponds to a first distributed interleaver, the first distributed CRC interleaver includes (K2 + L) elements, and the values of the (K2 + L - S)-th element to the (K2 + L)-th element of the first distributed CRC interleaver are (K2 + L - 1 - S) to (K2 + L - 1) in sequence, S is an integer greater than or equal to 0 and less than or equal to L, and K2 is an integer greater than or equal to K1. Optionally, the communication device further includes a transceiver module, and the transceiver module is configured to carry a signal carrying the sequence to be decoded.

[0048] For possible implementation manners of the communication device in the fourth aspect, reference may be made to various possible implementation manners of the second aspect.

[0049] Regarding the technical effects brought by various possible implementation manners of the fourth aspect, reference may be made to the introduction of the technical effects of various possible implementation manners of the second aspect.

[0050] Fifthly, an embodiment of the present application provides another communication device, which includes one or more processors, and the one or more processors are configured to process data or signaling so that the method in any one of the first aspect to the second aspect above is implemented.

[0051] Optionally, the communication device further includes a memory that stores programs or instructions. When the programs or instructions are executed by the processor, the communication device is caused to perform the methods as shown in the first aspect or the second aspect above. Exemplarily, the communication device may be a chip, the processor is a processing circuit in the chip, and the memory is a random access memory or cache in the chip.

[0052] In a possible implementation, during the process of executing the above method, the process of sending information (or signals) in the above method can be understood as a process of outputting information based on the instructions of the processor. When outputting information, the processor outputs the information to the transceiver for transmission by the transceiver. After the information is output by the processor, it may also be subject to other processing and then reach the transceiver. Similarly, when the processor receives input information, the transceiver receives the information and inputs it to the processor. Further, after the transceiver receives the information, the information may be subject to other processing before being input to the processor.

[0053] For operations such as sending and / or receiving involved by the processor, if there is no special indication, or if it does not conflict with its actual role or internal logic in the relevant description, it can generally be understood as an output based on the instructions of the processor.

[0054] During implementation, the above processor may be a processor dedicated to executing these methods, or a processor that executes computer instructions in the memory to execute these methods, such as a general-purpose processor, etc. For example, the processor can also be used to execute the program stored in the memory. When the program is executed, the communication device is caused to perform the methods as shown in the first aspect or any possible implementation manner of the first aspect above.

[0055] In a possible implementation manner, the memory is located outside the above communication device. In a possible implementation manner, the memory is located inside the above communication device.

[0056] In a possible implementation manner, the processor and the memory may also be integrated into one device, that is, the processor and the memory may also be integrated together.

[0057] In a possible implementation manner, the communication device further includes a transceiver, which is used to receive signals or send signals, etc.

[0058] In a sixth aspect, the present application provides another communication device, which includes a processing circuit and an interface circuit. The interface circuit is used to obtain data or output data; the processing circuit is used to perform the methods as shown in any one of the first aspect to the second aspect above.

[0059] In a seventh aspect, the present application provides a computer-readable storage medium storing a computer program, which includes program instructions that, when executed, cause a computer to execute the method as shown in any one of the first aspect to the second aspect above.

[0060] In an eighth aspect, the present application provides a computer program product, which includes a computer program that includes program instructions that, when executed, cause a computer to execute the method as shown in any one of the first aspect to the second aspect above.

[0061] In a ninth aspect, the present application provides a chip, including a communication interface and a processor; the communication interface is used for signal transceiver of the chip; the processor is used for executing computer program instructions to cause a communication device including the chip to execute the method as shown in any one of the first aspect to the second aspect above.

[0062] In a tenth aspect, an embodiment of the present application provides a communication system, including the communication device as described in the third aspect or any possible implementation manner of the third aspect, and the communication device as described in the fourth aspect or any possible implementation manner of the fourth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 A schematic diagram showing the working principle of a downlink low-power wake-up signal of a low-power device is given;

[0064] Figure 2 is a schematic diagram of the architecture of a communication system to which an embodiment of the present application can be applied;

[0065] Figure 3 is a schematic flowchart of a communication system;

[0066] Figure 4 is a flowchart of a coding method provided by an embodiment of the present application;

[0067] Figure 5 is another flowchart of a coding method provided by an embodiment of the present application;

[0068] Figure 6 is an example of a DCRC coding matrix corresponding to a first distributed CRC interleaver provided by an embodiment of the present application;

[0069] Figure 7 is another example of a DCRC coding matrix corresponding to a first distributed CRC interleaver provided by an embodiment of the present application;

[0070] Figure 8 is another example of a DCRC coding matrix corresponding to a first distributed CRC interleaver provided by an embodiment of the present application;

[0071] Figure 9 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0072] Figure 10 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0073] Figure 11 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0074] Figure 12 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0075] Figure 13 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0076] Figure 14 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0077] Figure 15 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0078] Figure 16 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0079] Figure 17 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0080] Figure 18 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0081] Figure 19 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0082] Figure 20 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0083] Figure 21An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0084] Figure 22 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0085] Figure 23 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0086] Figure 24 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0087] Figure 25 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0088] Figure 26 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0089] Figure 27 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0090] Figure 28 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0091] Figure 29 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0092] Figure 30 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0093] Figure 31 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0094] Figure 32 An example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application;

[0095] Figure 33 Another flowchart of the encoding method provided by the embodiments of the present application;

[0096] Figure 34Another flowchart of the encoding method provided by the embodiments of the present application;

[0097] Figure 35 A schematic structural diagram of a communication device 3500 provided by the embodiments of the present application;

[0098] Figure 36 A schematic structural diagram of another device 360 provided by the embodiments of the present application. Detailed implementation manners

[0099] Terms such as "first" and "second" in the description, claims and drawings of the present application are only used to distinguish different objects, rather than to describe a specific order. It can be understood that the various numerical numbers involved in the embodiments of the present application are only for the convenience of description and do not limit the scope of the embodiments of the present application. The magnitude of the serial numbers of the above processes does not mean the sequence of execution, and the execution sequence of each process should be determined by its function and internal logic. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device, etc. that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or devices, etc.

[0100] The "embodiments" mentioned herein mean that specific features, structures or characteristics described in combination with the embodiments can be included in at least one embodiment of the present application. The appearance of this phrase in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art can explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments. In the present application, the naming of messages is only used to distinguish different messages and should not be construed as a limitation. That is, the name of any message in the present application can be replaced by other naming, and the present application makes no limitation.

[0101] The terms used in the following embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the specification and appended claims of the present application, the singular forms "a", "an", "the", "above", "said", "this" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used in the present application refers to and includes any and all possible combinations of one or more of the listed items. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The term "plurality" used in the present application means two or more. In the written description of the present application, the character " / " generally indicates an "or" relationship between the associated objects before and after.

[0102] It can be understood that in the embodiments of the present application, "B corresponding to A" means that there is a corresponding relationship between A and B, and B can be determined according to A. However, it should also be understood that determining (or generating) B based on (or according to) A does not mean that B is determined (or generated) only based on (or according to) A, but B can also be determined (or generated) based on (or according to) A and / or other information.

[0103] It should be understood that in the present application, indication includes direct indication (also known as explicit indication) and implicit indication. Among them, directly indicating information A means including this information A; implicitly indicating information A means indicating information A through the corresponding relationship between information A and information B and directly indicating information B. Among them, the corresponding relationship between information A and information B can be predefined, prestored, pre-fired, or pre-configured.

[0104] It should be understood that in the present application, information C is used for the determination of information D, which includes both the case where information D is determined only based on information C and the case where information D is determined based on information C and other information. In addition, the situation where information C is used for the determination of information D can also be an indirect determination. For example, information D is determined based on information E, and information E is determined based on information C.

[0105] In addition, "network element A sends information A to network element B" in the embodiments of the present application can be understood as the destination end of the information A or the intermediate network element in the transmission path between the destination ends is network element B, which can include directly or indirectly sending information to network element B. "Network element B receives information A from network element A" can be understood as the source end of the information A or the intermediate network element in the transmission path between the source ends is network element A, which can include directly or indirectly receiving information from network element A. Necessary processing may be performed on the information between the source end and the destination end of the information transmission, such as format change, etc., but the destination end can understand the valid information from the source end. Similar expressions in the present application can be understood similarly and will not be elaborated here.

[0106] To facilitate the understanding of the solution of this application, the terms and technical solutions involved in the embodiments of this application are first introduced below.

[0107] Low-power wakeup signal (LP-WUS): If the main receiver of a user equipment (UE) is set to be turned off or to remain in a deep sleep state before being woken up, the power consumption of the UE can be significantly reduced. The wakeup of the UE can be achieved by triggering a low-power wakeup receiver with the ability to monitor the wakeup signal using a wakeup signal. Figure 1 A schematic diagram of the working principle of the downlink low-power wakeup signal of a low-power device is given. As Figure 1 shown, the UE is equipped with a main receiver and a low-power wakeup receiver. Both the main receiver and the low-power wakeup receiver have independent radio frequency (RF) circuits and antennas; the main receiver is used for data transmission and reception and is set to be turned off or to remain in a deep sleep state if not woken up by a wakeup signal; the low-power wakeup receiver serves as a supplementary chip for powering on and off the main receiver. The low-power wakeup receiver receives the LP-WUS through a separate antenna, which may put the main receiver into an ultra-deep sleep state when there is limited or no traffic activity; the UE wakes up the main receiver after detecting the LP-WUS through the low-power wakeup receiver. Exemplarily, before sending data to the UE, the base station may first send the LP-WUS to the UE; after the main receiver of the UE is woken up, a new radio (NR) signal is sent to the UE to transmit data.

[0108] Cyclic redundancy check code: In serial transmission (disks, communications), cyclic redundancy check codes are widely used. CRC also adds several check bits to the information bits to increase the code distance and error detection and correction capabilities of the entire coding system. The basic principle of cyclic redundancy check code is as follows: After K bits of information bits, R bits of check bits are concatenated. The entire coding length is N bits, so this coding is also called an (N, K) code. For a given (N, K) code, it can be proven that there exists a polynomial G(x) with the highest power of N - K = R. The check bits for the K bits of information bits can be generated according to G(x), and G(x) can be called the CRC generating polynomial (which can be simply called the generating polynomial). The specific process of generating the check bits is as follows: Assume that the transmitted information is represented by the information polynomial C(X). Shifting C(x) to the left by R bits can be expressed as C(X) * 2 R, so there will be R bits empty on the right side of C(x), which is the position of the check code. The remainder obtained by dividing C(x)*2 by the CRC generating polynomial G(x) is the check code. The CRC generating polynomial is an agreement between the receiver (or the receiving end) and the sender (or the sending end), that is, a binary number, which remains unchanged throughout the transmission process. At the sender, the check code is generated by performing modulo-2 division of the information polynomial using the CRC generating polynomial. At the receiver, the received coded polynomial is subjected to modulo-2 division using the CRC generating polynomial to detect and determine the error position. The CRC generating polynomial should meet the following conditions: a. The highest and lowest bits of the CRC generating polynomial must be 1; b. When any bit of the transmitted information (CRC code) is in error, the remainder after modulo-2 division by the generating polynomial should not be 0.

[0109] The following introduces the communication system applicable to the technical solution provided by this application.

[0110] The technical solutions provided by this application can be applied to various communication systems, such as: narrowband-internet of things (NB-IoT) systems, global system for mobile communications (GSM), enhanced data rate for GSM evolution (EDGE) systems, 5th generation (5G) or new radio (NR) systems, long term evolution (LTE) systems, LTE frequency division duplex (FDD) systems, wireless local area network (WLAN) systems, satellite communication systems, future communication systems, such as 6th generation (6G) mobile communication systems, or integrated systems of multiple systems, etc. The technical solutions provided by this application can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), and internet of things (IoT) communication systems or other communication systems. The technical solutions provided by the embodiments of this application are also applicable to other communication systems involving channel coding. The above-mentioned communication systems applicable to the technical solutions provided by the embodiments of this application are only examples, and the communication systems applicable to the technical solutions provided by this application are not limited thereto. It is hereby uniformly stated that the following will not be elaborated any further.

[0111] The first device in a communication system can send a signal to the second device or receive a signal from the third device. The signal can include information, signaling, data, etc. Herein, the device can also be replaced with an entity, a network entity, a communication device, a communication module, a node, a communication node, etc. In this disclosure, a network element is taken as an example for description. Herein, the first device can be a network device or a terminal device, the second device can be a network device or a terminal device, and the third device can be a network device or a terminal device. For example, a communication system can include at least one terminal device and at least one network device. The network device can send a downlink signal to the terminal device, and / or the terminal device can send an uplink signal to the network device. It can be understood that the terminal device in this disclosure can be replaced with the first device, and the network device can be replaced with the second device, and both execute the corresponding communication methods in this disclosure.

[0112] Figure 2 is a schematic diagram of the architecture of a communication system to which the embodiments of the present application can be applied. As Figure 2 shown, the communication system includes a network device 110, a terminal device 120, and a terminal device 130. The communication system to which the embodiments of the present application can be applied includes one or more terminal devices, and the terminal device 120 and the terminal device 130 are taken as examples of the terminal devices in the communication system. Figure 2 This is only a schematic diagram, and the embodiments of the present application do not limit the number of network devices and terminal devices included in the communication system. The terminal device 120 and the terminal device 130 can be connected to the network device 110 and communicate with the network device 110. The technical solution provided by the present application is applicable to low-power scenarios, such as Figure 2 the terminal device in is a low-power device.

[0113] In the embodiments of the present application, the terminal device can also be referred to as a user equipment (UE), an access terminal, a user unit, a user station, a mobile station, a mobile terminal, a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent, or a user device.

[0114] The terminal device can be a device that provides voice / data. For example, it can be a handheld device with wireless connection function, a vehicle-mounted device, etc. Currently, some examples of terminals are: mobile phone, tablet computer, laptop computer, palmtop computer, mobile internet device (MID), wearable device, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, cellular phone, cordless phone, session initiation protocol (SIP) phone, wireless local loop (WLL) station, personal digital assistant (PDA), a handheld device with wireless communication function, a computing device or other processing devices connected to a wireless modem, wearable device, terminal device in a 5G network or terminal device in a future evolved public land mobile network (PLMN), etc. The embodiments of the present application are not limited thereto.

[0115] By way of example and not limitation, in the embodiments of the present application, the terminal device can also be a wearable device. A wearable device can also be referred to as a wearable intelligent device, which is a general term for devices developed by applying wearable technology to the intelligent design of daily wear, such as glasses, gloves, watches, clothing, shoes, etc. A wearable device is a portable device that is directly worn on the body or integrated into the user's clothes or accessories. A wearable device is not just a hardware device, but also realizes powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable intelligent devices include those with complete functions and large sizes that can achieve complete or partial functions without relying on a smartphone, such as smart watches or smart glasses, etc., and those that only focus on a certain type of application function and need to cooperate with other devices such as smartphones, such as various smart bracelets and smart jewelry for physical sign monitoring.

[0116] In the embodiments of the present application, the device for implementing the functions of the terminal device may be the terminal device itself, or a device capable of supporting the terminal device to implement such functions, such as a chip system. This device may be installed in the terminal device or used in combination with the terminal device. In the embodiments of the present application, the chip system may be composed of chips, or may include chips and other discrete devices. In the embodiments of the present application, only the case where the device for implementing the functions of the terminal device is the terminal device is used as an example for illustration, which does not limit the solutions of the embodiments of the present application.

[0117] The network device in the embodiments of the present application can be a device for communicating with a terminal device. This network device can also be referred to as an access network device or a radio access network device. For example, the network device can be a base station. The network device in the embodiments of the present application can refer to a radio access network (RAN) node (or device) that connects a terminal device to a wireless network. A base station can generally cover various names as follows, or be replaced with the following names, such as: RAN node, Node B, evolved Node B (eNB), next generation Node B (gNB), relay station, access point, transmitting and receiving point (TRP), transmitting point (TP), master station, secondary station, multi-standard radio (MSR) node, home base station, network controller, access node, wireless node, access point (AP), transmission node, transceiver node, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), radio unit (RU), positioning node, etc. A base station can be a macro base station, a micro base station, a relay node, a donor node or the like, or a combination thereof. A base station can also refer to a communication module, a modem or a chip disposed in the foregoing device or apparatus. A base station can also be a mobile switching center and a device that undertakes the function of a base station in D2D, V2X, M2M communications, a network-side device in a 6G network, a device that undertakes the function of a base station in a future communication system, etc. A base station can support networks with the same or different access technologies. Optionally, the RAN node can also be a server, a wearable device, a vehicle or an in-vehicle device, etc. For example, the access network device in vehicle to everything (V2X) technology can be a road side unit (RSU). The embodiments of the present application do not limit the specific technologies and specific device forms adopted by the network device. A base station can be fixed or mobile. For example, a helicopter or a drone can be configured to act as a mobile base station, and one or more cells can move according to the position of the mobile base station. In other examples, a helicopter or a drone can be configured to be a device for communicating with another base station.

[0118] In some deployments, the network device mentioned in the embodiments of this application may be a device including a CU, or a DU, or a device including a CU and a DU, or a control plane CU node (Central Unit-Control Plane, CU-CP) and a user plane CU node (Central Unit-User Plane, CU-UP) and a DU node. For example, the network device may include a gNB-CU-CP, a gNB-CU-UP, and a gNB-DU.

[0119] In some deployments, multiple RAN nodes cooperate to assist a terminal in achieving wireless access, and different RAN nodes respectively implement partial functions of a base station. For example, the RAN node may be a CU, a DU, a CU-CP, a CU-UP, or an RU, etc. The CU and the DU may be separately provided, or may also be included in the same network element, such as a BBU. The RU may be included in a radio frequency device or a radio frequency unit, such as included in an RRU, an AAU, or an RRH.

[0120] In the embodiments of this application, the apparatus for implementing the functions of the network device may be the network device; it may also be an apparatus capable of supporting the network device in implementing such functions, such as a chip system, a hardware circuit, a software module, or a combination of a hardware circuit and a software module. The apparatus may be installed in the network device or used in cooperation with the network device. In the embodiments of this application, only the case where the apparatus for implementing the functions of the network device is the network device is taken as an example for illustration, which does not limit the solutions of the embodiments of this application.

[0121] It should be noted that the network architecture described in the embodiments of this application is for more clearly explaining the technical solutions of the embodiments of this application, and does not constitute a limitation on the technical solutions provided by the embodiments of this application. Those of ordinary skill in the art will know that with the evolution of the network architecture and the emergence of new service scenarios, the technical solutions provided by the embodiments of this application are equally applicable to similar technical problems.

[0122] Figure 3 For a schematic diagram of the process of a communication system, as Figure 3 shown, at the sending end, the information source sequentially undergoes source coding, channel coding, rate matching (optional step), and modulation before being sent out. At the receiving end, it sequentially passes through demodulation, rate dematching (optional step), channel decoding, and source decoding and outputs to the destination. The embodiments of this application mainly relate to channel coding and channel decoding (abbreviated as channel encoding and decoding). Among them, the channel coding part is located between source coding and modulation and is responsible for performing channel coding on the bits generated by the information source. The channel decoding part is located between demodulation and source decoding and is responsible for restoring the information source bit stream.

[0123] In the low-power scenario to which the technical solution provided by this application is applied, there can be only one channel coding method involved in low-power devices (such as terminal devices), that is, the data channel and the control channel adopt the same coding strategy. The main principle of the technical solution provided by this application is that the channel coding adopts a distributed CRC interleaver (subsequently referred to as the DCRC interleaver) that supports smaller payloads and shorter CRC lengths, in order to meet the requirements of low-power devices for energy efficiency, coverage, and false alarm rate (FAR). In a possible implementation, both the data channel and the control channel adopt the channel coding method proposed by this application. In a possible implementation, LP-WUS also adopts the above channel coding method. For example, when the number of payload bits to be sent by the sending end decreases, there is no need for a 24-bit CRC at this time, so the DCRC interleaver also needs to be redesigned accordingly and shortened. The CRC length can be 6, 11, 16, or other values, which are not limited in this application. The size of the payload can be less than or equal to 70.

[0124] The following first combines the attached Figure 4 to introduce the technical solution provided by this application. Figure 4 It is a flowchart of a coding method provided by an embodiment of this application.

[0125] As Figure 4 shown, the method includes:

[0126] 401. The sending end performs CRC coding on K1 information bits to obtain a first bit sequence.

[0127] In a possible implementation, the sending end is a network device and the receiving end is a terminal device. In a possible implementation, the sending end is a terminal device and the receiving end is a network device. The above first bit sequence includes the above K1 information bits and L CRC bits, where K1 is a positive integer and L is a positive integer less than 24. Exemplarily, the K1 information bits can be obtained by the sending end performing source coding on multiple bits to be sent, and the K1 information bits are the bits to be subjected to channel coding.

[0128] In a possible implementation, L is equal to 6, 11, or 16. L can also be other integers less than 24, which are not limited in this application.

[0129] In a possible implementation, K1 is equal to 32, 40, 48, 54, 64, 70, or 100. K1 can also be other integers less than 140, which are not limited in this application.

[0130] 402. The sending end interleaves the first bit sequence using a first distributed CRC interleaver to obtain a second bit sequence.

[0131] The first distributed CRC interleaver includes (K2 + L) elements. The values of the (K2 + L - S)-th element to the (K2 + L)-th element of the first distributed CRC interleaver are sequentially (K2 + L - 1 - S) to (K2 + L - 1), where S is an integer greater than or equal to 0 and less than or equal to L, and K2 is an integer greater than or equal to K1. (K2 + L) is less than 164. Alternatively, the first distributed CRC interleaver includes a total of (K2 + L) natural numbers from 0 to (K2 + L - 1). In the first distributed CRC interleaver, P is before Q, and both P and Q are integers greater than or equal to K2, and P is greater than Q. Alternatively, the first distributed CRC interleaver includes a total of (K2 + L) natural numbers from 1 to (K2 + L). In the first distributed CRC interleaver, P is before Q, and both P and Q are integers greater than or equal to K2, and P is greater than Q. For example, K2 is equal to 70, P is 75, and Q is 72. In this article, the elements in the DCRC interleaver can start from 0, that is, 0 represents the first position, or the elements in the DCRC interleaver can also start from 1, that is, 1 represents the first position. There is no restriction here.

[0132] In a possible implementation, K2 is equal to 70 or 100. K2 can also be other integers less than 140 and greater than or equal to K1, which is not limited in this application. Exemplarily, K2 is equal to 70, L = 6, S = 0, and the 76th element (i.e., the last element) of the first distributed CRC interleaver is 75; among them, the 75th element of the first distributed CRC interleaver may not be 74. Exemplarily, K2 is equal to 70, L = 11, S = 1, the 80th element (i.e., the last element) of the first distributed CRC interleaver is 79, and the 81st element is 80; among them, the 79th element of the first distributed CRC interleaver may not be 78, or the 78th element of the first distributed CRC interleaver may not be 77, or the 77th element of the first distributed CRC interleaver may not be 76.

[0133] In a possible implementation, the above-mentioned first distributed CRC interleaver is obtained by arranging L element sequences in order. Any two of the L element sequences are the first element sequence and the second element sequence. The elements included in the first element sequence are obtained based on the positions of the information bits associated with the first check column, and the elements included in the second element sequence are obtained based on the positions of the information bits associated with the second check column. The first check column and the second check column are any two columns in the check matrix obtained based on the L-length CRC generating polynomial. When the largest element representing the position of the information bit associated with the first check column in the first element sequence is greater than the largest element representing the position of the information bit associated with the second check column in the second element sequence, the sorting of the first element sequence in the first distributed CRC interleaver is after the second element sequence. Exemplarily, the second element sequence is [2 3 40 72], where the second element sequence represents the first check column (i.e., the 73rd column of the check matrix is associated with the 2nd, 3rd, and 40th information bits); the first element sequence is [1 60 71], where the first element sequence represents the second check column (i.e., the 72nd column of the check matrix is associated with the 1st and 60th information bits). In this implementation manner, when the largest element representing the position of the information bit associated with the first check column in the first element sequence is greater than the largest element representing the position of the information bit associated with the second check column in the second element sequence, the sorting of the first element sequence in the first distributed CRC interleaver is after the second element sequence, so that the receiving end can detect the CRC check failure earlier during decoding, thereby saving decoding power consumption.

[0134] An example of obtaining the first distributed CRC interleaver based on the L-length CRC generating polynomial is as follows: The transmitting end obtains the positions of the information bits associated with each column of the check matrix generated by the L-length CRC generating polynomial. Among them, a CRC generating polynomial g of length L is given L , such as g L = D^6 + D^5 + 1. This CRC generating polynomial corresponds to a matrix G with K rows and (K + L) columns crc , where the first K rows and K columns of G crc is an identity matrix, and the last K rows and L columns of G crc is the check matrix generated by the CRC generating polynomial, which is used to generate L-bit CRC check bits. K is equal to 70 and L is equal to 6. The first check column of this check matrix (the 71st column of matrix G crc ) is associated with the 023456713181923252829303133373839424547485051525455585961636566676869th information bits, and the second check column of this check matrix (the 72nd column of matrix G crcThe 72nd column) is associated with the 1238142024263234404346495356606264th information bit, and the third parity check column of this parity check matrix (matrix G crc The 73rd column) is associated with the 891415212735414457th information bit, and the fourth parity check column of this parity check matrix (matrix G crc The 74th column) is associated with the 1016222736th information bit, and the fifth parity check column of this parity check matrix (matrix G crc The 75th column) is associated with the 111728313965th information bit, and the sixth parity check column of this parity check matrix (matrix G crcThe 76th column) associates with the 5,122,534th information bit; the sender obtains element sequence #1 [0 2 3 4 5 6 7 13 18 19 23 25 28 29 30 31 33 37 38 39 42 45 47 48 50 51 52 54 55 58 59 61 63 65 66 67 68 69] based on the positions of the information bits associated with the first parity column, obtains element sequence #2 [1 2 3 8 14 20 24 26 32 34 40 43 46 49 53 56 60 62 64] based on the positions of the information bits associated with the second parity column, obtains element sequence #3 [8 9 14 15 21 27 35 41 44 57] based on the positions of the information bits associated with the third parity column, obtains element sequence #4 [10 16 22 27 36] based on the positions of the information bits associated with the fourth parity column, obtains element sequence #5 [11 17 28 31 39 65] based on the positions of the information bits associated with the fifth parity column, and obtains element sequence #6 [5 12 25 34] based on the positions of the information bits associated with the sixth parity column; the sender arranges them in ascending order of the maximum values in the element sequences corresponding to each parity column: [5 12 25 34], [10 16 22 27 36], [8 9 14 15 21 27 35 41 44 57], [1 2 3 8 14 20 24 26 32 34 40 43 46 49 53 56 60 62 64], [11 17 28 31 39 65], [0 2 3 4 5 6 7 13 18 19 23 25 28 29 30 31 33 37 38 39 42 45 47 48 50 51 52 54 55 58 59 61 63 65 66 67 68 69]; the sender packs [5 12 25 34] and the position of the column where the sixth parity column is located (i.e., 75) as a whole and places them in the first 5 positions; packs [10 16 22 27 36] and the position of the column where the fourth parity column is located (73) as a whole and places them behind the first packed sequence; packs [8 9 14 15 21 27 35 41 44 57] and the position of the column where the third parity column is located (72) as a whole and places them behind the second packed sequence; packs [1 2 20 24 26 32 40 43 46 49 53 56 60 62 64] and the position of the column where the second parity column is located (71) as a whole and places them behind the third packed sequence, noting that the elements in the subsequent packets need to remove the elements that already exist in the previous packets; and so on to obtain the final DCRC interleaver.

[0135] 403. The sender performs polarization coding on the second bit sequence to obtain a third bit sequence.

[0136] Among them, the encoding method for polar encoding the second bit sequence at the sending end can adopt existing polar encoding methods, which will not be elaborated here. Step 403 is optional. The sending end can use other encoding methods for the second bit sequence, or it can also stop encoding the second bit sequence. It should be noted that since this step is an optional step: this step is necessary only when polar encoding of the second bit sequence is required; if there is no such need, then this step can be omitted during the actual encoding process. In this case, the third bit sequence in step 404 is the second bit sequence.

[0137] 404. The sending end performs some or all of the steps including but not limited to rate matching, modulation, analog-to-digital conversion, frequency conversion, etc. on the third bit sequence and then sends the resulting sequence to be decoded.

[0138] Correspondingly, the receiving end receives the sequence to be decoded from the sending end. The sequence to be decoded sent by the sending end can be a data signal carrying the sequence to be decoded sent through a data channel, and the above K1 information bits can be data sent by the sending end to the receiving end; or it can be a control signal carrying the sequence to be decoded sent through a control channel, and the above K1 information bits can be control information sent by the sending end to the receiving end.

[0139] It should be noted that the rate matching step in step 404 is optional. If the code length of the encoding is the same as the code length of the target code, rate matching is not required. Since the focus of the embodiments of this application is not on step 404, it will not be described in detail here. For example, in a possible implementation, those skilled in the art can also refer to the practices in the prior art.

[0140] 405. The receiving end decodes the sequence to be decoded to obtain a sequence to be verified.

[0141] The receiving end can obtain the sequence to be decoded based on the signal carrying the sequence to be decoded from the sending end, which is not limited in this application. The above sequence to be decoded is obtained by polar encoding the second bit sequence, and the sequence to be verified can be the above second bit sequence.

[0142] 406. The receiving end performs CRC check on the sequence to be verified.

[0143] In a possible implementation, step 401 is: the sending end performs CRC encoding on K1 information bits based on a CRC generating polynomial to obtain a first bit sequence; step 406 is: the receiving end performs CRC check on the sequence to be verified based on the CRC generating polynomial.

[0144] 407. When the sequence to be verified passes the check, the receiving end uses a first distributed CRC deinterleaver to deinterleave the second bit sequence to obtain the above K1 information bits.

[0145] When the sequence to be verified passes the verification, the sequence to be verified is the second bit sequence. Among them, the above-mentioned first distributed CRC deinterleaver corresponds to the first distributed interleaver. Or rather, the first distributed CRC deinterleaver is obtained based on the first distributed interleaver. Obtaining the deinterleaver corresponding to an interleaver based on the interleaver is a common technical means in the art. Here, an example is used to illustrate the relationship between the interleaver and the deinterleaver: If the interleaver is [2 4 1 3] (that is, the second position is interleaved to the first position, the fourth position is interleaved to the second position, the first position is in the third position, and the third position is interleaved to the last position); then the corresponding deinterleaver is [3 1 4 2], that is, the third position in the interleaved sequence is swapped to the first position, the first position is placed in the second position, the fourth position is placed in the third position, and the second position is placed in the last position, and the sequence before interleaving can be obtained.

[0146] In a possible implementation, when the sequence to be verified fails the verification, the receiving end stops further parsing of the sequence to be verified, such as deinterleaving, etc. Or rather, when the sequence to be verified fails the verification, the decoding is terminated in advance. Optionally, the receiving end sends information to the sending end for indicating that the receiving end has not correctly received the sequence to be decoded.

[0147] In the embodiments of the present application, cyclic redundancy check (CRC) encoding is performed on K1 information bits to obtain a first bit sequence, and the number of CRC check bits is less than 24. The above-mentioned first bit sequence is interleaved using a first distributed CRC interleaver. The first distributed CRC deinterleaver supports DCRC encoding with a shorter payload, and can reduce the decoding power consumption and resource overhead.

[0148] Figure 5 This is a flowchart of another encoding method provided by the embodiments of the present application. Figure 5 The method flow in Figure 4 is a possible implementation manner of the method described in Figure 5 As shown in

[0149] 501. The sending end performs CRC encoding on K1 information bits based on the CRC generating polynomial to obtain a first bit sequence.

[0150] In one possible implementation, the sending end is a network device and the receiving end is a terminal device. In another possible implementation, the sending end is a terminal device and the receiving end is a network device. The first bit sequence includes the K1 information bits and L CRC bits, where K1 is a positive integer and L is a positive integer less than 24. Exemplarily, the K1 information bits can be obtained by the sending end performing source coding on multiple bits to be sent, and the K1 information bits are the bits to be channel-coded. In one possible implementation, L is equal to 6, 11, or 16. L can also be other integers less than 24, which is not limited in this application. In one possible implementation, K1 is equal to 32, 40, 48, 54, 64, 70, or 100. K1 can also be other integers less than 140, which is not limited in this application.

[0151] Exemplarily, the CRC generation polynomial is any one of the following:

[0152] D^6 + D^5 + 1, or 43(hex), where 43(hex) is the hexadecimal representation of the CRC generation polynomial;

[0153] D^6 + D^5 + D^4 + D^3 + 1, or 4F(hex), where 4F(hex) is the hexadecimal representation of the CRC generation polynomial;

[0154] D^6 + D^4 + D^3 + D + 1, or 6D(hex);

[0155] D^6 + D^3 + D^2 + D + 1, or 79(hex);

[0156] D^6 + D^5 + D^2 + 1, or 53(hex);

[0157] D^6 + D^5 + D^4 + D^2 + 1, or 57(hex);

[0158] D^6 + D^3 + D^2 + 1, or 59(hex);

[0159] D^6 + D^5 + D^3 + D^2 + 1, or 5B(hex);

[0160] D^6 + D^5 + D^4 + D^3 + D^2 + 1, or 5F(hex);

[0161] D^6 + D^5 + D^4 + D^3 + D + 1, or 6F(hex);

[0162] D^6 + D^4 + D^2 + D + 1, or 75(hex);

[0163] D^11 + D^10 + D^9 + D^5 + 1, or 847(hex);

[0164] D^11 + D^7 + D^6 + D^2 + 1, or A31 (hex);

[0165] D^11 + D^10 + D^9 + D^6 + D^4 + D^2 + 1, or AA7 (hex);

[0166] D^11 + D^10 + D^9 + D^7 + D^5 + D + 1, or C57 (hex);

[0167] D^11 + D^9 + D^8 + D^6 + D^5 + D + 1, or C6D (hex);

[0168] D^11 + D^10 + D^9 + D^8 + D^7 + D^5 + D^4 + D + 1, or CDF (hex);

[0169] D^11 + D^10 + D^3 + D + 1, or D03 (hex);

[0170] D^11 + D^5 + D^3 + D + 1, or D41 (hex);

[0171] D^11 + D^10 + D^9 + D^8 + D^6 + D^5 + D^3 + D + 1, or D6F (hex);

[0172] D^11 + D^10 + D^8 + D^7 + D^6 + D^5 + D^3 + D + 1, or D7B (hex);

[0173] D^11 + D^9 + D^7 + D^6 + D^5 + D^4 + D^3 + D + 1, or DF5 (hex);

[0174] D^11 + D^10 + D^9 + D^7 + D^6 + D^3 + D^2 + D + 1, or F37 (hex);

[0175] D^11 + D^8 + D^6 + D^5 + D^4 + D^3 + D^2 + D + 1, or FE9 (hex);

[0176] D^16 + D^12 + D^5 + 1, or 10811 (hex).

[0177] 502. The sender uses a first distributed CRC interleaver to interleave the first bit sequence to obtain a second bit sequence.

[0178] Step 502 can refer to Figure 4Step 402 in. The first distributed CRC interleaver can be obtained based on the CRC generating polynomial. An example of obtaining the first distributed CRC interleaver based on the CRC generating polynomial is as follows: First, calculate its corresponding parity-check matrix (K rows and L columns, taking K = 16 and L = 3 as an example below) according to the L-length CRC generating polynomial. Then, look at the positions of the message bits associated with the first column of parity-check columns (i.e., the first column of the parity-check matrix), and pack these positions into a group and then interleave them as a whole to the front (for example, if the first column of parity-check columns is associated with message bits [12 3 4 5 6 7 8], then [1 2 3 4 5 6 7 8] and the position of the first column of parity-check columns K + 1 = 17 are placed in the first 9 positions). Similarly, after packing the positions of the message bits associated with the second column of parity-check columns and the position of the second column of parity-check columns as a whole, place them behind the first packed sequence. For example, if the positions of the message bits associated with the second column of parity-check columns are [7 9 11 16], then pack the 3 message positions [9 11 16] and the position of the second column of parity-check columns K + 2 = 16 + 2 = 18 bits and place them behind the first packed one. Note that the message bit 7 in the message positions [7 9 11 16] associated with the second column of parity-check columns has already been in the first packet, so it needs to be removed in the second packet. Then, after removing duplicates with the message positions that already exist in the previous packets for the positions of the message bits [5 8 10 11 12 13 14 15 16] associated with the third column of parity-check columns, pack them together with the position of the third column of parity-check columns K + 3 = 16 + 3 = 19 and place them behind all the previous packets, that is, place the 6 bits [10 12 13 14 15 19] behind the second packed one to obtain the final DCRC interleaver. Note that for the DCRC interleaver and the CRC generating polynomial, the length of the message bits is K, and the length of the DCRC interleaver is equal to (K + L). In the above example, messages with K less than or equal to 16 are supported for distributed CRC encoding (the maximum support is up to 16).

[0179] Given a CRC generating polynomial g of length L L , such as g L = D^6 + D^5 + 1, this CRC generating polynomial corresponds to a matrix G of K rows and (K + L) columns crc , where the first K rows and K columns of G crc is an identity matrix, and G crcThe last K rows and L columns are the parity-check matrix generated by the CRC generating polynomial, and this parity-check matrix is used to generate L-bit CRC check bits. The transmitter uses the first distributed CRC interleaver to interleave the first bit sequence, and the obtained second bit sequence can be: after the first bit sequence (including K1 information bits + L CRC bits) is interleaved by the first distributed CRC interleaver, the second bit sequence (i.e., the interleaved CRC-encoded sequence) is obtained. The DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc can be in the following two forms. One is the upper triangular form G Dcrc1 , that is, perform DCRC interleaving on both the K rows and (K + L) columns of G crc . Among them, the interleaver used for interleaving the K rows is an interleaver formed by nestedly reading K elements with values greater than or equal to (76 - K) from the DCRC interleaver in natural order, and the interleaver used for interleaving the (K + L) columns is the above (K + L)-long DCRC interleaver; the other form is also a matrix of K rows and (K + L) columns, but it is not upper triangular, that is, G Dcrc2 , and its generation method is to only interleave the (K + L) columns of G crc , and do not interleave the K rows of the matrix. If the K1 information bits are a = a0, a1, a2, …, a69, that is, the payload bits are K1 = 70 bits, and the sequence after DCRC encoding of a is a bit sequence b = b0, b1, b2, …, b75 with a length of K + L = 70 + 6 = 76, then b = a·G Dcrc1 or b = a·G Dcrc2 . G Dcrc1 is the upper triangular matrix shown in Figure 6 . Figure 6 This is an example of the DCRC encoding matrix corresponding to the first distributed CRC interleaver provided by the embodiment of the present application.

[0180] G Dcrc2 is the non-upper triangular matrix shown in Figure 7 , that is, only interleave the columns of G crc . Figure 7 This is another example of the DCRC encoding matrix corresponding to the first distributed CRC interleaver provided by the embodiment of the present application. G Dcrc2 The advantage is that it is more convenient to nestedly read the DCRC encoding matrix. For a payload with K < 70, only the first (70 - K) rows of the matrix need to be skipped, and the last K rows of the matrix can be used for DCRC encoding. And G Dcrc1To support DCRC encoding with K less than 70 bits, it takes 2 steps to read a submatrix of K rows and (K + L) columns. The first step is to determine, according to the above DCRC interleaver (i.e., the first distributed CRC interleaver), the elements with values greater than or equal to (70 - K) (i.e., skip the elements less than (70 - K) without taking them) to form a sequence of length K. The second step is to select the corresponding rows from G Dcrc1 to form the DCRC encoding matrix at the corresponding positions in the sequence of length K obtained in the first step.

[0181] In a possible implementation, the sender multiplies the matrix corresponding to K1 information bits by the DCRC encoding matrix corresponding to the first distributed CRC interleaver to obtain a second bit sequence. For example, the matrix corresponding to K1 information bits is a = a0, a1, a2, …, a69, and G Dcrc1 is the DCRC encoding matrix corresponding to the first distributed CRC interleaver, and the second bit sequence b = a·G Dcrc1 . Another example, the matrix corresponding to K1 information bits is a = a0, a1, a2, …, a69, and G Dcrc2 is the DCRC encoding matrix corresponding to the first distributed CRC interleaver, and the second bit sequence b = a·G Dcrc2 .

[0182] 503. The sender performs polar encoding on the second bit sequence to obtain a third bit sequence.

[0183] 504. The sender performs some or all of the steps including but not limited to rate matching, modulation, analog-to-digital conversion, frequency conversion, etc. on the third bit sequence and then sends the resulting sequence to be decoded.

[0184] 505. The receiver decodes the sequence to be decoded to obtain a sequence to be verified.

[0185] 506. The receiver performs CRC check on the sequence to be verified.

[0186] 507. In the case where the sequence to be verified passes the check, the receiver uses the first distributed CRC deinterleaver to deinterleave the second bit sequence to obtain the above K1 information bits.

[0187] Steps 503 to 507 can refer to Figure 4 Steps 403 to 407 in. In a possible implementation, in the case where the sequence to be verified fails the check, the decoding is terminated prematurely.

[0188] In the embodiments of the present application, K1 information bits are CRC-encoded based on a CRC generation polynomial to obtain a first bit sequence, and the number of CRC check bits is less than 24. The above first bit sequence is interleaved using a first distributed CRC interleaver. The first distributed CRC deinterleaver supports DCRC encoding for shorter payloads and can reduce decoding power consumption.

[0189] The following describes an example of the CRC generation polynomial and an example of the first distributed CRC interleaver obtained based on the CRC generation polynomial.

[0190] Example 1, L is equal to 6, the above K2 is equal to 70, the above CRC generation polynomial is D^6 + D^5 + 1, and the values of the elements in the first distributed CRC interleaver obtained based on the CRC generation polynomial are as follows in sequence:

[0191] 0 2 3 4 5 6 7 13 18 19 23 25 28 29 30 31 33 37 38 39 42 45 47 48 50 51 52 54 55 58 59 61 63 65 66 67 68 69 70 1 8 14 20 24 26 32 34 40 43 46 49 53 56 60 62 64 71 9 15 21 27 35 41 44 57 72 10 16 22 36 73 11 17 74 12 75. An example of the DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc is Figure 6 the upper triangular matrix shown. Another example of the DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc is Figure 7 the non-upper triangular matrix shown.

[0192] The first distributed CRC interleaver in Example 1 is obtained based on D^6 + D^5 + 1. The manner of obtaining the first distributed CRC interleaver in Example 1 based on D^6 + D^5 + 1 can be similar to the manner in the example of obtaining the first distributed CRC interleaver based on the CRC generation polynomial in step 502, which will not be elaborated here.

[0193] Example 1', L is equal to 6, the above K2 is equal to 70, the above CRC generation polynomial is D^6 + D^5 + 1, and the values of the elements in the first distributed CRC interleaver obtained based on the CRC generation polynomial are as follows in sequence:

[0194] 0 1 2 8 13 14 18 20 23 24 25 26 28 32 33 34 37 40 42 43 45 46 47 49 50 53 54 56 58 60 61 62 63 64 65 71 3 9 15 19 21 27 29 35 38 41 44 48 51 55 57 59 66 72 4 10 16 22 30 36 39 52 67 73 5 11 17 31 68 74 6 7 69 70 12 75。

[0195] The first distributed CRC interleaver in Example 1' is obtained based on D^6 + D^5 + 1. The way to obtain the first distributed CRC interleaver in Example 1' based on D^6 + D^5 + 1 can be similar to the way in one of the examples of obtaining the first distributed CRC interleaver based on an L-length CRC generating polynomial in step 402, which will not be elaborated here. The first distributed CRC interleaver in Example 1 and the first distributed CRC interleaver in Example 1' are obtained based on the same CRC generating polynomial. The difference is that when obtaining the first distributed CRC interleaver in Example 1 based on D^6 + D^5 + 1, the positions of the message bits associated with each check column and the positions of each check column are packed together in the order of the sequence of the positions of each check column; when obtaining the first distributed CRC interleaver in Example 1' based on D^6 + D^5 + 1, the positions of the message bits associated with each check column and the positions of each check column are packed together in ascending order of the maximum value in the element sequence corresponding to each check column (i.e., the position of the last message bit checked by each check column). By comparing Example 1 and Example 1', it can be found that the 2nd check position 71 in the first distributed CRC interleaver in Example 1 becomes the 1st check position in the first distributed CRC interleaver in Example 1'; the 3rd check position 72 in the first distributed CRC interleaver in Example 1 becomes the 2nd check position in the first distributed CRC interleaver in Example 1'; the 4th check position 73 in the first distributed CRC interleaver in Example 1 becomes the 3rd check position in the first distributed CRC interleaver in Example 1'; the 5th check position 74 in the first distributed CRC interleaver in Example 1 becomes the 4th check position in the first distributed CRC interleaver in Example 1'; the 1st check position 70 in the first distributed CRC interleaver in Example 1 becomes the 5th check position in the first distributed CRC interleaver in Example 1'; the 6th check position in the first distributed CRC interleaver in Example 1 is still the 6th check position in the first distributed CRC interleaver in Example 1'. It should be noted that the message positions checked by each check position also change together with the change of the check position.

[0196] In this application, for any CRC generation polynomial, a corresponding distributed CRC interleaver can be generated in a manner similar to the example in step 502 for obtaining the first distributed CRC interleaver based on the CRC generation polynomial; or in a manner similar to the example in step 402 for obtaining the first distributed CRC interleaver based on the CRC generation polynomial of length L, a corresponding distributed CRC interleaver can be generated.

[0197] Example 2, where the above L is equal to 6, the above K2 is equal to 70, the above CRC generation polynomial is D^6 + D^5 + D^4 + D^3 + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence:

[0198] 1 4 5 6 9 10 16 19 20 21 24 25 31 34 35 36 39 40 46 49 50 51 54 55 61 64 65 66 69 70 2 7 11 17 22 26 32 37 41 47 52 56 62 67 71 3 8 12 18 23 27 33 38 42 48 53 57 63 68 72 13 28 43 58 73 14 29 44 59 74 0 15 30 45 60 75. The DCRC coding matrix G corresponding to the first distributed CRC interleaver Dcrc An example of Figure 8 is the upper triangular matrix shown. Figure 8 This is an example of the DCRC coding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of this application. If the payload bits are K = 50 bits a = a0, a1, a2,..., a49, and the sequence after DCRC encoding of a is a bit sequence b = b0, b1, b2,..., b55 of length K + L = 50 + 6 = 56, then b = a·G Dcrc , G Dcrc can be Figure 8 a sub - matrix of the upper triangular matrix shown, or it can also be Figure 9 a sub - matrix of a non - upper triangular matrix. Figure 9 This is an example of the DCRC coding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of this application. If a non - upper triangular matrix is used, the extraction method of the sub - matrix is to extract the last K rows of the non - upper triangular matrix and skip the first 20 rows without extraction. If a non - upper triangular matrix is used for DCRC encoding, the extraction method of the sub - matrix is to skip the elements less than 20 in the DCRC interleaver, select the remaining elements with values greater than 20 as row labels, and extract these rows from the upper triangular matrix to form a 50 - row and 56 - column matrix for DCRC encoding.

[0199] Example 3, where the above L is equal to 6, the above K2 is equal to 70, the above CRC generating polynomial is D^6 + D^4 + D^3 + D + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence:

[0200] 0 1 2 3 4 5 7 13 14 15 20 23 27 28 30 31 34 36 37 39 41 42 43 45 46 47 48 51 52 56 58 60 63 64 65 66 67 68 70 6 8 16 21 24 29 32 35 38 40 44 49 53 57 59 61 69 71 9 17 22 25 33 50 54 62 72 10 18 26 55 73 11 19 74 12 75. An example of the DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc is Figure 10 the upper triangular matrix shown. Figure 10 This is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application. In this article, nz (none zero) in the drawings represents the number of non-zero elements.

[0201] Example 4, where the above L is equal to 6, the above K2 is equal to 70, the above CRC generating polynomial is D^6 + D^3 + D^2 + D + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence:

[0202] 1 2 5 6 7 10 16 17 20 21 22 25 31 32 35 36 37 40 46 47 50 51 52 55 61 62 65 66 67 70 3 8 11 18 23 26 33 38 41 48 53 56 63 68 71 4 9 12 19 24 27 34 39 42 49 54 57 64 69 72 13 28 43 58 73 14 29 44 59 74 0 15 30 45 60 75. An example of the DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc is Figure 11 the upper triangular matrix shown. Figure 11 This is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application.

[0203] Example 5, where the above L is equal to 6, the above K2 is equal to 70, the above CRC generating polynomial is D^6 + D^5 + D^2 + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence:

[0204] 0 1 2 4 5 6 7 13 15 17 18 21 22 23 25 26 27 28 34 36 38 39 42 43 44 46 47 48 49 55 57 59 60 63 64 65 67 68 69 70 3 8 14 16 19 24 29 35 37 40 45 50 56 58 61 66 71 9 20 30 41 51 62 72 10 31 52 73 11 32 53 74 12 33 54 75. An example of the DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc is Figure 12 the upper triangular matrix shown. Figure 12 This is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiment of the present application.

[0205] Example 6, where the above L is equal to 6, the above K2 is equal to 70, the above CRC generating polynomial is D^6 + D^5 + D^4 + D^2 + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence:

[0206] 80 1 4 6 7 13 15 18 21 22 25 27 28 34 36 39 42 43 46 48 49 55 57 60 63 64 67 69 70 2 5 8 14 16 19 23 26 29 35 37 40 44 47 50 56 58 61 65 68 71 39 17 20 24 30 38 41 45 51 59 62 66 72 10 31 52 73 11 32 53 74 12 33 54 75. An example of the DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc is Figure 13 the upper triangular matrix shown. Figure 13 This is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiment of the present application.

[0207] Example 7, where the above L is equal to 6, the above K2 is equal to 70, the above CRC generating polynomial is D^6 + D^3 + D^2 + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence:

[0208] 0 4 5 8 14 16 17 18 20 21 23 25 28 29 30 31 35 36 39 45 47 48 49 51 52 54 56 59 60 61 62 66 67 70 1 6 9 15 19 22 24 26 32 37 40 46 50 53 55 57 63 68 71 2 7 10 27 33 38 41 58 64 69 72 3 11 34 42 65 73 12 43 74 13 44 75. The DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc An example of Figure 14 The upper triangular matrix shown in the figure Figure 14 This is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application

[0209] Example 8, where the above L is equal to 6, the above K2 is equal to 70, the above CRC generating polynomial is D^6 + D^5 + D^3 + D^2 + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence

[0210] 0 5 6 7 13 15 16 17 18 19 20 23 25 27 31 32 35 36 37 38 40 41 42 44 46 47 49 52 53 55 56 60 63 68 69 70 1 8 14 21 24 26 28 33 39 43 45 48 50 54 57 61 64 71 2 9 22 29 34 51 58 62 65 72 3 10 30 59 66 73 4 11 67 74 12 75. The DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc An example of Figure 15 The upper triangular matrix shown in the figure Figure 15 This is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application

[0211] Example 9, where the above L is equal to 6, the above K2 is equal to 70, the above CRC generating polynomial is D^6 + D^5 + D^4 + D^3 + D^2 + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence

[0212] 0 2 5 9 10 16 18 19 21 22 23 26 27 28 29 30 32 35 39 40 46 48 49 51 52 53 56 57 58 59 60 62 65 69 70 1 3 6 11 17 20 24 31 33 36 41 47 50 54 61 63 66 71 4 7 12 25 34 37 42 55 64 67 72 8 13 38 43 68 73 14 44 74 15 45 75. An example of the DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc is as follows Figure 16 the upper triangular matrix shown. Figure 16 This is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in the embodiments of the present application.

[0213] Example 10, where the above L is equal to 6, the above K2 is equal to 70, the above CRC generating polynomial is D^6 + D^5 + D^4 + D^3 + D + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence:

[0214] 1 2 4 7 8 14 15 16 19 23 25 27 28 29 30 32 33 35 38 39 45 46 47 50 54 56 58 59 60 61 63 64 66 69 70 0 3 5 9 17 20 24 26 31 34 36 40 48 51 55 57 62 65 67 71 6 10 18 21 37 41 49 52 68 72 11 22 42 53 73 12 43 74 13 44 75. An example of the DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc is as follows Figure 17 the upper triangular matrix shown. Figure 17 This is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided in the embodiments of the present application.

[0215] Example 11, where the above L is equal to 6, the above K2 is equal to 70, the above CRC generating polynomial is D^6 + D^4 + D^2 + D + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence:

[0216] 2 5 7 13 14 16 19 20 23 26 28 34 35 37 40 41 44 47 49 55 56 58 61 62 65 68 70 0 3 6 8 15 17 21 24 27 29 36 38 42 45 48 50 57 59 63 66 69 71 1 4 9 18 22 25 30 39 43 46 51 60 64 67 72 10 31 52 73 11 32 53 74 12 33 54 75. The DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc is exemplified by Figure 18 the upper triangular matrix shown Figure 18 which is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application

[0217] Example 12, where the above L is equal to 11, the above K2 is equal to 70, the above CRC generating polynomial is D^11 + D^10 + D^9 + D^5 + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence

[0218] 0 1 2 3 4 6 7 10 13 15 19 21 22 23 24 25 27 30 33 34 35 37 41 44 46 47 48 49 50 55 57 58 59 60 61 62 63 66 67 69 70 5 8 11 14 16 20 26 28 31 36 38 42 45 51 56 64 68 71 9 12 17 29 32 39 43 52 65 72 18 40 53 73 54 74 75 76 77 78 79 80

[0219] The first distributed CRC interleaver in Example 12 is obtained based on D^11 + D^10 + D^9 + D^5 + 1. The method of obtaining the first distributed CRC interleaver in Example 12 based on D^11 + D^10 + D^9 + D^5 + 1 can be similar to the method in the example of obtaining the first distributed CRC interleaver based on the CRC generating polynomial in step 502, which will not be elaborated here

[0220] The DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc can have the following two forms. One is the upper triangular form G Dcrc1 i.e., for G crcBoth the K rows and the (K + L) columns are subjected to DCRC interleaving. Among them, the interleaver used for interleaving the K rows is an interleaver formed by nestedly reading K elements with values less than K from the DCRC interleaver in natural order; the interleaver used for interleaving the (K + L) columns is the above-mentioned DCRC interleaver with a length of (K + L). Another form of the DCRC coding matrix is also a matrix with K rows and (K + L) columns, but it is not upper triangular, that is, G Dcrc2 , and its generation method is to only interleave the (K + L) columns of G crc , without interleaving the K rows of the matrix. If the payload bits are K = 70 bits a = a0, a1, a2, …, a69, and the sequence after DCRC coding is a bit sequence b = b0, b1, b2, …, b80 with a length of K + L = 70 + 11 = 81, then b = a·G Dcrc1 or b = a·G Dcrc2 . G Dcrc1 is the Figure 19 upper triangular matrix shown. Figure 19 This is an example of the DCRC coding matrix corresponding to a first distributed CRC interleaver provided by an embodiment of the present application. G Dcrc2 is the Figure 20 non-upper triangular matrix shown below, that is, only the columns of G crc are interleaved. Figure 20 This is an example of the DCRC coding matrix corresponding to another first distributed CRC interleaver provided by an embodiment of the present application. G Dcrc2 The advantage is that it is more convenient to nestedly read the DCRC coding matrix. For a payload with K < 70, only the first (70 - K) rows of the matrix need to be skipped, and the last K rows of the matrix can be used for DCRC coding.

[0221] Example 12’, where the above-mentioned L is equal to 11, the above-mentioned K2 is equal to 70, the above-mentioned CRC generating polynomial is D^11 + D^10 + D^9 + D^5 + 1, and the values of the elements in the above-mentioned first distributed CRC interleaver are as follows in sequence:

[0222] 1 2 5 8 10 14 16 17 18 19 20 22 25 28 29 30 32 36 39 41 42 43 44 4550 52 53 54 55 56 57 58 61 62 64 65 76 0 3 4 9 11 12 13 23 24 31 33 35 38 4849 59 60 63 66 72 6 15 21 26 37 40 46 51 77 34 67 737 27 47 78 68 74 79 69 7071 75 80.

[0223] The first distributed CRC interleaver in Example 12' is obtained based on D^11+D^10+D^9+D^5+1. The method of obtaining the first distributed CRC interleaver in Example 12' based on D^11+D^10+D^9+D^5+1 can be similar to the method in an example of obtaining the first distributed CRC interleaver based on an L-length CRC generating polynomial in step 402, which will not be elaborated here. The first distributed CRC interleaver in Example 12 and the first distributed CRC interleaver in Example 12' are obtained based on the same CRC generating polynomial. The difference is that when obtaining the first distributed CRC interleaver in Example 12 based on D^11+D^10+D^9+D^5+1, the positions of the message bits associated with each check column and the positions of each check column are packaged together in sequence according to the order of the positions of each check column; when obtaining the first distributed CRC interleaver in Example 12' based on D^11+D^10+D^9+D^5+1, the positions of the message bits associated with each check column and the positions of each check column are packaged together in sequence according to the order from small to large of the maximum value in the element sequence corresponding to each check column (i.e., the position of the last message bit checked by each check column).By comparing Example 12 and Example 12', it can be found that the 7th check position 76 of the first distributed CRC interleaver in Example 12 becomes the first check position of the first distributed CRC interleaver in Example 12'; the 3rd check position 72 of the first distributed CRC interleaver in Example 12 becomes the 2nd check position of the first distributed CRC interleaver in Example 12'; the 8th check position 77 of the first distributed CRC interleaver in Example 12 becomes the 3rd check position of the first distributed CRC interleaver in Example 12'; the 4th check position 73 of the first distributed CRC interleaver in Example 12 remains the 4th check position of the first distributed CRC interleaver in Example 12'; the 9th check position 78 of the first distributed CRC interleaver in Example 12 becomes the 5th check position of the first distributed CRC interleaver in Example 12'; the 5th check position 74 of the first distributed CRC interleaver in Example 12 becomes the 6th check position of the first distributed CRC interleaver in Example 12'; the 10th check position 79 of the first distributed CRC interleaver in Example 12 becomes the 7th check position of the first distributed CRC interleaver in Example 12'; the 1st check position 70 of the first distributed CRC interleaver in Example 12 becomes the 8th check position of the first distributed CRC interleaver in Example 12'; the 2nd check position 71 of the first distributed CRC interleaver in Example 12 becomes the 9th check position of the first distributed CRC interleaver in Example 12'; the 6th check position 75 of the first distributed CRC interleaver in Example 12 becomes the 10th check position of the first distributed CRC interleaver in Example 12'; the 11th check position 80 of the first distributed CRC interleaver in Example 12 remains the 11th check position of the first distributed CRC interleaver in Example 12'; and the message positions checked by each check position also change together with the change of the check position.

[0224] Example 13, where the above L is equal to 11, the above K2 is equal to 70, the above CRC generating polynomial is D^11 + D^7 + D^6 + D^2 + 1, and the values of the elements in the above first distributed CRC interleaver are as follows:

[0225] 1 5 11 13 15 16 19 20 23 24 29 30 31 32 33 35 37 39 41 43 47 52 53 54 55 56 57 58 59 60 61 62 65 66 70 2 6 12 14 17 21 25 34 36 38 40 42 44 48 63 67 71 3 7 18 22 26 45 49 64 68 72 0 4 8 27 46 50 69 73 9 28 51 74 10 75 76 77 78 79 80. The DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc An example of Figure 21 The upper triangular matrix shown in Figure 21 is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application

[0226] Example 14, where the above L is equal to 11, the above K2 is equal to 70, the above CRC generating polynomial is D^11 + D^10 + D^9 + D^6 + D^4 + D^2 + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence

[0227] 0 1 5 6 9 10 12 13 14 16 19 21 22 23 24 25 26 29 34 36 37 38 41 43 47 49 50 51 52 54 61 63 64 65 66 67 69 70 2 7 11 15 17 20 27 30 35 39 42 44 48 53 55 62 68 71 3 8 18 28 31 40 45 56 72 4 32 46 57 73 33 58 74 59 75 60 76 77 78 79 80. The DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc An example of Figure 22 The upper triangular matrix shown in Figure 22 is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application

[0228] Example 15, where the above L is equal to 11, the above K2 is equal to 70, the above CRC generating polynomial is D^11 + D^10 + D^9 + D^7 + D^5 + D + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence

[0229] 0 5 7 8 11 12 16 18 19 21 22 24 25 27 30 34 38 39 46 50 53 54 55 58 59 63 64 67 69 70 1 6 9 13 17 20 23 26 28 31 35 40 47 51 56 60 65 68 71 2 10 14 29 32 36 41 48 52 57 61 66 72 3 15 33 37 42 49 62 73 4 43 74 44 75 45 76 77 78 79 80. The DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc One example of Figure 23 is the upper triangular matrix shown in Figure 23 This is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application

[0230] Example 16, where the above L is equal to 11, the above K2 is equal to 70, the above CRC generating polynomial is D^11 + D^9 + D^8 + D^6 + D^5 + D + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence

[0231] 0 10 15 18 20 21 22 23 24 27 29 31 32 35 36 38 41 42 44 46 47 49 53 54 55 58 59 63 64 65 66 67 68 70 1 11 16 19 25 28 30 33 37 39 43 45 48 50 56 60 69 71 2 12 17 26 34 40 51 57 61 72 3 13 52 62 73 4 14 74 5 75 6 76 7 77 8 78 9 79 80. The DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc One example of Figure 24 is the upper triangular matrix shown in Figure 24 This is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application

[0232] Example 17, where the above L is equal to 11, the above K2 is equal to 70, the above CRC generating polynomial is D^11 + D^10 + D^9 + D^8 + D^7 + D^5 + D^4 + D + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence

[0233] 1 2 4 5 8 9 11 13 17 18 20 24 27 28 30 32 33 36 39 40 41 42 43 44 47 49 52 53 54 55 61 62 63 65 69 70 3 6 10 12 14 19 21 25 29 31 34 37 45 48 50 56 64 66 71 7 15 22 26 35 38 46 51 57 67 72 0 16 23 58 68 73 59 74 60 75 76 77 78 79 80. The DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc An example of Figure 25 is the upper triangular matrix shown Figure 25 This is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application

[0234] Example 18, where the above L is equal to 11, the above K2 is equal to 70, the above CRC generating polynomial is D^11 + D^10 + D^3 + D + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence

[0235] 2 3 4 5 9 16 17 18 19 20 22 25 28 29 30 31 32 33 38 39 40 42 44 47 50 52 53 56 58 60 61 63 64 65 66 67 68 69 70 0 6 10 21 23 26 34 41 43 45 48 51 54 57 59 62 71 1 7 11 24 27 35 46 49 55 72 8 12 36 73 13 37 74 14 75 15 76 77 78 79 80. The DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc An example of Figure 26 is the upper triangular matrix shown Figure 26 This is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application

[0236] Example 19, where the above L is equal to 11, the above K2 is equal to 70, the above CRC generating polynomial is D^11 + D^5 + D^3 + D + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence

[0237] 2 5 13 14 15 16 20 23 27 30 32 34 35 36 37 38 39 40 43 47 48 52 54 58 59 60 62 64 70 0 3 6 17 21 24 28 31 33 41 44 49 53 55 61 63 65 71 1 4 7 18 22 25 29 42 45 50 56 66 72 8 19 26 46 51 57 67 73 9 68 74 10 69 75 11 76 12 77 78 79 80. The DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc An example of Figure 27 The upper triangular matrix shown in Figure 27 This is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application

[0238] Example 20, where the above L is equal to 11, the above K2 is equal to 70, the above CRC generating polynomial is D^11 + D^10 + D^9 + D^8 + D^6 + D^5 + D^3 + D + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence

[0239] 0 1 3 4 5 8 9 10 13 22 24 28 33 34 39 41 46 47 49 53 54 56 57 60 61 62 63 64 66 69 70 2 6 11 14 23 25 29 35 40 42 48 50 55 58 65 67 71 7 12 15 26 30 36 43 51 59 68 72 16 27 31 37 44 52 73 17 32 38 45 74 18 75 19 76 20 77 21 78 79 80. The DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc An example of Figure 28 The upper triangular matrix shown in Figure 28 This is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application

[0240] Example 21, where the above L is equal to 11, the above K2 is equal to 70, the above CRC generating polynomial is D^11 + D^10 + D^8 + D^7 + D^6 + D^5 + D^3 + D + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence

[0241] 0 3 5 6 7 8 11 13 15 17 19 21 22 26 27 30 31 32 33 35 36 41 42 43 47 49 53 61 62 65 68 69 70 1 4 9 12 14 16 18 20 23 28 34 37 44 48 50 54 63 66 71 2 10 24 29 38 45 51 55 64 67 72 25 39 46 52 56 73 40 57 74 58 75 59 76 60 77 78 79 80. The DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc An example of Figure 29 is the upper triangular matrix shown Figure 29 This is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application

[0242] Example 22, where the above L is equal to 11, the above K2 is equal to 70, the above CRC generating polynomial is D^11 + D^9 + D^7 + D^6 + D^5 + D^4 + D^3 + D + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence

[0243] 1 4 6 9 12 14 15 16 23 28 30 34 35 37 38 39 41 42 43 45 46 47 48 51 52 53 56 60 61 63 65 68 70 2 5 7 10 13 17 24 29 31 36 40 44 49 54 57 62 64 66 69 71 0 3 8 11 18 25 32 50 55 58 67 72 19 26 33 59 73 20 27 74 21 75 22 76 77 78 79 80. The DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc An example of Figure 30 is the upper triangular matrix shown Figure 30 This is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application

[0244] Example 23, where the above L is equal to 11, the above K2 is equal to 70, the above CRC generating polynomial is D^11 + D^10 + D^9 + D^7 + D^6 + D^3 + D^2 + D + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence

[0245] 2 3 6 8 9 11 12 13 14 21 24 26 27 28 29 30 31 32 34 36 37 38 39 40 41 47 48 49 53 54 57 61 65 67 69 70 0 4 7 10 15 22 25 33 35 42 50 55 58 62 66 68 71 1 5 16 23 43 51 56 59 63 72 17 44 52 60 64 73 18 45 74 19 46 75 20 76 77 78 79 80. The DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc is exemplified by Figure 31 the upper triangular matrix shown. Figure 31 This is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application.

[0246] Example 24, where the above L is equal to 11, the above K2 is equal to 70, the above CRC generating polynomial is D^11 + D^8 + D^6 + D^5 + D^4 + D^3 + D^2 + D + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence:

[0247] 2 3 4 5 6 7 12 14 16 20 22 23 26 31 34 37 39 40 41 44 46 49 51 52 53 54 58 62 63 65 67 70 0 8 13 15 17 21 24 27 32 35 38 42 45 47 50 55 59 64 66 68 71 1 9 18 25 28 33 36 43 48 56 60 69 72 10 19 29 57 61 73 11 30 74 75 76 77 78 79 80. The DCRC encoding matrix G corresponding to the first distributed CRC interleaver Dcrc is exemplified by Figure 32 the upper triangular matrix shown. Figure 32 This is an example of the DCRC encoding matrix corresponding to another first distributed CRC interleaver provided by the embodiments of the present application.

[0248] Example 25, where the above L is equal to 16, the above K2 is equal to 100, the above CRC generating polynomial is D^16 + D^12 + D^5 + 1, and the values of the elements in the above first distributed CRC interleaver are as follows in sequence:

[0249] 2 4 5 12 14 16 18 19 20 23 25 26 28 30 33 34 35 36 37 42 44 45 48 49 51 52 58 65 67 68 72 73 74 78 80 81 88 89 92 96 100 3 6 13 15 17 21 24 27 29 31 38 43 46 50 53 59 66 69 75 79 82 90 93 97 101 7 22 32 39 47 54 60 70 76 83 91 94 98 102 8 40 55 61 71 77 84 95 99 103 0 9 41 56 62 85 104 1 10 57 63 86 105 11 64 87 106 107 108 109 110 111 112 113 114 115。

[0250] In one possible implementation, the channel coding method adopted by the low-power device can be only one. For example, the data channel, broadcast channel, and control channel of passive IoT all adopt the NR control channel coding, that is, the channel coding method provided in this application, but the maximum and minimum mother code lengths are modified to further reduce power consumption. For example, the minimum mother code length N m can be less than 32, such as N m = 16; the maximum mother code length N max can be reduced to the following values {32, 64, 128, 256}. Figure 33 Another flowchart of the coding method provided by the embodiment of this application. Figure 33 The method flow in Figure 4 is a possible implementation manner of the method described. Figure 33 The method flow in Figure 33 can be applied to a low-power scenario. As

[0251] 3301. The sending end performs CRC encoding on K1 information bits based on the CRC generating polynomial to obtain a first bit sequence.

[0252] 3302. The sending end interleaves the first bit sequence using a first distributed CRC interleaver to obtain a second bit sequence.

[0253] 3303. The sending end performs polarization coding on the second bit sequence to obtain a third bit sequence.

[0254] Exemplarily, the minimum mother code length N m can be less than 32, such as N m = 16; the maximum mother code length Nmax It can be reduced to the following values: {32, 64, 128, 256}.

[0255] 3304. The first sequence to be decoded is obtained after the transmitting end performs some or all of the steps including but not limited to rate matching, modulation, analog-to-digital conversion, frequency conversion, etc. on the third bit sequence and then transmits it.

[0256] Correspondingly, the receiving end receives the signal carrying the first sequence to be decoded from the transmitting end.

[0257] In a possible implementation, in step 3304, the first sequence to be decoded obtained by the transmitting end can be a transmitted data signal, that is, a data signal for the receiving end to decode K1 information bits. Steps 3301 to 3304 include the process of the transmitting end performing channel coding on the K1 information bits that need to be transmitted through the data channel.

[0258] In a possible implementation, in step 3304, the first sequence to be decoded obtained by the transmitting end can be a transmitted broadcast signal, that is, a broadcast signal for the receiving end to decode K1 information bits. Steps 3301 to 3304 include the process of the transmitting end performing channel coding on the K1 information bits that need to be transmitted through the broadcast channel.

[0259] 3305. The receiving end decodes the first sequence to be decoded to obtain the first sequence to be verified.

[0260] The receiving end can obtain the first sequence to be decoded based on the signal carrying the first sequence to be decoded from the transmitting end, which is not limited in this application.

[0261] 3306. The receiving end performs CRC check on the first sequence to be verified.

[0262] 3307. When the first sequence to be verified passes the check, the receiving end uses the first distributed CRC deinterleaver to deinterleave the second bit sequence to obtain the above K1 information bits.

[0263] When the first sequence to be verified passes the check, the sequence to be verified is the second bit sequence. Steps 3301 to 3307 can refer to Figure 4 Steps 401 to 407 in. In a possible implementation, when the first sequence to be verified fails the check, the decoding terminates prematurely.

[0264] 3308. The transmitting end performs CRC coding on K3 control bits based on the CRC generating polynomial to obtain the fourth bit sequence.

[0265] K3 is an integer greater than 0.

[0266] 3309. The sender uses a first distributed CRC interleaver to interleave the fourth bit sequence to obtain a fifth bit sequence.

[0267] 3310. The sender performs polar coding on the fifth bit sequence to obtain a sixth bit sequence.

[0268] 3311. The sender performs some or all of the steps including but not limited to rate matching, modulation, analog-to-digital conversion, frequency conversion, etc. on the sixth bit sequence and then sends the obtained second sequence to be decoded.

[0269] Correspondingly, the receiver receives the signal carrying the second sequence to be decoded from the sender.

[0270] In step 3311, the second sequence to be decoded sent by the sender may be a transmission control signal, that is, a control signal for the receiver to decode K3 control bits. Steps 3308 to 3311 include the process of the sender performing channel coding on the K3 control bits that need to be sent through the control channel. Exemplarily, the second sequence to be decoded sent by the sender is carried on the LP-WUS.

[0271] 3312. The receiver decodes the second sequence to be decoded to obtain a second sequence to be verified.

[0272] 3313. The receiver performs CRC verification on the second sequence to be verified.

[0273] 3314. When the second sequence to be verified passes the verification, the receiver uses a first distributed CRC deinterleaver to deinterleave the fifth bit sequence to obtain the above K3 control bits.

[0274] When the second sequence to be verified passes the verification, the sequence to be verified is the fifth bit sequence. Steps 3308 to 3314 can refer to Figure 4 Steps 401 to 407 in. The order of steps 3301 to 3307 and steps 3308 to 3314 is not limited. In one possible implementation, when the second sequence to be verified does not pass the verification, the decoding is terminated in advance.

[0275] In the embodiments of the present application, the control channel and the data channel share the NR control channel coding, that is, the channel coding method provided by the present application is friendly and compatible with the NR standard, and the complexity of encoding and decoding is reduced.

[0276] Figure 34 It is a flowchart of another coding method provided by the embodiments of the present application. Figure 34 The method flow in is Figure 4 A possible implementation manner of the method described. Figure 34 The method flow in can be applied to a low-power scenario. Such asFigure 34 As shown, the method includes:

[0277] 3401. The sender performs CRC encoding on K3 control bits based on a CRC generating polynomial to obtain a fourth bit sequence.

[0278] K3 is an integer greater than 0.

[0279] 3402. The sender interleaves the fourth bit sequence using a first distributed CRC interleaver to obtain a fifth bit sequence.

[0280] 3403. The sender performs polarization encoding on the fifth bit sequence to obtain a sixth bit sequence.

[0281] 3404. The sender sends a low-power wake-up signal to the receiver, where the low-power wake-up signal carries a second sequence to be decoded obtained after the sender performs some or all of the steps including but not limited to rate matching, modulation, analog-to-digital conversion, frequency conversion, etc. on the sixth bit sequence.

[0282] Correspondingly, the receiver receives the low-power wake-up signal from the sender.

[0283] The low-power wake-up signal is used to wake up the main receiver of the receiver. The receiver may include, for example, Figure 1 the above-mentioned main receiver and low-power wake-up receiver.

[0284] 3405. The receiver decodes the second sequence to be decoded to obtain a second sequence to be verified.

[0285] 3406. The receiver performs CRC verification on the second sequence to be verified.

[0286] 3407. When the second sequence to be verified passes the verification, the receiver deinterleaves the fifth bit sequence using a first distributed CRC deinterleaver to obtain the above-mentioned K3 control bits.

[0287] Steps 3401 to 3407 can refer to Figure 4 Steps 401 to 407 therein. In a possible implementation, when the second sequence to be verified fails the verification, the decoding is terminated prematurely.

[0288] 3408. The sender performs CRC encoding on K1 information bits based on a CRC generating polynomial to obtain a first bit sequence.

[0289] 3409. The sender interleaves the first bit sequence using a first distributed CRC interleaver to obtain a second bit sequence.

[0290] 3410. The sender performs polarization encoding on the second bit sequence to obtain a third bit sequence.

[0291] 3411. The transmitting end sends an NR signal to the receiving end, where the NR signal carries a first sequence to be decoded obtained after the transmitting end performs some or all of the steps including but not limited to rate matching, modulation, analog-to-digital conversion, frequency conversion, etc. on the third bit sequence.

[0292] Correspondingly, the receiving end receives the NR signal from the transmitting end.

[0293] In a possible implementation, in step 3411, the first sequence to be decoded obtained by the transmitting end for sending can be a transmitted data signal, that is, a data signal for the receiving end to decode and obtain K1 information bits. Steps 3408 to 3411 include a process in which the transmitting end performs channel coding on the K1 information bits that need to be sent through the data channel.

[0294] In a possible implementation, in step 3411, the first sequence to be decoded obtained by the transmitting end for sending can be a transmitted broadcast signal, that is, a broadcast signal for the receiving end to decode and obtain K1 information bits. Steps 3408 to 3411 include a process in which the transmitting end performs channel coding on the K1 information bits that need to be sent through the broadcast channel.

[0295] 3412. The receiving end decodes the first sequence to be decoded to obtain a first sequence to be verified.

[0296] 3413. The receiving end performs CRC check on the first sequence to be verified.

[0297] 3414. When the first sequence to be verified passes the check, the receiving end uses a first distributed CRC deinterleaver to deinterleave the second bit sequence to obtain the above-mentioned K1 information bits.

[0298] Steps 3408 to 3414 can refer to Figure 4 Steps 401 to 407 therein. In a possible implementation, when the first sequence to be verified fails the check, the decoding is terminated in advance.

[0299] In the embodiments of the present application, the low-power wake-up signal and the NR signal share the NR control channel coding, that is, the channel coding method provided by the present application is friendly and compatible with the NR standard, and the complexity of encoding and decoding is reduced.

[0300] Next, the structure of the transmitting end that can implement the encoding method provided by the embodiments of the present application and the structure of the receiving end that can implement the decoding method provided by the embodiments of the present application are introduced in conjunction with the accompanying drawings. In the present application, both the transmitting end and the receiving end can be communication devices. The following only briefly describes the case where the transmitting end and the receiving end are communication devices. For the implementation details of the solution, reference can be made to the description of the method embodiments above, and details will not be repeated below.

[0301] Figure 35 FIG. 3500 is a schematic structural diagram of a communication device 3500 provided by an embodiment of the present application. The communication device 3500 can correspondingly implement the functions or steps implemented by the sending end in the above-mentioned various method embodiments, or can correspondingly implement the functions or steps implemented by the receiving end in the above-mentioned various method embodiments. The communication device may include a processing module 3510 and a transceiver module 3520. In a possible implementation manner, a storage unit may further be included, and the storage unit may be used to store instructions (codes or programs) and / or data. The processing module 3510 and the transceiver module 3520 may be coupled to the storage unit. For example, the processing module 3510 may read the instructions (codes or programs) and / or data in the storage unit to implement the corresponding method. The above-mentioned various units may be independently provided, or may be partially or fully integrated. For example, the transceiver module 3520 may include a sending module and a receiving module. The sending module may be a transmitter, and the receiving module may be a receiver. The entity corresponding to the transceiver module 3520 may be a transceiver circuit, such as a transceiver or a communication interface.

[0302] In some possible implementation manners, the communication device 3500 can correspondingly implement the behaviors and functions of the sending end in the above-mentioned method embodiments. For example, the communication device 3500 may be the sending end, or may be a component (such as a chip or a circuit) applied to the sending end. The transceiver module 3520 may be used to perform, for example, Figure 3 , Figure 4 , Figure 33 , or Figure 34 all the receiving or sending operations performed by the sending end in the embodiments of Figure 3 , Figure 4 , Figure 33 , or Figure 34 . The processing module 3510 may be used to perform, for example,

[0303] all the operations other than the receiving and sending operations performed by the sending end in the embodiments of Figure 3 , Figure 4 , Figure 33 , or Figure 34 . Figure 3 , Figure 4 , Figure 33 , or Figure 34 .

[0304] Figure 36 This is a schematic structural diagram of another device 360 provided by an embodiment of the present application. Figure 36 The device in [description] can be the above-mentioned sending end or a chip for the above-mentioned sending end, or the above-mentioned receiving end or a chip in the above-mentioned receiving end. As Figure 36 shown, the device 360 includes a processing circuit 3610 and a transceiver circuit 3620.

[0305] In some embodiments of the present application, the processing circuit 3610 and the transceiver circuit 3620 can be used to perform the functions or operations executed by the sending end, etc. The transceiver circuit 3620 is, for example, used to perform Figure 3 , Figure 4 , Figure 33 , or Figure 34 all the receiving or sending operations executed by the sending end in the embodiment of [description]. The processing circuit 3610 is, for example, used to perform Figure 3 , Figure 4 , Figure 33 , or Figure 34 all the operations other than the receiving and sending operations executed by the sending end in the embodiment of [description].

[0306] In some embodiments of the present application, the processing circuit 3610 and the transceiver circuit 3620 can be used to perform the functions or operations executed by the receiving end, etc. The transceiver circuit 3620 is, for example, used to perform Figure 3 , Figure 4 , Figure 33 , or Figure 34 all the receiving or sending operations executed by the receiving end in the embodiment of [description]. The processing circuit 3610 is, for example, used to perform Figure 3 , Figure 4 , Figure 33 , or Figure 34 all the operations other than the receiving and sending operations executed by the receiving end in the embodiment of [description].

[0307] In a possible implementation, the transceiver circuit 3620 includes at least one transceiver, the processing circuit 3610 includes at least one processor, or the circuit for processing or controlling in at least one processor.

[0308] The transceiver is used to communicate with other devices / v apparatuses via a transmission medium. The processor utilizes the transceiver to send and receive data and / or signaling, and is used to implement the methods in the above method embodiments. The processor can implement the functions of the processing module 3510, and the transceiver can implement the functions of the transceiver module 3520. Optionally, the transceiver may include a radio frequency circuit and an antenna. The radio frequency circuit is mainly used for the conversion between baseband signals and radio frequency signals and the processing of radio frequency signals. The antenna is mainly used for transmitting and receiving radio frequency signals in the form of electromagnetic waves. Input / output devices, such as touch screens, display screens, keyboards, etc., are mainly used for receiving data input by users and outputting data to users.

[0309] Optionally, the apparatus 360 may further include at least one memory for storing program instructions and / or data. The memory is coupled to the processor. The coupling in the embodiments of the present application is an indirect coupling or communication connection between devices, units or modules, which can be electrical, mechanical or other forms, and is used for information interaction between devices, units or modules. The processor may cooperate with the memory. The processor may execute the program instructions stored in the memory. At least one of the at least one memory may be included in the processor.

[0310] The processor can read the software program in the memory, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be wirelessly transmitted, after the processor performs baseband processing on the data to be transmitted, it outputs a baseband signal to the radio frequency circuit, and the radio frequency circuit performs radio frequency processing on the baseband signal and then transmits the radio frequency signal outward in the form of electromagnetic waves through the antenna. When data is sent to the apparatus 360, the radio frequency circuit receives the radio frequency signal through the antenna, converts the radio frequency signal into a baseband signal, and outputs the baseband signal to the processor. The processor converts the baseband signal into data and processes the data.

[0311] In another implementation, the above radio frequency circuit and antenna may be provided independently of the processor for baseband processing. For example, in a distributed scenario, the radio frequency circuit and antenna may be independent of the apparatus 360 and arranged in a remote manner.

[0312] In the embodiments of the present application, the specific connection media between the above transceiver, processor and memory are not limited.

[0313] In an embodiment of the present application, the processor may be one of the following devices: a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field-programmable gate array, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or all or part of the circuits for processing functions in the foregoing devices, which can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present application may be directly embodied as being executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.

[0314] In a possible implementation manner, the processing circuit 3610 includes at least one logic circuit, and the transceiver circuit 3620 includes at least one interface. Figure 35 The processing module 3510 in may be implemented by a logic circuit. Figure 35 The transceiver module 3520 in may be implemented by an interface. Wherein, the logic circuit may be a chip, a processing circuit, an integrated circuit, or a system-on-chip (SoC) chip, etc., and the interface may be a communication interface, an input / output interface, etc. In the embodiments of the present application, the logic circuit and the interface may also be coupled to each other. For the specific connection manner between the logic circuit and the interface, the embodiments of the present application do not make any limitation.

[0315] The present application also provides a computer-readable storage medium, in which a computer program or instruction is stored. When the computer program or instruction runs on a computer, the computer is enabled to execute the method of the foregoing embodiment.

[0316] The present application also provides a computer program product, which includes an instruction or a computer program. When the instruction or the computer program runs on a computer, the method in the foregoing embodiment is enabled to be executed.

[0317] The present application also provides a communication system, including the foregoing sending end and the foregoing receiving end.

[0318] The present application also provides a chip, which includes: a communication interface and a processor; the communication interface is used for signal transceiver of the foregoing chip; the processor is used for executing computer program instructions, so that a communication device including the foregoing chip executes the method as in the foregoing embodiment.

[0319] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The above computer program product includes one or more computer programs or instructions. When the above computer program or instructions are loaded and executed on a computer, the processes or functions described above in the embodiments of the present application are executed in whole or in part. The above computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device, or other programmable devices. The above computer program or instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the above computer program or instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired or wireless manner. The above computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that integrates one or more available media. The above available medium can be a magnetic medium, such as a floppy disk, a hard disk, or a magnetic tape; it can also be an optical medium, such as a digital video disc; it can also be a semiconductor medium, such as a solid-state drive. The computer-readable storage medium can be a volatile or non-volatile storage medium, or can include both volatile and non-volatile types of storage media.

[0320] In various embodiments of the present application, if there is no special description and logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

Claims

1. A coding method, characterized in that, comprising: performing cyclic redundancy check (CRC) coding on K1 information bits to obtain a first bit sequence, the first bit sequence including the K1 information bits and L CRC bits, where K1 is a positive integer and L is a positive integer less than 24; interleaving the first bit sequence using a first distributed CRC interleaver to obtain a second bit sequence; wherein, the first distributed CRC interleaver includes (K2 + L) elements, and the values of the (K2 + L - S)-th element to the (K2 + L)-th element of the first distributed CRC interleaver are sequentially (K2 + L - 1 - S) to (K2 + L - 1), S is an integer greater than or equal to 0 and less than or equal to L, and K2 is an integer greater than or equal to K1; or, the first distributed CRC interleaver includes a total of (K2 + L) natural numbers from 0 to (K2 + L - 1), P is before Q in the first distributed CRC interleaver, both P and Q are integers greater than or equal to K2, and P is greater than Q.

2. The coding method according to claim 1, characterized in that, the L is equal to 6, 11 or 16.

3. The coding method according to claim 2, characterized in that, the K2 is equal to 32, 40, 48, 54, 64, 70 or 100.

4. The coding method according to any one of claims 1 to 3, characterized in that, the first distributed CRC interleaver is obtained by arranging L element sequences in order. For any two element sequences among the L element sequences, they are a first element sequence and a second element sequence. The elements included in the first element sequence are obtained based on the positions of the information bits associated with the first check column, and the elements included in the second element sequence are obtained based on the positions of the information bits associated with the second check column. The first check column and the second check column are any two columns in the check matrix obtained based on the CRC generating polynomial of length L. When the largest element representing the position of the information bit associated with the first check column in the first element sequence is greater than the largest element representing the position of the information bit associated with the second check column in the second element sequence, the sorting of the first element sequence in the first distributed CRC interleaver is after the second element sequence.

5. The coding method according to any one of claims 1 to 4, characterized in that, the performing cyclic redundancy check (CRC) coding on K1 information bits to obtain a first bit sequence includes: performing CRC coding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, the L is equal to 6, the K2 is equal to 70, the CRC generating polynomial is D^6 + D^5 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 2 3 4 5 6 7 13 18 19 23 25 28 29 30 31 33 37 38 39 42 45 47 48 50 51 5254 55 58 59 61 63 65 66 67 68 69 70 1 8 14 20 24 26 32 34 40 43 46 49 53 5660 62 64 71 9 15 21 27 35 41 44 57 72 10 16 2236 73 11 17 74 12 75。 6. The coding method according to any one of claims 1 to 4, characterized in that, the performing cyclic redundancy check (CRC) coding on K1 information bits to obtain a first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L equals 6, K2 equals 70, the CRC generating polynomial is D^6 + D^5 + D^4 + D^3 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 1 4 5 6 9 10 16 19 20 21 24 25 31 34 35 36 39 40 46 49 50 51 54 55 61 6465 66 69 70 2 7 11 17 22 26 32 37 41 47 52 56 62 67 71 3 8 12 18 23 27 33 3842 48 53 57 63 68 72 13 28 43 58 73 14 29 44 5974 0 15 30 45 60 75。 7. The encoding method according to any one of claims 1 to 4, characterized in that, the performing cyclic redundancy check CRC encoding on the K1 information bits to obtain the first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L equals 6, K2 equals 70, the CRC generating polynomial is D^6 + D^4 + D^3 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 1 2 3 4 5 7 13 14 15 20 23 27 28 30 31 34 36 37 39 41 42 43 45 46 47 4851 52 56 58 60 63 64 65 66 67 68 70 6 8 16 21 24 29 32 35 38 40 44 49 53 5759 61 69 71 9 17 22 25 33 50 54 62 72 10 18 2655 73 11 19 74 12 75。 8. The encoding method according to any one of claims 1 to 4, characterized in that, the performing cyclic redundancy check CRC encoding on the K1 information bits to obtain the first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L equals 6, K2 equals 70, the CRC generating polynomial is D^6 + D^3 + D^2 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 1 2 5 6 7 10 16 17 20 21 22 25 31 32 35 36 37 40 46 47 50 51 52 55 61 6265 66 67 70 3 8 11 18 23 26 33 38 41 48 53 56 63 68 71 4 9 12 19 24 27 34 3942 49 54 57 64 69 72 13 28 43 58 73 14 29 44 5974 0 15 30 45 60 75。 9. The encoding method according to any one of claims 1 to 4, characterized in that, the performing cyclic redundancy check CRC encoding on the K1 information bits to obtain the first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L equals 6, K2 equals 70, the CRC generating polynomial is D^6 + D^5 + D^2 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 1 2 4 5 6 7 13 15 17 18 21 22 23 25 26 27 28 34 36 38 39 42 43 44 46 4748 49 55 57 59 60 63 64 65 67 68 69 70 3 8 14 16 19 24 29 35 37 40 45 50 5658 61 66 71 9 20 30 41 51 62 72 10 31 52 7311 32 53 74 12 33 54 75。 10. The encoding method according to any one of claims 1 to 4, characterized in that, the performing cyclic redundancy check CRC encoding on the K1 information bits to obtain the first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L equals 6, K2 equals 70, the CRC generating polynomial is D^6 + D^5 + D^4 + D^2 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 80 1 4 6 7 13 15 18 21 22 25 27 28 34 36 39 42 43 46 48 49 55 57 60 63 6467 69 70 2 5 8 14 16 19 23 26 29 35 37 40 44 47 50 56 58 61 65 68 71 3 9 1720 24 30 38 41 45 51 59 62 66 72 10 31 52 7311 32 53 74 12 33 54 75。 11. The encoding method according to any one of claims 1 to 4, characterized in that, the performing cyclic redundancy check CRC encoding on the K1 information bits to obtain the first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L equals 6, K2 equals 70, the CRC generating polynomial is D^6 + D^3 + D^2 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 4 5 8 14 16 17 18 20 21 23 25 28 29 30 31 35 36 39 45 47 48 49 51 52 5456 59 60 61 62 66 67 70 1 6 9 15 19 22 24 26 32 37 40 46 50 53 55 57 63 68 712 7 10 27 33 38 41 58 64 69 72 3 11 34 42 6573 12 43 74 13 44 75。 12. The encoding method according to any one of claims 1 to 4, characterized in that, Performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: Performing CRC encoding on the K1 information bits based on a CRC generating polynomial to obtain the first bit sequence, where L = 6, K2 = 70, the CRC generating polynomial is D^6 + D^5 + D^3 + D^2 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 5 6 7 13 15 16 17 18 19 20 23 25 27 31 32 35 36 37 38 40 41 42 44 46 4749 52 53 55 56 60 63 68 69 70 1 8 14 21 24 26 28 33 39 43 45 48 50 54 57 6164 71 2 9 22 29 34 51 58 62 65 72 3 10 30 59 6673 4 11 67 74 12 75。 13. The encoding method according to any one of claims 1 to 4, characterized in that, Performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: Performing CRC encoding on the K1 information bits based on a CRC generating polynomial to obtain the first bit sequence, where L = 6, K2 = 70, the CRC generating polynomial is D^6 + D^5 + D^4 + D^3 + D^2 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 2 5 9 10 16 18 19 21 22 23 26 27 28 29 30 32 35 39 40 46 48 49 51 52 5356 57 58 59 60 62 65 69 70 1 3 6 11 17 20 24 31 33 36 41 47 50 54 61 63 66 714 7 12 25 34 37 42 55 64 67 72 8 13 38 43 6873 14 44 74 15 45 75。 14. The encoding method according to any one of claims 1 to 4, characterized in that, Performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: Performing CRC encoding on the K1 information bits based on a CRC generating polynomial to obtain the first bit sequence, where L = 6, K2 = 70, the CRC generating polynomial is D^6 + D^5 + D^4 + D^3 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 1 2 4 7 8 14 15 16 19 23 25 27 28 29 30 32 33 35 38 39 45 46 47 50 54 5658 59 60 61 63 64 66 69 70 0 3 5 9 17 20 24 26 31 34 36 40 48 51 55 57 62 6567 71 6 10 18 21 37 41 49 52 68 72 11 22 42 5373 12 43 74 13 44 75。 15. The encoding method according to any one of claims 1 to 4, characterized in that, Performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: Performing CRC encoding on the K1 information bits based on a CRC generating polynomial to obtain the first bit sequence, where L = 6, K2 = 70, the CRC generating polynomial is D^6 + D^4 + D^2 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 2 5 7 13 14 16 19 20 23 26 28 34 35 37 40 41 44 47 49 55 56 58 61 62 6568 70 0 3 6 8 15 17 21 24 27 29 36 38 42 45 48 50 57 59 63 66 69 71 1 4 9 1822 25 30 39 43 46 51 60 64 67 72 10 31 52 7311 32 53 74 12 33 54 75。 16. The encoding method according to any one of claims 1 to 4, characterized in that, Performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: Performing CRC encoding on the K1 information bits based on a CRC generating polynomial to obtain the first bit sequence, where L = 11, K2 = 70, the CRC generating polynomial is D^11 + D^10 + D^9 + D^5 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 1 2 3 4 6 7 10 13 15 19 21 22 23 24 25 27 30 33 34 35 37 41 44 46 47 4849 50 55 57 58 59 60 61 62 63 66 67 69 70 5 8 11 14 16 20 26 28 31 36 38 4245 51 56 64 68 71 9 12 17 29 32 39 43 52 65 7218 40 53 73 54 74 75 76 77 7879 80。 17. The encoding method according to any one of claims 1 to 4, characterized in that, Performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain a first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence. L equals 11, K2 equals 70, the CRC generating polynomial is D^11 + D^7 + D^6 + D^2 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 1 5 11 13 15 16 19 20 23 24 29 30 31 32 33 35 37 39 41 43 47 52 53 54 5556 57 58 59 60 61 62 65 66 70 2 6 12 14 17 21 25 34 36 38 40 42 44 48 63 6771 3 7 18 22 26 45 49 64 68 72 0 4 8 27 46 50 6973 9 28 51 74 10 75 76 77 7879 80。 18. The encoding method according to any one of claims 1 to 4, characterized in that the performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain the first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence. L equals 11, K2 equals 70, the CRC generating polynomial is D^11 + D^10 + D^9 + D^6 + D^4 + D^2 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 1 5 6 9 10 12 13 14 16 19 21 22 23 24 25 26 29 34 36 37 38 41 43 47 4950 51 52 54 61 63 64 65 66 67 69 70 2 7 11 15 17 20 27 30 35 39 42 44 48 5355 62 68 71 3 8 18 28 31 40 45 56 72 4 32 46 5773 33 58 74 59 75 60 76 77 7879 80。 19. The encoding method according to any one of claims 1 to 4, characterized in that the performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain the first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence. L equals 11, K2 equals 70, the CRC generating polynomial is D^11 + D^10 + D^9 + D^7 + D^5 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 5 7 8 11 12 16 18 19 21 22 24 25 27 30 34 38 39 46 50 53 54 55 58 59 6364 67 69 70 1 6 9 13 17 20 23 26 28 31 35 40 47 51 56 60 65 68 71 2 10 14 2932 36 41 48 52 57 61 66 72 3 15 33 37 42 49 6273 4 43 74 44 75 45 76 77 78 7980。 20. The encoding method according to any one of claims 1 to 4, characterized in that the performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain the first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence. L equals 11, K2 equals 70, the CRC generating polynomial is D^11 + D^9 + D^8 + D^6 + D^5 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 10 15 18 20 21 22 23 24 27 29 31 32 35 36 38 41 42 44 46 47 49 53 54 5558 59 63 64 65 66 67 68 70 1 11 16 19 25 28 30 33 37 39 43 45 48 50 56 60 6971 2 12 17 26 34 40 51 57 61 72 3 13 52 62 73 414 74 5 75 6 76 7 77 8 78 9 7980。 21. The encoding method according to any one of claims 1 to 4, characterized in that the performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain the first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence. L equals 11, K2 equals 70, the CRC generating polynomial is D^11 + D^10 + D^9 + D^8 + D^7 + D^5 + D^4 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 1 2 4 5 8 9 11 13 17 18 20 24 27 28 30 32 33 36 39 40 41 42 43 44 47 4952 53 54 55 61 62 63 65 69 70 3 6 10 12 14 19 21 25 29 31 34 37 45 48 50 5664 66 71 7 15 22 26 35 38 46 51 57 67 72 0 16 2358 68 73 59 74 60 75 76 77 7879 80。 22. The encoding method according to any one of claims 1 to 4, characterized in that the performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain the first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L equals 11, K2 equals 70, the CRC generating polynomial is D^11 + D^10 + D^3 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 2 3 4 5 9 16 17 18 19 20 22 25 28 29 30 31 32 33 38 39 40 42 44 47 50 5253 56 58 60 61 63 64 65 66 67 68 69 70 0 6 10 21 23 26 34 41 43 45 48 51 5457 59 62 71 1 7 11 24 27 35 46 49 55 72 8 12 3673 13 37 74 14 75 15 76 77 7879 80。 23. The encoding method according to any one of claims 1 to 4, characterized in that, the performing cyclic redundancy check CRC encoding on the K1 information bits to obtain the first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L equals 11, K2 equals 70, the CRC generating polynomial is D^11 + D^5 + D^3 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 2 5 13 14 15 16 20 23 27 30 32 34 35 36 37 38 39 40 43 47 48 52 54 58 5960 62 64 70 0 3 6 17 21 24 28 31 33 41 44 49 53 55 61 63 65 71 1 4 7 18 22 2529 42 45 50 56 66 72 8 19 26 46 51 57 67 73 968 74 10 69 75 11 76 12 77 78 7980。 24. The encoding method according to any one of claims 1 to 4, characterized in that, the performing cyclic redundancy check CRC encoding on the K1 information bits to obtain the first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L equals 11, K2 equals 70, the CRC generating polynomial is D^11 + D^10 + D^9 + D^8 + D^6 + D^5 + D^3 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 1 3 4 5 8 9 10 13 22 24 28 33 34 39 41 46 47 49 53 54 56 57 60 61 62 6364 66 69 70 2 6 11 14 23 25 29 35 40 42 48 50 55 58 65 67 71 7 12 15 26 30 3643 51 59 68 72 16 27 31 37 44 52 73 17 32 3845 74 18 75 19 76 20 77 21 78 7980。 25. The encoding method according to any one of claims 1 to 4, characterized in that, the performing cyclic redundancy check CRC encoding on the K1 information bits to obtain the first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L equals 11, K2 equals 70, the CRC generating polynomial is D^11 + D^10 + D^8 + D^7 + D^6 + D^5 + D^3 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 3 5 6 7 8 11 13 15 17 19 21 22 26 27 30 31 32 33 35 36 41 42 43 47 4953 61 62 65 68 69 70 1 4 9 12 14 16 18 20 23 28 34 37 44 48 50 54 63 66 71 210 24 29 38 45 51 55 64 67 72 25 39 46 52 56 7340 57 74 58 75 59 76 60 77 7879 80。 26. The encoding method according to any one of claims 1 to 4, characterized in that, the performing cyclic redundancy check CRC encoding on the K1 information bits to obtain the first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L equals 11, K2 equals 70, the CRC generating polynomial is D^11 + D^9 + D^7 + D^6 + D^5 + D^4 + D^3 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 1 4 6 9 12 14 15 16 23 28 30 34 35 37 38 39 41 42 43 45 46 47 48 51 52 5356 60 61 63 65 68 70 2 5 7 10 13 17 24 29 31 36 40 44 49 54 57 62 64 66 69 710 3 8 11 18 25 32 50 55 58 67 72 19 26 33 5973 20 27 74 21 75 22 76 77 78 7980。 27. The encoding method according to any one of claims 1 to 4, characterized in that, the performing cyclic redundancy check CRC encoding on the K1 information bits to obtain the first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L equals 11, K2 equals 70, the CRC generating polynomial is D^11 + D^10 + D^9 + D^7 + D^6 + D^3 + D^2 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 2 3 6 8 9 11 12 13 14 21 24 26 27 28 29 30 31 32 34 36 37 38 39 40 41 4748 49 53 54 57 61 65 67 69 70 0 4 7 10 15 22 25 33 35 42 50 55 58 62 66 68 711 5 16 23 43 51 56 59 63 72 17 44 52 60 64 7318 45 74 19 46 75 20 76 77 78 7980。 28. The encoding method according to any one of claims 1 to 4, characterized in that, the performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain the first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L equals 11, K2 equals 70, the CRC generating polynomial is D^11 + D^8 + D^6 + D^5 + D^4 + D^3 + D^2 + D + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 2 3 4 5 6 7 12 14 16 20 22 23 26 31 34 37 39 40 41 44 46 49 51 52 53 5458 62 63 65 67 70 0 8 13 15 17 21 24 27 32 35 38 42 45 47 50 55 59 64 66 6871 1 9 18 25 28 33 36 43 48 56 60 69 72 10 19 2957 61 73 11 30 74 75 76 77 7879 80。 29. The encoding method according to any one of claims 1 to 4, characterized in that, the performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain the first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L equals 16, K2 equals 100, the CRC generating polynomial is D^16 + D^12 + D^5 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 2 4 5 12 14 16 18 19 20 23 25 26 28 30 33 34 35 36 37 42 44 45 48 49 5152 58 65 67 68 72 73 74 78 80 81 88 89 92 96 100 3 6 13 15 17 21 24 27 29 3138 43 46 50 53 59 66 69 75 79 82 90 93 97 101 7 22 32 39 47 54 60 70 76 83 9194 98 102 8 40 55 61 71 77 84 95 99 103 0 9 41 56 62 85 104 1 10 57 63 86 10511 64 87 106 107 108 109 110 111 112113 114 115。 30. The encoding method according to any one of claims 1 to 4, characterized in that, the performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain the first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L equals 6, K2 equals 70, the CRC generating polynomial is D^6 + D^5 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 0 1 2 8 13 14 18 20 23 24 25 26 28 32 33 34 37 40 42 43 45 46 47 49 50 5354 56 58 60 61 62 63 64 65 71 3 9 15 19 21 27 29 35 38 41 44 48 51 55 57 5966 72 4 10 16 22 30 36 39 52 67 73 5 11 17 31 6874 6 7 69 70 12 75。 31. The encoding method according to any one of claims 1 to 4, characterized in that, the performing cyclic redundancy check (CRC) encoding on the K1 information bits to obtain the first bit sequence includes: Perform CRC encoding on the K1 information bits based on the CRC generating polynomial to obtain the first bit sequence, where L equals 11, K2 equals 70, the CRC generating polynomial is D^11 + D^10 + D^9 + D^5 + 1, and the values of the elements in the first distributed CRC interleaver are as follows in sequence: 1 2 5 8 10 14 16 17 18 19 20 22 25 28 29 30 32 36 39 41 42 43 44 45 50 5253 54 55 56 57 58 61 62 64 65 76 0 3 4 9 11 12 13 23 24 31 33 35 38 48 49 5960 63 66 72 6 15 21 26 37 40 46 51 77 34 67 737 27 47 78 68 74 79 69 70 71 7580。 32. A decoding method, characterized in that, includes: Obtain the sequence to be decoded; Perform a check on the sequence to be decoded based on the first cyclic redundancy check (CRC) generating polynomial, where the sequence to be decoded is obtained based on a second bit sequence obtained by interleaving the first bit sequence, and the first bit sequence includes K1 information bits and L CRC bits, K1 is a positive integer, and L is a positive integer less than 24; When the to-be-decoded sequence passes the check, use a first distributed CRC deinterleaver to deinterleave the second bit sequence to obtain the K1 information bits; Among them, the first distributed CRC deinterleaver corresponds to a first distributed interleaver. The first distributed CRC interleaver includes (K2 + L) elements. The values of the (K2 + L - S)-th element to the (K2 + L)-th element of the first distributed CRC interleaver are sequentially (K2 + L - 1 - S) to (K2 + L - 1), where S is an integer greater than or equal to 0 and less than or equal to L, and K2 is an integer greater than or equal to K1.

33. According to the encoding method described in claim 32, characterized in that, The first distributed CRC interleaver is obtained by arranging L element sequences in order. Any two of the L element sequences are a first element sequence and a second element sequence. The elements included in the first element sequence are obtained based on the positions of the information bits associated with the first check column. The elements included in the second element sequence are obtained based on the positions of the information bits associated with the second check column. The first check column and the second check column are any two columns in the check matrix obtained based on the L-length CRC generating polynomial. When the largest element representing the position of the information bit associated with the first check column in the first element sequence is greater than the largest element representing the position of the information bit associated with the second check column in the second element sequence, the sorting of the first element sequence in the first distributed CRC interleaver is after the second element sequence.

34. A communication device, characterized in that, It includes a module for implementing the method described in any one of claims 1 to 31.

35. A communication device, characterized in that, It includes a module for implementing the method described in claim 32 or 33.

36. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program. The computer program includes program instructions. When the program instructions are executed by a processor, the method described in any one of claims 1 to 33 is executed.

37. A communication device, characterized in that, It includes a processor. The processor is used to make the communication device execute the method described in any one of claims 1 to 33 when executing instructions.

38. A chip, characterized in that, including: A communication interface for signal transceiver of the chip; A processor for executing computer program instructions to make a communication device including the chip execute the method described in any one of claims 1 to 33.

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