Rate matching method and device, rate de-matching method and device and electronic equipment

Abstract

The invention provides a rate matching method and device, a rate de-matching method and device and electronic equipment, and the method comprises the steps: carrying out the coding of an original bit stream, and obtaining a coded bit stream; bit separation is carried out on the coding bit stream to obtain a target information bit stream, a target check bit stream and a tail bit stream, the tail bit stream comprises a tail bit of the original information bit stream and a tail bit of the original check bit stream, the target information bit stream and the tail bit of the original information bit stream form the original information bit stream, and the target check bit stream and the tail bit of the original check bit stream form the target check bit stream. The target check bit stream and the tail bit of the original check bit stream form an original check bit stream, rate matching is carried out on the target check bit stream to obtain a first matching bit stream, and bit merging is carried out on the target information bit stream, the first matching bit stream and the tail bit stream to obtain a second matching bit stream as a transmission bit stream. Therefore, the tail bit information can be reserved, and the method is suitable for narrow-band communication of low-orbit satellites.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technologies, and in particular, to a rate matching method, a de-rate matching method, a device, an electronic device, and a storage medium. Background Art

[0002] Rate matching refers to that the bits on the transmission channel are repeated or punctured to match the carrying capacity of the physical channel, so as to achieve the bit rate required by the transmission format during channel mapping. Rate matching is an important part of the baseband signal processing of the physical layer of the access network. By controlling rate matching, different transmission code rates are generated to balance the relationship between transmission efficiency and reliability. However, the rate matching method in the related art has the problem of error floor under high code rate short codes. Summary of the Invention

[0003] The present disclosure aims to solve at least one of the technical problems in the related art to some extent.

[0004] A rate matching method according to an embodiment of the first aspect of the present disclosure includes: encoding an original bit stream to obtain an encoded bit stream; separating the encoded bit stream to obtain a target information bit stream, a target parity bit stream, and a tail bit stream, where the tail bit stream includes the tail bits of the original information bit stream and the tail bits of the original parity bit stream, the tail bits of the target information bit stream and the original information bit stream form the original information bit stream, and the tail bits of the target parity bit stream and the original parity bit stream form the original parity bit stream; performing rate matching on the target parity bit stream to obtain a first matching bit stream; and combining the target information bit stream, the first matching bit stream, and the tail bit stream to obtain a second matching bit stream as a transmission bit stream.

[0005] According to the rate matching method of the embodiments of the present disclosure, the target information bit stream, the target parity bit stream, and the tail bit stream can be separated from the encoded bit stream. The tail bit stream includes the tail bits of the original information bit stream and the tail bits of the original parity bit stream. Only the target parity bit stream is subjected to rate matching, and the tail bit stream does not participate in the rate matching process. Compared with the related art where the tail bits may be deleted during rate matching, the tail bit information can be retained in this solution, avoiding the error floor under high code rate short codes, and being applicable to the application scenario of low-earth orbit satellite narrowband communication.

[0006] A rate matching method according to an embodiment of the second aspect of the present disclosure includes: performing bit separation on a transmission bit stream to obtain a target information bit stream, a first matching bit stream, and a tail bit stream, where the tail bit stream includes the tail bits of the original information bit stream and the tail bits of the original parity bit stream, the tail bits of the target information bit stream and the original information bit stream form the original information bit stream, and the tail bits of the target parity bit stream and the original parity bit stream form the original parity bit stream; performing rate dematching on the first matching bit stream to obtain the target parity bit stream; and decoding the target information bit stream, the target parity bit stream, and the tail bit stream to obtain the original bit stream.

[0007] A rate matching device according to an embodiment of the third aspect of the present disclosure includes: an encoding module for encoding an original bit stream to obtain an encoded bit stream; a separation module for performing bit separation on the encoded bit stream to obtain a target information bit stream, a target parity bit stream, and a tail bit stream, where the tail bit stream includes the tail bits of the original information bit stream and the tail bits of the original parity bit stream, the tail bits of the target information bit stream and the original information bit stream form the original information bit stream, and the tail bits of the target parity bit stream and the original parity bit stream form the original parity bit stream; a matching module for performing rate matching on the target parity bit stream to obtain a first matching bit stream; and a merging module for performing bit merging on the target information bit stream, the first matching bit stream, and the tail bit stream to obtain a second matching bit stream as the transmission bit stream.

[0008] A rate dematching device according to an embodiment of the fourth aspect of the present disclosure includes: a separation module for performing bit separation on a transmission bit stream to obtain a target information bit stream, a first matching bit stream, and a tail bit stream, where the tail bit stream includes the tail bits of the original information bit stream and the tail bits of the original parity bit stream, the tail bits of the target information bit stream and the original information bit stream form the original information bit stream, and the tail bits of the target parity bit stream and the original parity bit stream form the original parity bit stream; a processing module for performing rate dematching on the first matching bit stream to obtain the target parity bit stream; and a decoding module for decoding the target information bit stream, the target parity bit stream, and the tail bit stream to obtain the original bit stream.

[0009] Embodiments of the fifth aspect of the present disclosure provide an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the rate matching method described in the embodiments of the first aspect of the present disclosure is implemented, or the rate dematching method described in the embodiments of the second aspect of the present disclosure is implemented.

[0010] Embodiments of the sixth aspect of the present disclosure provide a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the rate matching method described in the embodiments of the first aspect of the present disclosure is implemented, or the rate dematching method described in the embodiments of the second aspect of the present disclosure is implemented.

[0011] Embodiments of the seventh aspect of the present disclosure provide a computer program product. When the instructions in the computer program product are executed by a processor, the rate matching method described in the embodiments of the first aspect of the present disclosure is implemented, or the rate dematching method described in the embodiments of the second aspect of the present disclosure is implemented.

[0012] Additional aspects and advantages of the present disclosure will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present disclosure. Description of the Drawings

[0013] The above and / or additional aspects and advantages of the present disclosure will become apparent and be readily understood from the following description of the embodiments in conjunction with the drawings, where:

[0014] Figure 1 is a schematic flowchart of a rate matching method provided by an embodiment of the present disclosure;

[0015] Figure 2 is a schematic diagram of a rate matching method provided by an embodiment of the present disclosure;

[0016] Figure 3 is a schematic flowchart of bit separation of an encoded bit stream in a rate matching method provided by an embodiment of the present disclosure;

[0017] Figure 4 is a schematic flowchart of rate matching for a first parity bit stream in a rate matching method provided by an embodiment of the present disclosure;

[0018] Figure 5 is a schematic flowchart of a rate dematching method provided by an embodiment of the present disclosure;

[0019] Figure 6 is a schematic structural diagram of a rate matching device provided by an embodiment of the present disclosure;

[0020] Figure 7Schematic diagram of a rate dematching device provided by an embodiment of the present disclosure;

[0021] Figure 8 It is a block diagram of an electronic device shown according to an exemplary embodiment. Detailed implementation manners

[0022] The embodiments of the present disclosure will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure, and should not be construed as a limitation to the present disclosure.

[0023] The rate matching method, rate dematching method, device, electronic device and storage medium of the embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0024] Figure 1 It is a flowchart of a rate matching method provided by an embodiment of the present disclosure.

[0025] As Figure 1 shown, the rate matching method may include the following steps:

[0026] S101, encode the original bit stream to obtain an encoded bit stream.

[0027] It should be noted that the execution subject of the rate matching method of the embodiments of the present disclosure is the data sending end. There is no excessive limitation on the data sending end. For example, it may include any device in a communication system. Among them, the communication system may include a low-earth orbit satellite narrowband communication system, and the device may include a network device and a terminal device. Among them, the network device may include a base station, and the terminal device may include a mobile phone, a computer, a smart home appliance, a vehicle-mounted terminal, etc.

[0028] It should be noted that the original bit stream refers to the bit stream to be encoded. For example, it may include the information bit stream to be encoded. The encoded bit stream refers to the bit stream after encoding the original bit stream. Encoding the original bit stream can be implemented by using any encoding method in related technologies, and there is no excessive limitation here. For example, it may include Turbo coding and Polar coding.

[0029] In one implementation manner, the encoded bit stream is obtained based on Turbo coding. For example, the original bit stream may be input to a Turbo encoder, and the Turbo encoder outputs the encoded bit stream.

[0030] It should be noted that there is no excessive limitation on the coding rate. For example, it may include 1 / 3.

[0031] For example, the number of bits of the information bit stream to be encoded is k, where k is a positive integer, and the encoded bit stream C is as follows:

[0032] C = [x 1 z 1 z' 1 x 2 z 2 z' 2 …x k z k z' k x k+1 z k+1 x k+2 z k+2 x k+3 z k+3 x' k+1 z' k+1 x' k+2 z' k+2 x' k+3 z' k+3

[0033] Among them, x j is the j-th information bit of the original information bit stream A, x' j is the j-th information bit of the interleaved information bit stream B, z j is the j-th parity bit of the original parity bit stream D 1 under the first parity branch, and z' j is the j-th parity bit of the original parity bit stream D 2 under the second parity branch, where j is a positive integer not greater than k + 3. There are no excessive restrictions on the parity branches. For example, they can include odd parity and even parity.

[0034] The information bit stream to be encoded can be encoded to obtain the original information bit stream A.

[0035] The information bit stream to be encoded can be interleaved to obtain an interleaved bit stream, and the interleaved bit stream can be encoded to obtain the interleaved information bit stream B.

[0036] The original information bit stream A, the interleaved information bit stream B, and the original parity bit streams D 1 , D 2 are respectively as follows:

[0037] A = [x 1 x 2 …x k x k+1 x k+2 x k+3

[0038] B = [x' 1 x'​​2 …x' k x' k+1 x' k+2 x' k+3

[0039] D 1 =[z 1 z 2 …z k z k+1 z k+2 z k+3

[0040] D 2 =[z' 1 z' 2 …z' k z' k+1 z' k+2 z' k+3

[0041] S102. Bit-separate the coded bitstream to obtain a target information-bit bitstream, a target parity-bit bitstream, and a tail bitstream. The tail bitstream includes the tail bits of the original information-bit bitstream and the tail bits of the original parity-bit bitstream. The tail bits of the target information-bit bitstream and the original information-bit bitstream form the original information-bit bitstream, and the tail bits of the target parity-bit bitstream and the original parity-bit bitstream form the original parity-bit bitstream.

[0042] It should be noted that the target information-bit bitstream, the target parity-bit bitstream, and the tail bitstream form the coded bitstream, and the original information-bit bitstream and the original parity-bit bitstream also form the coded bitstream. There is no excessive limitation on the number of bits of the tail bits. For example, it can be 3 bits.

[0043] It should be noted that bit-separating the coded bitstream can be implemented by using any bit-separation method in the related technologies, and there is no excessive limitation here.

[0044] In one implementation, the tail bitstream further includes the tail bits of the interleaved information-bit bitstream.

[0045] For example, continuing with the above-mentioned coded bitstream C as an example, bit-separate the coded bitstream C to obtain a target information-bit bitstream X, a target parity-bit bitstream Z 1 、Z 2 and a tail bitstream Tail.

[0046] The target information-bit bitstream X, the target parity-bit bitstream Z 1 、Z 2 and the tail bitstream Tail are respectively as follows:

[0047] X=[x 1 x​​​2 …x k

[0048] Z 1 =[z 1 z 2 …z k

[0049] Z 2 =[z' 1 z' 2 …z' k

[0050] Tail = [x k+1 z k+1 x k+2 z k+2 x k+3 z k+3 x' k+1 z' k+1 x' k+2 z' k+2 x' k+3 z' k+3

[0051] Among them, x k+1 、x k+2 、x k+3 are the tail bits of the original information bit stream A, x' k+1 、x' k+2 、x' k+3 are the tail bits of the interleaved information bit stream B, z k+1 、z k+2 、z k+3 are the tail bits of the original parity bit stream D 1 's tail bits, z' k+1 、z' k+2 、z' k+3 are the tail bits of the original parity bit stream D 2 's tail bits.

[0052] The tail bits of the target information bit stream X and the original information bit stream A form the original information bit stream A, and the tail bits of the target parity bit stream Z 1 and the original parity bit stream D 1 's tail bits form the original parity bit stream D 1 , and the tail bits of the target parity bit stream Z 2 and the original parity bit stream D 2 's tail bits form the original parity bit stream D 2 .

[0053] It can be known that the number of bits of the encoded bit stream C is 3k + T, and the number of bits of the target information bit stream X is k, and the target parity bit stream Z 1 、Z​​​​2 The number of bits of each is k, and the number of bits of the tail bit stream Tail is T. In this embodiment, T = 12.

[0054] S103. Perform rate matching on the target parity bit stream to obtain a first matched bit stream.

[0055] It should be noted that rate matching on the target parity bit stream can be implemented by any rate matching method in related technologies, which will not be elaborated here.

[0056] In one implementation, the target parity bit stream includes the target parity bit streams under N check branches. Performing rate matching on the target parity bit stream to obtain a first matched bit stream includes bitwise combining the target parity bit streams under N check branches to obtain a first parity bit stream, and performing rate matching on the first parity bit stream to obtain a first matched bit stream.

[0057] It should be noted that bitwise combining the target parity bit streams under N check branches can be implemented by any bitwise combining method in related technologies, and no excessive limitation is made here. For example, the target parity bit streams under N check branches can be bitwise combined in the order of the target parity bit streams under the 1st to Nth check branches.

[0058] For example, continuing with the above-mentioned coded bit stream C as an example, the target parity bit stream Z 1 、Z 2 can be bitwise combined to obtain a first parity bit stream Z, and rate matching is performed on the first parity bit stream Z to obtain a first matched bit stream Y.

[0059] The first parity bit stream Z is as follows:

[0060] Z = [z 1 z 2 …z k z' 1 z' 2 …z' k .

[0061] S104. Bitwise combine the target information bit stream, the first matched bit stream, and the tail bit stream to obtain a second matched bit stream as the transmission bit stream.

[0062] For example, as Figure 2As shown, the original bitstream can be encoded to obtain an encoded bitstream. The encoded bitstream is bit-separated to obtain a target information-bit bitstream, a target parity-bit bitstream, and a tail bitstream. The target parity-bit bitstream is rate-matched to obtain a first matched bitstream. The target information-bit bitstream, the first matched bitstream, and the tail bitstream are bit-combined to obtain a second matched bitstream as the transmission bitstream.

[0063] In one implementation, bit-combining the target information-bit bitstream, the first matched bitstream, and the tail bitstream includes bit-combining the target information-bit bitstream, the first matched bitstream, and the tail bitstream in the order of the target information-bit bitstream, the tail bitstream, and the first matched bitstream.

[0064] For example, continuing with the above encoded bitstream C as an example, the target information-bit bitstream X, the first matched bitstream Y, and the tail bitstream Tail can be bit-combined in the order of the target information-bit bitstream X, the tail bitstream Tail, and the first matched bitstream Y to obtain a second matched bitstream G as the transmission bitstream.

[0065] The second matched bitstream G = [X, Tail, Y].

[0066] In one implementation, the method further includes sending the transmission bitstream to a data receiving end, that is, sending the second matched bitstream to the data receiving end.

[0067] In summary, according to the rate matching method of the embodiments of the present disclosure, the original bitstream is encoded to obtain an encoded bitstream. The encoded bitstream is bit-separated to obtain a target information-bit bitstream, a target parity-bit bitstream, and a tail bitstream. The tail bitstream includes the tail bits of the original information-bit bitstream and the tail bits of the original parity-bit bitstream. The tail bits of the target information-bit bitstream and the original information-bit bitstream form the original information-bit bitstream. The tail bits of the target parity-bit bitstream and the original parity-bit bitstream form the original parity-bit bitstream. The target parity-bit bitstream is rate-matched to obtain a first matched bitstream. The target information-bit bitstream, the first matched bitstream, and the tail bitstream are bit-combined to obtain a second matched bitstream as the transmission bitstream. Thus, the target information-bit bitstream, the target parity-bit bitstream, and the tail bitstream can be separated from the encoded bitstream. The tail bitstream includes the tail bits of the original information-bit bitstream and the tail bits of the original parity-bit bitstream. Only the target parity-bit bitstream is rate-matched, and the tail bitstream does not participate in the rate matching process. Compared with the related art where the tail bits may be deleted during rate matching, the tail bit information can be retained in this solution, avoiding the error floor under high code rate short codes, and is applicable to the application scenario of low-earth orbit satellite narrowband communication.

[0068] Based on any of the above embodiments, the original parity bit stream includes the original parity bit streams under N parity branches, the target parity bit stream includes the target parity bit streams under N parity branches, the tail bits of the target parity bit stream and the original parity bit stream under the i-th parity branch form the original parity bit stream under the i-th parity branch, and the tail bit stream includes the tail bits of the original information bit stream and the tail bits of the original parity bit streams under N parity branches. Wherein, N is a positive integer, and i is a positive integer not greater than N. There is no excessive limitation on N. For example, it can be 1, 2, etc.

[0069] Based on any of the above embodiments, as Figure 3 shown, in step S101, bit separation is performed on the encoded bit stream to obtain the target information bit stream, the target parity bit stream, and the tail bit stream, including the following steps:

[0070] S301, perform bit separation on the encoded bit stream to obtain the original information bit stream and the original parity bit stream.

[0071] In one implementation manner, in the process of performing bit separation on the encoded bit stream to obtain the original information bit stream and the original parity bit stream, the tail bits of the interleaved information bit stream are also obtained.

[0072] For example, continuing with the above encoded bit stream C as an example, bit separation can be performed on the encoded bit stream C to obtain the original information bit stream A, the tail bits of the interleaved information bit stream B (i.e., x' k+1 、x' k+2 、x' k+3 ) and the original parity bit stream D 1 、D 2 .

[0073] S302, perform bit separation on the original information bit stream to obtain the target information bit stream and the tail bits of the original information bit stream.

[0074] For example, continuing with the above encoded bit stream C as an example, bit separation can be performed on the original information bit stream A to obtain the target information bit stream X and the tail bits of the original information bit stream A (i.e., x k+1 、x k+2 、x k+3 ).

[0075] S303, perform bit separation on the original parity bit stream to obtain the target parity bit stream and the tail bits of the original parity bit stream.

[0076] In one implementation manner, the original parity bit stream includes the original parity bit streams under N parity branches, and the target parity bit stream includes the target parity bit streams under N parity branches.

[0077] Perform bit separation on the original check bit stream to obtain the target check bit stream and the tail bits of the original check bit stream, including performing bit separation on the original check bit stream under the i-th check branch to obtain the target check bit stream under the i-th check branch and the tail bits of the original check bit stream under the i-th check branch, where N is a positive integer and i is a positive integer not greater than N.

[0078] For example, continuing with the above-mentioned encoded bit stream C as an example, the original check bit stream D under the first check branch can be 1 bit-separated to obtain the target check bit stream Z under the first check branch 1 and the tail bits of the original check bit stream D under the first check branch 1 (i.e., z k+1 , z k+2 , z k+3 ).

[0079] For example, continuing with the above-mentioned encoded bit stream C as an example, the original check bit stream D under the second check branch can be 2 bit-separated to obtain the target check bit stream Z under the second check branch 2 and the tail bits of the original check bit stream D under the second check branch 2 (i.e., z' k+1 , z' k+2 , z' k+3 ).

[0080] S304. Perform bit merging on the tail bits of the original information bit stream and the tail bits of the original check bit stream to obtain the tail bit stream.

[0081] In one implementation, performing bit merging on the tail bits of the original information bit stream and the tail bits of the original check bit stream to obtain the tail bit stream includes performing bit merging on the tail bits of the original information bit stream and the tail bits of the original check bit stream under N check branches to obtain the tail bit stream.

[0082] In some examples, performing bit merging on the tail bits of the original information bit stream and the tail bits of the original check bit stream under N check branches to obtain the tail bit stream includes performing bit merging on the tail bits of the original information bit stream, the tail bits of the interleaved information bit stream, and the tail bits of the original check bit stream under N check branches to obtain the tail bit stream.

[0083] For example, continuing with the above-mentioned encoded bit stream C as an example, the tail bits of the original information bit stream A (i.e., x k+1 , x k+2 , x k+3) The tail bits of the interleaved information bit stream B (i.e., x' k+1 , x' k+2 , x' k+3 ), the tail bits of the original parity bit stream D 1 under the first parity branch (i.e., z k+1 , z k+2 , z k+3 ), and the tail bits of the original parity bit stream D 2 under the second parity branch (i.e., z' k+1 , z' k+2 , z' k+3 ) are bit - combined to obtain the tail bit stream Tail.

[0084] Thus, in this method, the coded bit stream can be bit - separated to obtain the original information bit stream and the original parity bit stream, and the original information bit stream and the original parity bit stream are respectively bit - separated to obtain the target information bit stream, the tail bits of the original information bit stream, the target parity bit stream, and the tail bits of the original parity bit stream. The tail bits of the original information bit stream and the tail bits of the original parity bit stream are bit - combined to obtain the tail bit stream, so as to separate the target information bit stream, the target parity bit stream, and the tail bit stream from the coded bit stream.

[0085] Based on any of the above - mentioned embodiments, as Figure 4 shown, rate - matching the first parity bit stream to obtain the first matched bit stream includes the following steps:

[0086] S401, obtain the first number of bits of the first parity bit stream.

[0087] In one implementation, obtaining the first number of bits of the first parity bit stream includes obtaining the sum of the numbers of bits of the target parity bit streams under N parity branches as the first number of bits.

[0088] For example, continuing with the above - mentioned coded bit stream C as an example, the first number of bits of the first parity bit stream Z is 2k.

[0089] For example, continuing with the above - mentioned coded bit stream C as an example, the number of bits k of the target parity bit stream Z 1 under the first parity branch and the number of bits k of the target parity bit stream Z 2 under the second parity branch can be obtained, and their sum value 2k is used as the first number of bits.

[0090] In one implementation, obtaining the first number of bits of the first check bit stream includes obtaining the number of bits of the tail bits of the original information bit stream and the sum value of the number of bits of the original check bit streams under N check branches, obtaining the third number of bits of the tail bit stream, and obtaining the first number of bits based on the difference between the sum value and the third number of bits.

[0091] In some examples, obtaining the first number of bits based on the difference between the sum value and the third number of bits includes using the difference between the sum value and the third number of bits as the first number of bits.

[0092] In some examples, obtaining the first number of bits based on the difference between the sum value and the third number of bits includes obtaining the sum value between the difference between the sum value and the third number of bits and the number of bits of the tail bits of the interleaved coded bit stream as the first number of bits.

[0093] For example, continuing with the above-mentioned coded bit stream C as an example, the number of bits 3 of the tail bits of the original information bit stream A, the original check bit stream D 1 under the first check branch with the number of bits (k + 3), and the original check bit stream D 2 under the second check branch with the number of bits (k + 3) can be obtained, and the sum value (2k + 9) is obtained. The third number of bits 12 of the tail bit stream Tail is obtained. That is, the difference between the sum value and the third number of bits is (2k - 3). The sum value 2k between (2k - 3) and the number of bits 3 of the tail bits of the interleaved coded bit stream B is obtained as the first number of bits.

[0094] S402. Obtain the second number of bits of the first matching bit stream.

[0095] In one implementation, obtaining the second number of bits of the first matching bit stream includes obtaining the transmission code rate, obtaining the number of bits of the transmission bit stream based on the transmission code rate and the number of bits of the original bit stream, obtaining the sum value between the number of bits of the target information bit stream and the number of bits of the tail bit stream, and obtaining the difference between the number of bits of the transmission bit stream and the sum value as the second matching number.

[0096] In some examples, obtaining the number of bits of the transmission bit stream based on the transmission code rate and the number of bits of the original bit stream includes obtaining the ratio between the number of bits of the original bit stream and the transmission code rate as the number of bits of the transmission bit stream.

[0097] For example, continuing with the above-mentioned encoded bitstream C as an example, obtain the transmission code rate R, obtain the ratio k / R between the number of bits k of the original bitstream and the transmission code rate R as the number of bits of the transmitted bitstream, obtain the sum value (k + T) between the number of bits k of the target information bitstream X and the number of bits T of the tail bitstream Tail, and obtain the difference (k / R - (k + T)) between the number of bits k / R of the transmitted bitstream and the sum value (k + T) as the second matching number. In this embodiment, T = 12.

[0098] S403. Obtain the difference between the first number of bits and the second number of bits as the target number of bits to be deleted.

[0099] S404. Delete the data of the target number of bits from the first parity bitstream to obtain the first matching bitstream.

[0100] For example, if the first number of bits is P and the second number of bits is Q, then (P - Q) can be used as the target number of bits to be deleted.

[0101] It should be noted that deleting the data of the target number of bits from the first parity bitstream can be implemented by any rate matching method in related technologies, and no further limitations are imposed here.

[0102] In one implementation, deleting the data of the target number of bits from the first parity bitstream to obtain the first matching bitstream includes starting from a set position of the first parity bitstream, taking the set position as the currently traversed position, deleting the data of the fourth number of bits from the currently traversed position, and updating the position that is a set number of bits after the currently traversed position as the currently traversed position until the data of the target number of bits is deleted from the first parity bitstream to obtain the first matching bitstream. It should be noted that the fourth number of bits is less than or equal to the target number of bits. Thus, uniform deletion of data in the first parity bitstream can be achieved in this method.

[0103] Thus, in this method, obtain the first number of bits of the first parity bitstream, obtain the second number of bits of the first matching bitstream, obtain the difference between the first number of bits and the second number of bits as the target number of bits to be deleted, and delete the data of the target number of bits from the first parity bitstream to obtain the first matching bitstream to achieve rate matching.

[0104] Figure 5 It is a schematic flowchart of a rate dematching method provided by an embodiment of the present disclosure.

[0105] As Figure 5 shown, the rate dematching method may include the following steps:

[0106] S501. Perform bit separation on the transmitted bitstream to obtain a target information bitstream, a first matching bitstream, and a tail bitstream. Among them, the tail bitstream includes the tail bits of the original information bitstream and the tail bits of the original parity bitstream. The tail bits of the target information bitstream and the original information bitstream form the original information bitstream, and the tail bits of the target parity bitstream and the original parity bitstream form the original parity bitstream.

[0107] It should be noted that the execution entity of the rate dematching method in the embodiments of the present disclosure is the data receiving end. There are no excessive limitations on the data receiving end. For example, it may include any device in the communication system. Among them, the communication system may include a low-earth orbit satellite narrowband communication system, and the device may include a network device and a terminal device. Among them, the network device may include a base station, and the terminal device may include a mobile phone, a computer, a smart home appliance, a vehicle-mounted terminal, etc.

[0108] In one implementation, the method further includes receiving the transmitted bitstream sent by the data sending end.

[0109] For example, continuing with the above-mentioned encoded bitstream C as an example, perform bit separation on the transmitted bitstream, that is, the second matching bitstream G, to obtain a target information bitstream X, a first matching bitstream Y, and a tail bitstream Tail.

[0110] S502. Perform rate dematching on the first matching bitstream to obtain a target parity bitstream.

[0111] It should be noted that rate dematching of the first matching bitstream can be implemented by using any rate dematching method in related technologies, and there are no excessive limitations here.

[0112] For example, continuing with the above-mentioned encoded bitstream C as an example, perform rate dematching on the first matching bitstream Y to obtain a target parity bitstream Z 1 、Z 2 .

[0113] S503. Decode the target information bitstream, the target parity bitstream, and the tail bitstream to obtain the original bitstream.

[0114] It should be noted that decoding the target information bitstream, the target parity bitstream, and the tail bitstream can be implemented by using any decoding method in related technologies, and there are no excessive limitations here.

[0115] In one embodiment, the target information bit stream, the target check bit stream, and the tail bit stream are decoded to obtain the original bit stream, including decoding the target information bit stream to obtain the decoded information bit stream, decoding the target check bit stream to obtain the decoded check bit stream, decoding the tail bit stream to obtain the decoded tail bit stream, and based on the decoded check bit stream and the decoded tail bit stream, checking the decoded information bit stream. If the decoded information bit stream passes the check, the decoded information bit stream is used as the original bit stream.

[0116] In summary, according to the rate matching method of the embodiments of the present disclosure, the transmission bit stream is bit-separated to obtain the target information bit stream, the first matching bit stream, and the tail bit stream. Among them, the tail bit stream includes the tail bits of the original information bit stream and the tail bits of the original check bit stream. The tail bits of the target information bit stream and the original information bit stream constitute the original information bit stream, and the tail bits of the target check bit stream and the original check bit stream constitute the original check bit stream. The first matching bit stream is rate-matched to obtain the target check bit stream, and the target information bit stream, the target check bit stream, and the tail bit stream are decoded to obtain the original bit stream. Thus, the target information bit stream, the first matching bit stream, and the tail bit stream can be separated from the transmission bit stream. The tail bit stream includes the tail bits of the original information bit stream and the tail bits of the original check bit stream. Only the first matching bit stream is rate-matched, and the tail bit stream does not participate in the rate matching process. Compared with the related art where the tail bits need to be processed during rate matching, in this solution, the tail bit information can be directly separated from the transmission bit stream, the retention of the tail bit information can be achieved, the error floor under high code rate short codes can be avoided, and it is applicable to the application scenario of low-earth orbit satellite narrowband communication.

[0117] To implement the above embodiments, the present disclosure also proposes a rate matching device.

[0118] Figure 6 FIG. is a schematic structural diagram of a rate matching device provided by an embodiment of the present disclosure.

[0119] As Figure 6 shown, the rate matching device 100 includes: an encoding module 110, a separation module 120, a matching module 130, and a merging module 140.

[0120] The encoding module 110 is configured to encode the original bit stream to obtain an encoded bit stream;

[0121] A separation module 120 is configured to perform bit separation on the encoded bit stream to obtain a target information bit stream, a target check bit stream, and a tail bit stream. The tail bit stream includes the tail bits of the original information bit stream and the tail bits of the original check bit stream. The tail bits of the target information bit stream and the original information bit stream form the original information bit stream, and the tail bits of the target check bit stream and the original check bit stream form the original check bit stream.

[0122] A matching module 130 is configured to perform rate matching on the target check bit stream to obtain a first matched bit stream.

[0123] A merging module 140 is configured to perform bit merging on the target information bit stream, the first matched bit stream, and the tail bit stream to obtain a second matched bit stream as the transmission bit stream.

[0124] In an embodiment of the present disclosure, the separation module 120 is further configured to: perform bit separation on the encoded bit stream to obtain the original information bit stream and the original check bit stream; perform bit separation on the original information bit stream to obtain the target information bit stream and the tail bits of the original information bit stream; perform bit separation on the original check bit stream to obtain the target check bit stream and the tail bits of the original check bit stream; perform bit merging on the tail bits of the original information bit stream and the tail bits of the original check bit stream to obtain the tail bit stream.

[0125] In an embodiment of the present disclosure, the original check bit stream includes the original check bit streams under N check branches, and the target check bit stream includes the target check bit streams under N check branches.

[0126] The separation module 120 is further configured to: perform bit separation on the original check bit stream under the i-th check branch to obtain the target check bit stream under the i-th check branch and the tail bits of the original check bit stream under the i-th check branch, where N is a positive integer and i is a positive integer not greater than N.

[0127] In an embodiment of the present disclosure, the separation module 120 is further configured to: perform bit merging on the tail bits of the original information bit stream and the tail bits of the original check bit streams under N check branches to obtain the tail bit stream.

[0128] In one embodiment of the present disclosure, the target check bit stream includes target check bit streams under N check branches, and the matching module 130 is further configured to: perform bit merging on the target check bit streams under N check branches to obtain a first check bit stream; perform rate matching on the first check bit stream to obtain the first matched bit stream.

[0129] In one embodiment of the present disclosure, the matching module 130 is further configured to: obtain a first number of bits of the first check bit stream; obtain a second number of bits of the first matched bit stream; obtain a difference between the first number of bits and the second number of bits as a target number of bits to be deleted; delete data of the target number of bits from the first check bit stream to obtain the first matched bit stream.

[0130] In one embodiment of the present disclosure, the matching module 130 is further configured to: obtain the number of bits of the tail bits of the original information bit stream and the sum value of the number of bits of the original check bit streams under N check branches; obtain a third number of bits of the tail bit stream; obtain the first number of bits based on the difference between the sum value and the third number of bits.

[0131] In one embodiment of the present disclosure, the encoded bit stream is obtained based on Turbo coding.

[0132] It should be noted that the foregoing explanation of the rate matching method embodiment also applies to the rate matching device of this embodiment, and will not be elaborated here.

[0133] The rate matching device of the embodiments of the present disclosure encodes the original bit stream to obtain an encoded bit stream, performs bit separation on the encoded bit stream to obtain a target information bit stream, a target check bit stream, and a tail bit stream. The tail bit stream includes the tail bits of the original information bit stream and the tail bits of the original check bit stream. The tail bits of the target information bit stream and the original information bit stream constitute the original information bit stream, and the tail bits of the target check bit stream and the original check bit stream constitute the original check bit stream. Perform rate matching on the target check bit stream to obtain a first matched bit stream, and perform bit merging on the target information bit stream, the first matched bit stream, and the tail bit stream to obtain a second matched bit stream as the transmission bit stream. Thus, the target information bit stream, the target check bit stream, and the tail bit stream can be separated from the encoded bit stream. The tail bit stream includes the tail bits of the original information bit stream and the tail bits of the original check bit stream. Only the target check bit stream is rate-matched, and the tail bit stream does not participate in the rate matching process. Compared with the related art where tail bits may be deleted during rate matching, the tail bit information can be retained in this solution, avoiding the error floor under high code rate short codes, and is applicable to the application scenario of low-earth orbit satellite narrowband communication.

[0134] To implement the above embodiments, the present disclosure also proposes a rate dematching device.

[0135] Figure 7 FIG. is a schematic structural diagram of a rate dematching device provided by an embodiment of the present disclosure.

[0136] As Figure 7 shown, the rate dematching device 200 includes: a separation module 210, a processing module 220, and a decoding module 230.

[0137] The separation module 210 is configured to perform bit separation on the transmitted bit stream to obtain a target information bit stream, a first matching bit stream, and a tail bit stream, where the tail bit stream includes the tail bits of the original information bit stream and the tail bits of the original check bit stream, and the tail bits of the target information bit stream and the original information bit stream constitute the original information bit stream, and the tail bits of the target check bit stream and the original check bit stream constitute the original check bit stream;

[0138] The processing module 220 is configured to perform rate dematching on the first matching bit stream to obtain the target check bit stream;

[0139] The decoding module 230 is configured to decode the target information bit stream, the target check bit stream, and the tail bit stream to obtain the original bit stream.

[0140] It should be noted that the foregoing explanation of the embodiments of the rate dematching method also applies to the rate dematching device of this embodiment, and will not be repeated here.

[0141] The rate matching device according to the embodiments of the present disclosure separates bits from the transmitted bit stream to obtain a target information bit stream, a first matching bit stream, and a tail bit stream. Among them, the tail bit stream includes the tail bits of the original information bit stream and the tail bits of the original parity bit stream. The tail bits of the target information bit stream and the original information bit stream form the original information bit stream, and the tail bits of the target parity bit stream and the original parity bit stream form the original parity bit stream. The first matching bit stream is subjected to rate dematching to obtain a target parity bit stream. The target information bit stream, the target parity bit stream, and the tail bit stream are decoded to obtain the original bit stream. Thus, the target information bit stream, the first matching bit stream, and the tail bit stream can be separated from the transmitted bit stream. The tail bit stream includes the tail bits of the original information bit stream and the tail bits of the original parity bit stream. Only the first matching bit stream is subjected to rate dematching, and the tail bit stream does not participate in the rate dematching process. Compared with the related art where the tail bits need to be processed during rate dematching, in this solution, the tail bit information can be directly separated from the transmitted bit stream, the tail bit information can be retained, the error floor under high code rate short codes can be avoided, and it is applicable to the application scenario of low-earth orbit satellite narrowband communication.

[0142] To implement the above embodiments, the present application also proposes an electronic device, as Figure 8 shown, Figure 8 is a block diagram of an electronic device shown according to an exemplary embodiment.

[0143] As Figure 8 shown, the above-mentioned electronic device 300 includes:

[0144] A memory 310 and a processor 320, and a bus 330 connecting different components (including the memory 310 and the processor 320). The memory 310 stores a computer program, and when the processor 320 executes the program, the rate matching method and the rate dematching method described in the embodiments of the present disclosure are implemented.

[0145] The bus 330 represents one or more of several types of bus structures, including a memory bus or a memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any bus structure in a variety of bus structures. For example, these architectures include, but are not limited to, Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

[0146] The electronic device 300 typically includes a variety of electronic device-readable media. These media can be any available media accessible by the electronic device 300, including volatile and non-volatile media, removable and non-removable media.

[0147] The memory 310 may also include computer system readable media in the form of volatile memory, such as random access memory (RAM) 340 and / or cache memory 350. The electronic device 300 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the storage system 360 can be used for reading and writing on non-removable, non-volatile magnetic media ( Figure 8 not shown, commonly referred to as a "hard disk drive"). Although Figure 8 not shown in the figure, a disk drive for reading and writing on removable non-volatile disks (such as "floppy disks"), and an optical disk drive for reading and writing on removable non-volatile optical disks (such as CD-ROM, DVD-ROM or other optical media) can be provided. In these cases, each drive can be connected to the bus 330 through one or more data media interfaces. The memory 310 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of the embodiments of the present disclosure.

[0148] A program / utility 380 having a set (at least one) of program modules 370 can be stored, for example, in the memory 310. Such program modules 370 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. The program modules 370 generally perform the functions and / or methods in the embodiments described in the present disclosure.

[0149] The electronic device 300 can also communicate with one or more external devices 390 (such as a keyboard, a pointing device, a display 391, etc.), and can also communicate with one or more devices that enable a user to interact with the electronic device 300, and / or communicate with any device that enables the electronic device 300 to communicate with one or more other computing devices (such as a network card, a modem, etc.). Such communication can be carried out through the input / output (I / O) interface 392. Moreover, the electronic device 300 can also communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through the network adapter 393. As Figure 8 shown, the network adapter 393 communicates with other modules of the electronic device 300 through the bus 330. It should be understood that although Figure 8 not shown in the figure, other hardware and / or software modules can be used in combination with the electronic device 300, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0150] The processor 320 executes various functional applications and data processing by running programs stored in the memory 310.

[0151] It should be noted that for the implementation process and technical principle of the electronic device in this embodiment, refer to the foregoing explanations of the rate matching method and the rate dematching method in the embodiments of the present disclosure, which will not be elaborated here.

[0152] To implement the above embodiments, the present application also proposes a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the rate matching method and the rate dematching method described in the above embodiments are implemented.

[0153] To implement the above embodiments, the present disclosure also provides a computer program product. When the instructions in the computer program product are executed by a processor, the rate matching method and the rate dematching method described in the above embodiments are executed.

[0154] In the description of this specification, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present application, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0155] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0156] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A rate matching method, characterized in that, comprising: encoding the original bit stream to obtain an encoded bit stream; performing bit separation on the encoded bit stream to obtain a target information bit stream, a target parity bit stream, and a tail bit stream, where the tail bit stream includes the tail bits of the original information bit stream and the tail bits of the original parity bit stream, the target information bit stream and the tail bits of the original information bit stream constitute the original information bit stream, and the target parity bit stream and the tail bits of the original parity bit stream constitute the original parity bit stream; performing rate matching on the target parity bit stream to obtain a first matched bit stream; performing bit merging on the target information bit stream, the first matched bit stream, and the tail bit stream to obtain a second matched bit stream as the transmission bit stream.

2. The method according to claim 1, characterized in that, the performing bit separation on the encoded bit stream to obtain a target information bit stream, a target parity bit stream, and a tail bit stream includes: performing bit separation on the encoded bit stream to obtain the original information bit stream and the original parity bit stream; performing bit separation on the original information bit stream to obtain the target information bit stream and the tail bits of the original information bit stream; performing bit separation on the original parity bit stream to obtain the target parity bit stream and the tail bits of the original parity bit stream; performing bit merging on the tail bits of the original information bit stream and the tail bits of the original parity bit stream to obtain the tail bit stream.

3. The method according to claim 2, characterized in that, the original parity bit stream includes the original parity bit streams under N check branches, and the target parity bit stream includes the target parity bit streams under N check branches; the performing bit separation on the original parity bit stream to obtain the target parity bit stream and the tail bits of the original parity bit stream includes: performing bit separation on the original parity bit stream under the i-th check branch to obtain the target parity bit stream under the i-th check branch and the tail bits of the original parity bit stream under the i-th check branch, where N is a positive integer and i is a positive integer not greater than N.

4. The method according to claim 3, characterized in that, the performing bit merging on the tail bits of the original information bit stream and the tail bits of the original parity bit stream to obtain the tail bit stream includes: performing bit merging on the tail bits of the original information bit stream and the tail bits of the original parity bit streams under N check branches to obtain the tail bit stream.

5. The method according to claim 1, characterized in that, the target parity bit stream includes the target parity bit streams under N check branches, and the performing rate matching on the target parity bit stream to obtain a first matched bit stream includes: performing bit merging on the target parity bit streams under N check branches to obtain a first parity bit stream; Perform rate matching on the first parity bit stream to obtain the first matched bit stream.

6. The method according to claim 5, wherein, the performing rate matching on the first parity bit stream to obtain the first matched bit stream includes: obtaining a first number of bits of the first parity bit stream; obtaining a second number of bits of the first matched bit stream; obtaining a difference between the first number of bits and the second number of bits as a target number of bits to be deleted; deleting data of the target number of bits from the first parity bit stream to obtain the first matched bit stream.

7. The method according to claim 6, wherein, the obtaining the first number of bits of the first parity bit stream includes: obtaining a number of bits of the tail bit of the original information bit stream and a sum value of the number of bits of the original parity bit streams under N parity branches; obtaining a third number of bits of the tail bit stream; obtaining the first number of bits based on a difference between the sum value and the third number of bits.

8. The method according to any one of claims 1-7, wherein, the coded bit stream is obtained based on Turbo coding.

9. A rate dematching method, wherein, it includes: performing bit separation on a transmission bit stream to obtain a target information bit stream, a first matched bit stream and a tail bit stream, wherein the tail bit stream includes the tail bits of the original information bit stream and the tail bits of the original parity bit streams, the target information bit stream and the tail bits of the original information bit stream constitute the original information bit stream, and the target parity bit stream and the tail bits of the original parity bit streams constitute the original parity bit stream; performing rate dematching on the first matched bit stream to obtain the target parity bit stream; decoding the target information bit stream, the target parity bit stream and the tail bit stream to obtain an original bit stream.

10. A rate matching device, wherein, it includes: an encoding module for encoding an original bit stream to obtain a coded bit stream; a separation module for performing bit separation on the coded bit stream to obtain a target information bit stream, a target parity bit stream and a tail bit stream, wherein the tail bit stream includes the tail bits of the original information bit stream and the tail bits of the original parity bit streams, the target information bit stream and the tail bits of the original information bit stream constitute the original information bit stream, and the target parity bit stream and the tail bits of the original parity bit streams constitute the original parity bit stream; a matching module for performing rate matching on the target parity bit stream to obtain a first matched bit stream; a merging module for performing bit merging on the target information bit stream, the first matched bit stream and the tail bit stream to obtain a second matched bit stream as a transmission bit stream.

11. A rate dematching device, wherein, it includes: A separation module, configured to perform bit separation on a transmitted bit stream to obtain a target information bit stream, a first matching bit stream, and a tail bit stream, where the tail bit stream includes tail bits of an original information bit stream and tail bits of an original check bit stream, the tail bits of the target information bit stream and the original information bit stream form the original information bit stream, and the tail bits of the target check bit stream and the original check bit stream form the original check bit stream; A processing module, configured to perform rate dematching on the first matching bit stream to obtain the target check bit stream; A decoding module, configured to decode the target information bit stream, the target check bit stream, and the tail bit stream to obtain an original bit stream.

12. An electronic device, characterized in that, it includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the program, the method described in any one of claims 1-9 is implemented.

13. A computer-readable storage medium, on which a computer program is stored, characterized in that, when the computer program is executed by a processor, the method described in any one of claims 1-9 is implemented.

Images