Bit sequence processing method and related device

Abstract

According to the bit sequence processing method and the related device provided by the embodiment of the invention, the CCDM coding is introduced in the process of obtaining the bit sequence which can be used as modulation input, and the Gaussian-like distribution bit sequence which can be used as the modulation input can be obtained by utilizing the characteristics of the CCDM coding; therefore, constellation points in the constellation symbols obtained through final modulation can conform to Gaussian-like distribution, relevant performance gains can be obtained accordingly, and the theoretical limit of communication capacity can be further approached.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and specifically relates to some bit sequence processing methods, communication devices, chips, computer programs, etc. Background Art

[0002] With the continuous increase in the demand for wireless communication services, the industry has begun to explore transmission on higher-frequency spectrums to meet the future demand for the communication capacity of wireless communication systems. The higher propagation loss of high-frequency electromagnetic waves will limit the coverage range of base stations. To reduce the cost of base station deployment, more efficient wireless transmission solutions need to be sought.

[0003] Traditional wireless communication systems mostly use uniformly distributed bit sequences as modulation inputs, and obtain constellation symbols by performing modulation mapping on the bit sequences used as modulation inputs. There is still some room for optimization for traditional mechanisms from the theoretical limit of communication capacity. Summary of the Invention

[0004] Embodiments of this application disclose a bit sequence processing method and related devices.

[0005] In a first aspect of the embodiments of this application, a bit sequence processing method is provided, including: performing fixed composition distribution matching coding on a sub-bit sequence a2 with a length of k in a second bit sequence to obtain a sub-bit sequence a3 with a length of s, where the second bit sequence includes a sub-bit sequence a1 and a sub-bit sequence a2 with a length of k, the length of the second bit sequence is t, and k is less than or equal to t. Performing code block segmentation processing on the sub-bit sequence a3 with a length of s to obtain a sub-bit sequence a4; performing low-density parity-check code encoding processing on a third bit sequence to obtain a fourth bit sequence, where the third bit sequence includes the sub-bit sequence a1 and the sub-bit sequence a4; performing rate matching processing on the fourth bit sequence to obtain a fifth bit sequence, where every Q m -2 amplitude bits are adjacent to every 2 phase bits, and 1 constellation symbol is mapped from Q m bits, and the Q m bits for mapping to one constellation symbol include 2 phase bits and Q m -2 amplitude bits.

[0006] In the solution of the embodiments of this application, CCDM coding is introduced in the process of obtaining a bit sequence that can be used as a modulation input. Utilizing the characteristics of CCDM coding is beneficial to obtaining a bit sequence with a quasi-Gaussian distribution that can be used as a modulation input. Furthermore, it is beneficial to make the constellation points in the finally modulated constellation symbols conform to a quasi-Gaussian distribution. Furthermore, it is beneficial to obtain relevant performance gains accordingly, thereby being beneficial to further approaching the theoretical limit of communication capacity.

[0007] In some possible embodiments, performing block segmentation processing on the sub-bit sequence a3 with length s to obtain the sub-bit sequence a4 may include: performing deinterleaving processing on the sub-bit sequence a3 with length s.

[0008] Among them, performing deinterleaving processing on the sub-bit sequence a3 with length s includes: filling the s×1 bit vector corresponding to the sub-bit sequence a3 with length s into the first matrix column by column; flipping the first matrix row by row to obtain a second matrix; filling the second matrix into a s×1 column vector row by row to obtain the sub-bit sequence a4.

[0009] In some possible embodiments, performing rate matching processing on the fourth bit sequence to obtain the fifth bit sequence includes: performing interleaving processing on the fourth bit sequence;

[0010] Among them, performing interleaving processing on the fourth bit sequence includes: filling the c×1 bit vector corresponding to the fourth bit sequence into the third matrix; flipping the third matrix column by column to obtain a fourth matrix; filling the fourth matrix into a c×1 column vector row by row to obtain the fifth bit sequence, where c represents the length of the fourth bit sequence.

[0011] In the bit sequence obtained by CCDM coding, there is a certain arrangement relationship between the amplitude bits and the phase bits, and the arrangement relationship satisfies the relevant protocol modulation mapping rules. The interleaving operation in the traditional physical link may rearrange the bits and cause matching mismatch. In the CB segmentation processing process of the embodiment of the present application, the amplitude bits are deinterleaved in advance. While satisfying the "column out" characteristic of the traditional interleaving, a row flipping operation is added. At the same time, a column flipping operation is added during the interleaving process of rate matching. In this way, the overall interleaving process still satisfies column out, and at the same time, the originally paired amplitude bits and phase bits are still connected together.

[0012] In some possible embodiments, if then H(A) = r dm = h * , where

[0013] If then where k = t;

[0014] Among them, in the case of k = t, the length of the sub-bit sequence a1 is 0; in the case of k < t, the length of the sub-bit sequence a1 is greater than 0; the r dm represents the code rate of the fixed component distribution matching coding, the h * is the amplitude entropy of the optimal distribution, and the H(A) represents the amplitude entropy of the expected distribution.

[0015] It can be seen that in the solution of the embodiment of the present application, the lengths of the input / output bit sequences (input length k, input length s) of the CCDM coding can be flexibly allocated in combination with the transport block size according to link parameters (such as code rate) and the amplitude entropy of the expected distribution, etc., which is conducive to ensuring that the expected distribution can be achieved in the current transmission task.

[0016] In some possible implementation manners, the second bit sequence is a bit sequence attached with cyclic redundancy check; the method further includes: scrambling the fifth bit sequence to obtain a sixth bit sequence, where the phase bits in the sixth bit sequence are scrambled but the amplitude bits in the sixth bit sequence are not scrambled.

[0017] It can be seen that in the solution of the embodiment of the present application, for the CCDM coding, if a conventional scrambling operation is adopted, it may change the bit probability problem after shaping. Therefore, in combination with the pseudo-random property of the bit sequence output by the CCDM coding, only the phase bits are scrambled, which is conducive to being compatible with the bit probability distribution of the CCDM coding and the pseudo-random property of the bit scrambling, and obtaining a dual gain effect.

[0018] In some possible implementation manners, the method further includes: mapping every consecutive Q m bits in the sixth bit sequence to 1 constellation symbol.

[0019] In some possible implementation manners, the second bit sequence is a bit sequence attached with cyclic redundancy check and scrambled; the method further includes: mapping every consecutive Q m bits in the fifth bit sequence to 1 constellation symbol.

[0020] The second aspect of the embodiment of the present application provides a communication device, including: a processor and a memory;

[0021] The memory is used to store a computer program; the processor is used to call the computer program in the memory to implement the method according to any one of claims 1 to 7.

[0022] The third aspect of the embodiment of the present application provides a computer storage medium, which is used to store a computer program; when the computer program is executed by hardware, it is used to implement the method according to any one of claims 1 to 7.

[0023] The fourth aspect of the embodiment of the present application provides a computer program, which when executed by hardware, is used to implement the method according to any one of claims 1 to 7.

[0024] A fifth aspect of the embodiments of the present application provides a chip, which is used to implement the method according to any one of claims 1 to 7. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 FIG. is a schematic diagram of performance simulation comparison provided by an embodiment of the present application.

[0026] Figure 2A FIG. is a schematic structural diagram of a communication device provided by an embodiment of the present application.

[0027] Figure 2B FIG. is a schematic structural diagram of another communication device provided by an embodiment of the present application.

[0028] Figure 3A FIG. is a schematic flowchart of a method for processing a bit sequence provided by an embodiment of the present application.

[0029] Figure 3B FIG. is a schematic diagram of performing fixed component distribution matching encoding on a bit sequence provided by an embodiment of the present application.

[0030] Figure 3C FIG. is a schematic diagram of performing deinterleaving processing on a bit sequence provided by an embodiment of the present application.

[0031] Figure 3D FIG. is a schematic diagram of performing interleaving processing on a bit sequence provided by an embodiment of the present application.

[0032] Figure 3E FIG. is a schematic diagram of bit scrambling processing provided by an embodiment of the present application.

[0033] Figure 3F FIG. is a schematic diagram of bit sequence length transformation provided by an embodiment of the present application.

[0034] Figure 4 FIG. is a schematic flowchart of a method for processing a bit sequence provided by an embodiment of the present application.

[0035] Figure 5 FIG. is a schematic structural diagram of another communication device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0036] The terms "first", "second", etc. in the specification, claims and drawings of the present application are used to distinguish different objects, rather than to describe a specific order. The terms "comprising" and "having", and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or devices.

[0037] Reference to embodiments in this text means that the specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The appearance of this phrase at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0038] Traditional wireless communication systems mostly use uniformly distributed bit sequences as modulation inputs, and obtain constellation symbols by performing modulation mapping on the bit sequences used as modulation inputs. It has been found in practice that there is still room for optimization in the traditional mechanism from the theoretical limit of communication capacity. The inventors of the present application have found through a large amount of research that by transforming the modulation input from a uniformly distributed bit sequence into a bit sequence with a Gaussian-like distribution, relevant shaping gains can be obtained, which is conducive to further approaching the theoretical limit of communication capacity. For example, see Figure 1 , Figure 1 for a performance simulation comparison example of using a bit sequence with a Gaussian-like distribution and a bit sequence with a uniform distribution as modulation inputs. Among them, the performance curves of the bit sequence with a uniform distribution under different modulation methods can be exemplified by Y1, Y2, Y3, and Y4. The performance curve of using a bit sequence with a Gaussian-like distribution as the modulation input can be exemplified by Y0. The figure exemplifies that the performance difference between using a bit sequence with a Gaussian-like distribution and a bit sequence with a uniform distribution as the modulation input is at least about 1.5 dB.

[0039] Therefore, how to obtain a bit sequence with a Gaussian-like distribution as the modulation input is a very worthy research topic. The inventors of the present application have found through a large amount of research and testing that the Constant Composition Distribution Matching (CCDM) coding technique can be used to transform a uniformly distributed bit sequence into a bit sequence that conforms to a set distribution rule (a bit sequence that conforms to a set distribution rule can include, for example, a bit sequence with a Gaussian-like distribution). Therefore, the CCDM coding technique can be used to obtain a bit sequence with a Gaussian-like distribution that can be used as a modulation input, which in turn is conducive to making the constellation points in the finally modulated constellation symbols conform to a Gaussian-like distribution, and thus is conducive to obtaining relevant performance gains accordingly, and further approaching the theoretical limit of communication capacity.

[0040] Next, under the condition that parameters such as the transport block size, code rate, and modulation method are given, how to obtain a bit sequence with a Gaussian-like distribution that can be used as a modulation input will be discussed. If a bit sequence with a Gaussian-like distribution is used as the modulation input, it is possible to make the constellation points in the finally modulated constellation symbols conform to a Gaussian-like distribution, and thus obtain relevant performance gains accordingly.

[0041] See Figure 2A and Figure 2B , embodiments of the present application first provide schematic diagrams of the architectures of several communication devices. Figure 2A In [reference], the communication device 100 may include a CRC attachment unit 101, a CCDM encoding unit 102, a CB segmentation unit 103, an LDPC encoding unit 104, a rate matching unit 105, and a scrambling unit 106. The quantity flow in the communication device 100 is as shown in Figure 2A For example, a bit sequence is input from the CRC attachment unit 101 and output after passing through the CRC attachment unit 101, the CCDM encoding unit 102, the CB segmentation unit 103, the LDPC encoding unit 104, the rate matching unit 105, and the scrambling unit 106 in sequence. Figure 2B In [reference], the communication device 200 includes a CRC attachment unit 201, a scrambling unit 206, a CCDM encoding unit 202, a CB segmentation unit 203, an LDPC encoding unit 204, and a rate matching unit 205. The quantity flow in the communication device 200 is as shown in Figure 2B For example, a bit sequence is input from the CRC attachment unit 201 and output after passing through the scrambling unit 206, the CCDM encoding unit 202, the CB segmentation unit 203, the LDPC encoding unit 204, and the rate matching unit 205 in sequence.

[0042] It can be understood that when using the communication device 100, scrambling can be performed after CCDM encoding of the bit sequence, while when using the communication device 200, scrambling can be performed before CCDM encoding of the bit sequence.

[0043] It can be understood that the communication device may also have other structures. For example, the communication device may include a processor and a memory; the memory is used to store computer programs; the processor is used to call the computer programs in the memory to implement some or all of the steps of any method in the embodiments of the present application. The functions of some or all of the units in the communication device may also be implemented by a chip. The specific product form of the communication device is not limited herein.

[0044] Next, some bit sequence processing methods in the embodiments of the present application are introduced. It can be understood that the bit sequence processing methods provided in the embodiments of the present application can be implemented in the communication device with the architecture shown in Figure 2A or Figure 2B For example, it can also be implemented in communication devices with other architectures. The embodiments of the present application do not limit this.

[0045] See Figure 3A , Figure 3A which is a schematic flowchart of a bit sequence processing method provided in the embodiments of the present application. A bit sequence processing method may include:

[0046] 301. Perform Cyclic Redundancy Check (CRC) attachment processing on the first bit sequence to obtain a second bit sequence. The second bit sequence includes a sub-bit sequence a1 and a sub-bit sequence a2 of length k, where k is less than or equal to t. The length of the first bit sequence is the transport block length t0, and the CRC overhead = t - t0.

[0047] It can be understood that when the transport block length t0 and the CRC overhead are determined, then the value of t is also determined. Different CRC modes may have different CRC overheads. When the CRC mode is determined, the CRC overhead is also determined.

[0048] 302. Perform fixed composition distribution matching coding on the sub-bit sequence a2 of length k in the second bit sequence to obtain a sub-bit sequence a3 of length s.

[0049] It can be understood that when k = t, it means that the length of the sub-bit sequence a1 is 0, which also means that the lengths of the sub-bit sequence a2 and the second bit sequence are the same, that is, the second bit sequence only includes the sub-bit sequence a2 and the sub-bit sequence a1 does not exist. At this time, the entire second bit sequence will be subjected to fixed composition distribution matching coding.

[0050] In addition, when k < t, it means that the length of the sub-bit sequence a1 is greater than 0, which also means that the length of the sub-bit sequence a2 is less than the length of the second bit sequence, that is, the sub-bit sequence a1 exists. At this time, a part of the second bit sequence (sub-bit sequence a2) will be subjected to fixed composition distribution matching coding, and the remaining sub-bit sequence a1 will not be subjected to fixed composition distribution matching coding.

[0051] See Figure 3B , Figure 3B illustrates the processing method of fixed composition distribution matching coding. The sub-bit sequence a2 of length k is first transformed into a non-uniform bit sequence of length n, and then the non-uniform bit sequence of length n is transformed into a sub-bit sequence a3 of length s.

[0052] 303. Perform Code Block (CB) segmentation processing on the sub-bit sequence a3 of length s to obtain a sub-bit sequence a4.

[0053] In some possible implementation manners, performing code block segmentation processing on the sub-bit sequence a3 of length s may include: performing deinterleaving processing on the sub-bit sequence a3 of length s.

[0054] Performing deinterleaving processing on the sub-bit sequence a3 of length s may include: filling the s×1 bit vector corresponding to the sub-bit sequence a3 of length s column by column in the first matrix; flipping the first matrix row by row to obtain a second matrix (flipping row by row means filling the 1st, 2nd, …, Q m -2 rows in the matrix into the Qth m -2, Q m -3, …, 1st rows); filling the second matrix row by row into an s×1 column vector to obtain a sub-bit sequence a4.

[0055] For example Figure 3C As an example, assume that the sub-bit sequence a3 includes 0 a 0 b 1 a 1 b 0 c 0 d 1 c 1 d , a total of 8 bits (the superscripts of the bits are mainly used to distinguish different bits). Then, the process of de-interleaving the sub-bit sequence a3 with length s can be as follows Figure 3C As an example Figure 3C Examples illustrate specific possible ways of filling by column, flipping by row, and filling by row.

[0056] 304. Performing low-density parity-check code encoding processing on the third bit sequence to obtain a fourth bit sequence, where the third bit sequence includes the sub-bit sequence a1 and the sub-bit sequence a4.

[0057] 305. Performing rate matching processing on the fourth bit sequence to obtain a fifth bit sequence, where every Q m -2 amplitude bits are adjacent to every 2 phase bits in the fifth bit sequence.

[0058] Wherein, 1 constellation symbol is mapped from Q m bits, and the Q m bits for mapping to one constellation symbol include 2 phase bits and Q m -2 amplitude bits.

[0059] In some possible implementation manners

[0060] Performing rate matching processing on the fourth bit sequence to obtain a fifth bit sequence, including: performing interleaving processing on the fourth bit sequence.

[0061] Wherein, performing interleaving processing on the fourth bit sequence may include:

[0062] filling the c×1 bit vector corresponding to the fourth bit sequence column by column into The third matrix; flipping the third matrix column - by - column to obtain a fourth matrix (the column - by - column flipping here is to move the phase bits filled in the right - hand column to the left - hand column to match the subsequent modulation rules, which echoes the row - by - row flipping operation on the bit sequence in the above de - interleaving process); filling the fourth matrix row - by - row into a c×1 column vector to obtain a fifth bit sequence, where c represents the length of the fourth bit sequence.

[0063] For example Figure 3D For illustration, assume that the fourth bit sequence includes amplitude bits 0 b 0 d 0 a 0 c 1 b 1 d 1 a 1 c and phase bits 0 1 0 2 0 3 0 4 , a total of 12 bits. Then, performing rate - matching processing on the fourth bit sequence to obtain the fifth bit sequence can be as Figure 3D For illustration, Figure 3D The example shows specific possible ways of filling by column, flipping by column, and filling by row. Figure 3D The example shows the interleaving process in the case of 64QAM modulation, and finally generates 2 64QAM constellation symbols 000011, where 0 b 0 d 、0 a 0 c 、1 b 1 d 、1 a 1 c can be mapped by one amplitude symbol respectively.

[0064] In some possible implementation manners,

[0065] If then H(A)=r dm =h * , where

[0066] If then where k = t;

[0067] where, in the case of k = t, the length of the sub - bit sequence a1 is 0; in the case of k < t, the length of the sub - bit sequence a1 is greater than 0. Wherein, the r dm represents the code rate of CCDM coding, the h * is the amplitude entropy of the optimal distribution, and the H(A) represents the amplitude entropy of the expected distribution.

[0068] Among them, when usually indicates that the code rate setting of LDPC coding is relatively high. At this time, if this is conducive to obtaining the optimal distribution H(A)=h * .

[0069] Among them, when usually indicates that the code rate setting of LDPC coding is relatively low. It can be set that indicates that the second bit sequence has been all CCDM - coded. Theoretically, at this time, it satisfies h * >r dm , so it is still possible to adjust the distribution to the theoretical optimum of the mutual - information curve.

[0070] In addition, for the interleaving scheme, when it is required that every Q m - 2 amplitude bits are taken as a group and not scattered, the amplitude bits and phase bits can be interleaved separately, and the amplitude bits need to regard every Q m - 2 bits as a symbol and perform column - extraction. This interleaving scheme increases the interleaving granularity.

[0071] 306. Scramble the fifth bit sequence to obtain the sixth bit sequence. The phase bits in the sixth bit sequence are scrambled, but the amplitude bits in the sixth bit sequence are not scrambled.

[0072] Refer to Figure 3E , in Figure 3E the scenario shown in the example, the phase bits in the bit sequence are scrambled, but the amplitude bits in the bit sequence are not scrambled.

[0073] Furthermore, every consecutive Q m bits in the sixth bit sequence can be mapped to 1 constellation symbol.

[0074] The positive and negative of the real and imaginary parts of 1 constellation symbol are determined by the mapping of 1 phase bit respectively; the remaining Q m - 2 bits are amplitude bits, and the amplitudes of the real and imaginary parts are determined by the mapping of bits respectively.

[0075] As Figure 3F shown in the example, for the physical - layer link, for each transmission task (for example, it is required to transmit a transport block), the length c of the bit sequence to be modulated (such as the length of the sixth bit sequence is c) and the length t of the bit sequence after CRC attachment processing (such as the length of the second bit sequence is t) are both determined values. Then, the length of the amplitude bits in the sixth bit sequence is Among them, the length of the amplitude bits is determined by k and the code rate of the fixed - component distribution matching coding (code rate = s / k), The length s of the amplitude bits is equal to the length of the sub-bit sequence a3. The length of the phase bits in the fifth bit sequence is The phase bits are jointly determined by the sub-bit sequence a1 and the error correction code bits obtained by LDPC coding. For example, the length of the phase bits is less than or equal to the sum of the error correction code bits and the length of the sub-bit sequence a1. For example, the length of the phase bits is less than or equal to the sum of the error correction code bits and the length of the sub-bit sequence a1. For example, the phase bits = the error correction code bits + (the sub-bit sequence a1 - the LDPC puncturing bits), where the length of the sub-bit sequence a1 - the LDPC puncturing bits = t - k - z, and z represents the length of the LDPC puncturing bits.

[0076] In the solution of the embodiment of the present application, CCDM coding is introduced in the process of obtaining the bit sequence that can be used as the modulation input. Utilizing the characteristics of CCDM coding is beneficial to obtaining a bit sequence with a Gaussian-like distribution that can be used as the modulation input. Furthermore, it is beneficial to make the constellation points in the finally modulated constellation symbols conform to the Gaussian-like distribution, and thus it is beneficial to obtain relevant performance gains accordingly, thereby facilitating further approaching the theoretical limit of the communication capacity.

[0077] Furthermore, in the solution of the embodiment of the present application, in combination with the transport block size, the lengths of the input / output bit sequences of CCDM coding (input length k, input length s) can be flexibly allocated according to link parameters (such as code rate) and the amplitude entropy of the expected distribution, etc., which is beneficial to ensuring that the expected distribution can be achieved in the current transmission task.

[0078] In the bit sequence obtained by CCDM coding, there is a certain arrangement relationship between the amplitude bits and the phase bits, and the arrangement relationship satisfies the relevant protocol modulation mapping rules. The interleaving operation in the traditional physical link may cause a mismatch in rearrangement of the bits. In the solution of the embodiment of the present application, during the CB segmentation process, the amplitude bits are pre-deinterleaved. While satisfying the "column-first out" characteristic of the traditional interleaving, a row flipping operation is added, and a column flipping operation is added during the rate matching interleaving process. In this way, the overall interleaving process still satisfies column-first out, and at the same time, the originally paired amplitude bits and phase bits are still connected together.

[0079] Furthermore, in the solution of the embodiment of the present application, for CCDM coding, if a conventional scrambling operation is adopted, it may change the bit probability problem after shaping. Therefore, in combination with the pseudo-random property of the bit sequence output by CCDM coding, only the phase bits are scrambled, which is beneficial to compatible with the bit probability distribution of CCDM coding and the pseudo-random property of bit scrambling, and obtaining a dual gain effect.

[0080] See Figure 4 , Figure 4 is a schematic flowchart of another method for processing bit sequences provided by the embodiment of the present application. Another method for processing bit sequences may include:

[0081] 401. Perform cyclic redundancy check attachment processing on the first bit sequence to obtain a seventh bit sequence.

[0082] 402. Scramble the seventh bit sequence to obtain a second bit sequence.

[0083] The second bit sequence includes a sub-bit sequence a1 and a sub-bit sequence a2 of length k, where k is less than or equal to t. The length of the first bit sequence is the transport block length t0, and the CRC overhead = t - t0.

[0084] It can be understood that when the transport block length t0 and the CRC overhead are determined, then the value of t is also determined. Different CRC modes may have different CRC overheads. When the CRC mode is determined, the CRC overhead is also determined.

[0085] 403. Perform fixed composition distribution matching coding on the sub-bit sequence a2 of length k to obtain a sub-bit sequence a3 of length s.

[0086] It can be understood that when k = t, it means that the length of the sub-bit sequence a1 is 0, which also means that the lengths of the sub-bit sequence a2 and the second bit sequence are the same, that is, the second bit sequence only includes the sub-bit sequence a2 and the sub-bit sequence a1 does not exist. At this time, the entire second bit sequence will be subjected to fixed composition distribution matching coding.

[0087] In addition, when k < t, it means that the length of the sub-bit sequence a1 is greater than 0, which also means that the length of the sub-bit sequence a2 is less than the length of the second bit sequence, that is, the sub-bit sequence a1 exists. At this time, a part of the second bit sequence (sub-bit sequence a2) will be subjected to fixed composition distribution matching coding, and the remaining sub-bit sequence a1 will not be subjected to fixed composition distribution matching coding.

[0088] 404. Perform code block segmentation processing on the sub-bit sequence a3 of length s to obtain a sub-bit sequence a4.

[0089] In some possible implementation manners, performing code block segmentation processing on the sub-bit sequence a3 of length s may include: performing deinterleaving processing on the sub-bit sequence a3 of length s.

[0090] Performing deinterleaving processing on the sub-bit sequence a3 of length s may include: filling the s×1 bit vector corresponding to the sub-bit sequence a3 of length s column by column into the first matrix; flipping the first matrix row by row to obtain a second matrix (flipping row by row means that the 1st, 2nd,..., Q m -2 rows are filled into the Qth m -2, Qm -3, …, 1 row); Fill the second matrix row by row into an s×1 column vector to obtain a sub-bit sequence a4.

[0091] 405. Perform low-density parity-check code encoding on the third bit sequence to obtain a fourth bit sequence, where the third bit sequence includes the sub-bit sequence a1 and the sub-bit sequence a4.

[0092] 406. Perform rate matching on the fourth bit sequence to obtain a fifth bit sequence, where every Q m -2 amplitude bits are adjacent to every 2 phase bits.

[0093] where 1 constellation symbol is mapped from Q m bits, and the Q m bits for mapping one constellation symbol include 2 phase bits and Q m -2 amplitude bits.

[0094] In some possible implementation manners,

[0095] Performing rate matching on the fourth bit sequence to obtain a fifth bit sequence includes: performing interleaving on the fourth bit sequence.

[0096] Among them, performing interleaving on the fourth bit sequence may include:

[0097] Fill the c×1 bit vector corresponding to the fourth bit sequence column by column into the third matrix; Flip the third matrix column by column to obtain a fourth matrix (the column-by-column flip here is to move the phase bits filled in the right column to the left column to match the subsequent modulation rule, which corresponds to the row-by-row flip operation on the bit sequence in the above deinterleaving process); Fill the fourth matrix row by row into a c×1 column vector to obtain a fifth bit sequence, where c represents the length of the fourth bit sequence.

[0098] In some possible implementation manners,

[0099] If then H(A) = r dm = h * , where

[0100] If then where k = t;

[0101] Among them, in the case of k = t, the length of the sub-bit sequence a1 is 0; in the case of k < t, the length of the sub-bit sequence a1 is greater than 0. Among them, the r dmrepresents the code rate of the CCDM coding, where h * is the amplitude entropy of the optimal distribution, and H(A) represents the amplitude entropy of the expected distribution.

[0102] Among them, when it usually means that the code rate setting of the LDPC coding is relatively high. At this time, if this is conducive to obtaining the optimal distribution H(A)=h * .

[0103] Among them, when it usually means that the code rate setting of the LDPC coding is relatively low, and it can be set that represents that the second bit sequence has been fully CCDM-coded. Theoretically, at this time, it satisfies h * >r dm , so it is still possible to adjust the distribution to the theoretical optimum of the mutual information curve.

[0104] In addition, for the interleaving scheme, when it is required that every Q m -2 amplitude bits are taken as a group without being scattered, the amplitude bits and phase bits can be interleaved separately, and the amplitude bits need to take every Q m -2 bits as a symbol and perform column extraction. This interleaving scheme increases the interleaving granularity.

[0105] For the physical layer link, for each transmission task (for example, it is required to transmit a transport block), the length c of the bit sequence to be modulated (such as the length of the sixth bit sequence is c) and the length t of the bit sequence after CRC attachment processing (such as the length of the second bit sequence is t) are both determined values. Then, the length of the amplitude bits in the sixth bit sequence is Among them, the length of the amplitude bits is determined by k and the code rate of the fixed component distribution matching coding (code rate = s / k), the length s of the amplitude bits is equal to the length of the sub-bit sequence a3. The length of the phase bits in the fifth bit sequence is the phase bits are jointly determined by the sub-bit sequence a1 and the error correction code bits obtained by LDPC coding. For example, the length of the phase bits is less than or equal to the length of the error correction code bits + the sub-bit sequence a1. For example, the length of the phase bits is less than or equal to the length of the error correction code bits + the sub-bit sequence a1. For example, the phase bits = the error correction code bits + (the sub-bit sequence a1 - the LDPC puncturing bits), where the length of the sub-bit sequence a1 - the LDPC puncturing bits = t - k - z, and z represents the length of the LDPC puncturing bits.

[0106] In the solution of the embodiment of the present application, CCDM coding is introduced in the process of obtaining the bit sequence that can be used as modulation input. Utilizing the characteristics of CCDM coding is beneficial to obtaining a bit sequence with a Gaussian-like distribution that can be used as modulation input. Furthermore, it is beneficial to make the constellation points in the finally modulated constellation symbols conform to the Gaussian-like distribution, and thus it is beneficial to obtain relevant performance gains accordingly, which is conducive to further approaching the theoretical limit of the communication capacity.

[0107] Furthermore, in the solution of the embodiment of the present application, the lengths of the input / output bit sequences of CCDM coding (input length k, input length s) can be flexibly allocated in combination with the transport block size according to link parameters (such as code rate) and the amplitude entropy of the expected distribution, etc., which is beneficial to ensuring that the expected distribution can be achieved in the current transmission task.

[0108] In the bit sequence obtained by CCDM coding, there is a certain arrangement relationship between the amplitude bits and the phase bits, and the arrangement relationship satisfies the relevant protocol modulation mapping rules. The interleaving operation in the traditional physical link may cause a matching mismatch by rearranging the bits. In the solution of the embodiment of the present application, during the CB segmentation process, the amplitude bits are pre-deinterleaved. While satisfying the "column-first output" characteristic of the traditional interleaving, a row flipping operation is added, and a column flipping operation is added during the interleaving process of rate matching. In this way, the overall interleaving process still satisfies column-first output, and at the same time, the originally paired amplitude bits and phase bits are still connected together.

[0109] See Figure 5 , the embodiment of the present application also provides a communication device 500, including: a processor 510 and a memory 520.

[0110] The memory 520 is used to store a computer program; the processor 510 is used to call the computer program in the memory to implement part or all of the steps of any method of the embodiment of the present application.

[0111] Among them, the processor 510 may include one or more processing cores. The processor 510 connects various parts within the entire electronic device 510 through various interfaces and circuits. By running or executing instructions, programs, code sets, or instruction sets stored in the memory 520, and by calling the data stored in the memory 520, it performs various functions of the communication device 500 and processes data. Optionally, the processor 510 may be implemented in at least one hardware form among digital signal processing (DSP), field programmable gate array (FPGA), and programmable logic array (PLA). The processor 510 may integrate a combination of one or several of a central processing unit (CPU), a graphics processing unit (GPU), and a modem, etc. It can be understood that the above-mentioned modem may not be integrated into the processor 510 and may be implemented separately through a communication chip.

[0112] The memory 520 may include a random access memory (RAM) and may also include a read-only memory. The memory 520 is used to store instructions, programs, code, code sets, or instruction sets. The memory 520 may include a program storage area and a data storage area. The program storage area may store instructions for implementing an operating system, instructions for implementing at least one function, instructions for implementing the above various method examples, etc. The data storage area may also store data created during the use of the communication device 500.

[0113] It can be understood that the communication device 500 may include more or fewer structural elements than those in the above structural block diagram, such as a power module, physical buttons, a WiFi (Wireless Fidelity) module, a speaker, a Bluetooth module, sensors, etc., which are not limited herein.

[0114] The embodiment of the present application also provides a computer storage medium for storing a computer program; when the computer program is executed by hardware, it is used to implement some or all of the steps of any method in the embodiment of the present application.

[0115] The embodiment of the present application also provides a chip that can be used to implement some or all of the steps of any method in the embodiment of the present application.

[0116] The embodiments of the present application also provide a computer program, which, when executed by hardware, is used to implement some or all of the steps of any one of the methods of the embodiments of the present application.

[0117] It should be understood that in various embodiments of the present application, the order of the above-mentioned processes does not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0118] In several embodiments provided by the present application, it should be understood that the disclosed methods, devices and systems can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation; for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point, the displayed or discussed mutual coupling or direct coupling or communication connection can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be in electrical, mechanical or other forms.

[0119] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place, or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0120] In addition, in each embodiment of the present invention, the functional units can be integrated into a processing unit, or each unit can be physically included separately, or two or more units can be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware, or in the form of hardware plus software functional units.

[0121] The above-mentioned integrated units implemented in the form of software functional units can be stored in a computer-readable storage medium. The above-mentioned software functional units are stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server or a network device, etc.) to execute some steps of the methods described in each embodiment of the present invention. The foregoing storage medium may include: USB flash drive, mobile hard disk, magnetic disk, optical disk, volatile memory or non-volatile memory.

[0122] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions without departing from the spirit and scope of the present invention, and can make various modifications and alterations, including combinations of the above different functions and implementation steps, including software and hardware implementation manners, all within the disclosure scope of the present invention.

Claims

1. A method for processing a bit sequence, characterized in that, comprising: performing fixed-component distribution matching coding on a sub-bit sequence a2 of length k in a second bit sequence to obtain a sub-bit sequence a3 of length s, where the second bit sequence includes a sub-bit sequence a1 and a sub-bit sequence a2 of length k, the length of the second bit sequence is t, and k is less than or equal to t; performing code block segmentation processing on the sub-bit sequence a3 of length s to obtain a sub-bit sequence a4; performing low-density parity-check code encoding processing on a third bit sequence to obtain a fourth bit sequence, where the third bit sequence includes the sub-bit sequence a1 and the sub-bit sequence a4; Perform rate matching processing on the fourth bit sequence to obtain a fifth bit sequence, where every Q m -2 amplitude bits are adjacent to every 2 phase bits. Among them, 1 constellation symbol is mapped from Q m bits, and the Q m bits for mapping one constellation symbol include 2 phase bits and Q m -2 amplitude bits.

2. The method according to claim 1, characterized in that, the performing code block segmentation processing on the sub-bit sequence a3 of length s to obtain a sub-bit sequence a4 includes: performing deinterleaving processing on the sub-bit sequence a3 of length s; Among them, deinterleaving the sub-bit sequence a3 with a length of s includes: filling the s×1 bit vector corresponding to the sub-bit sequence a3 with a length of s into the first matrix by columns ; flipping the first matrix row by row to obtain a second matrix; filling the second matrix into an s×1 column vector row by row to obtain the sub-bit sequence a4.

3. The method according to claim 2, characterized in that, performing rate matching processing on the fourth bit sequence to obtain a fifth bit sequence includes: performing interleaving processing on the fourth bit sequence; Among them, performing interleaving processing on the fourth bit sequence includes: filling the c×1 bit vector corresponding to the fourth bit sequence into the third matrix by column; flipping the third matrix by column to obtain a fourth matrix; filling the fourth matrix into a c×1 column vector by row to obtain a fifth bit sequence, where c represents the length of the fourth bit sequence.

4. The method according to claim 3, characterized in that, If then H(A) = r dm = h * , where If then where k = t; Among them, the length of the sub-bit sequence a1 is 0 when k = t; the length of the sub-bit sequence a1 is greater than 0 when k < t; the r dm represents the code rate of the fixed component distribution matching coding, the amplitude entropy of the h* optimal distribution, and the H(A) represents the amplitude entropy of the expected distribution.

5. The method according to any one of claims 1 to 4, characterized in that, the second bit sequence is a bit sequence attached with cyclic redundancy check; the method further includes: performing scrambling processing on the fifth bit sequence to obtain a sixth bit sequence, where the phase bits in the sixth bit sequence are scrambled but the amplitude bits in the sixth bit sequence are not scrambled.

6. The method according to claim 5, characterized in that, The method further includes: mapping every consecutive Q m bits in the sixth bit sequence to one constellation symbol.

7. The method according to any one of claims 1 to 4, characterized in that, The second bit sequence is a bit sequence subjected to cyclic redundancy check attachment processing and scrambling processing; the method further includes: mapping every consecutive Q m bits in the fifth bit sequence to one constellation symbol.

8. A communication device, characterized in that, comprising: a processor and a memory; the memory is used for storing a computer program; the processor is used for calling the computer program in the memory to implement the method according to any one of claims 1 to 7.

9. A computer storage medium, characterized in that, the computer storage medium is used for storing a computer program; when the computer program is executed by hardware, it is used to implement the method according to any one of claims 1 to 7.

10. A computer program, characterized in that, when the computer program is executed by hardware, it is used to implement the method according to any one of claims 1 to 7.

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