High-reliability downlink telemetering baseband signal code rate recovery system and method

Abstract

The invention relates to the technical field of satellite remote control and telemetering, in particular to a high-reliability downlink telemetering baseband signal code rate recovery system and method. Comprising a programmable logic device FPGA, a FLASH memory and a reset module, the programmable logic device FPGA and the FLASH memory are interconnected through an address line, a data line and a control line, and the reset module is used for outputting power-on reset signals to the programmable logic device FPGA and the FLASH memory after a power supply is powered on; the programmable logic device FPGA stores an initial rate through high and low level states of an IO pin of the programmable logic device FPGA; the programmable logic device FPGA controls the storage default rate of an internal digital logic circuit by using a hardware description language; according to the method, three-level reliability measures, namely an application level, a model level and a product level, are adopted; the three measures complement each other to jointly ensure that the service continuity can be ensured when a first fault occurs and the safety can be ensured when a second fault occurs under any condition.

Description

Technical Field

[0001] The present invention relates to the technical field of satellite remote control and telemetry, and particularly relates to a high-reliability downlink telemetry baseband signal code rate recovery system and method. Background Art

[0002] The satellite TT&C system is a complex and delicate system, and its core components mainly include the space segment and the ground segment. The main body of the space segment lies in the communication equipment carried on the spacecraft, which is responsible for communicating with the ground in space and is the bridge for information transmission. The ground segment is mainly responsible for receiving signals from the satellite, demodulating, decoding and processing them. At the same time, the ground segment can also send commands and data to the satellite to achieve remote control of the satellite.

[0003] In the satellite TT&C system, the downlink plays a crucial role. It transmits downlink telemetry data from the spacecraft to the ground, and these data are important bases for analyzing the working state of the spacecraft and preventing failures, and play a decisive role in the safe operation of the spacecraft in orbit. Therefore, the reliability requirements for the downlink telemetry data transmission process are extremely high, and any data loss or error may have a significant impact on the operation of the spacecraft.

[0004] Each subsystem on the spacecraft will collect various telemetry data in real time. These data are processed by the telemetry and remote control unit carried on the spacecraft to complete the conversion of the baseband signal, and then are sent to the transponder device. In the transponder, the baseband signal is converted into a radio frequency signal for transmission in space. Finally, these radio frequency signals are sent to the ground TT&C station through the TT&C channel, and are received and processed by the ground TT&C station.

[0005] With the increasing complexity of space missions, the requirements for the flexibility of the TT&C system are also getting higher and higher. To meet this demand, the spacecraft needs to have the ability to reliably and stably support variable code rates of the downlink telemetry baseband signal in orbit. In this way, no matter how the mission changes, the spacecraft can adjust the transmission rate of the downlink telemetry data according to the demand to ensure the efficiency and accuracy of data transmission.

[0006] However, in the complex space environment, the telemetry and remote control unit on the spacecraft may be affected by various interferences, resulting in reset and restart. Once the telemetry and remote control unit resets and restarts, it is necessary to ensure that the baseband signal code rate of each downlink telemetry output channel (the baseband signal code rate is the communication rate between the telemetry and remote control unit and the transponder) can be reliably restored to the final value set last time. This is because if the code rates do not match, the ground station will not be able to correctly receive and process the data from the spacecraft, thus affecting the continuity and security of the service. Summary of the Invention

[0007] The present invention provides a high-reliability downlink telemetry baseband signal code rate recovery system and method, aiming to solve the problem that after the existing telemetry and remote control unit is reset and restarted, the baseband signal code rate of each downlink telemetry output channel cannot be reliably restored to the last finally set value, resulting in the inability to ensure continuous and safe operation of services.

[0008] To achieve the above object, the technical solution of the present invention is as follows:

[0009] The present invention provides a high-reliability downlink telemetry baseband signal code rate recovery system and method, including a programmable logic device FPGA, a FLASH memory, and a reset module. The programmable logic device FPGA is interconnected with the FLASH memory through address lines, data lines, and control lines. The reset module is used to output a power-on reset signal to the programmable logic device FPGA and the FLASH memory after the power is turned on;

[0010] Among them, the programmable logic device FPGA stores the initial rate through the high and low level states of its IO pins, with every 2 bits as a group, and each group represents a different initial rate; at the same time, the programmable logic device FPGA controls its internal digital logic circuit to store the default rate by using a hardware description language;

[0011] In addition, the programmable logic device FPGA further includes:

[0012] A proportional instruction receiving module, which is used to receive the proportional instruction sent by the ground and judge the correctness of the proportional instruction; if the proportional instruction is correct, it will send the proportional instruction to the following downlink telemetry code rate control module;

[0013] A reset management module, which is used to receive the power-on reset signal and control the programmable logic device FPGA to be in a reset state;

[0014] A downlink telemetry code rate control module, which is used to change the baseband signal code rate of the corresponding downlink telemetry output channel according to the proportional instruction sent by the proportional instruction receiving module, the initial rate, or the default rate;

[0015] An important data storage module, which is connected to the FLASH memory and is used to write the baseband signal code rate of each downlink telemetry output channel into the FLASH memory three times respectively; in addition, when reading a certain baseband signal code rate from the FLASH memory, a two-out-of-three comparison is performed bit by bit to judge whether the data reading is correct;

[0016] A telemetry packetizing and transmitting module, which is used to implement downlink telemetry data acquisition and output downlink telemetry data to the transponder.

[0017] Furthermore, the FLASH memory is a non-volatile memory FLASH.

[0018] Further, the reset module includes a power supply monitoring chip.

[0019] A method for recovering the baseband signal code rate of downlink telemetry after reset specifically includes the following steps:

[0020] S11. After the telemetry and remote control unit restarts due to power anomaly, the reset module outputs a power-on reset signal to make the programmable logic device FPGA and the FLASH memory in a reset state; when the reset signal is withdrawn, the programmable logic device FPGA and the FLASH memory start to work;

[0021] S12. The important data storage module of the programmable logic device FPGA sequentially reads the baseband signal code rates of each downlink telemetry output channel from the FLASH memory, and sequentially performs a two-out-of-three comparison bit by bit on the read baseband signal code rates of each downlink telemetry output channel to determine whether the data reading is correct; if the read data of the baseband signal code rate of a certain downlink telemetry output channel is incorrect, then execute S13, and at the same time set the failure flag for the baseband signal code rate recovery from the FLASH, and this telemetry flag is written into the insertion field in the telemetry frame; if the read data of the baseband signal code rate of a certain downlink telemetry output channel is correct, send the correct baseband signal code rate data of this downlink telemetry output channel to the downlink telemetry code rate control module and then execute S15; if all reads are correct, set the success flag for the baseband signal code rate recovery from the FLASH.

[0022] S13. The downlink telemetry code rate control module reads the initial rate of the downlink telemetry output channel. If the read initial rate meets the specified value, then execute S15; if the read initial rate does not meet the specified value, then execute S14;

[0023] S14. The downlink telemetry code rate control module reads the default rate of the downlink telemetry output channel, and then executes S15;

[0024] S15. The downlink telemetry code rate control module recovers the baseband signal code rate of the corresponding downlink telemetry output channel according to the obtained baseband signal code rate data;

[0025] S16. Loop and execute S12 to S15 until the baseband signal code rate of each downlink telemetry output channel is recovered.

[0026] A method for setting the baseband signal code rate of downlink telemetry specifically includes the following steps:

[0027] S21. The proportional instruction receiving module receives the proportional instruction sent by the ground;

[0028] The proportional command receiving module determines the correctness of the proportional command. If it does not conform to the command encoding of the rate switching command, execute S23; if it conforms to the command encoding of the rate switching command, execute S24;

[0029] S23. The proportional command receiving module regards this proportional command as an incorrect command, increments the incorrect proportional command count in the telemetry data, and the programmable logic device FPGA does not change the rate information stored in the FLASH memory, and at the same time does not change the baseband signal code rate of each downlink telemetry output channel;

[0030] S24. The downlink telemetry code rate control module changes the baseband signal code rate of the corresponding downlink telemetry output channel to the command set value, and increments the correct proportional command count in the telemetry data;

[0031] S25. The important data storage module stores the judged correct rate information in the FLASH memory or updates the stored rate data in the FLASH memory;

[0032] S26. After the rate data storage is completed, the important data storage module reads the data stored in the FLASH memory for consistency comparison, and sets the "baseband signal code rate command setting status" telemetry. If they are consistent, then set the storage success flag. If they are inconsistent, then set the storage failure flag and write it into the insertion field in the telemetry frame.

[0033] The beneficial effects achieved by the present invention are as follows:

[0034] The present invention can flexibly change the baseband signal code rate of each downlink telemetry before launch or in orbit according to mission requirements. This feature greatly enhances the adaptability of the satellite TT&C system to different mission scenarios, ensures the accurate matching of data transmission efficiency and mission requirements, and improves resource utilization efficiency.

[0035] Most importantly, in view of the fact that spacecraft are vulnerable to complex space environments, the present invention adopts three-level reliability measures, namely application level, model level, and product level; these three-level measures complement each other and jointly ensure that in any case, especially after the telemetry and telecontrol unit is reset, the downlink telemetry code rate can be restored to the previous final set value after the reset ends; the purpose of ensuring service continuity when a single fault occurs and ensuring safety when a double fault occurs is achieved. Description of the Drawings

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0037] Figure 1 It is a schematic structural diagram of the code rate recovery system disclosed by the present invention.

[0038] Figure 2 It is a flowchart of the code rate recovery of the baseband signal after reset in the present invention.

[0039] Figure 3 It is a flowchart of setting the baseband signal code rate through instructions in the present invention. Specific embodiments

[0040] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0041] In addition, if there are descriptions such as "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the meaning of "and / or" appearing throughout the text is that it includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, or solution B, or a solution that satisfies both A and B at the same time. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0042] The present invention provides a highly reliable downlink telemetry baseband signal code rate recovery system, which is set on an existing spacecraft and is used to control the baseband signal code rate of each downlink telemetry output channel, and is also used to restore the baseband signal code rate of each downlink telemetry output channel to the last final set value after the telemetry and telecommand unit carried on the spacecraft is reset and restarted; the present invention solves the problem that the downlink telemetry code rate cannot be reliably restored to the last final set value after the telemetry and telecommand unit carried on the existing spacecraft is reset and restarted.

[0043] As Figure 1 shown, the baseband signal code rate recovery system includes a programmable logic device FPGA, a FLASH memory, and a reset module. The programmable logic device FPGA is interconnected with the FLASH memory through address lines, data lines, and control lines. The reset module is used to output a power-on reset signal to the programmable logic device FPGA and the FLASH memory after the power is turned on;

[0044] Among them, the programmable logic device FPGA stores the initial rate through the high and low level states of its IO pins (specifically, the IO pins of the FPGA have configurable characteristics. By setting them to the input mode, the high and low level states input by the external circuit are read, that is, the high and low level states of the IO pins; since the circuits that can output high and low levels are relatively common and simple, the specific structure will not be described in this article). Every 2 bits form a group, and each group represents the initial rate of a different downlink telemetry output channel; at the same time, the programmable logic device FPGA controls its internal digital logic circuit to store the default rate by using a hardware description language; the number of the initial rate and the default rate is the same as the number of downlink telemetry output channels, and both the initial rate and the default rate are baseband signal code rates set before leaving the factory; the storage positions of the initial rate and the default rate of different downlink telemetry output channels are also set before leaving the factory to facilitate accurate and fast reading after the system is reset;

[0045] In addition, the programmable logic device FPGA includes:

[0046] A proportional instruction receiving module, which is used to receive the proportional instruction sent by the ground and judge the correctness of the proportional instruction; if the proportional instruction is correct, the proportional instruction is sent to the following downlink telemetry code rate control module;

[0047] A reset management module, which is used to receive the power-on reset signal and control the programmable logic device FPGA to be in the reset state;

[0048] A downlink telemetry code rate control module, which is used to change the baseband signal code rate of the corresponding downlink telemetry output channel according to the proportional instruction sent by the proportional instruction receiving module, or the initial rate or the default rate;

[0049] An important data storage module, which is connected to the FLASH memory and is used to write the baseband signal code rate of each downlink telemetry output channel into the FLASH memory three times respectively; in addition, when reading a certain baseband signal code rate from the FLASH memory, a two-out-of-three comparison is performed bit by bit to judge whether the data reading is correct;

[0050] The telemetry packetizing and transmission module is used to implement the acquisition of downlink telemetry data and output the downlink telemetry data to the transponder.

[0051] To introduce this embodiment in detail, an example is given where nine downlink telemetry output channels need to restore three baseband signal code rate states after product reset; among them, the nine downlink telemetry output channels need to occupy twenty-seven independent sectors in the FLASH memory, and each downlink telemetry output channel corresponds to an initial rate and a default rate; it should be noted that the nine downlink telemetry output channels and the three baseband signal code rate states here are only for illustrative purposes and do not limit the quantity.

[0052] The programmable logic device FPGA is interconnected with the FLASH memory through address lines, data lines and control lines. Through the "important data storage module" inside the programmable logic device FPGA, the storage and acquisition of the baseband signal code rate data of each downlink telemetry output channel are realized. The programmable logic device FPGA receives the scaling instructions sent from the ground through its internal "scaling instruction receiving module" and judges the correctness of the scaling instructions (judging the correctness according to the pre-agreed scaling instruction format). After the judgment is correct, the baseband signal code rate of the corresponding downlink telemetry output channel is immediately switched to the corresponding code rate. Among them, each scaling instruction includes four bytes, and a total of twenty-seven scaling instructions are designed to realize the three-code rate switching of the nine downlink telemetry output channels of the telemetry and remote control unit, that is, one scaling instruction corresponds to one code rate switching of one downlink telemetry output channel; each scaling instruction is manually defined, such as EB, 90, 01, 01, etc. After receiving the rate change instruction through the scaling instruction receiving module of the telemetry and remote control unit, the rate data stored in the FLASH is updated.

[0053] The initial rate is determined by the high and low level states of the IO pins of the FPGA. Every 2 bits form a group, and each group represents an initial rate; for example, assume that before leaving the factory, the program of the programmable logic device FPGA defines three rates from high to low: 01b, 10b, 11b, then reading other values except these three states are all error values. The initial rate is set before the telemetry and remote control unit leaves the factory and is responsible for being read by the downlink telemetry code rate control module. Nine initial rates are required for the nine downlink telemetry output channels.

[0054] The FLASH memory is a non-volatile FLASH memory. The storage of telemetry rate in the FLASH memory adopts a triple-backup design. The rates of each downlink telemetry output channel are respectively stored in three independent sectors of the FLASH memory. The rates of N downlink telemetry output channels altogether occupy 3N independent sectors of the FLASH memory. In this embodiment, the nine downlink telemetry output channels altogether occupy twenty-seven sectors. In addition, the position where each downlink telemetry output channel stores data in the FLASH is known. Therefore, when the important data storage module reads data, it can directly read the baseband signal code rate of the corresponding downlink telemetry output channel. When the important data storage module reads the code rate of a certain downlink telemetry output channel from the FLASH memory, it will simultaneously read out three copies of the baseband signal code rate, and perform a two-out-of-three bitwise comparison on the three copies of the baseband signal code rate to exclude error values and prevent the data stored in the FLASH memory from being incorrect and resulting in an incorrect rate being read. If the three values read are all different, it means that the data reading from the FLASH memory fails.

[0055] The reset module includes a power supply monitoring chip, and the power supply monitoring chip can adopt the JSR706SD chip. In addition to supporting power-on (the power-on reset time is 200 ms) and power-off reset, the JSR706SD chip can also monitor the power supply. It monitors +3.3V. When +3.3V drops below +2.93V, the chip generates a reset signal to make the single board in a reset state to prevent abnormalities caused by power fluctuations. Naturally, other reset chips with similar functions can also be used for the power supply monitoring chip, and they are not listed one by one in this embodiment.

[0056] After the product is powered on, the reset module outputs a power-on reset signal. The power-on reset signal makes the programmable logic device FPGA and the non-volatile memory FLASH in a reset state. When the reset signal is cancelled, the FPGA and the FLASH start to work. After the reset signal is processed by the "reset management module" inside the programmable logic device FPGA for "asynchronous reset and synchronous cancellation", it is instantiated to the global clock network to perform a reset initialization operation on all signals and restore the internal flip-flops of the FPGA to their initial values.

[0057] The programmable logic device FPGA completes the restoration and control of the telemetry code rate through its internal "downlink telemetry code rate control module".

[0058] The programmable logic device FPGA completes the acquisition of telemetry data and outputs downlink telemetry data to the transponder through its internal "telemetry packetization and transmission module".

[0059] Generally speaking, the code rate recovery system disclosed by the present invention adopts three-level reliability measures in the process of code rate recovery of the downlink telemetry baseband signal, namely the application level, the model level, and the product level. The telemetry rate recovery priorities are, from high to low, the application level, the model level, and the product level.

[0060] First, at the application level, a non-volatile memory NOR FLASH is used to store the downlink telemetry rate data. The downlink telemetry rate data stored in the FLASH adopts a two-out-of-three reliability measure. The data stored in the FLASH is triple-backed up, and a two-out-of-three comparison is performed bit by bit when reading.

[0061] The baseband signal code rate of the downlink telemetry output channel stored in the FLASH is set through a proportional instruction. After receiving each proportional instruction, first, the correctness of the instruction is judged according to the format. If it conforms to the instruction code of the rate switching instruction, the baseband signal code rate of the corresponding downlink telemetry output channel is changed to the value set by the instruction, and the correct proportional instruction count in the telemetry data is incremented by 1. The correct rate information is stored in the FLASH or used to update the rate data already stored in the FLASH. After the FLASH storage is completed, the data stored in the FLASH is read for consistency comparison, and the "PCM rate instruction setting status" telemetry is set. If they are consistent, then the storage success flag is set. If they are inconsistent, then the storage failure flag is set and written into the insertion field in the telemetry frame. If it does not conform to the instruction code of the rate switching instruction, it is considered an incorrect instruction. The incorrect proportional instruction count in the telemetry data is incremented by 1, the rate information stored in the FLASH is not changed, and at the same time, the baseband signal code rate of each downlink telemetry output channel is not changed.

[0062] Second, the model-level measure is to configure the hardware state of the IO pins of the programmable logic device FPGA to correspond to the initial rate of each downlink telemetry output channel. When the downlink telemetry rate data cannot be obtained from the NOR FLASH memory, the downlink telemetry code rate control module reads and adopts the initial rate.

[0063] Third, the product-level measure is the default rate state stored in the programmable logic device FPGA. When the downlink telemetry rate data cannot be obtained from both the NOR FLASH memory and the hardware state of the IO pins of the programmable logic device, the downlink telemetry code rate control module reads and adopts the default rate of the product.

[0064] As Figure 2 shown, a method for recovering the baseband signal code rate of the downlink telemetry after reset, based on the above-mentioned downlink telemetry baseband signal code rate recovery system, specifically includes the following steps:

[0065] S11. After the telemetry and remote control unit restarts due to abnormal power supply, the reset module outputs a power-on reset signal, putting the programmable logic device FPGA and the FLASH memory in a reset state; when the reset signal is withdrawn, the programmable logic device FPGA and the FLASH memory start to work;

[0066] S12. The important data storage module of the programmable logic device FPGA sequentially reads the baseband signal code rates of each downlink telemetry output channel from the FLASH memory, and sequentially performs a two-out-of-three comparison bit by bit on the read baseband signal code rates of each downlink telemetry output channel to determine whether the data reading is correct; if the read data of the baseband signal code rate of a certain downlink telemetry output channel is incorrect, then execute S13, and at the same time set the failure flag for the baseband signal code rate to be restored from the FLASH, and this telemetry flag is written into the insertion field in the telemetry frame; if the read data of the baseband signal code rate of a certain downlink telemetry output channel is correct, send the correct baseband signal code rate data of this downlink telemetry output channel to the downlink telemetry code rate control module and then execute S15; if all reads are correct, then set the success flag for the baseband signal code rate to be restored from the FLASH; the success / failure flag telemetry can be downlinked to the ground for ground personnel to judge the status of the on-board FLASH; among them, these two flags are set by the "telemetry packetizing and transmission module" and sent to the ground without storage;

[0067] S13. The downlink telemetry code rate control module reads the initial rate of the downlink telemetry output channel. If the read initial rate meets the specified value, then execute S15; if the read initial rate does not meet the specified value, then execute S14;

[0068] S14. The downlink telemetry code rate control module reads the default rate of the downlink telemetry output channel from the programmable logic device FPGA, and then executes S15;

[0069] S15. The downlink telemetry code rate control module restores the baseband signal code rate of the corresponding downlink telemetry output channel according to the obtained baseband signal code rate data;

[0070] S16. Loop through S12 to S15 until the baseband signal code rate of each downlink telemetry output channel is restored.

[0071] As Figure 3 shown, a method for setting the baseband signal code rate of downlink telemetry, based on the above-mentioned downlink telemetry baseband signal code rate recovery system, specifically includes the following steps:

[0072] S21. The proportional instruction receiving module receives the proportional instruction sent from the ground;

[0073] The proportional command receiving module determines the correctness of the proportional command. If it does not conform to the command encoding of the rate switching command, execute S23; if it conforms to the command encoding of the rate switching command, execute S24;

[0074] S23. The proportional command receiving module regards this proportional command as an incorrect command, increments the incorrect proportional command count in the telemetry data, and the programmable logic device FPGA does not change the rate information stored in the FLASH memory, and at the same time does not change the baseband signal code rate of each downlink telemetry output channel;

[0075] S24. The downlink telemetry code rate control module changes the baseband signal code rate of the corresponding downlink telemetry output channel to the value set by the command, and increments the correct proportional command count in the telemetry data;

[0076] S25. The important data storage module stores the judged correct rate information in the FLASH memory or updates the stored rate data in the FLASH memory;

[0077] S26. After the rate data storage is completed, the important data storage module reads the data stored in the FLASH memory for consistency comparison, and sets the "baseband signal code rate command setting status" telemetry. If they are consistent, then set the storage success flag. If they are inconsistent, then set the storage failure flag and write it into the insertion field in the telemetry frame.

[0078] Among them, the incorrect proportional command count, the correct proportional command count, and the "baseband signal code rate command setting status" telemetry, etc. are all set by the "telemetry packetizing and transmission module" and sent to the ground to facilitate the ground staff to judge the working status of the telemetry and remote control unit.

[0079] The above are only optional embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent structural transformation made under the inventive concept of the present invention by using the content of the specification and drawings of the present invention, or directly / indirectly applied in other related technical fields, is included in the patent protection scope of the present invention.

Claims

1. A highly reliable downlink telemetry baseband signal code rate recovery system, characterized by: It includes a programmable logic device FPGA, a FLASH memory and a reset module, wherein the programmable logic device FPGA and the FLASH memory are interconnected through an address line, a data line and a control line, and the reset module is used to output a power-on reset signal to the programmable logic device FPGA and the FLASH memory after the power supply is powered on; The programmable logic device FPGA stores the initial rate through the high and low level states of its IO pins, with 2 bits forming a group, and each group represents a different initial rate; at the same time, the programmable logic device FPGA controls its internal digital logic circuit to store the default rate by using a hardware description language; In addition, the programmable logic device FPGA also includes: The proportional instruction receiving module is used to receive the proportional instruction sent by the ground and judge the correctness of the proportional instruction; if the proportional instruction is correct, the proportional instruction is sent to the downlink telemetry code rate control module described below; A reset management module, used for receiving a power-on reset signal and controlling the programmable logic device FPGA to be in a reset state; A downlink telemetry code rate control module, used to change the baseband signal code rate of the corresponding downlink telemetry output channel according to the proportional instruction, initial rate or default rate sent by the proportional instruction receiving module; The important data storage module is connected to the FLASH memory and is used to write the baseband signal code rate of each downlink telemetry output channel into the FLASH memory three times respectively; in addition, when reading a certain baseband signal code rate from the FLASH memory, a two-out-of-three comparison is performed bit by bit to determine whether the data reading is correct; The telemetry packetization and transmission module is used to realize downlink telemetry data collection and output downlink telemetry data to the transponder.

2. A highly reliable downlink telemetry baseband signal code rate recovery system according to claim 1, characterized in that: The FLASH memory is a non-volatile memory FLASH.

3. A highly reliable downlink telemetry baseband signal code rate recovery system according to claim 1, characterized in that: The reset module includes a power monitoring chip.

4. A method for recovering the bit rate of a downlink telemetry baseband signal after reset, based on the downlink telemetry baseband signal bit rate recovery system according to any one of claims 1 to 3, characterized in that: The specific steps include: S11. After the telemetry remote control unit restarts due to power failure, the reset module outputs a power-on reset signal, so that the programmable logic device FPGA and FLASH memory are in a reset state; when the reset signal is revoked, the programmable logic device FPGA and FLASH memory start working; S12. The important data storage module of the programmable logic device FPGA reads the baseband signal code rate of each downlink telemetry output channel from the FLASH memory in turn, and compares the baseband signal code rate of each downlink telemetry output channel read in turn by three out of two, to determine whether the data reading is correct; if the baseband signal code rate reading data of a downlink telemetry output channel is incorrect, S13 is executed, and the baseband signal code rate recovery failure flag from FLASH is set at the same time, and this telemetry flag is written into the insertion field in the telemetry frame; If the baseband signal code rate reading data of a certain downlink telemetry output channel is correct, the correct baseband signal code rate data of this downlink telemetry output channel is sent to the downlink telemetry code rate control module and then S15 is executed; if all readings are correct, the baseband signal code rate is set to a flag that is successfully restored from FLASH; S13. The downlink telemetry code rate control module reads the initial rate of the downlink telemetry output channel. If the read initial rate meets the specified value, S15 is executed; if the read initial rate does not meet the specified value, S14 is executed; S14. The downlink telemetry code rate control module reads the default rate of the downlink telemetry output channel, and then executes S15; S15. The downlink telemetry code rate control module recovers the baseband signal code rate of the corresponding downlink telemetry output channel according to the acquired baseband signal code rate data; S16. Execute S12 to S15 in a loop until the baseband signal code rate of each downlink telemetry output channel is restored.

5. A method for setting the code rate of a downlink telemetry baseband signal, based on the downlink telemetry baseband signal code rate recovery system according to any one of claims 1 to 3, characterized in that: The specific steps include: S21. The proportional command receiving module receives the proportional command sent from the ground; S22. The proportional instruction receiving module determines the correctness of the proportional instruction. If it does not conform to the instruction code of the rate switching instruction, execute S23; if it conforms to the instruction code of the rate switching instruction, execute S24; S23. The ratio instruction receiving module regards this ratio instruction as an error instruction, and the error ratio instruction count in the telemetry data is increased by 1. The programmable logic device FPGA does not change the rate information stored in the FLASH memory, and does not change the baseband signal code rate of each downlink telemetry output channel; S24. The downlink telemetry code rate control module changes the baseband signal code rate of the corresponding downlink telemetry output channel to the command setting value, and adds 1 to the correct proportion command count in the telemetry data; S25. The important data storage module determines the correct rate information stored in the FLASH memory or updates the rate data stored in the FLASH memory; S26. After the rate data is stored, the important data storage module reads the data stored in the FLASH memory for consistency comparison, and sets the "baseband signal code rate instruction setting status" telemetry. If they are consistent, the storage success flag is set. If they are inconsistent, the storage failure flag is set, and the "baseband signal code rate instruction setting status" telemetry is written into the insertion field in the telemetry frame.

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