Single-wire half-duplex communication system and backlight system

Abstract

The embodiment of the invention provides a single-line half-duplex communication system and a backlight system, in the system, a host is connected with N slaves in a single-line half-duplex mode, communication protocol analysis modules in the slaves analyze and verify data packets through ports of the slaves, and only at frame tails of the received data packets, the communication protocol analysis modules in the slaves are connected with the N slaves in a single-line half-duplex mode. When the data packet passes the verification, a transmission direction control signal is output, and the data packet is transmitted to a corresponding port along the communication direction of the data packet; the protocol control bit synchronization module is used for receiving a transmission direction control signal, determining delay time when transition influence range information contained in the signal comprises a current slave, starting timing at the same time, outputting a direction switching signal to the transmission direction control module based on data transmission direction information in the signal when the timing time is equal to the delay time, and transmitting the direction switching signal to the transmission direction control module. Therefore, the communication direction of the slave is controlled. According to the invention, the slave machines in the transition influence range can be ensured to be in the uplink mode or the downlink mode at the same time, complete transmission of transmission data is ensured, and the reliability is good.

Description

Technical Field

[0001] The present invention relates to the field of communications, and in particular, to a single-wire half-duplex communication system and a backlight system. Background Art

[0002] Currently, there are mainly three forms of data communication methods: two-wire form, single-wire form, and single-wire half-duplex form, which respectively correspond to the product forms of large partitions, medium partitions, and small partitions in the application system.

[0003] The single-wire half-duplex system adds a two-way communication function to the single-wire system. The communication direction of the slave in this system usually depends on monitoring the level change of the IO port, and determines the direction of the port by detecting whether there is a signal flip. Specifically, if a level flip is detected at any port of the slave, it is determined that the port is an input port.

[0004] However, if level flips are detected at both ports of the slave, the system will have an error, is not suitable for a complex communication environment, and has poor reliability.

[0005] Therefore, how to ensure the reliability of the single-wire half-duplex system in scenarios with high requirements for data transmission accuracy has become a technical problem that the industry urgently needs to solve at present. Summary of the Invention

[0006] The present invention provides a single-wire half-duplex communication system and a backlight system, which solve the technical problem of how to ensure the reliability of the single-wire half-duplex system in scenarios with high requirements for data transmission accuracy.

[0007] According to a first aspect of the present invention, an embodiment of the present invention provides a single-wire half-duplex communication system, including a host and N slave devices. The N slave devices are connected to each other through a single data line, where N is an integer greater than 2; the host is connected to the first slave device and sends or receives data packets through the first slave device;

[0008] The slave device includes a first port and a second port, and the first port and the second port are used to send or receive the data packet. The slave device further includes:

[0009] A communication protocol parsing module, which parses and verifies the data packet through the first port or the second port, and is used to output a transmission direction control signal only when the end of the frame of the data packet is received and the verification of the data packet passes. The transmission direction control signal includes the parsed data transmission direction information and the state influence range information;

[0010] And transmits the data packet along the communication direction of the data packet to the corresponding first port or second port;

[0011] A protocol control bit synchronization module is used to receive the transmission direction control signal, and after receiving the transmission direction control signal, output a direction switching signal based on the data transmission direction information and the state influence range information. Among them, when the state influence range includes the current slave, determine the delay time based on the state influence range information, start timing after receiving the transmission direction control signal, and when the timing time is equal to the delay time, output a direction switching signal based on the data transmission direction information;

[0012] A transmission direction control module is used to control the input and output directions of the first port and the second port based on the direction switching signal, so as to control the slave to be in the upstream mode or the downstream mode.

[0013] Optionally, the frame format of the data packet sequentially includes a preamble, a frame header, a description field, a start address, an end address, a data frame, and a check field;

[0014] Among them, the description field includes the data transmission direction information, the start address and the end address are used to determine the state influence range, and the check field is used to provide data integrity guarantee.

[0015] Optionally, when the state influence range includes the corresponding slave, the method for the current slave to determine the delay time based on the state influence range includes:

[0016] Obtain the fixed delay time between the current slave and the slave corresponding to the end address based on the end address;

[0017] Set the delay time, where the delay time is equal to the fixed delay time.

[0018] Optionally, the slave further includes a target recognition module;

[0019] The target recognition module, coupled to the communication protocol analysis module, is used to receive the transmission direction control signal and based on whether the slave corresponding to the end address is the current slave, where:

[0020] If the slave corresponding to the end address is the current slave and the data transmission direction information indicates the upstream direction, send the data packet corresponding to the current slave along the upstream direction through the communication protocol analysis module, and the data transmission direction information contained in the last data packet corresponding to the slave is the downstream direction.

[0021] Optionally, the slave further includes a monitoring module;

[0022] The monitoring module is coupled to the protocol control bit synchronization module and the target recognition module, and is configured to obtain the transmission duration of the data packet, and when the transmission duration of the data packet is equal to the time window time, control the output direction switching signal output by the protocol control bit synchronization module to indicate the downlink direction.

[0023] Optionally, the monitoring module is further configured to:

[0024] When the timing time is equal to the time window time, control the target recognition module to stop outputting the corresponding data packet.

[0025] Optionally, the first port and the second port each include a bidirectional IO unit, and the bidirectional IO unit includes a first tri-state gate sub-unit and a second tri-state gate sub-unit;

[0026] The input end of the first tri-state gate sub-unit is coupled to the output end of the second tri-state gate sub-unit, the output end of the first tri-state gate sub-unit is coupled to the input end of the second tri-state gate sub-unit, and the enable control ends of the first tri-state gate sub-unit and the second tri-state gate sub-unit are both controlled by the transmission direction control module.

[0027] Optionally, the transmission direction control module is configured to output an enable signal and a disable signal based on the direction switching signal;

[0028] Then, the method for controlling the input / output directions of the first port and the second port based on the direction switching signal includes:

[0029] If the data transmission direction information indicates the uplink mode, output the disable signal to the enable control end of the first tri-state gate sub-unit, and output the enable signal to the enable control end of the second tri-state gate sub-unit;

[0030] If the data transmission direction information indicates the downlink mode, output the enable signal to the enable control end of the first tri-state gate sub-unit, and output the disable signal to the enable control end of the second tri-state gate sub-unit.

[0031] According to a second aspect of the present invention, an embodiment of the present invention provides a backlight system, including an LED driver, and the LED driver includes the single-wire half-duplex communication system according to any one of the first aspects of the present invention.

[0032] Optionally, the data frame is used to transmit dimming data.

[0033] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0034] In the single - wire half - duplex communication system and the backlight system of the technical solution of the present invention, the host is connected to N slave devices in a single - wire half - duplex manner. The communication protocol parsing module in the slave device parses and verifies the data packet through the port of the slave device, and only outputs a transmission direction control signal when the end - of - frame of the data packet is received and the verification of the data packet passes, and transmits the data packet along its communication direction to the corresponding port; the protocol control bit synchronization module is used to receive the transmission direction control signal, determine the delay time when the state influence range information included in the signal includes the current slave device, and start timing at the same time. When the timing time is equal to the delay time, it outputs a direction switching signal to the transmission direction control module based on the data transmission direction information in the signal, so as to control the slave device to be in the upstream mode or the downstream mode. The present invention can ensure that the slave devices within the state influence range can be in the upstream mode or the downstream mode simultaneously, ensuring the complete transmission of the transmitted data and having better reliability.

[0035] Furthermore, the slave device further includes a target recognition module; the target recognition module is coupled to the communication protocol parsing module and is used to receive the transmission direction control signal and determine whether the slave device corresponding to the end address is the current slave device, where: if the slave device corresponding to the end address is the current slave device and the data transmission direction information indicates the upstream direction, the communication protocol parsing module is used to send the data packet corresponding to the current slave device along the upstream direction, and the data transmission direction information included in the last data packet corresponding to the slave device is the downstream direction. Thus, the present invention can also ensure that after the upstream data transmission is completed, all the slave devices in the system are in the downstream mode and will not affect the communication of the host.

[0036] Furthermore, the slave device further includes a monitoring module; the monitoring module is coupled to the protocol control bit synchronization module and the target recognition module and is used to obtain the transmission duration of the data packet, and when the transmission duration of the data packet is equal to the time - window time, control the output direction switching signal output by the protocol control bit synchronization module to indicate the downstream direction. Thus, the present invention also ensures that when an error occurs in the slave devices of the system, the communication between the slave devices and the host can be cut off in time, ensuring the overall safety of the system, and all the slave devices will switch to the downstream mode, still ensuring the consistency of the input and output port states of all the slave devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0038] Figure 1It is a schematic structural diagram of a two-wire communication system provided by an embodiment of the prior art;

[0039] Figure 2 It is a schematic structural diagram of a single-wire communication system provided by an embodiment of the prior art;

[0040] Figure 3 It is a schematic structural diagram of a single-wire half-duplex communication system provided by an embodiment of the present invention;

[0041] Figure 4 It is a schematic structure of a slave device provided by an embodiment of the present invention Figure 1 ;

[0042] Figure 5 Schematic diagram of the frame format of a data packet provided by an embodiment of the present invention;

[0043] Figure 6 It is a control timing diagram of a protocol control bit synchronization module provided by an embodiment of the present invention;

[0044] Figure 7 It is a schematic structure of a slave device provided by an embodiment of the present invention Figure 2 ;

[0045] Figure 8 It is a schematic structure of a slave device provided by an embodiment of the present invention Figure 3 ;

[0046] Figure 9 It is the control timing of a monitoring module provided by an embodiment of the present invention Figure 1 ;

[0047] Figure 10 It is the control timing of a monitoring module provided by an embodiment of the present invention Figure 2 ;

[0048] Figure 11 It is a schematic structural diagram of a bidirectional IO unit provided by an embodiment of the present invention.

[0049] Reference numerals:

[0050] 10 - Host;

[0051] 20 - Slave;

[0052] 201 - First port;

[0053] 202 - Second port;

[0054] 206 - Target recognition module;

[0055] 203 - Communication protocol analysis module;

[0056] 204 - Protocol control bit synchronization module;

[0057] 205 - Transmission direction control module;

[0058] 207 - Monitoring module;

[0059] 2001 - First tri - state gate sub - unit;

[0060] 2002 - Second tri - state gate sub - unit. Detailed implementation manner

[0061] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0062] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above - mentioned accompanying drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "include" and "have" and any variations thereof are intended to cover non - exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or modules does not necessarily have to be limited to those clearly listed steps or modules, but may include other steps or modules not clearly listed or inherent to these processes, methods, products or devices.

[0063] The following uses specific embodiments to elaborate on the technical solutions of the present invention in detail. These several specific embodiments can be combined with each other, and for the same or similar concepts or processes, they may not be repeated in some embodiments.

[0064] As described in the background art, in scenarios where high data - transmission accuracy is required, ensuring the reliability of a single - wire half - duplex system has become a technical problem urgently needed to be solved in the industry. The following will be described in detail with reference to the accompanying drawings.

[0065] In a display system, especially a system involving real - time adjustment of brightness, color, or dynamic effects, data must be transmitted accurately and stably within a predetermined time window. Data packet loss or delay will affect the smoothness and accuracy of the display effect, and may cause flickering, delay, or inconsistent display performance.

[0066] Currently, there are mainly three forms of data communication in display systems: the two-wire form, the single-wire form, and the single-wire half-duplex form, which respectively correspond to the product forms of large partitions, medium partitions, and small partitions in the application system.

[0067] Specifically, please refer to Figure 1 , which shows a two-wire communication system, including a host 10 and N slave devices 20. The N slave devices 20 are connected to each other through two communication lines, which are respectively a data line and a clock line. The output end of the Nth slave device 20 is also coupled to the host 10 through the corresponding two communication lines, where N is an integer greater than or equal to 2;

[0068] Since the two-wire system topology introduces SCK as the data transmission clock, this data transmission method can improve the data transmission rate, enabling more backlight data to be transmitted per unit time and supporting lighting more partition numbers. However, the disadvantage is that it requires occupying too many lamp board routing resources, which is not conducive to reducing the lamp board consumable cost.

[0069] Please refer to Figure 2 , which shows a single-wire communication system, including a host 10 and N slave devices 20. The N slave devices 20 are connected to each other through a communication line, and the Nth slave device 20 is also coupled to the host 10 through the communication line.

[0070] The single-wire system topology has only one data line and uses Manchester coding for long data packet transmission. Since it is asynchronous communication, the communication rate is limited by the sampling theorem theoretical value, and the communication rate in the backlight system is generally below the Mbit level. Therefore, compared with the two-wire system, the backlight data transmitted per unit time is relatively limited. However, the advantage is that it is very friendly to the lamp board routing compared with the two-wire system topology and saves the number of Driver device package pins.

[0071] The single-wire half-duplex system adds a bidirectional communication function to the single-wire system, making the lamp board arrangement simpler and more conducive to reducing the lamp board cost in small partition backlight systems such as special-shaped lamp boards. The communication direction of the slave device 20 in this system usually depends on monitoring the level change of the IO port, and determines the direction of the port by detecting whether there is a signal flip. Specifically, if a level flip is detected at any port of the slave device 20, it is determined that the port is an input port.

[0072] However, if level flips are detected at both ports of the slave device 20, the system will have an error and is not suitable for complex communication environments, with poor reliability.

[0073] To solve the above problems, an embodiment of the present invention provides a single - wire half - duplex communication system. The host is connected to N slave devices in a single - wire half - duplex manner. The communication protocol parsing module in the slave device parses and verifies the data packet through the port of the slave device, and only outputs a transmission direction control signal when the end - of - frame of the data packet is received and the verification of the data packet passes, and transmits the data packet along its communication direction to the corresponding port. The protocol control bit synchronization module is used to receive the transmission direction control signal, determine the delay time when the state influence range information included in the signal includes the current slave device, and start timing at the same time. When the timing time is equal to the delay time, it outputs a direction switching signal to the transmission direction control module based on the data transmission direction information in the signal, so as to control the slave device to be in the upstream mode or the downstream mode. The present invention can ensure that the slave devices within the state influence range can be in the upstream mode or the downstream mode simultaneously, ensuring the complete transmission of the transmitted data and having better reliability.

[0074] To make the above - mentioned objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0075] Please refer to Figure 3 , an embodiment of the present invention provides a single - wire half - duplex communication system, including a host 10 and N slave devices 20. The N slave devices 20 are connected to each other through a data line, where N is an integer greater than 2; the host 10 is connected to the first slave device 20 and sends or receives data packets through the first slave device 20.

[0076] As an example, the host 10 can be a microcontroller (MCU), a central processing unit (CPU), a system - on - chip (SoC), etc. The present invention does not limit this, and those skilled in the art can select a suitable host 10 according to needs.

[0077] Please continue to refer to Figure 4 , the slave device 20 provided by the embodiment of the present invention includes a first port 201 and a second port 202. The first port 201 and the second port 202 are used to send or receive the data packet. The slave device 20 further includes:

[0078] A communication protocol parsing module 203, which parses and verifies the data packet through the first port 201 or the second port 202, and is used to output a transmission direction control signal only when the end - of - frame of the data packet is received and the verification of the data packet passes. The transmission direction control signal includes the parsed data transmission direction information and the state influence range information;

[0079] And transmits the data packet along the communication direction of the data packet to the corresponding first port 201 or second port 202;

[0080] For example, if the communication protocol parsing module 203 parses and verifies the data packet through the first port 201, the communication protocol parsing module 203 will transmit the data packet to the second port 202.

[0081] A protocol control bit synchronization module 204, configured to receive the transmission direction control signal, and after receiving the transmission direction control signal, output a direction switching signal based on the data transmission direction information and the state influence range information, wherein when the state influence range includes the current slave 20, determine a delay time based on the state influence range information, start timing after receiving the transmission direction control signal, and when the timing time is equal to the delay time, output a direction switching signal based on the data transmission direction information;

[0082] A transmission direction control module 205, configured to control the input / output directions of the first port 201 and the second port 202 based on the direction switching signal, so as to control the slave 20 to be in an upstream mode or a downstream mode.

[0083] It can be seen that the present invention switches the slave 20 between the upstream mode and the downstream mode in the form of a data packet, thereby ensuring that data transmission does not go wrong. Moreover, the present invention can ensure that the slaves 20 within the state influence range can be in the upstream mode or the downstream mode simultaneously, ensuring the complete transmission of the transmitted data and having good reliability.

[0084] In a specific embodiment, please refer to Figure 5 , the frame format of the data packet sequentially includes a preamble, a frame header, a description field, a start address, an end address, a data frame (i.e., data1 to dataN), and a check field;

[0085] Wherein, the description field includes the data transmission direction information, the start address and the end address are used to determine the state influence range, and the check field is used to provide data integrity guarantee.

[0086] It should be understood that the embodiments of the present invention do not limit the specific placement position of the description field, and the data transmission direction information can also be placed in any description field or at any position in the description field. Those skilled in the art can select a suitable place for description according to needs.

[0087] In actual implementation, the data packet can also be understood as a communication frame.

[0088] In this case, the data transfer direction information may be in the form of bits in the communication frame format description field. For example, it is the status indication bits of several bit inputs / outputs. When the communication protocol parsing module 203 receives and correctly parses the status indication bit signal for indicating the input / output, the bit field control status is latched at the end of the communication protocol frame into the protocol control synchronization unit;

[0089] Among them, the position at the end of the communication protocol frame can be understood as the moment when the communication link is idle.

[0090] As an example, in Figure 5 the example of, the check field of the present invention can be in the mode of cyclic redundancy check (CRC). Of course, the present invention is not limited thereto, and it can also be other forms of check methods, such as parity check, checksum, hash check, and so on.

[0091] Regarding the start address field and the end address field, it can be understood as the range and corresponding positions of the slave 20 that needs to switch the IO direction, and the position of the last target slave 20 that needs to switch the IO direction can also be determined.

[0092] Furthermore, when the state influence range includes the corresponding slave 20, the method for the current slave 20 to determine the delay time based on the state influence range includes:

[0093] Based on the end address, obtain the fixed delay time of the current slave 20 and the slave 20 corresponding to the end address;

[0094] Set the delay time, where the delay time is equal to the fixed delay time.

[0095] This is because, in a single-wire half-duplex communication system, the delay between each slave 20 can be relatively fixed. By determining the position of any slave 20, the delay between this slave 20 and the master 10 or other slaves 20 can be determined, and then the delay time can be set.

[0096] In actual work, this delay time can also be understood as the time to complete the synchronization compensation.

[0097] Furthermore, in combination with Figure 6 the effect of the protocol control bit synchronization module 204 of the present invention is described. In Figure 6 the example of, the control timing diagram of the protocol control bit synchronization module 204 corresponding to 4 slaves 20 is shown, where:

[0098] din_1 can be understood as the first slave 20 in the state influence range;

[0099] din_2 can be understood as the second slave 20 within the state influence range;

[0100] din_3 can be understood as the third slave 20 within the state influence range;

[0101] din_4 can be understood as the fourth slave 20 within the state influence range, i.e., the last slave 20.

[0102] It can be seen that in the embodiments of the present invention, each slave 20 will obtain the fixed delay time of the slave 20 corresponding to the end address, and set the delay time based on the fixed delay time, so as to ensure that the slaves 20 within the state influence range are simultaneously in the uplink mode or the downlink mode at the handover response moment, ensuring the complete transmission of the transmitted data and having better reliability.

[0103] Of course, the slave 20 in the embodiments of the present invention can not only receive and transmit the data packet, but also return its own data packet to the host 10 based on the requirements of the host 10.

[0104] In a specific implementation manner, please refer to Figure 7 , the slave 20 further includes a target recognition module 206;

[0105] The target recognition module 206 is coupled to the communication protocol parsing module 203 and is used to receive the transmission direction control signal and determine whether the slave 20 corresponding to the end address is the current slave 20, where:

[0106] If the slave 20 corresponding to the end address is the current slave 20 and the data transmission direction information indicates an uplink direction, the communication protocol parsing module 203 is used to send the data packet corresponding to the current slave 20 in the uplink direction, and the data transmission direction information included in the last data packet corresponding to the slave 20 is a downlink direction.

[0107] It should be understood that the slave 20 can transmit multiple data packets in the uplink within a time period, and only the data transmission direction information included in the last data packet must be a downlink direction.

[0108] Thus, the present invention can also ensure that after the uplink data transmission is completed, all the slaves 20 in the system are in the downlink mode, without affecting the communication of the host 10.

[0109] In actual implementation, errors may also occur in the data transmission between the host 10 and the slave 20, such as continuously outputting data packets to the port. To solve this problem, in a preferred implementation manner, please refer to Figure 8 , the slave 20 further includes a monitoring module 207;

[0110] The monitoring module 207 is coupled to the protocol control bit synchronization module 204 and the target recognition module 206, and is configured to obtain the transmission duration of the data packet, and when the transmission duration of the data packet is equal to the time window time, control the output direction switching signal output by the protocol control bit synchronization module 204 to be characterized as the downlink direction.

[0111] In a preferred embodiment, please continue to refer to Figure 8 , the monitoring module 207 is further configured to:

[0112] When the timing time is equal to the time window time, control the target recognition module 206 to stop outputting the corresponding data packet.

[0113] Thus, the present invention also ensures that when an error occurs in the slave 20 of the system, the communication between the slave 20 and the host 10 can be cut off in time, ensuring the overall safety of the system, and all slaves 20 will be switched to the downlink mode, still ensuring the consistency of the input / output port states of all slaves 20.

[0114] Now, in combination with Figure 9 and Figure 10 the timing diagram of, the effect of the monitoring module 207 provided by the present invention is described, where:

[0115] clk_osc can be understood as a clock signal;

[0116] rx_frame can be understood as the valid state of the transmitted data packet or the passing frame;

[0117] up / done_en can be understood as the permission of the monitoring module 207 for the downlink communication (low level) and the uplink communication (high level) states;

[0118] timer can be understood as a time window;

[0119] up2dowm can be understood as the switching from the uplink mode to the downlink mode;

[0120] up_frame can be understood as an uplink data frame.

[0121] It can be seen that in the Figure 9 example, the data transmission of the slave 20 is in a normal state, and the slave 20 can continuously transmit different data packets in the uplink. Each data packet has a corresponding time window. As long as the transmission time of the data packet is within the corresponding time window, the control of the monitoring module 207 will not be triggered.

[0122] In Figure 10In the example, the data transmission of slave 20 is in an abnormal state (up_frame_err). Slave 20 continuously transmits an uplink data packet. The monitoring module 207 starts timing at the beginning of the transmission of the data packet. When the timing time is equal to the time window time (i.e., timeout_flag), it controls the output direction switching signal output by the protocol control bit synchronization module 204 to be characterized as the downlink direction, and resets slave 20.

[0123] It can be seen that the present invention can prevent the input and output port states of each slave 20 from being inconsistent in a single - wire half - duplex system under abnormal system conditions. When the uplink time is equal to the set time window of the monitoring module 207, the single - wire half - duplex system switches to the initial state of the system (i.e., the downlink mode) to ensure the consistency of the input and output port states of each slave 20 in the single - wire half - duplex system after abnormal operation.

[0124] Now, the input and output ports of the present invention will be further elaborated.

[0125] In a specific embodiment, please refer to Figure 11 , the first port 201 and the second port 202 each include a bidirectional IO unit. The bidirectional IO unit includes a first tri - state gate sub - unit 2001 and a second tri - state gate sub - unit 2002;

[0126] The input end of the first tri - state gate sub - unit 2001 is coupled to the output end of the second tri - state gate sub - unit 2002. The output end of the first tri - state gate sub - unit 2001 is coupled to the input end of the second tri - state gate sub - unit 2002. The enable control end Out_en of the first tri - state gate sub - unit 2001 and the enable control end In_en of the second tri - state gate sub - unit 2002 are both controlled by the transmission direction control module 205.

[0127] In this case, the transmission direction control module 205 is used to output an enable signal and a disable signal based on the direction switching signal;

[0128] Then, the method for controlling the input and output directions of the first port 201 and the second port 202 based on the direction switching signal includes:

[0129] If the data transmission direction information is characterized as the uplink mode, the disable signal is output to the enable control end of the first tri - state gate sub - unit 2001, and the enable signal is output to the enable control end of the second tri - state gate sub - unit 2002;

[0130] If the data transmission direction information is characterized as the downlink mode, the enable signal is output to the enable control terminal of the first tri-state gate sub-unit 2001, and the disable signal is output to the enable control terminal of the second tri-state gate sub-unit 2002.

[0131] Specifically, if the data transmission direction information is characterized as the uplink mode, the disable signal 0 is output to the enable control terminal Out_en of the first tri-state gate sub-unit 2001, and the enable signal 1 is output to the enable control terminal In_en of the second tri-state gate sub-unit 2002;

[0132] If the data transmission direction information is characterized as the downlink mode, the enable signal 1 is output to the enable control terminal Out_en of the first tri-state gate sub-unit 2001, and the disable signal 0 is output to the enable control terminal In_en of the second tri-state gate sub-unit 2002.

[0133] In a preferred embodiment, to ensure the mutual exclusion of the input and output of the first tri-state gate sub-unit 2001 and the second tri-state gate sub-unit 2002, there may be a mutual exclusion switching delay response between the first tri-state gate sub-unit 2001 and the second tri-state gate sub-unit 2002, that is, after one tri-state gate sub-unit is closed, another tri-state gate sub-unit is opened after a set time period.

[0134] In summary, in the embodiment of the present invention, the host is connected to N slave devices in a single-wire half-duplex manner. The communication protocol parsing module in the slave device parses and verifies the data packet through the port of the slave device, and outputs a transmission direction control signal only when the end of the data packet is received and the verification of the data packet passes, and transmits the data packet to the corresponding port along its communication direction; the protocol control bit synchronization module is used to receive the transmission direction control signal, determine the delay time when the state influence range information included in the signal includes the current slave device, and start timing at the same time. When the timing time is equal to the delay time, a direction switching signal is output to the transmission direction control module based on the data transmission direction information in the signal, so as to control the slave device to be in the uplink mode or the downlink mode. The present invention can ensure that the slave devices within the state influence range can be in the uplink mode or the downlink mode at the same time, ensuring the complete transmission of the transmitted data and having good reliability.

[0135] In addition, the embodiment of the present invention also provides a backlight system, including an LED driver, and the LED driver includes the single-wire half-duplex communication system as described in any one of the above.

[0136] In this case, the data frame is used to transmit dimming data.

[0137] As an example, the LED driver can be used to control N LEDs, each LED is correspondingly connected to a slave 20, and the slave 20 can also be configured to:

[0138] Dim the corresponding LED based on the dimming data.

[0139] In summary, since the backlight system provided by the embodiment of the present invention adopts a single-line half-duplex communication system, the arrangement of the lamp board is simpler, which is beneficial to reducing the lamp board cost of small-zone backlight systems such as special-shaped lamp boards. Moreover, since the single-line half-duplex communication system provided by the invention can ensure that the slaves 20 within the influence range of the transition state can be in the uplink mode or the downlink mode simultaneously, ensuring the complete transmission of the transmitted data and having good reliability, the backlight system provided by the present invention can be applied to lamp boards with high frame rates, has a wide application range, and has good reliability.

[0140] Of course, the present invention does not limit the application scenarios of the single-line half-duplex communication system, and it can of course also be applied to other scenarios with high requirements for data transmission accuracy.

[0141] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A single-line half-duplex communication system, comprising a host and N slaves, wherein the N slaves are connected via a data line, wherein N is an integer greater than 2; characterized in that: The host is connected to the first slave and sends or receives data packets through the first slave; The slave includes a first port and a second port, the first port and the second port are used to send or receive the data packet, and the slave also includes: a communication protocol parsing module, which parses and verifies the data packet through the first port or the second port, and is used to output a transmission direction control signal only when the frame tail of the data packet is received and the verification of the data packet passes, wherein the transmission direction control signal includes the parsed data transmission direction information and the transition influence range information; and transmitting the data packet along the communication direction of the data packet to the corresponding first port or the second port; A protocol control bit synchronization module, used to receive the transmission direction control signal, and after receiving the transmission direction control signal, output a direction switching signal based on the data transmission direction information and the transition state impact range information, wherein when the transition state impact range includes the current slave, the delay time is determined based on the transition state impact range information, and the timing is started after the transmission direction control signal is received, and when the timing time is equal to the delay time, the direction switching signal is output based on the data transmission direction information; The transmission direction control module is used to control the input and output directions of the first port and the second port based on the direction switching signal, so as to control the slave machine to be in an uplink mode or a downlink mode.

2. The single-line half-duplex communication system according to claim 1, characterized in that: The frame format of the data packet includes a preamble, a frame header, a description field, a start address, an end address, a data frame and a check field in sequence; The description field includes the data transmission direction information, the start address and the end address are used to determine the transition impact range, and the check field is used to provide data integrity assurance.

3. The single-line half-duplex communication system according to claim 2, characterized in that: When the transition state influence range includes the corresponding slave, the method for the current slave to determine the delay time based on the transition state influence range includes: Based on the end address, obtaining a fixed delay time of a current slave and a slave corresponding to the end address; The delay time is set, wherein the delay time is equal to the fixed delay time.

4. The single-line half-duplex communication system according to claim 2, characterized in that: The slave also includes a target identification module; The target identification module is coupled to the communication protocol analysis module, and is used to receive the transmission direction control signal, and determine whether the slave corresponding to the end address is the current slave, wherein: If the slave corresponding to the end address is the current slave and the data transmission direction information is characterized as an uplink direction, the data packet corresponding to the current slave is sent in the uplink direction through the communication protocol parsing module, and the data transmission direction information contained in the last data packet corresponding to the slave is a downlink direction.

5. The single-line half-duplex communication system according to claim 4, characterized in that: The slave also includes a monitoring module; The monitoring module is coupled to the protocol control bit synchronization module and the target identification module, and is used to obtain the transmission duration of the data packet, and when the transmission duration of the data packet is equal to the time window time, control the output direction switching signal output by the protocol control bit synchronization module to represent the downlink direction.

6. The single-line half-duplex communication system according to claim 5, characterized in that: The monitoring module is further configured to: When the timing time is equal to the time window time, the target identification module is controlled to stop outputting the corresponding data packet.

7. The single-line half-duplex communication system according to claim 1, characterized in that: The first port and the second port each include a bidirectional IO unit, and the bidirectional IO unit includes a first tri-state gate sub-unit and a second tri-state gate sub-unit; The input end of the first three-state gate subunit is coupled to the output end of the second three-state gate subunit, the output end of the first three-state gate subunit is coupled to the input end of the second three-state gate subunit, and the enable control end of the first three-state gate subunit and the enable control end of the second three-state gate subunit are both controlled by the transmission direction control module.

8. The single-line half-duplex communication system according to claim 7, characterized in that: The transmission direction control module is used to output an enable signal and a disable signal based on the direction switching signal; The method for controlling the input and output directions of the first port and the second port based on the direction switching signal includes: If the data transmission direction information indicates an uplink mode, outputting the disable signal to the enable control terminal of the first tri-state gate subunit, and outputting the enable signal to the enable control terminal of the second tri-state gate subunit; If the data transmission direction information indicates a downlink mode, the enable signal is output to the enable control terminal of the first tri-state gate subunit, and the disable signal is output to the enable control terminal of the second tri-state gate subunit.

9. A backlight system, characterized in that: It comprises an LED driver, wherein the LED driver comprises the single-line half-duplex communication system according to any one of claims 1 to 8.

10. The backlight system according to claim 9, wherein: The data frame is used to transmit dimming data.

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