Chip layout optimization method and device, electronic equipment and storage medium

Abstract

The invention provides a chip layout optimization method and device, electronic equipment and a storage medium, and relates to the technical field of chips. The method comprises the following steps: acquiring signal flipping rates of a plurality of network nodes of a chip, wherein the network nodes are input and output nodes of the chip and interconnection nodes among units; screening at least one target network node according to the signal flipping rates of the plurality of network nodes, and determining a weight attribute value of each target network node; according to the unit and / or port connected with each target network node, the group of each target network node is divided, and the weight attribute value of each target network node is the weight attribute value of the corresponding group; and optimizing the layout of the units in each group according to the weight attribute value of each group and the number of the units and / or ports in each group. According to the invention, the power consumption of the chip can be optimized based on the signal upset rate of the network node in the chip.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular, to a method, apparatus, electronic device, and storage medium for optimizing chip layout. Background Art

[0002] For portable electronic products, when the battery capacity is limited, the lower the power consumption of the chips used, the longer the working time. For example, for portable electronic products such as laptop computers, tablet computers, and mobile phones, the chips used have strict requirements for power consumption. Therefore, various low-power design technologies are adopted in the design of embedded chips for portable devices to reduce the power consumption of the chips.

[0003] The power consumption of a chip mainly consists of static power consumption and dynamic power consumption. When the chip is operating normally, usually the dynamic power consumption dominates. The dynamic power consumption mainly consists of the signal switching power consumption of the network nodes inside the unit, the short-circuit power consumption, and the signal switching power consumption of the network nodes between the units. Existing low-power design technologies often ignore how to optimize the dynamic power consumption of the network nodes with high signal switching rates to optimize the dynamic power consumption of the chip. Summary of the Invention

[0004] The purpose of the present application is to provide a method, apparatus, electronic device, and storage medium for optimizing chip layout, so as to optimize the chip power consumption based on the signal switching rates of the network nodes inside the chip, aiming at the deficiencies in the above-mentioned existing technologies.

[0005] To achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:

[0006] In a first aspect, an embodiment of the present application provides a method for optimizing chip layout, the method comprising:

[0007] Obtaining the signal switching rates of multiple network nodes of the chip, where the network nodes are input / output nodes of the chip and interconnection nodes between units;

[0008] Filtering at least one target network node according to the signal switching rates of the multiple network nodes, and determining the weight attribute value of each target network node;

[0009] Dividing the groups of each target network node according to the units and / or ports connected to each target network node, and the weight attribute value of each target network node is the weight attribute value of the corresponding group;

[0010] Optimizing the layout of the units within each group according to the weight attribute value of each group and the number of units and / or ports in each group.

[0011] Optionally, screening at least one target network node according to the signal flipping rates of multiple network nodes includes:

[0012] Determining the weight attribute values of multiple network nodes according to the signal flipping rates of multiple network nodes, where the higher the signal flipping rate, the larger the weight attribute value;

[0013] Screening at least one target network node from multiple network nodes according to the weight attribute values of multiple network nodes.

[0014] Optionally, determining the weight attribute values of multiple network nodes according to the signal flipping rates of multiple network nodes includes:

[0015] Sorting multiple network nodes according to the signal flipping rates of multiple network nodes;

[0016] Grouping the sorted multiple network nodes with a preset step size to obtain multiple groups of network nodes;

[0017] Setting corresponding weight attribute values for the multiple groups of network nodes respectively, where the network nodes included in each group of network nodes have the same weight attribute value.

[0018] Optionally, optimizing the unit layout within each group according to the weight attribute value of each group and the number of units and / or ports in each group includes:

[0019] Determining the relative distance of units in each group according to the weight attribute value of each group and the number of units and / or ports in each group;

[0020] Optimizing the unit layout within each group according to the relative distance of units in each group.

[0021] Optionally, before determining the relative distance of units in each group according to the weight attribute value of each group and the number of units and / or ports in each group, it further includes:

[0022] Using a preset algorithm to establish a mapping relationship between the weight attribute value of the group, the number of units and / or ports in the group, and the relative distance of units, where the higher the weight attribute value, the smaller the relative distance of units, and the more the number of units and / or ports in the group, the larger the relative distance of units.

[0023] Optionally, optimizing the unit layout within each group according to the relative distance of units in each group includes:

[0024] Determine the target member in each of the groups according to the member type in each of the groups;

[0025] Adjust the unit positions in each of the groups with the target member as the center according to the relative distance between units in each of the groups.

[0026] Optionally, the determining the target member in each of the groups according to the member type in each of the groups includes:

[0027] If a port is included in the group, determine the target member of the group as the port;

[0028] The adjusting the unit positions in each of the groups with the target member as the center according to the relative distance between units in each of the groups includes:

[0029] Adjust the positions of the units in the group with the port as the center according to the relative distance between units in the group, so that the distance between the units in the group and the port is less than the relative distance between units in the group.

[0030] Optionally, the determining the target member in each of the groups according to the member type in each of the groups includes:

[0031] If a macro cell is included in the group, determine the target member of the group as the macro cell;

[0032] The adjusting the unit positions in each of the groups with the target member as the center according to the relative distance between units in each of the groups includes:

[0033] Adjust the unit layout in the group with the target pin of the macro cell as the center according to the relative distance between units in the group, so that the distance between the units in the group and the target pin of the macro cell is less than the relative distance between units in the group, where the target pin is the pin of the macro cell connected to the target network node corresponding to the group.

[0034] Optionally, the determining the target member in each of the groups according to the member type in each of the groups includes:

[0035] If all members in the group are standard cells, determine the target member of the group as the driving unit;

[0036] The adjusting the unit positions in each of the groups with the target member as the center according to the relative distance between units in each of the groups includes:

[0037] Adjust the unit layout within the group centered on the driving unit according to the relative distance between the units of the group, so that the distance between the units within the group and the driving unit is less than the relative distance between the units of the group.

[0038] In a second aspect, an embodiment of the present application further provides a chip layout optimization device, which includes:

[0039] An acquisition module, configured to acquire the signal transition rates of multiple network nodes of a chip, where the network nodes are input / output nodes of the chip and interconnection nodes between units;

[0040] A screening module, configured to screen at least one target network node according to the signal transition rates of the multiple network nodes, and determine the weight attribute value of each target network node;

[0041] A partitioning module, configured to partition the groups of each target network node according to the units and / or ports connected to each target network node, and the weight attribute value of each target network node is the weight attribute value of the corresponding group;

[0042] An optimization module, configured to optimize the unit layout within each group according to the weight attribute value of each group and the number of units and / or ports in each group.

[0043] Optionally, the screening module is specifically configured to determine the weight attribute values of the multiple network nodes according to the signal transition rates of the multiple network nodes, where the higher the signal transition rate, the larger the weight attribute value; and screen at least one of the target network nodes from the multiple network nodes according to the weight attribute values of the multiple network nodes.

[0044] Optionally, the screening module is further configured to sort the multiple network nodes according to the signal transition rates of the multiple network nodes; group the sorted multiple network nodes with a preset step size to obtain multiple groups of network nodes; and set corresponding weight attribute values for the multiple groups of network nodes respectively, where the network nodes included in each group of network nodes have the same weight attribute value.

[0045] Optionally, the optimization module is specifically configured to determine the relative distance between the units of each group according to the weight attribute value of each group and the number of units and / or ports in each group; and optimize the unit layout within each group according to the relative distance between the units of each group.

[0046] Optionally, the device further includes:

[0047] A mapping module, configured to establish a mapping relationship between the weight attribute value of the group, the number of units and / or ports in the group, and the relative distance between the units, using a preset algorithm, wherein the higher the weight attribute value, the smaller the relative distance between the units, and the more the number of units and / or ports in the group, the larger the relative distance between the units.

[0048] Optionally, the optimization module is further configured to determine a target member in each group according to the member type in each group; and adjust the positions of the units in each group with the target member as the center according to the relative distance between the units in each group.

[0049] Optionally, the optimization module is specifically configured to, if the group includes a port, determine the target member of the group as the port; and adjust the positions of the units in the group with the port as the center according to the relative distance between the units in the group, so that the distance between the units in the group and the port is less than the relative distance between the units in the group.

[0050] Optionally, the optimization module is specifically configured to, if the group includes a macro cell, determine the target member of the group as the macro cell; and adjust the unit layout in the group with the target pin of the macro cell as the center according to the relative distance between the units in the group, so that the distance between the units in the group and the target pin of the macro cell is less than the relative distance between the units in the group, where the target pin is the pin through which the macro cell is connected to the target network node corresponding to the group.

[0051] Optionally, the optimization module is specifically configured to, if all members in the group are standard cells, determine the target member of the group as the driving unit; and adjust the unit layout in the group with the driving unit as the center according to the relative distance between the units in the group, so that the distance between the units in the group and the driving unit is less than the relative distance between the units in the group.

[0052] In a third aspect, an embodiment of the present application further provides an electronic device, including: a processor, a storage medium, and a bus. The storage medium stores program instructions executable by the processor. When the electronic device runs, the processor communicates with the storage medium through the bus, and the processor executes the program instructions to perform the steps of the chip layout optimization method according to any one of the first aspects.

[0053] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is run by a processor, it performs the steps of the chip layout optimization method according to any one of the first aspects.

[0054] The beneficial effects of the present application are:

[0055] The chip layout optimization method, device, electronic device, and storage medium provided by this application screen target network nodes with high signal transition rates based on the signal transition rates of each network node in the chip, determine the weight attribute values of the target network nodes, and optimize the layout of the units connected to the target network nodes according to the weight attribute values of the target network nodes and the number of units and / or ports connected to the target network nodes, so as to place the units connected to the network nodes with high signal transition rates as compactly as possible, reduce the dynamic power consumption of the network nodes with high signal transition rates, and thus reduce the dynamic power consumption of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] To more clearly illustrate the technical solutions of the embodiments of this application, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of this application, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained based on these drawings without creative efforts.

[0057] Figure 1 Schematic diagram of network nodes of an existing chip Figure 1 ;

[0058] Figure 2 Schematic diagram of network nodes of an existing chip Figure 2 ;

[0059] Figure 3 Schematic diagram of network nodes of an existing chip Figure 3 ;

[0060] Figure 4 Schematic diagram of network nodes of an existing chip Figure 4 ;

[0061] Figure 5 Flow schematic diagram of the chip layout optimization method provided by the embodiment of this application Figure 1 ;

[0062] Figure 6 Schematic diagram of network nodes and groups provided by the embodiment of this application;

[0063] Figure 7 Flow schematic diagram of the chip layout optimization method provided by the embodiment of this application Figure 2 ;

[0064] Figure 8 Flow schematic diagram of the chip layout optimization method provided by the embodiment of this application Figure 3 ;

[0065] Figure 9 Flow schematic diagram of the chip layout optimization method provided by the embodiment of this applicationFigure 4 ;

[0066] Figure 10 Schematic flow of the chip layout optimization method provided by the embodiments of the present application Figure 5 ;

[0067] Figure 11 Schematic diagram of the group layout provided by the embodiments of the present application;

[0068] Figure 12 Schematic diagram of the structure of the chip layout optimization device provided by the embodiments of the present application;

[0069] Figure 13 Schematic diagram of the electronic device provided by the embodiments of the present application. Detailed implementation manners

[0070] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some but not all of the embodiments of the present application.

[0071] Therefore, the detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0072] In addition, the terms "first", "second", etc. in the specification and claims of the present application and the above accompanying drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these process, method, product or device.

[0073] It should be noted that, without conflict, the features in the embodiments of the present application can be combined with each other.

[0074] Figure 1 Schematic of network nodes of an existing chip Figure 1 , such as Figure 1As shown, netab is the network node between standard cell a and standard cell b in the chip. The switching power consumption caused by signal inversion on the network node netab can be expressed as: P switch = KCVdd 2 f, where K is the signal inversion rate of the network node netab, C is the equivalent capacitance of the network node netab, Vdd is the operating voltage, and f is the operating frequency.

[0075] It can be seen from the above switching power consumption calculation formula that under the same operating voltage and frequency, the switching power consumption on the network node is proportional to the signal inversion rate and the equivalent capacitance. And when the equivalent capacitance is the same, the dynamic power consumption of the network node with a high signal inversion rate is much greater than that of the network node with a low signal inversion rate. Therefore, how to handle the network node with a high signal inversion rate is the key to optimizing the dynamic power consumption on the network nodes in the chip.

[0076] The prior art generally places and optimizes the positions of units based on the principle of timing priority, which will bring the following problems.

[0077] First, if Figure 1 the network node netab in is a node with a very high signal switching activity, and the timing of the path between standard cells a and b is relatively loose, then based on the timing-driven layout method, the layout tool generally places standard cells a and b at a relatively far distance. The farther they are apart, the larger the capacitance value of the equivalent capacitance C of the network node netab, resulting in a larger switching power consumption caused by this network node netab. In addition, Figure 2 is a schematic diagram of the network nodes of an existing chip Figure 2 , as Figure 2 shown, when standard cells a and b are far apart, the layout tool will also insert one or more buffer units between standard cells a and b to meet the slew requirement of signal conversion in chip design. In this way, the original network element node netab will be divided into multiple sub-network nodes net1, net2,..., netn with the same signal switching activity. Then the dynamic power consumption of the network node netab is equal to the sum of the dynamic power consumptions of each sub-network node, plus the internal power consumption of the inserted buffer unit. Because of the high signal switching activity, the internal power consumption of the inserted buffer unit is also much higher than that of the buffer units inserted on other network nodes with low signal switching activity.

[0078] Second, Figure 3 is a schematic diagram of the network nodes of an existing chip Figure 3 , as Figure 3As shown, in the physical design of a chip module, the timing of the paths between the internal timing units of the module is usually prioritized, and the timing priority of the paths from the module input ports to the internal timing units of the module is lower. The placement tool will prioritize the internal timing of the units, thereby placing the interface logic at a position farther from the ports. Figure 4 Schematic diagram of network nodes of an existing chip Figure 4 For example Figure 4 As shown, in order to meet the signal slew requirements, multiple buffer units are also inserted. If the signal transition rate of the port is high, it will also cause a large switch power consumption in the network node netina.

[0079] Based on the problems existing in the above-mentioned prior art, the present application intends to provide a chip placement optimization method, device, electronic device and storage medium. The target network nodes with high signal transition rates are screened based on the signal transition rates of each network node in the chip, and the weight attribute values of the target network nodes are determined. According to the weight attribute values of the target network nodes and the number of units and / or ports connected to the target network nodes, the placement of the units connected to the target network nodes is optimized, so as to place the units connected to the network nodes with high signal transition rates as compactly as possible, reduce the dynamic power consumption of the network nodes with high signal transition rates, and thus reduce the dynamic power consumption of the chip.

[0080] It should be noted that the chip placement optimization method of the present application is executed by a placement tool running in an electronic device, and this placement tool can execute the chip placement optimization method provided by the present application during the placement and routing stage of the chip.

[0081] The following describes the specific implementation manners of the chip placement optimization method, device, electronic device and storage medium provided by the present application in conjunction with embodiments.

[0082] Figure 5 Flow schematic diagram of the chip placement optimization method provided by the embodiment of the present application Figure 1 This method can be executed by a processing device such as a computer, and specifically can be executed by chip design or simulation software. For example Figure 5 As shown, this method may include:

[0083] S101. Obtain the signal transition rates of multiple network nodes of the chip, where the network nodes are the input and output nodes of the chip and the interconnection nodes between units.

[0084] In this embodiment, a gate-level synthesis netlist of the chip is obtained, and the gate-level synthesis netlist of the chip is simulated by a simulation tool to obtain a waveform file of the chip. The waveform file records the signal transition information of each network node of the chip, and the signal transition information is that the signal logic value of the network node changes, for example, from logic 0 to logic 1, or from logic 1 to logic 0.

[0085] The network nodes include input nodes, output nodes in the chip, and nodes for interconnection between various units. According to the signal transition information of each network node recorded in the waveform file of the chip, the number of transitions of the signal of each network node in the corresponding clock cycle within a preset simulation time period is counted, and according to the number of transitions of the signal of each network node in the corresponding clock cycle, the signal transition rate of each network node is determined. Among them, the clock cycles of the network nodes within the same clock domain are unified.

[0086] In some embodiments, the time period with the highest number of signal transitions of each network node can be determined from the waveform file, and within this time period, according to the number of transitions of the signal of each network node in the corresponding clock cycle, the signal transition rate of each network node is determined.

[0087] In other embodiments, the number of signal transitions of each network node in multiple time periods can also be determined from the waveform file. According to the number of transitions of the signal of each network node in the corresponding clock cycle in each time period, the signal transition rate of each network node in each time period is determined. According to the signal transition rates of each network node in multiple time periods, the average signal transition rate is calculated as the signal transition rate of each network node.

[0088] It should be noted that the waveform file can be, for example, a Value Change Dump (VCD) file or a Fast Signal DataBase (FSDB) file.

[0089] S102. According to the signal transition rates of multiple network nodes, at least one target network node is screened, and the weight attribute value of each target network node is determined.

[0090] In this embodiment, according to the signal transition rates of multiple network nodes, the network nodes with high signal transition rates are screened from the multiple network nodes as the target network nodes.

[0091] In some embodiments, according to a preset signal transition rate threshold, the network nodes with signal transition rates greater than the preset signal transition rate threshold can be screened from the multiple network nodes as the target network nodes.

[0092] In other embodiments, the signal transition rates of multiple network nodes are sorted, and the network nodes with the top preset number in the sorting are determined as the target network nodes. For example, the network nodes with signal transition rates in the top ten are the target network nodes.

[0093] According to the signal flip rate of the target network node, a weight attribute value is assigned to the target network node. The weight attribute value represents the priority for optimizing the network node. Among them, the higher the signal flip rate of the network node, the higher the priority for optimizing the network node.

[0094] S103. Divide the groups of each target network node according to the units and / or ports connected to each target network node. The weight attribute value of each target network node is the weight attribute value of the corresponding group.

[0095] In this embodiment, each target network node is traversed in sequence to determine the units and / or ports connected to the target network node on the chip. Among them, the units connected to the target network node on the chip may include: macro units and / or standard units, and the ports connected to the target network node on the chip may be input ports or output ports.

[0096] Divide the units and / or ports connected to each target network node into a group (group). This group inherits the weight attribute value of the target network node to which it belongs. The weight attribute value represents the priority for layout optimization of the units within the group.

[0097] Exemplarily, Figure 6 is a schematic diagram of the network node and the group provided by the embodiment of the present application. As Figure 6 shown, the units connected to the target network node net include unit a, unit b, and unit c. The weight attribute value of the target network node net is 50. Unit a, unit b, and unit c are divided into a group group, then the weight attribute value of this group is also 50.

[0098] S104. Optimize the unit layout within each group according to the weight attribute value of each group and the number of units and / or ports in each group.

[0099] In this embodiment, according to the weight attribute value of each group, determine the priority for layout optimization of the units within each group, and optimize the unit layout within multiple groups in sequence according to the priority. Among them, the optimization process is to adjust the distance between the units within each group.

[0100] In some embodiments, according to the number of units and / or ports in each group, determine the optimized distance between the units in each group, and adjust the positions of the units within each group according to the optimized distance between the units in each group, so that the distance between the units in each group is less than or equal to the optimized distance.

[0101] Among them, the larger the number of units and / or ports in each group, the longer the optimized distance between the units in each group; the smaller the number of units and / or ports in each group, the shorter the optimized distance between the units in each group, so as to avoid timing violation problems caused by too short distances between units when the number of units and / or ports in the group is large.

[0102] It can be seen that by adjusting the distances between the units connected to the target network nodes with high signal transition rates, the equivalent capacitance value on the target network nodes is reduced, so that the switch power consumption of the target network nodes with high signal transition rates can be effectively reduced, and thus the dynamic power consumption of the chip can be reduced.

[0103] The chip layout optimization method provided in the above embodiments screens target network nodes with high signal transition rates based on the signal transition rates of each network node in the chip, determines the weight attribute values of the target network nodes, and optimizes the layout of the units connected to the target network nodes according to the weight attribute values of the target network nodes and the number of units and / or ports connected to the target network nodes, so as to place the units connected to the network nodes with high signal transition rates as compactly as possible, reduce the dynamic power consumption of the network nodes with high signal transition rates, and thus reduce the dynamic power consumption of the chip.

[0104] In a possible implementation manner, Figure 7 is a flowchart of the chip layout optimization method provided by the embodiments of the present application Figure 2 , as Figure 7 shown, the process of screening at least one target network node according to the signal transition rates of multiple network nodes in S102 above may include:

[0105] S201. Determine the weight attribute values of multiple network nodes according to the signal transition rates of multiple network nodes, where the higher the signal transition rate, the larger the weight attribute value.

[0106] S202. Screen at least one target network node from multiple network nodes according to the weight attribute values of multiple network nodes.

[0107] In this embodiment, multiple network nodes are sorted according to the signal transition rates of multiple network nodes, and weight attribute values are assigned to the sorted multiple network nodes respectively, where the network nodes with higher signal transition rates, that is, those ranked higher, have larger weight attribute values.

[0108] In some embodiments, network nodes with weight attribute values greater than a preset weight threshold are screened from multiple network nodes as target network nodes.

[0109] In some other embodiments, multiple network nodes are sorted according to the weight attribute values of the multiple network nodes, and a preset number of the top-ranked network nodes are selected from the sorted multiple network nodes as target network nodes.

[0110] Among them, the target network nodes are the network nodes for which the switch power consumption is to be optimized. For the target network nodes, by adjusting the distance between the units connected to the target network nodes, the equivalent capacitance value on the target network nodes is reduced, thereby reducing the switch power consumption of the target network nodes.

[0111] It should be noted that the number of target network nodes screened from the multiple network nodes can be determined according to the scale and requirements of the chip, and this embodiment does not limit this.

[0112] In a possible implementation manner, Figure 8 is the flowchart of the chip layout optimization method provided by the embodiment of the present application Figure 3 , as Figure 8 shown, the process of determining the weight attribute values of multiple network nodes according to the signal transition rates of the multiple network nodes in S201 above may include:

[0113] S301. Sort the multiple network nodes according to the signal transition rates of the multiple network nodes.

[0114] S302. Group the sorted multiple network nodes with a preset step size to obtain multiple groups of network nodes.

[0115] S303. Set corresponding weight attribute values for the multiple groups of network nodes respectively, where the network nodes included in each group of network nodes have the same weight attribute value.

[0116] Exemplarily, Table 1 is a comparison table of signal transition rates and weight attribute values provided by the embodiment of the present application. As shown in Table 1, the multiple network nodes are sorted according to the signal transition rates of the multiple network nodes, grouped according to a preset step size step for the sorted multiple network nodes, and a weight attribute value is set for each group of network nodes. The higher the signal transition rate of a group of network nodes, the greater the weight attribute value.

[0117] Among them, the preset step size step can be flexibly set according to the number of network nodes in the chip. If the number of network nodes is large, the step size step can be set to a larger value, such as a value greater than or equal to 5. If the number of network nodes is small, the step size step can be set to a smaller value, such as a value less than 5.

[0118] Table 1 Comparison table of signal transition rates and weight attribute values

[0119]

[0120]

[0121] In some other embodiments, network nodes with the same signal transition rate can also be grouped into a set of network nodes according to the signal transition rates of multiple network nodes, and weight attribute values can be set for each set of network nodes according to the signal transition rates of each set of network nodes.

[0122] In still some other embodiments, network nodes with a difference in signal transition rate less than a preset difference threshold can also be grouped into a set of network nodes according to the signal transition rates of multiple network nodes, and weight attribute values can be set for each set of network nodes according to the signal transition rates of each set of network nodes.

[0123] The method of grouping multiple network nodes is not limited to the above examples, and other methods can also be used for grouping, and this embodiment does not limit this.

[0124] For the chip layout optimization method provided in the above embodiments, weight attribute values are set for network nodes according to the signal transition rates of the network nodes, and target network nodes are screened according to the weight attribute values, so as to use network nodes with high signal transition rates as target network nodes to be optimized. By adjusting the distances between the units connected to the target network nodes, the equivalent capacitance values on the target network nodes are reduced, thereby reducing the switch power consumption of the target network nodes and reducing the chip power consumption.

[0125] In one possible implementation manner, Figure 9 is a schematic flowchart of the chip layout optimization method provided in the embodiments of the present application Figure 4 as Figure 9 shown, the process of optimizing the unit layout within each group according to the weight attribute value of each group and the number of units and / or ports in each group in the above S104 may include:

[0126] S401. Determine the relative distance of units in each group according to the weight attribute value of each group and the number of units and / or ports in each group.

[0127] S402. Optimize the unit layout within each group according to the relative distance of units in each group.

[0128] In some embodiments, according to the correspondence between the weight attribute value and the range of relative unit distances, determine the range of relative unit distances corresponding to the weight attribute value of each group, and determine the relative unit distance of each group within the range of relative unit distances according to the correspondence between the number of units and / or ports and the relative unit distance.

[0129] For example, determine the quantity range corresponding to the unit relative distance range, and determine the unit relative distance of each group at the corresponding position within the unit relative distance range according to the position of the quantity of the units and / or ports in each group within the quantity range.

[0130] In some other embodiments, according to the correspondence between the quantity of the units and / or ports and the unit relative distance range, determine the unit relative distance range corresponding to the quantity of the units and / or ports in each group, and determine the unit relative distance of each group within the unit relative distance range according to the correspondence between the weight attribute value and the unit relative distance.

[0131] For example, determine the weight range corresponding to the unit relative distance range, and determine the unit relative distance of each group at the corresponding position within the unit relative distance range according to the position of the weight attribute value in each group within the weight range.

[0132] In this embodiment, the unit relative distance can be understood as the region attribute value, which is used to indicate the relative distance between the units included in each group. The unit relative distance can represent the intimacy between the units included in each group. The smaller the unit relative distance, the higher the intimacy between the units and / or between the unit and the port, and the more compact the placement between the units and / or between the unit and the port. The larger the unit relative distance, the lower the intimacy between the units and / or between the unit and the port, and the looser the placement between the units and / or between the unit and the port.

[0133] Adjust the positions of the units in each group according to the unit relative distance, so that the distance between the units and / or between the unit and the port is less than or equal to the unit relative distance, so that the equivalent capacitance value on the target network node between the units and / or between the unit and the port is reduced, thereby reducing the switch power consumption of the target network node.

[0134] In some embodiments, before determining the unit relative distance of each group according to the weight attribute value of each group and the quantity of the units and / or ports in each group in S401 above, the method may further include:

[0135] Adopt a preset algorithm to establish a mapping relationship between the weight attribute value of the group, the quantity of the units and / or ports in the group, and the unit relative distance, where the higher the weight attribute value, the smaller the unit relative distance, and the more the quantity of the units and / or ports in the group, the larger the unit relative distance.

[0136] In this embodiment, a two-dimensional mapping table is established in advance using a preset algorithm. One dimension of the two-dimensional mapping table is the weight attribute value, and the other dimension is the number of cells and / or ports. In the weight attribute dimension, the higher the weight attribute value, the higher the signal flip rate of the network node, the greater the switch power consumption of the network node, and the smaller the relative distance between the cells needs to be reduced by reducing the distance between the cells and / or ports connected to the network node, so the relative distance between the cells is smaller.

[0137] In the quantity dimension, under the same weight attribute value, the more the number of cells and / or ports in the group, in order to avoid causing timing violations, the farther the distance between the cells and / or ports in the group, that is, the greater the relative distance between the cells.

[0138] In some embodiments, when determining the relative distance between cells of each group, a set of relative distances between cells corresponding to the weight attribute value can be determined from the two-dimensional mapping table according to the weight attribute value of each group. Each relative distance between cells in this set of relative distances has a corresponding number of cells and / or ports, and then the relative distance between cells of each group is determined from this set of relative distances according to the number of cells and / or ports of each group.

[0139] In other embodiments, when determining the relative distance between cells of each group, a set of relative distances between cells corresponding to the number of cells and / or ports can be determined from the two-dimensional mapping table according to the number of cells and / or ports of each group. Each relative distance between cells in this set of relative distances has a corresponding weight attribute value, and then the relative distance between cells of each group is determined from this set of relative distances according to the weight attribute value of each group.

[0140] The chip layout optimization method provided in the above embodiments determines the relative distance between cells of each group according to the weight attribute value of each group and the number of cells and / or ports in each group, so that when optimizing the cell layout within each group according to the relative distance between cells of the group, the placement position of the cells is jointly restricted by the weight attribute value and the number of cells and / or ports, ensuring that the switch power consumption of the network node corresponding to the cells after layout optimization is optimized, and timing violations will not be caused due to the placement distance between cells and between cells and ports being too close, effectively reducing the dynamic power consumption of the chip.

[0141] In one possible implementation, Figure 10 is a schematic flow of the chip layout optimization method provided by the embodiments of the present application Figure 5 , as Figure 10 shown, the method may include:

[0142] S501. Determine the target members in each group according to the member types in each group.

[0143] S502. Adjust the positions of the units within each group centered around the target member according to the relative distances between the units in each group.

[0144] In this embodiment, according to the types of the units and / or ports included in each group, determine the target member from the units and / or ports included in each group. Centered around the target member, adjust the placement positions of the other units so that the distances between the other units and the target member are less than or equal to the relative distances between the units, so as to complete the optimization of the unit layout within the group.

[0145] In some embodiments, if a group includes a port, determine the target member of the group as the port, and adjust the positions of the units within the group centered around the port according to the relative distances between the units in the group, so that the distances between the units within the group and the port are less than the relative distances between the units in the group.

[0146] In this embodiment, if there is a port within the group, such as the input port IN or the output port OUT, then centered around the position of the port, place all the units included in the group around the port so that the distances between the units included in the group and the port are less than or equal to the relative distances between the units in the group, that is, the distances between the units and the port are within the constraint range of the region value.

[0147] In some other embodiments, if a group includes macro cells, determine the target member of the group as the macro cell, and adjust the unit layout within the group centered around the target pin of the macro cell according to the relative distances between the units in the group, so that the distances between the units within the group and the target pin of the macro cell are less than the relative distances between the units in the group, where the target pin is the pin where the macro cell is connected to the target network node corresponding to the group.

[0148] In this embodiment, if the group does not include a port but has a macro cell, then centered around the position of the macro cell, place all the other units within the group around the macro cell so that the distances between the other units included in the group and the macro cell are less than or equal to the relative distances between the units in the group. Further, since the macro cell has multiple pins, centered around the target pin where the macro cell is connected to the target network node corresponding to the group, place all the other units within the group around the target pin of the macro cell so that the distances between the other units included in the group and the target pin of the macro cell are less than or equal to the relative distances between the units in the group.

[0149] In some other embodiments, if all the members within the group are standard cells, determine the target member of the group as the driving unit; adjust the unit layout within the group centered around the driving unit according to the relative distances between the units in the group, so that the distances between the units within the group and the driving unit are less than the relative distances between the units in the group.

[0150] In this embodiment, if the group contains neither ports nor macro cells and all cells are standard cells, the standard cell before the target network node of the group is the drive unit, and the standard cell after the target network node is the load unit. For example, Figure 6 as shown, unit a before the target network node net is the drive unit, and units b and c after the target network node net are load units.

[0151] Centering on the drive unit, place all the load units in the group around the drive unit so that the distance between the load units and the drive unit in the group is less than or equal to the relative distance of the units in the group.

[0152] For example, Figure 11 is the schematic diagram of the group layout provided by the embodiment of the present application. As Figure 11 shown, group group1 includes port IN and unit a. Centering on port IN, adjust the placement position of unit a so that the distance between unit a and port IN is less than the relative distance of the units in group group1, which is 20.

[0153] Group group2 includes unit a1, unit b1, and unit c1. Unit a1 is the drive unit, and units b1 and c1 are load units. Centering on unit a1, adjust the placement positions of units b1 and c1 so that the distances between units b1 and c1 and unit a1 are less than the relative distance of the units in group group2, which is 20.

[0154] Group group3 includes macro cell sram, unit a2, and unit b2. Centering on the target pin of macro cell sram, adjust the placement positions of units a2 and b2 so that the distances between units a2 and b2 and the target pin of macro cell sram are less than the relative distance of the units in group group3, which is 20.

[0155] The chip layout optimization method provided in the above embodiment selects the target member according to the member type in the group, adjusts the distance between other units in the group and the target member centering on the target member, completes the layout optimization of the units in the group, effectively reduces the switch power consumption of the target network node corresponding to the group, and thus reduces the dynamic power consumption of the chip.

[0156] Based on the above method embodiment, the embodiment of the present application further provides a chip layout optimization device. Figure 12 is the structural schematic diagram of the chip layout optimization device provided by the embodiment of the present application. As Figure 12 shown, the device may include:

[0157] An acquisition module 601, configured to acquire the signal transition rates of multiple network nodes of a chip, where the network nodes are input / output nodes of the chip and interconnection nodes between units;

[0158] A screening module 602, configured to screen at least one target network node according to the signal transition rates of the multiple network nodes, and determine the weight attribute value of each target network node;

[0159] A partitioning module 603, configured to partition groups of each target network node according to the units and / or ports connected to each target network node, and the weight attribute value of each target network node is the weight attribute value of the corresponding group;

[0160] An optimization module 604, configured to optimize the unit layout within each group according to the weight attribute value of each group and the number of units and / or ports in each group.

[0161] Optionally, the screening module 602 is specifically configured to determine the weight attribute values of the multiple network nodes according to the signal transition rates of the multiple network nodes, where the higher the signal transition rate, the larger the weight attribute value; and screen at least one target network node from the multiple network nodes according to the weight attribute values of the multiple network nodes.

[0162] Optionally, the screening module 602 is further configured to sort the multiple network nodes according to the signal transition rates of the multiple network nodes; group the sorted multiple network nodes with a preset step size to obtain multiple groups of network nodes; and set corresponding weight attribute values for the multiple groups of network nodes respectively, where the network nodes included in each group of network nodes have the same weight attribute value.

[0163] Optionally, the optimization module 604 is specifically configured to determine the relative distance of units in each group according to the weight attribute value of each group and the number of units and / or ports in each group; and optimize the unit layout within each group according to the relative distance of units in each group.

[0164] Optionally, the apparatus may further include:

[0165] A mapping module, configured to establish a mapping relationship between the weight attribute value of a group, the number of units and / or ports in the group, and the relative distance of units by using a preset algorithm, where the higher the weight attribute value and the smaller the relative distance of units, and the more the number of units and / or ports in the group and the larger the relative distance of units.

[0166] Optionally, the optimization module 604 is further configured to determine the target members within each group according to the member type within each group; and adjust the unit positions within each group with the target members as the center according to the relative distance of units in each group.

[0167] Optionally, the optimization module 604 is specifically configured to, if the group contains a port, determine that the target member of the group is the port; according to the relative distance between the units in the group, adjust the positions of the units in the group centered on the port, so that the distance between the units in the group and the port is less than the relative distance between the units in the group.

[0168] Optionally, the optimization module 604 is specifically configured to, if the group contains macro cells, determine that the target member of the group is the macro cell; according to the relative distance between the units in the group, adjust the unit layout in the group centered on the target pin of the macro cell, so that the distance between the units in the group and the target pin of the macro cell is less than the relative distance between the units in the group, and the target pin is the pin where the macro cell is connected to the target network node corresponding to the group.

[0169] Optionally, the optimization module 604 is specifically configured to, if all members in the group are standard cells, determine that the target member of the group is the driving cell; according to the relative distance between the units in the group, adjust the unit layout in the group centered on the driving cell, so that the distance between the units in the group and the driving cell is less than the relative distance between the units in the group.

[0170] The above device is used to execute the method provided in the foregoing embodiment, and its implementation principle and technical effects are similar, which will not be elaborated here.

[0171] The above modules may be one or more integrated circuits configured to implement the above method, such as: one or more application specific integrated circuits (ASICs), or, one or more microprocessors, or, one or more field programmable gate arrays (FPGAs), etc. Again, when a certain above module is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processors that can call program code. Again, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0172] Figure 13 Schematic diagram of the electronic device provided in the embodiment of the present application, as Figure 13As shown, the electronic device 700 may include: a processor 701, a storage medium 702, and a bus. The storage medium 702 stores program instructions executable by the processor 701. When the electronic device 700 runs, communication between the processor 701 and the storage medium 702 is through the bus. The processor 701 executes the program instructions to implement the above method embodiments. The specific implementation manners and technical effects are similar and will not be elaborated here.

[0173] Optionally, the present application also provides a computer-readable storage medium storing a computer program, which, when run by a processor, implements the above method embodiments.

[0174] In several embodiments provided by the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0175] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0176] In addition, in each embodiment of the present application, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware, or in the form of hardware plus software functional units.

[0177] The integrated unit implemented in the form of software functional units can be stored in a computer-readable storage medium. The above-mentioned software functional units are stored in a storage medium and include several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (English: processor) to execute some steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (English: Read-Only Memory, abbreviated as: ROM), random access memories (English: Random Access Memory, abbreviated as: RAM), magnetic disks, or optical discs that can store program codes.

[0178] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should be covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A chip layout optimization method, characterized in that: The method comprises: Acquire signal flip rates of multiple network nodes of a chip, where the network nodes are input and output nodes of the chip and interconnection nodes between units; According to the signal flipping rates of the plurality of network nodes, at least one target network node is screened, and a weight attribute value of each target network node is determined; Divide each of the target network nodes into groups according to the units and / or ports to which each of the target network nodes is connected, and the weight attribute value of each of the target network nodes is the weight attribute value of the corresponding group; The cell layout in each of the groups is optimized according to the weight attribute value of each of the groups and the number of cells and / or ports in each of the groups.

2. The method according to claim 1, characterized in that The step of screening at least one target network node according to the signal flip rates of the plurality of network nodes comprises: Determining weight attribute values ​​of the plurality of network nodes according to the signal flip rates of the plurality of network nodes, wherein the higher the signal flip rate, the greater the weight attribute value; At least one target network node is selected from the plurality of network nodes according to the weight attribute values ​​of the plurality of network nodes.

3. The method according to claim 2, characterized in that Determining the weight attribute values ​​of the plurality of network nodes according to the signal flip rates of the plurality of network nodes includes: sorting the plurality of network nodes according to signal flip rates of the plurality of network nodes; Using a preset step size to group the sorted plurality of network nodes to obtain a plurality of groups of network nodes; Corresponding weight attribute values ​​are set for the multiple groups of network nodes respectively, wherein the network nodes included in each group of network nodes have the same weight attribute value.

4. The method according to claim 1, characterized in that The optimizing the layout of the cells in each of the groups according to the weight attribute value of each of the groups and the number of cells and / or ports in each of the groups comprises: Determining the relative distance of the units of each group according to the weight attribute value of each group and the number of units and / or ports in each group; The cell layout in each of the groups is optimized according to the relative distance between the cells in each of the groups.

5. The method according to claim 4, characterized in that Before determining the relative distance of the units in each group according to the weight attribute value of each group and the number of units and / or ports in each group, the method further includes: A preset algorithm is used to establish a mapping relationship between the weight attribute value of the group and the number of units and / or ports in the group and the relative distance of the units, wherein the higher the weight attribute value, the smaller the relative distance of the units, and the more the number of units and / or ports in the group, the larger the relative distance of the units.

6. The method according to claim 4, characterized in that The optimizing the layout of the cells in each group according to the relative distance of the cells in each group includes: Determining target members in each of the groups according to the type of members in each of the groups; According to the relative distance of the units in each group, the position of the units in each group is adjusted with the target member as the center.

7. The method according to claim 6, characterized in that The step of determining a target member in each of the groups according to the type of members in each of the groups includes: If the group includes a port, determining that the target member of the group is the port; The adjusting the position of the units in each group based on the relative distance of the units in each group and taking the target member as the center includes: According to the relative distance of the units in the group, the positions of the units in the group are adjusted with the port as the center, so that the distance between the units in the group and the port is smaller than the relative distance of the units in the group.

8. The method according to claim 6, characterized in that The step of determining a target member in each of the groups according to the type of members in each of the groups includes: If the group includes a macro unit, determining that the target member of the group is the macro unit; The adjusting the position of the units in each group based on the relative distance of the units in each group and taking the target member as the center includes: According to the relative distance of the cells of the group, the layout of the cells within the group is adjusted with the target pin of the macro cell as the center, so that the distance between the cells in the group and the target pin of the macro cell is smaller than the relative distance of the cells of the group, and the target pin is the pin connecting the macro cell to the target network node corresponding to the group.

9. The method according to claim 6, characterized in that The step of determining a target member in each of the groups according to the type of members in each of the groups includes: If all members in the group are standard units, determining the target member of the group to be a driving unit; The adjusting the position of the units in each group based on the relative distance of the units in each group and taking the target member as the center includes: According to the relative distance of the cells in the group, the layout of the cells in the group is adjusted with the driving unit as the center, so that the distance between the cells in the group and the driving unit is smaller than the relative distance of the cells in the group.

10. A chip layout optimization device, characterized in that: The device comprises: An acquisition module, used to acquire signal flip rates of multiple network nodes of a chip, wherein the network nodes are input and output nodes of the chip and interconnection nodes between units; A screening module, used to screen at least one target network node according to the signal flip rates of the plurality of network nodes, and determine a weight attribute value of each target network node; A division module, used for dividing each of the target network nodes into groups according to the units and / or ports to which each of the target network nodes is connected, wherein the weight attribute value of each of the target network nodes is the weight attribute value of the corresponding group; The optimization module is used to optimize the layout of the cells in each of the groups according to the weight attribute value of each of the groups and the number of cells and / or ports in each of the groups.

11. An electronic device, characterized in that: include: A processor, a storage medium and a bus, wherein the storage medium stores program instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the program instructions to perform the steps of the chip layout optimization method according to any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the chip layout optimization method according to any one of claims 1 to 9 are executed.

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