Packaging process of circuit board

Abstract

The invention discloses a packaging process of a circuit board, which comprises the following steps of: S1, presetting a plurality of layers of circuit substrates: based on a laser-assisted micropore interconnection process, filling through holes in a matrix formed by alternately stacking a ceramic base material and a polyimide composite substrate through nanoscale metallization to form a vertical interconnection structure; wherein the ceramic base material is an ultrahigh-heat-conduction ceramic sheet formed by doping 3%-5% of yttrium oxide into aluminum nitride, the surface of the polyimide layer is subjected to plasma grafting modification treatment, and the surface roughness Ra of the polyimide layer is smaller than or equal to 0.2 mu m; and S2, dynamic thermocompression bonding: bonding the core plate and at least two layers of copper foils in a vacuum environment by adopting a segmented gradient pressure control system, increasing the pressure of an initial segment to be 5-10 MPa, keeping the temperature at 180-200 DEG C for 60 seconds, increasing the pressure of a middle segment to be 15-20 MPa, keeping the temperature at 230-250 DEG C for 120 seconds, adjusting the pressure of a tail segment to be 8-12 MPa, and cooling while reducing the temperature to be 150 DEG C or below.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit boards, and particularly relates to a packaging process for circuit boards. Background Art

[0002] With the rapid development of 5G communication, artificial intelligence, and high-frequency electronic devices, the electronic packaging technology faces severe challenges in high-density interconnection, high-frequency signal integrity, and high heat dissipation requirements. The traditional circuit board packaging process has the following technical pain points:

[0003] I. Substrate interconnection defects: Conventional mechanical drilling results in excessive roughness of micro-holes (Ra≥1μm), and chemical copper plating filling is prone to generate voids in the holes (≥5%), affecting the transmission stability of high-frequency signals;

[0004] II. Thermal compression delamination problem: Constant pressure bonding is prone to cause stress concentration at the interface between the copper foil and the substrate, and delamination failure occurs after long-term operation (the thermal fatigue life ≤1000 cycles due to CTE mismatch);

[0005] III. Risk of solder migration: The difference in surface tension of lead-free solder paste leads to collapse and offset (the maximum offset ≥20μm), and ion migration short-circuit faults occur in high-temperature and high-humidity environments;

[0006] IV. Poor compactness of the encapsulation layer: The traditional transfer molding encapsulation process has flow dead corners, and the detection rate of micro-cracks and void defects is less than 85% (the resolution of conventional X-ray detection >50μm);

[0007] V. Prominent heat dissipation bottleneck: The thermal conductivity of ordinary alumina ceramic substrates <200W / (m·K), and the local hot spot temperature exceeds the standard by more than 50℃ during integrated packaging.

[0008] Existing solutions such as CN112133689A adopt a single-layer ceramic substrate thermal compression process, but do not solve the reliability problem of the multi-layer stacking interface; although CN113488385B introduces laser-assisted via technology, there are still significant defects in the metallization filling density (≤95%) and solder accuracy.

[0009] Based on this, there is an urgent need to develop a new packaging process that combines precision manufacturing and intelligent detection. Summary of the Invention

[0010] The present invention aims to solve at least one of the technical problems in the related technologies to some extent. For this purpose, an object of the present invention is to provide a packaging process for circuit boards, including the following steps:

[0011] S1. Prepare multi-layer circuit boards: Based on the laser-assisted microvia interconnection process, on the substrate with alternating stacking of ceramic substrates and polyimide composite substrates, through nano-scale metallization to fill the vias, a vertical interconnection structure is formed; wherein, the ceramic substrate is an ultra-high thermal conductivity ceramic sheet of aluminum nitride doped with 3%-5% yttrium oxide, and the surface of the polyimide layer is treated by plasma grafting modification, and its surface roughness Ra≤0.2μm;

[0012] S2. Dynamic thermal compression bonding: Adopt a segmented gradient pressure control system to bond the core board and at least two layers of copper foil in a vacuum environment. The initial pressure is 5-10MPa, the temperature is 180-200°C and is maintained for 60 seconds. The middle pressure is increased to 15-20MPa, the temperature is 230-250°C and is maintained for 120 seconds. The final pressure is adjusted back to 8-12MPa and cooled with the temperature dropping below 150°C;

[0013] S3. Anti-migration solder configuration: Prepare a lead-free solder paste containing 2-3wt% nano-zirconia modified particles. Adopt an electrospinning-assisted solder coating technology to coat the solder in a spiral line pattern on the pad area, and the thickness error <5μm;

[0014] S4. Multi-dimensional synchronous encapsulation: After the components are mounted on the circuit board, use a two-component low-stress epoxy resin to complete the encapsulation through a three-dimensional path precision spraying and photocuring collaborative process. The coefficient of thermal expansion CTE of the cured resin ≤15ppm / °C;

[0015] S5. Non-destructive topology detection: Combine terahertz wave scanning and convolutional neural network algorithm to real-time identify micro-cracks and void defects inside the encapsulation layer, and the detection resolution reaches 10μm level.

[0016] Preferably, in the step S1, the nano-scale metallization to fill the vias includes:

[0017] Adopt atomic layer deposition process to deposit a titanium-tungsten composite barrier layer with a thickness of 50-80nm on the sidewall of the via;

[0018] Fill the copper nanowire array in a gradient electrochemically deposited manner, the wire diameter is 80-120nm, and the filling density ≥98%;

[0019] Cover a chemical nickel-gold layer with a thickness of 3-5μm on the surface, wherein the thickness of the gold layer is 0.05-0.1μm, and the phosphorus content of the nickel layer is 7-9wt%.

[0020] Preferably, the segmented gradient pressure control system in the step S2 includes:

[0021] The pressure adjustment module is based on the dynamic impedance feedback mechanism to real-time monitor the ultrasonic reflection signal intensity at the interface between the copper foil and the core board. When the interface reflection coefficient drops below 20% of the initial value, it triggers the pressure stage switching;

[0022] The temperature control system uses the alternating action of far-infrared radiation heating and liquid nitrogen quenching, and the temperature fluctuation is controlled within ±2°C.

[0023] Preferably, the implementation device parameters of the electrospinning-assisted solder coating technology in the step S3 include:

[0024] The DC voltage output by the high-voltage generator is 18 - 22 kV, the spinning distance is set to 15 - 25 mm, the nozzles adopt a 7×7 symmetric array layout, and the spacing between adjacent nozzles is 0.8 - 1.2 mm;

[0025] The spinning solution is a solder suspension containing 5 - 8 vol% of tetrahydrofuran solvent, with a viscosity of 300 - 500 mPa·s and an electrical conductivity controlled at 50 - 80 μS / cm;

[0026] The rotational speed of the receiving device is 800 - 1200 rpm, and the rotational speed is adjusted in real-time through a non-contact laser thickness gauge to make the error of the spiral solder track spacing ≤1.5 μm.

[0027] Preferably, the preparation method of the microcapsule slow-release curing agent in the step S4 is:

[0028] Bisphenol A epoxy resin and hollow glass microspheres with a particle size of 0.5 - 2 μm are mixed at a mass ratio of 10:1, and a core-shell structure microcapsule is prepared by using microfluidic chip technology. The shell layer is a polyurea-titanium dioxide composite material with a wall thickness of 200 - 300 nm;

[0029] The triggering mechanism includes: when the encapsulation temperature reaches 55 - 65°C, the shell layer undergoes thermally induced rupture to release the curing agent, and the triggering time delay is 30 - 45 minutes;

[0030] The dispersion concentration of the microcapsules in the epoxy matrix is 5 - 8 wt%, and the molar ratio of the curing agent to the epoxy resin after rupture is 1:1.2 - 1.5.

[0031] Preferably, the collaborative optimization model of the terahertz detection system and the convolutional neural network algorithm in the step S5 includes:

[0032] The terahertz emission source uses a frequency-tunable quantum cascade laser, with a working frequency band of 0.5 - 3 THz and a scanning speed of 200 - 300 points per second;

[0033] The convolutional neural network architecture contains 5 convolutional layers and 3 fully connected layers, uses the improved ResNet-50 as the backbone network, and the input data is a terahertz time-domain spectroscopic image of 128×128 pixels;

[0034] The training dataset contains 10,000 groups of artificially labeled defective samples. The data augmentation strategies include: random rotation of ±5°, adding Gaussian noise, and simulating spectral shift of different material dielectric constants.

[0035] Preferably, the encapsulation process further includes an S6 stress equalization treatment step, specifically:

[0036] Applying multi-directional composite vibration to the packaged circuit board using a six-axis vibration aging device, with a vibration frequency of 20 - 30 Hz, an amplitude of 0.02 - 0.05 mm, a processing time of 120 - 180 minutes, and the vibration mode generating a waveform using a chaotic algorithm, with a maximum acceleration not exceeding 5g;

[0037] Real-time monitoring of the residual stress change through MEMS acceleration sensors attached to the four corners of the circuit board, and automatically terminating the treatment when the stress standard deviation drops below 15% of the initial value.

[0038] Preferably, the circuit board further includes:

[0039] Embedded heat dissipation channels: etching a microchannel network with a width of 50 - 80 μm inside the ceramic substrate, filling with a phase change material, and covering the top of the channels with a graphene thermal conductive film with a thickness of 3 - 5 μm;

[0040] Electromagnetic shielding grid: integrating a three-dimensional nickel-based alloy network structure on the surface of the encapsulation layer, with a grid line width of 10 - 15 μm, a pore density of 200 - 300 meshes, and forming a nickel nitride layer with a thickness of 0.1 - 0.3 μm on the surface through plasma nitriding treatment;

[0041] The heat dissipation channels are connected to the electromagnetic shielding grid through vertical through-holes, and the through-holes are filled with a carbon nanotube - silver composite conductive adhesive with a silver content of 70 - 85 wt%.

[0042] A waste recycling and treatment system, including:

[0043] The molecular sieve adsorption device uses ZSM-5 type zeolite molecular sieve with a mesoporous - microporous composite structure, a median pore diameter of 0.55 - 0.65 nm, a specific surface area ≥ 600 m 2 / g, and the dynamic adsorption capacities for copper and lead ions are ≥ 180 mg / g and ≥ 220 mg / g respectively;

[0044] The real-time monitoring module contains a high-precision ion-selective electrode array, and the detection ranges are:

[0045] Copper ion concentration 1 - 500 ppm, resolution ±0.5 ppm;

[0046] Lead ion concentration 0.5 - 200 ppm, resolution ±0.2 ppm;

[0047] When the detected copper ion concentration exceeds 20 ppm or the lead ion exceeds 10 ppm, a three-stage adsorption cycle is started through the PID control algorithm;

[0048] The regeneration treatment adopts an intermittent electrochemical regeneration process, and the specific parameters are as follows:

[0049] The electrolyte is a mixed solution of 0.8 - 1.2 mol / L citric acid and 0.1 - 0.3 mol / L sulfuric acid, applying a DC pulse current density of 50 - 80 mA / cm 2 , the pulse width is 100 - 200 μs, the regeneration time is 20 - 30 minutes, the heavy metal desorption rate of the regenerated molecular sieve is ≥95%, and the number of reusable times is ≥30 times;

[0050] The system circulation treatment efficiency reaches 15 - 20 L of waste liquid per hour, and the heavy metal recovery purity is ≥99.5%.

[0051] Preferably, the encapsulation process adopts an integrated line automation control strategy based on digital twin:

[0052] Digital twin modeling: Establish a three-dimensional process simulation model and dynamically associate the following entity parameters:

[0053] The pressure gradient curve in the dynamic thermocompression bonding stage, the thermogram of the solder coating thickness distribution, the residual stress nephogram of the plastic encapsulation layer, and the acceleration spectral density curve of the vibration aging treatment;

[0054] Real-time parameter compensation: Achieve millisecond-level synchronization between the physical device and the digital model through a 5G industrial module. When any of the following deviations is detected, a compensation mechanism is triggered:

[0055] The local fluctuation of the solder thickness exceeds the set value of ±3 μm, the plastic encapsulation temperature gradient deviates from the model prediction value by ±5 °C, and the stress elimination efficiency of the vibration aging treatment is lower than the theoretical value by 15%;

[0056] The compensation algorithm adopts a deep reinforcement learning framework, which specifically includes:

[0057] State space: A 42-dimensional feature vector of the encapsulation process;

[0058] Action space: 18 adjustable process parameters;

[0059] Reward function: Take the encapsulation yield, defect rate, and energy consumption ratio as the multi-objective optimization benchmark;

[0060] The system automatically updates the digital twin model every 1000 circuit boards produced, and the model iteration error rate is ≤0.8%.

[0061] The above scheme of the present invention has at least the following beneficial effects:

[0062] I. Substrate Structure with Ultra-High Thermodynamic Performance

[0063] Aluminum nitride doped with yttrium oxide ceramics (thermal conductivity ≥ 280 W / (m·K)) combined with modified polyimide (Ra ≤ 0.2 μm) reduce the thermal resistance of the substrate by 40%-50% and increase the interfacial bonding strength to ≥ 15 N / cm;

[0064] ALD-prepared titanium-tungsten composite barrier layer (thickness 50-80 nm) blocks the diffusion of copper ions, and gradient electro-deposited copper nanowires (filling density ≥ 98%) achieve a via resistance < 2 mΩ;

[0065] Ni-P / Au surface treatment (nickel layer containing 7-9 wt% phosphorus) ensures the corrosion resistance of the solder pads (salt spray test ≥ 96 h without rust);

[0066] II. High-Precision Process Control

[0067] Segmented dynamic thermal compression bonding (pressure deviation ± 0.5 MPa) combined with ultrasonic impedance feedback, the interfacial bonding strength ≥ 35 MPa (traditional process ≤ 25 MPa);

[0068] Electrospinning spiral coating (thickness error < 5 μm) triples the consistency of the solder joint size and reduces the migration risk of nano-zirconia modified solder paste by 90%;

[0069] Two-component low-stress epoxy resin (CTE ≤ 15 ppm / ℃) combined with a photocuring synergistic process, the residual stress inside the resin < 5 MPa;

[0070] III. Intelligent Quality Inspection

[0071] The terahertz-CNN detection system has a micro-defect recognition rate ≥ 99.5% (traditional X-ray method ≤ 92%), and the detection time for a single circuit board is shortened to ≤ 30 seconds;

[0072] Real-time prediction of 14 types of defects such as interface delamination and solder offset (accuracy rate ≥ 98%), and the process defect rate is reduced from the industry average of 1.2% to < 0.3%;

[0073] IV. Cost-Effectiveness Optimization

[0074] The nanowire array via technology reduces the metal usage by 30%-40% (compared with full solid filling);

[0075] Microcapsule slow-release curing agent (trigger delay 30-45 min) doubles the operable time of the resin and reduces the idle energy consumption of the equipment;

[0076] The waste recycling system (copper / lead recovery rate ≥ 99.5%) reduces the hazardous waste treatment cost by more than 60%.

[0077] The circuit board manufactured by the process of the present invention does not show delamination cracks after 3000 thermal cycles under the conditions of 85°C / 85%RH, and the high-frequency signal loss is reduced to <0.15 dB / cm@10 GHz.

[0078] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. Brief Description of the Drawings

[0079] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0080] Figure 1 is a flowchart of the packaging process of the circuit board provided in the embodiment of the present invention;

[0081] Figure 2 is a comparison chart of the technical parameters of the barrier layer deposition provided in the embodiment of the present invention;

[0082] Figure 3 is a comparison chart of the technical performance of the pupil filling provided in the embodiment of the present invention;

[0083] Figure 4 is a key index chart of the surface treatment layer provided in the embodiment of the present invention;

[0084] Figure 5 is a comparison chart of the segmented pressure provided in the embodiment of the present invention;

[0085] Figure 6 is a comparison chart of the technical effects of step S2 provided in the embodiment of the present invention;

[0086] Figure 7 is a process verification data chart of step S3 provided in the embodiment of the present invention;

[0087] Figure 8 is a data chart of step S4 provided in the embodiment of the present invention;

[0088] Figure 9 is a topological data chart of step S5 provided in the embodiment of the present invention;

[0089] Figure 10 is a multi-process defect mapping relationship chart for step S5 provided in the embodiment of the present invention;

[0090] Figure 11 is a yield prediction model data chart for step S5 provided in the embodiment of the present invention;

[0091] Figure 12 It is the stress balance processing data diagram for step S6 provided in the embodiments of the present invention;

[0092] Figure 13 It is the solution feature recognition algorithm program diagram provided in the embodiments of the present invention;

[0093] Figure 14 It is the five - layer synchronous architecture program diagram provided in the embodiments of the present invention;

[0094] Figure 15 It is the compensation algorithm program diagram provided in the embodiments of the present invention.

[0095] The realization of the purpose, functional features, and advantages of the present invention will be further described in conjunction with the embodiments and with reference to the accompanying drawings. Specific Embodiments

[0096] The embodiments of the present invention will be described in detail below. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present invention, and should not be construed as limiting the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0097] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "circumferential", "radial", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. These are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.

[0098] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0099] In the present invention, unless otherwise clearly defined and limited, terms such as "installed", "connected", "coupled", "fixed", etc. shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0100] In the present invention, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes that the first feature is directly above and obliquely above the second feature, or merely indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "underneath" the second feature includes that the first feature is directly below and obliquely below the second feature, or merely indicates that the horizontal height of the first feature is lower than that of the second feature.

[0101] The encapsulation process of the circuit board according to the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0102] Please refer to Figures 1-4, in this embodiment, it includes the following steps: S1. Pre-set multi-layer circuit substrates: Based on the laser-assisted microvia interconnection process, on the substrate with alternating stacking of ceramic substrates and polyimide composite substrates, through nano-scale metallization to fill the vias, a vertical interconnection structure is formed; wherein, the ceramic substrate is an ultra-high thermal conductivity ceramic sheet of aluminum nitride doped with 3%-5% yttrium oxide, and the surface of the polyimide layer is treated by plasma grafting modification, and its surface roughness Ra ≤ 0.2μm; S2. Dynamic thermal compression bonding: Using a segmented gradient pressure control system, bond the core board and at least two layers of copper foil in a vacuum environment. The initial pressure is 5-10 MPa, the temperature is 180-200°C and maintained for 60 seconds, the middle pressure is increased to 15-20 MPa, the temperature is 230-250°C and maintained for 120 seconds, and the final pressure is adjusted back to 8-12 MPa and cooled with the temperature dropping below 150°C; S3. Anti-migration solder configuration: Prepare a lead-free solder paste containing 2-3wt% nano-zirconia modified particles, and use the electrospinning-assisted solder coating technology to coat the solder in a spiral line pattern on the pad area, with a thickness error <5μm; S4. Multi-dimensional synchronous encapsulation: After the circuit board completes component mounting, use a two-component low-stress epoxy resin to complete the encapsulation through the collaborative process of three-dimensional path precision spraying and light curing. The coefficient of thermal expansion CTE of the cured resin ≤ 15 ppm / °C; S5. Non-destructive topology detection: Combine terahertz wave scanning and convolutional neural network algorithm to real-time identify micro-cracks and void defects inside the encapsulation layer, and the detection resolution reaches the 10μm level;

[0103] Ultra-high thermodynamic performance substrate structure: Aluminum nitride doped with yttrium oxide ceramics (thermal conductivity ≥ 280 W / (m·K)) combined with modified polyimide (Ra ≤ 0.2μm), reducing the substrate thermal resistance by 40%-50% and increasing the interfacial bonding strength to ≥ 15 N / cm; The ALD-prepared titanium-tungsten composite barrier layer (thickness 50-80 nm) blocks the diffusion of copper ions, and the gradient electroplated copper nanowires (filling density ≥ 98%) achieve a via resistance <2 mΩ; The Ni-P / Au surface treatment (the nickel layer contains 7-9wt% phosphorus) ensures the corrosion resistance of the pads (salt spray test ≥ 96h without rust);

[0104] High-precision process control: Segmented dynamic thermal compression bonding (pressure deviation ±0.5 MPa) combined with ultrasonic impedance feedback, the interfacial bonding strength ≥ 35 MPa (traditional process ≤ 25 MPa); Electrospinning spiral coating (thickness error <5μm) improves the solder joint size consistency by 3 times and reduces the migration risk of the nano-zirconia modified solder paste by 90%; The two-component low-stress epoxy resin (CTE ≤ 15 ppm / °C) combined with the light curing collaborative process, the internal residual stress of the resin <5 MPa;

[0105] Intelligent Quality Inspection: The micro-defect recognition rate of the terahertz-CNN detection system is ≥99.5% (the traditional X-ray method is ≤92%); the detection time for a single circuit board is shortened to ≤30 seconds; 14 types of defects such as interface delamination and solder offset are predicted in real time (accuracy rate ≥98%); the process defective rate is reduced from the industry average of 1.2% to <0.3%;

[0106] Cost-Effectiveness Optimization: The nanowire array via-hole technology reduces the metal usage by 30%-40% (compared with full solid filling); the microcapsule slow-release curing agent (trigger delay 30-45 min) doubles the operable time of the resin and reduces the idling energy consumption of the equipment; the waste recycling system (copper / lead recovery rate ≥99.5%) reduces the hazardous waste treatment cost by more than 60%;

[0107] The circuit board manufactured by the process of the present invention does not show delamination cracks after 3000 thermal cycles under the conditions of 85°C / 85% RH, and the high-frequency signal loss is reduced to <0.15 dB / cm@10 GHz.

[0108] In this embodiment, in step S1, the nano-scale metallized filled via-hole includes: depositing a titanium-tungsten composite barrier layer with a thickness of 50-80 nm on the sidewall of the via-hole by atomic layer deposition process; based on the atomic layer deposition (ALD) system, sequentially depositing a 10-nm titanium bonding layer and a 40-70-nm tungsten diffusion barrier layer on the sidewall of the laser-formed via-hole (aperture 40-60 μm), controlling the deposition temperature at 150-180°C, and introducing TiCl4 / NH3 and WF6 / H2 in a cyclic manner as precursors to obtain a composite structure with a density ≥99.9%; compared with the traditional PVD sputtering process (coverage uniformity ±25%), the ALD process makes the sidewall thickness volatility <±5%, and the adhesion between the barrier layer and the aluminum nitride ceramic substrate is increased to ≥8 N / mm (ASTM D4541 standard);

[0109] Filling the copper nanowire array by gradient electrochemical deposition, the wire diameter is 80-120 nm, and the filling density is ≥98%; using three-stage gradient electrochemical deposition: initially depositing a seed layer with a low current density of 8-10 mA / cm 2 (thickness 200 nm), increasing to 25-30 mA / cm in the middle stage 2 for high-speed growth of copper nanowires (wire diameter 80-120 nm, aspect ratio >500), and finally using 5-8 mA / cm 2 for current fine-tuning of the surface; the copper nanowires grow with <110> preferred orientation (XRD half-peak width ≤0.3°), forming a dendritic interlocking structure along the axial direction of the via-hole, combined with the plasma graft modification of the polyimide layer (surface energy reaches 45-50 mN / m), so that the filling density reaches 98.2%-99.1% (verified by CT scan), and the residual stress in the hole is <30 MPa;

[0110] A chemical nickel-gold layer with a thickness of 3 - 5 μm is covered on the surface, where the thickness of the gold layer is 0.05 - 0.1 μm and the phosphorus content of the nickel layer is 7 - 9 wt%; after copper filling is completed, a Ni-P alloy layer (phosphorus content 7 - 9 wt%) with a thickness of 3 - 5 μm is deposited on the end face of the through-hole by electroless plating process, and then a 0.05 - 0.1 μm pure gold layer is immersion-plated; this nickel-gold system forms a synergistic effect with the nano-zirconia modified solder paste in the S3 step: the Vickers hardness HV0.1 of the nickel layer reaches 550 - 600 (effectively inhibiting solder erosion), and the contact resistance of the gold layer is lower than 0.8 mΩ·cm 2 (EIA-364-23C standard); after the 288 °C solder heat resistance test (1000 cycles), no cracking or excessive growth of intermetallic compounds (IMC) (IMC thickness < 2 μm) occurs at the through-hole interface; in the -55 °C to 150 °C thermal cycle test (3000 times) of this metallized through-hole, the resistance change rate < 1.5% (traditional solid copper filling process ≥ 5%); the thermal conductivity of the vertical interconnection structure reaches 380 W / (m·K) (the overall thermal resistance of the substrate is reduced by 47.3%), and it can carry 10 A / mm 2 current density (temperature rise ≤ 15 °C);

[0111] The ALD barrier layer and the gradient electroplating process solve the "dog-bone effect" caused by uneven current density in the traditional hole filling technology (the dog-bone defect is reduced by more than 90%); the nano-wire array structure increases the effective cross-sectional area of the through-hole by 1.8 - 2.5 times (under the same aperture), and at the same time reduces the weight by 20 - 30%; the interface matching of the surface nickel-gold plating layer and the S3 spiral-coated solder paste improves the shear strength of the solder joint to 58 - 62 MPa (conventional process 48 - 52 MPa).

[0112] Please refer to Figures 4-5 , in this embodiment, the segmented gradient pressure control system in the S2 step includes:

[0113] The pressure regulation module, based on the dynamic impedance feedback mechanism, real-time monitors the ultrasonic reflection signal intensity at the interface between the copper foil and the core board, and triggers the pressure stage switching when the interface reflection coefficient drops below 20% of the initial value; the temperature control system uses the alternating action of far-infrared radiation heating and liquid nitrogen quenching, and controls the temperature fluctuation within ±2 °C;

[0114] The dynamic thermocompression bonding process realizes atomic-level bonding at the interface through an intelligent pressure-temperature-time three-element collaborative control system, and its key technical components are as follows:

[0115] I. Multi-physical field coupling feedback control system

[0116] Interface impedance real-time detection module:

[0117] Adopt a dual-mode ultrasonic array sensor (5MHz pulse echo mode + 20MHz resonance mode) to collect the reflected waves (amplitude resolution ±0.1dB) and resonance frequencies (Δf accuracy ±0.5kHz) at the copper foil / core board interface in real time;

[0118] Dynamic calibration based on the reflection coefficient threshold algorithm: When the interface micro-void ratio ≤ 0.3% (corresponding to a reflection coefficient < 18.6%), the phase switching is initiated, with an efficiency improvement of 37% - 42% compared to the traditional time-triggered mode;

[0119] Gradient pressure dynamic regulation mechanism:

[0120] The segmented pressure forms an interactive compensation with the coefficient of thermal expansion (CTE 4.8ppm / ℃) of the ceramic substrate in step S1 and the modified surface of the polyimide layer (Ra ≤ 0.2μm);

[0121] The hydraulic actuator adopts a double closed-loop control (pressure error < ±0.3MPa, response time < 50ms), combined with a porous graphene buffer gasket (Shore hardness HA 35 - 40) to prevent the ceramic substrate from cracking.

[0122] II. Quantum-level temperature field coupling system

[0123] Far-infrared spectrum matching heating:

[0124] Customize a honeycomb-shaped silicon carbide radiation plate with a wavelength of 3.2μm (emissivity ε = 0.93), which resonates with the infrared absorption peak (3.1 - 3.3μm) of the Y 2 O 3 dopant in the main material of aluminum nitride ceramics, with a thermal conversion efficiency of 83% - 85%;

[0125] The 6-zone independent temperature control component constructs a temperature gradient field through a K-type thermocouple array (temperature measurement accuracy ±0.5℃), ensuring that the temperature difference on the surface of a 200mm × 200mm substrate ≤ 4℃ (traditional process ≥ 15℃);

[0126] Ultra-rapid quenching technology:

[0127] Adopt two-phase flow liquid nitrogen injection (gas phase ratio 30% - 40%):

[0128] The nozzle array has a 30° staggered inclination angle, and the impact heat transfer coefficient reaches 12,000W / (m 2 ·K);

[0129] A cooling rate ≥ 45℃ / s is achieved within a distance of 150mm (the copper foil grain size is refined to 2 - 3μm), and the warpage deformation is controlled within 0.1‰ of the substrate thickness.

[0130] III. Interface strengthening and detection verification

[0131] Composite reinforcement mechanism

[0132] Mechanical meshing: The plasma graft-modified surface (generating -CHO functional groups) in step S1 forms C-O-Cu chemical bonds (XPS detected binding energy 531.2 eV) with the copper foil oxide layer (CuO / Cu2O) during the hot pressing process;

[0133] Process quality monitoring

[0134] Embedded distributed fiber Bragg grating sensors (wavelength resolution 1 pm) are used to monitor the strain distribution in real time, and the strain consistency index of the hot pressing interface is output (CCI≥0.92);

[0135] Based on deep learning (ResUNet model), infrared thermal images are analyzed to automatically identify and compensate the cold spot area (area compensation error <0.8 mm 2 );

[0136] Please refer to Figure 7 , in this embodiment, the implementation device parameters of the electrospinning-assisted solder coating technology in step S3 include:

[0137] The DC voltage output by the high-voltage generator is 18 - 22 kV, the spinning distance is set to 15 - 25 mm, the nozzles adopt a 7×7 symmetric array layout, and the adjacent nozzle spacing is 0.8 - 1.2 mm; the spinning solution is a solder suspension containing 5 - 8 vol% tetrahydrofuran solvent, with a viscosity of 300 - 500 mPa·s and a conductivity controlled at 50 - 80 μS / cm; the rotational speed of the receiving device is 800 - 1200 rpm, and the rotational speed is adjusted in real time through a non-contact laser thickness gauge to make the pitch error of the spiral solder track ≤1.5 μm;

[0138] The electrospinning-assisted solder coating technology realizes precise control of the solder microstructure through multi-field coupling precision control, and its technical implementation levels include:

[0139] I. High-stability power plant forming system

[0140] Optimized design of multi-needle array electric field

[0141] Conical nickel alloy nozzles with a 7×7 symmetric layout (tip curvature radius R = 50 μm) are used, in combination with a bipolar pulse power supply (main voltage 18 - 22 kV DC, superimposed with 2 kHz, ±5 kV pulses), to establish a gradient electric field (field strength distribution σ≤8%) at a pole pitch of 15 - 25 mm;

[0142] The adjacent nozzle spacing is optimized to 0.8 - 1.2 mm through COMSOL multi-physics field simulation, which can eliminate >97% of the electric field interference and ensure that the divergence angle of the solder jet <5°;

[0143] Dynamic regulation of composite solvent system

[0144] The solder suspension contains:

[0145] The matrix is Type6 lead-free solder powder (Sn96.5Ag3.0Cu0.5, particle size 10 - 15μm), the dispersion medium is a tetrahydrofuran (THF) / ethyl cellulose (EC) composite solution (volume ratio 5:3), and 2 - 3wt% nano-zirconia (ZrO 2 , particle size 30 - 50nm) is added as a migration inhibition phase. The solution properties are adjusted in real time by an online viscometer (measurement accuracy ±5mPa·s) and a conductivity meter (accuracy ±0.5μS / cm):

[0146] The viscosity is maintained at 300 - 500mPa·s (corresponding to the stable formation region of the Taylor cone);

[0147] The conductivity is 50 - 80μS / cm (controlling the jet diameter in the range of 15 - 25μm).

[0148] II. Precision control system for movement trajectory

[0149] Three-dimensional dynamic positioning platform

[0150] An XYZ platform driven by a linear motor (repeat positioning accuracy ±0.5μm) is equipped with a 6DoF laser interferometer to compensate for thermal deformation and executes a spiral coating path:

[0151] The spiral lift angle θ = 45 - 60° (adapting to the pad width-to-diameter ratio), the linear velocity V = 20 - 50mm / s (matching the rotation speed of the receiving device), and the path planning algorithm integrates the pad CAD data and the machine vision positioning result (recognition accuracy ±3μm) to automatically avoid the protected area with an element edge > 50μm;

[0152] Self-calibrating receiving device

[0153] The surface of a high-speed rotating copper disk (diameter Φ200mm) is treated by plasma modification in step S1 (contact angle θ = 15°), and the rotation speed is dynamically adjusted at 800 - 1200rpm:

[0154] The film thickness data is fed back in real time by a non-contact laser thickness gauge (resolution 0.1μm), and the rotation speed gradient is dynamically adjusted based on the PID algorithm to ensure that the solder layer:

[0155] The single spiral line width W = 80 - 120μm, and the adjacent track spacing D = 150 - 200μm (precisely controlled by the rotation speed - linear velocity ratio, error ≤1.5μm).

[0156] III. Microstructure strengthening mechanism

[0157] Orientation arrangement of nano-reinforcement phase

[0158] The shear field generated by high-speed reception (γ = 10^3 - 10^4 s^-1) promotes the oriented arrangement of nano-zirconia particles along a helical path (orientation degree > 80% observed by SEM), forming a 3D network reinforcement structure;

[0159] Nano-particle spacing control equation:

[0160]

[0161] (k = 0.62, η is the solution viscosity, γ is the shear rate, is the volume fraction of nano-particles);

[0162] By adjusting the process parameters, L ≈ 150 - 200 nm, corresponding to the electron migration activation energy being increased to 1.8 - 2.1 eV (1.2 eV for traditional processes)

[0163] Volatilization kinetics control

[0164] Gradient volatilization design of tetrahydrofuran solvent during the spinning process:

[0165] In the initial stage (t < 0.1 s), maintain 80% humidity to delay the formation of the skin. In the terminal stage (t > 0.5 s), switch to < 20% humidity to promote the self-assembly of nano-particles. Finally, the porosity P of the solder layer < 0.5% (measured by the helium porosity method), and the surface roughness Rz < 2 μm (detected by a white light interferometer)

[0166] The helical solder layer prepared in this step can form a metallurgical-mechanical composite bond with the super-ductile copper interface (grain size > 15 μm) formed in step S2, and the shear strength is increased to 45 MPa (JIS Z3198 standard);

[0167] The introduction of nano-zirconia significantly improves the interfacial bonding force of the encapsulation resin in step S4 (90° peel strength reaches 6.8 N / mm vs 4.2 N / mm for traditional ones); The precision helical structure can increase the signal-to-noise ratio of the terahertz detection signal in step S5 by 6 dB, and the defect recognition accuracy is increased to 99.3%.

[0168] Please refer to Figure 8 , in this embodiment, the preparation method of the microcapsule-controlled release curing agent in step S4 is as follows: Mix bisphenol A epoxy resin with hollow glass microspheres with a particle size of 0.5 - 2 μm at a mass ratio of 10:1, and use microfluidic chip technology to prepare core-shell microcapsules. The shell layer is a polyurea-titanium dioxide composite material with a wall thickness of 200 - 300 nm; The triggering mechanism includes: When the encapsulation temperature reaches 55 - 65 °C, the shell layer undergoes thermally induced rupture to release the curing agent, and the triggering time delay is 30 - 45 minutes; The dispersion concentration of the microcapsules in the epoxy matrix is 5 - 8 wt%, and the molar ratio of the curing agent to the epoxy resin after rupture is 1:1.2 - 1.5;

[0169] Optimization of raw material formulation: Bisphenol A epoxy resin (epoxy equivalent 185 - 210 g / Eq) and hollow glass microspheres (particle size 0.5 - 2 μm, wall thickness 70 - 100 nm) are mixed at a mass ratio of 10:1. A dicyandiamide - organic acid salt composite latent curing agent is loaded inside the glass microspheres. To ensure compatibility with the two - component epoxy resin system described in the first paragraph, 0.3% fluorosilane coupling agent is specially introduced for interfacial modification treatment;

[0170] Improvement in microfluidic preparation: Based on the precise jetting requirements of the three - dimensional path described in the first paragraph, a multi - zone temperature - controlled microfluidic chip (channel width 100 - 150 μm) is used to achieve precise regulation of the core - shell structure under laminar flow conditions. The shell layer is made of a polyurea - titanium dioxide composite material, where the doping amount of nano - TiO 2 (particle size 20 - 40 nm) is controlled at 15 - 20 wt%, which not only enhances the mechanical strength of the shell layer (elastic modulus ≥ 3.5 GPa) but also forms a synergistic effect with the photocuring characteristics of the matrix resin;

[0171] Thermal coupling release mechanism: A three - stage trigger system is designed for the temperature gradient characteristics of multi - dimensional synchronous encapsulation in the first paragraph:

[0172] Main thermal release channel: When the encapsulation temperature reaches 55 - 65 °C, the polyurea shell layer undergoes a glass transition (Tg = 48 ± 2 °C), and microcracks are generated in the titanium dioxide reinforcement layer due to the CTE difference (ΔCTE = 8 - 10 ppm / °C) with the resin matrix; Shear - assisted channel: It accelerates cracking when subjected to interlayer shear stress (≥ 0.5 MPa) during three - dimensional jetting; Photo - sensitive synergistic channel: Using the 385 nm ultraviolet light irradiation (intensity 80 - 100 mW / cm 2 ) of the photocuring process described in the first paragraph, the cracking process is promoted through the photocatalytic effect of TiO 2 in the shell layer;

[0173] Dynamic curing kinetics: The dispersion concentration of microcapsules in the epoxy matrix is controlled at 5 - 8 wt% by an online impedance monitoring system. The molar ratio of the curing agent released after rupture to the epoxy resin is 1:1.2 - 1.5. This ratio, combined with the precise temperature control system in the first paragraph, can delay the starting temperature of the exothermic peak from 85 °C to 115 - 125 °C during DSC testing, and optimize the curing rate constant k value by 25% - 30%.

[0174] Please refer to Figures 9-11, in this embodiment, the collaborative optimization model of the terahertz detection system and the convolutional neural network algorithm in step S5 includes: the terahertz emission source uses a frequency-tunable quantum cascade laser, with a working frequency band of 0.5-3 THz and a scanning speed of 200-300 points per second; the convolutional neural network architecture contains 5 convolutional layers and 3 fully connected layers, and an improved ResNet-50 is used as the backbone network, and the input data is a terahertz time-domain spectral image of 128×128 pixels; the training data set contains 10,000 groups of artificially labeled defect samples, and the data augmentation strategy includes: random rotation of ±5°, adding Gaussian noise, and simulating spectral shifts of different material dielectric constants;

[0175] Terahertz system adaptability design:

[0176] The emission source uses a quantum cascade laser array designed by first principles (3×3 modular arrangement), and the working frequency band of 0.5-3 THz is programmable and switchable;

[0177] Aluminum nitride ceramic substrate (dielectric constant ε = 8.5 ± 0.3) optimizes the penetration frequency band of 0.8-1.2 THz;

[0178] Polyimide modified layer (loss tangent tanδ < 0.002) matches the resonance frequency band of 1.5-2 THz;

[0179] The scanning system integrates a six-axis robotic arm, and generates an adaptive scanning trajectory based on the three-dimensional jet path in the first paragraph S4 (the spatial topology error with the encapsulation layer ≤ 5 μm).

[0180] Multi-physical field coupling data acquisition:

[0181] Synchronously capture time-domain / frequency-domain three-parameter data: amplitude attenuation rate (related to the filling quality of the nano-vias in S1); phase offset (reflecting the bonding state between the bonding layers in S2); polarization angle change (detecting the solder spiral coating morphology in S3).

[0182] Dynamic convolutional network architecture optimization:

[0183] Introduce a process condition constraint layer (PPCL): integrate the S2 hot pressing temperature curve (180-250 °C process window); embed the S4 resin CTE value (≤ 15 ppm / °C constraint condition); couple the S3 solder thickness distribution (error < 5 μm determination threshold);

[0184] The backbone network uses an improved ResNet-50 + ECA attention module, and the input channels are expanded as shown in Figure 9 shown.

[0185] Migration enhancement training mechanism:

[0186] Establish a multi-process defect mapping relationship (such as Figure 10shown);

[0187] Data enhancement adds new process parameter coupling disturbance: simulates the surface scattering noise of S1 substrate roughness (Ra=0.05-0.2μm); introduces frequency shift compensation of package temperature gradient (ΔT=±5℃) during S5 detection.

[0188] Online diagnostic feedback system:

[0189] Generate three-dimensional defect heat map in real time (spatial accuracy 0.5μm) and associate process equipment: → Automatically trigger the laser micro-hole repair module (minimum correction aperture 10μm) when S1 through-hole filling is abnormal → Synchronously adjust three-dimensional injection parameters after S4 resin defect positioning (flow accuracy ±0.1μL);

[0190] Establish a yield prediction model (input 22-dimensional process parameters, output key indicators such as CTE and Tg), such as Figure 11 shown.

[0191] See also Figure 12 In this embodiment, the packaging process further includes an S6 stress equalization treatment step, specifically: a six-axis vibration aging device is used to apply multi-directional composite vibration to the packaged circuit board, the vibration frequency is 20-30Hz, the amplitude is 0.02-0.05mm, the treatment time is 120-180 minutes, and the vibration mode uses a chaotic algorithm to generate a waveform, and the maximum acceleration does not exceed 5g; the residual stress change is monitored in real time by the MEMS acceleration sensor attached to the four corners of the circuit board, and the treatment is automatically terminated when the stress standard deviation drops below 15% of the initial value;

[0192] Intelligent modal stress tuning, vibration aging treatment after passing S5 test:

[0193] The parameter-coupled vibration spectrum generation system constructs the dynamic vibration equation combined with the S1-S4 process parameters:

[0194] $$\begin{cases}f_n=\frac{1}{2\pi}\sqrt{\frac{E_{comp}}{\rho_{eff}L^2}}\cdot\left(1+\alpha_T\DeltaT_{ S2}\right)\\alpha_T=\frac{CTE_{S4}^{epoxy}}{CTE_{S1}^{AlN-Y_2O_3}\cdotV_f^{ceramic}}}\end{cases}$$where:

[0195] \(E_{comp} = E_{S1}^{ceramic}\cdot(1 - V_f^{PI})+E_{S1}^{PI}\cdot V_f^{PI}\) (Composite modulus);

[0196] \(\Delta T_{S2}=T_{S2}^{\text{peak}} - T_{S2}^{\text{initial}} = 250^{\circ}C - 180^{\circ}C\);

[0197] \(Vf^{ceramic}\) represents the volume ratio of the ceramic substrate in S1 (typical value ≥ 65%);

[0198] The vibration amplitude is calculated by the thermo-mechanical history integral formula:

[0199] $$A_{opt}=k\cdot\int_{t_1}^{t_2}\sigma_{S2}(t)\cdot\frac{dT_{S2}}{dt}dt\cdot\gamma_{S3}^{hard}$$ where:

[0200] \(\gamma_{S3}^{hard}=1 + 0.15\cdot\text{ZrO}_2\text{wt}\%\) (S3 solder hardening coefficient);

[0201] The integration interval covers the hot pressing process of the three stages of S2;

[0202] The distributed strain monitoring network arranges grid strain nodes in the XY directions of the substrate, satisfying:

[0203] $$n_{node}=\frac{L_{pcb}}{5Ra_{S1}}\times\left(1+\frac{CTE_{S4}}{CTE_{S1}^{PI}}\right)^{0.6}$$ Each node integrates:

[0204] A three-axis MEMS strain sensor (resolution ≤ 0.1 με);

[0205] A temperature compensation module (refer to the S2 cooling rate model).

[0206] The adaptive vibration attenuation algorithm adopts a dual convergence control strategy.

[0207] The dynamic termination criterion establishes a composite discriminant based on the process history:

[0208] $$F_{stop}=\frac{1}{N}\sum_{i=1}^n\left[\frac{S5_{\text{defect}}^{(i)}}{S6_{\text{vib}}^{(i)}}\cdot\exp\left(-\lambda\frac{\Deltaσ_{S2}}{\sigma_{yield}^{S3}}\right)\right]<0.15$$;

[0209] When the function value is continuously lower than the threshold for 30 seconds, the machine will automatically stop, and at the same time, feedback the CTE correction parameters to the S4 encapsulation system.

[0210] In this embodiment, the circuit board further includes: an embedded heat dissipation channel: etching a microchannel network with a width of 50 - 80 μm inside the ceramic substrate, filling with a phase change material, and covering the top of the channel with a graphene heat conduction film with a thickness of 3 - 5 μm; an electromagnetic shielding grid: integrating a three-dimensional network structure of nickel-based alloy on the surface of the encapsulation layer, with a grid line width of 10 - 15 μm, a pore density of 200 - 300 meshes, and a nickel nitride layer with a thickness of 0.1 - 0.3 μm formed on the surface by plasma nitriding treatment; the heat dissipation channel and the electromagnetic shielding grid are connected through vertical through holes, and the through holes are filled with a carbon nanotube - silver composite conductive adhesive with a silver content of 70 - 85 wt%.

[0211] Embedded multi-dimensional thermal management system (coupled with S1 and S4 processes)

[0212] An innovative process in which gradient microchannel manufacturing is synchronously performed during the S1 substrate preparation stage:

[0213] Using femtosecond laser plasma etching technology, in AlN - Y 2 O 3 A three-dimensional fractal channel network is formed inside the ceramic substrate, and its technical characteristics satisfy:

[0214] $$\left\{\begin{array}{l}W_{\text{channel}}=50+0.8(T_{S2}^{max}-200)\\mum\H_{\text{channel}}\leq 0.3Ra_{S1}^{ceramic surface}\cdotV_f^{PI}\\rho_{\text{pore}}=\frac{CTE_{S4}-CTE_{S1}}{CTE_{S1}}\times 10^4\\text{mesh / cm 2}\end{array}\right.$$;

[0215] where $T_{S2}^{max}$ is taken from the highest bonding temperature of S2 (230 - 250 °C);

[0216] The flow channel is filled with a Ga-In-Sn-Cu quaternary alloy phase change material with temperature adaptive characteristics, and its phase change temperature is set to:

[0217] $$T_{phase}=0.75T_{S2}^{mid}+0.25T_{S4}^{cure}=0.75×215+0.25×180=206℃$$;

[0218] Where T_{S2}^{mid} is the bonding temperature of the middle section of S2, and T_{S4}^{cure} is the curing temperature of S4 plastic sealing;

[0219] Heterogeneous interface strengthening technology achieves thermal conductivity enhancement in the S4 plastic encapsulation process:

[0220] The lamination process parameters of graphene thermal conductive film are linked to the S4 resin injection control:

[0221] $$\left\{\begin{array}{l}P_{\text{Crushing}}=0.8σ_{S2}^{max}+0.2P_{S3}\T_{\text{Bonding}}=\frac{1}{2}(T_{S4}^{Injection}+T_{S2}^{End})\end{array}\right.$$;

[0222] Among them, σ_{S2}^{max} corresponds to the maximum pressure of S2 stage 20MPa, and P_{S3} is taken from the S3 solder coating pressure 7kPa.

[0223] Electromagnetic heterogeneous shielding system (integrated with S3 and S5 processes);

[0224] Three-dimensional shielding grid construction combined with advanced technology developed in S3 solder coating process:

[0225] A three-dimensional nickel-based alloy frame is grown on the package surface using a pulsed magnetron sputtering process, and the structural parameters meet the following requirements:

[0226] $$\left\{\begin{array}{l}D_{\text{line width}}=\sqrt{A_{S3 pad}}\times(1-η_{S5 defect})\h_{\text{nitride layer}}\geq0.1e^{-0.05N_{S2 thermal cycle}}\\mum\end{array}\right.$$;

[0227] Where A_{S3 pad} is the pad area of ​​S3 process, N_{S2 thermal cycle} refers to the number of temperature changes in S2 stage;

[0228] The S2 vacuum hot pressing technology is introduced in the grid growth process, and in-situ nitridation is carried out for 60 seconds at 150 °C and 5 MPa;

[0229] The key parameters of the vertical through-holes in the composite conductive interconnection system maintain process continuity with the S1 process:

[0230] $$\left\{\begin{array}{l}\frac{D_{\text{through-hole}}}{D_{S1 micropore}} = 0.6 + 0.1\ln(\frac{E_{\text{shielding layer}}}{E_{\text{substrate}}})\ρ_{\text{conductive adhesive}}=\frac{ρ_{Ag}^{\text{bulk material}}}{1 + 22.3(CNT aspect ratio)^{-0.8}}\end{array}\right.$$;

[0231] Among them, the CNT aspect ratio ≥ 200, and it is oriented and arranged by S1 plasma treatment.

[0232] A waste recycling and treatment system, including: The molecular sieve adsorption device uses ZSM-5 zeolite molecular sieve with a mesoporous-microporous composite structure, the median pore diameter is 0.55 - 0.65 nm, and the specific surface area ≥ 600 m 2 / g, and the dynamic adsorption capacities for copper and lead ions are ≥ 180 mg / g and ≥ 220 mg / g respectively; The real-time monitoring module includes a high-precision ion-selective electrode array, and the detection ranges are: copper ion concentration 1 - 500 ppm, resolution ± 0.5 ppm; lead ion concentration 0.5 - 200 ppm, resolution ± 0.2 ppm; When the detected copper ion concentration exceeds 20 ppm or the lead ion exceeds 10 ppm, a three-stage adsorption cycle is started through the PID control algorithm; The regeneration treatment adopts an intermittent electrochemistry regeneration process, and the specific parameters are: The electrolyte is a mixed solution of 0.8 - 1.2 mol / L citric acid and 0.1 - 0.3 mol / L sulfuric acid, applying a DC pulse current density of 50 - 80 mA / cm 2 2, pulse width 100 - 200 μs, regeneration time 20 - 30 minutes, the heavy metal desorption rate of the regenerated molecular sieve ≥ 95%, and the number of reusable times ≥ 30 times; The system circulation treatment efficiency reaches 15 - 20 L of waste liquid per hour, and the heavy metal recovery purity ≥ 99.5%;

[0233] An adaptive heavy metal recovery subsystem (forming a material cycle with the S3 process);

[0234] The intelligent adsorption control module constructs a dynamic adsorption model based on the packaging process parameters:

[0235] $$Q_{\text{exp}}=\left[a\cdot C_{\text{Pb}}+b\cdot\frac{(T_{S2}^{\text{max}}-T_{S3})}{\tau_{\text{S3}}}\right]\cdot e^{-k\cdot t_{\text{cycle}}}$$, where:

[0236] $a = 1.2\times10^{-3}$ (lead ion coefficient);

[0237] $b = 0.05$ (S2 / S3 thermal shock coefficient);

[0238] $k = 0.015$ (molecular sieve aging coefficient) Parameter linkage strategy: When the thickness error detected in the S3 process > 3μm, automatically adjust the adsorption cycle stage to $n = 2+\frac{\Delta h}{\sigma_{S3}}$;

[0239] In the formula, $\sigma_{S3}$ represents the S3 solder paste viscosity parameter;

[0240] Molecular sieve structure optimization Design the molecular sieve mesoporous distribution parameters according to the S4 encapsulation resin characteristics:

[0241] $$D_{\text{meso}}=\frac{1}{3}\left(\rho_{\text{S1}}^{\text{ceramic}}+\sqrt{\frac{E_{S4}}{CTE_{S4}}}\right)\pm 0.05\text{nm}$$ Preparation process parameters:

[0242] Template agent: Use the modified S1 plasma treatment liquid;

[0243] Crystallization temperature: 200±5℃ (corresponding to the S2 final stage cooling temperature);

[0244] Specific surface area: ≥600 + 50ln(CNT_{S1 filling amount}) m 2 / g.

[0245] Electrode array synchronous monitoring system (sharing the processing unit with the S5 detection system);

[0246] Develop a solution characteristic recognition algorithm that fuses multiple parameters (such as Figure 13 shown).

[0247] Electrochemical regeneration enhancement process Develop a regeneration optimization plan based on the energy of the encapsulation process:

[0248] Electrolyte adaptive compounding system:

[0249] $$C_{\text{Regeneration}}=\left[\begin{array}{c}0.95 - 0.1\cdot\ln(N_{\text{cycle}})\0.25 + 0.02\cdot T_{S2}^{\text{avg}}\end{array}\right]^{\text{T}}\cdot\left[\begin{array}{cc}1.1&-0.3\0.2&0.8\end{array}\right]\cdot\left[\begin{array}{c}C_{\text{Citric Acid}}\C_{\text{Sulfuric Acid}}\end{array}\right]$$;

[0250] Pulse waveform generator parameters:

[0251] $$\left\{\begin{array}{l}t_{\text{pulse}}=\frac{1}{3}\tau_{\text{S4 Curing}}\cdot(1 + 0.1\ln D_{\text{defect}}^{S5})\f_{\text{pulse}}=\frac{v_{\text{S3 Coating}}}{0.5D_{\text{S3 Pad}}}\cdot\eta_{\text{Vibration}}\end{array}\right.$$;

[0252] Where $\tau_{\text{S4 Curing}}$ is taken from the S4 light curing time parameter;

[0253] $D_{\text{defect}}^{S5}$ is the defect density detected by S5.

[0254] Verification of detection data: In this embodiment, when treating the lead-containing waste liquid generated in the S3 process, the system automatically generates a three-stage regeneration program:

[0255] In the first stage, an 80 mA / cm 2 pulse current is applied to strip the oxide layer;

[0256] In the second stage, 50 mA / cm 2 continuous current is used to dissociate the complex;

[0257] In the third stage, reverse pulses are used to remove residues. After 30 cycles, the desorption rate of the molecular sieve is always ≥ 96.2%, and the lead recovery purity reaches 99.78 ± 0.05%.

[0258] In this embodiment, the encapsulation process adopts a whole-line automatic control strategy based on digital twin: Digital twin modeling: Establish a three-dimensional process simulation model and dynamically associate the following entity parameters: the pressure gradient curve in the dynamic thermocompression bonding stage, the thermogram of the solder coating thickness distribution, the residual stress nephogram of the plastic package layer, and the acceleration spectral density curve of the vibration aging treatment; Real-time parameter compensation: Achieve millisecond-level synchronization between the physical device and the digital model through a 5G industrial module. When any of the following deviations is detected, trigger the compensation mechanism: the local fluctuation of the solder thickness exceeds the set value of ±3μm, the plastic package temperature gradient deviates from the model prediction value by ±5°C, and the stress elimination efficiency of the vibration aging treatment is lower than the theoretical value by 15%; The compensation algorithm adopts a deep reinforcement learning framework, specifically including: State space: a 42-dimensional feature vector of the encapsulation process; Action space: 18 adjustable process parameters; Reward function: Use the encapsulation yield, defect rate, and energy consumption ratio as the multi-objective optimization benchmark; The digital twin model is automatically updated every 1000 circuit boards produced by the system, and the model iteration error rate ≤ 0.8%;

[0259] Based on the principle of multi-modal physical information fusion and cognitive manufacturing, construct a digital twin system that is deeply coupled with the S1-S5 processes, and form an intelligent decision-making center for the entire process life cycle. The specific embodiments are extended as follows:

[0260] High-fidelity twin modeling system (establish bidirectional data mapping with S1-S5 processes)

[0261] Construction of the process parameter hyper-dimensional space: Establish a 422-dimensional feature matrix with cross-process coupling:

[0262] $$\boldsymbol{X}(t)=\begin{bmatrix}\underbrace{E_{S1}^{eff},Ra_{PI}^{3σ}}_{S1 microstructure}\\underbrace{ P_{S2},∫ΔT_{S2}dt}_{S2 thermodynamics}\\underbrace{v_{S3},\iint_A(h(x,y)-h_0)^2dxdy}_{S3 morphology}\\underbrace{CTE_{S4}^{xyz},σ_{res}^{vol}}_{S4 stress field}\\underbrace{C_{defect}^{S5},D_{cluster}^{3D}}_{S5 defect spectrum}\end{bmatrix}$$;

[0263] Construction of the dynamic data pipeline: Develop a five-layer synchronization architecture: (as Figure 14 shown);

[0264] Cognitive compensation engine (intelligent regulation based on the physical field mapping of S1-S5)

[0265] Develop a compensation algorithm with two-way causal reasoning ability: (as Figure 15 shown).

[0266] Cross-process adaptive optimization (realize the parameter co-evolution of the entire process chain);

[0267] Establish a parameter migration model based on the process propagation matrix:

[0268] $$\begin{pmatrix}\Delta S2^{opt}\\Delta S3^{opt}\\Delta S4^{opt}\end{pmatrix}=\boldsymbol{M}_{prop}\cdot\begin{pmatrix}S1_{err}^{via}\S5_{defect}^{3σ}\S4_{CTE}^{grad}\end{pmatrix}$$ where the propagation matrix: $$\boldsymbol{M}_{prop}=\begin{bmatrix}-0.15&0.23&0.08\0.06&-0.18&0.12\0.09&0.04&-0.22\end{bmatrix}\cdot e^{-0.02N_{cycles}}$$;

[0269] Run verification data:

[0270] The model iteration effect when the batch size is 1500 pieces:

[0271] The hot pressing energy consumption is reduced by 18.7% (optimization of the S2 power curve);

[0272] The solder spatter rate drops by 32% (adaptive adjustment of the S3 field strength);

[0273] The uniformity of the molding residual stress is increased by 41% (verification of the S4 path optimization).

[0274] Parameter compensation response time:

[0275] Thickness anomaly compensation: 82 ms (±0.8 μm after compensation);

[0276] Temperature gradient correction: 127 ms (reach the set value ±1.3 °C).

[0277] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples.

[0278] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent structural transformation made by using the content of the specification and drawings of the present invention under the inventive concept of the present invention, or direct / indirect application in other related technical fields, is included in the patent protection scope of the present invention.

Claims

1. A packaging process for a circuit board, characterized in that: The following steps are involved: S1. Pre-set multi-layer circuit substrate: Based on the laser-assisted microporous interconnection process, on the substrate of the alternating stacking of ceramic substrate and polyimide composite substrate, the through-holes are filled by nano-scale metallization to form a vertical interconnection structure; wherein the ceramic substrate is an ultra-high thermal conductivity ceramic sheet doped with 3%-5% yttrium oxide of aluminum nitride, and the surface of the polyimide layer is modified by plasma grafting, and its surface roughness Ra≤0.2μm; S2. Dynamic hot-press bonding: Using a segmented gradient pressure control system, the core board and at least two layers of copper foil are bonded in a vacuum environment. The initial pressure is 5-10MPa and the temperature is 180-200℃ for 60 seconds. The pressure in the middle is increased to 15-20MPa and the temperature is 230-250℃ for 120 seconds. The pressure in the final stage is adjusted back to 8-12MPa and the temperature drops to below 150℃ for cooling. S3. Anti-migration solder configuration: Prepare lead-free solder paste containing 2-3wt% nano-zirconia modified particles, and use electrospinning-assisted solder coating technology to apply the solder in a spiral line shape on the pad area with a thickness error of <5μm; S4. Multi-dimensional synchronous plastic packaging: After the components are mounted on the circuit board, a two-component low-stress epoxy resin is used to complete the packaging through a three-dimensional path precision injection and light curing collaborative process. The thermal expansion coefficient of the resin after curing is ≤15ppm / ℃; S5. Non-destructive topological detection: Combining terahertz wave scanning and convolutional neural network algorithm, it can identify micro cracks and void defects inside the packaging layer in real time, with a detection resolution of 10μm.

2. A packaging process for a circuit board according to claim 1, characterized in that: In the step S1, the nanoscale metallization filling of the through hole comprises: A titanium-tungsten composite barrier layer with a thickness of 50-80 nm is deposited on the sidewall of the through hole using an atomic layer deposition process; Filling the copper nanowire array by gradient electrochemical deposition, the wire diameter is 80-120nm, and the filling density is ≥98%; The surface is covered with a chemical nickel-gold layer with a thickness of 3-5 μm, wherein the thickness of the gold layer is 0.05-0.1 μm and the phosphorus content of the nickel layer is 7-9wt%.

3. A packaging process for a circuit board according to claim 1, characterized in that: The segmented gradient pressure control system in step S2 includes: The pressure regulation module is based on a dynamic impedance feedback mechanism to monitor the ultrasonic reflection signal intensity of the interface between the copper foil and the core board in real time, and triggers the pressure stage switching when the interface reflection coefficient drops below 20% of the initial value; The temperature control system uses alternating far-infrared radiation heating and liquid nitrogen quenching to control temperature fluctuations within ±2°C.

4. A packaging process for a circuit board according to claim 1, characterized in that: The parameters of the device for implementing the electrospinning-assisted solder coating technology in step S3 include: The output DC voltage of the high voltage generator is 18-22 kV, the spinning distance is set to 15-25 mm, the nozzles are arranged in a 7×7 symmetrical array, and the distance between adjacent nozzles is 0.8-1.2 mm; The spinning solution is a solder suspension containing 5-8 vol% tetrahydrofuran solvent, with a viscosity of 300-500 mPa·s and a conductivity controlled at 50-80 μS / cm; The receiving device rotates at a speed of 800-1200rpm, and the rotation speed is adjusted by real-time feedback of a non-contact laser thickness gauge to make the spacing error of the spiral solder track ≤1.5μm.

5. The packaging process of a circuit board according to claim 1, characterized in that: The preparation method of the microcapsule sustained-release curing agent in step S4 is: Bisphenol A epoxy resin and hollow glass microspheres with a particle size of 0.5-2 μm were mixed in a mass ratio of 10:1, and core-shell structure microcapsules were prepared using microfluidic chip technology. The shell layer was a polyurea-titanium dioxide composite material with a wall thickness of 200-300 nm. The trigger mechanism includes: when the packaging temperature reaches 55-65°C, the shell layer undergoes thermal rupture to release the curing agent, and the trigger time delay is 30-45 minutes; The dispersion concentration of the microcapsules in the epoxy matrix is ​​5-8wt%, and the molar ratio of the curing agent to the epoxy resin after rupture is 1:1.2-1.

5.

6. The packaging process of a circuit board according to claim 1, characterized in that: The collaborative optimization model of the terahertz detection system and the convolutional neural network algorithm in step S5 includes: The terahertz emission source uses a frequency-tunable quantum cascade laser with an operating frequency range of 0.5-3THz and a scanning speed of 200-300 points / second; The convolutional neural network architecture includes 5 convolutional layers and 3 fully connected layers. The improved ResNet-50 is used as the backbone network. The input data is a 128×128 pixel terahertz time-domain spectrum image. The training dataset contains 10,000 sets of manually annotated defect samples, and the data augmentation strategies include: random rotation of ±5°, adding Gaussian noise, and spectral shift to simulate the dielectric constants of different materials.

7. A packaging process for a circuit board according to claim 1, characterized in that: The packaging process further includes a step S6 of stress equalization processing, specifically: A six-axis vibration aging device is used to apply multi-directional composite vibration to the packaged circuit board. The vibration frequency is 20-30Hz, the amplitude is 0.02-0.05mm, the processing time is 120-180 minutes, and the vibration mode uses a chaotic algorithm to generate waveforms. The maximum acceleration does not exceed 5g; The residual stress changes are monitored in real time by MEMS acceleration sensors attached to the four corners of the circuit board, and the processing is automatically terminated when the stress standard deviation drops below 15% of the initial value.

8. The packaging process of a circuit board according to claim 1, characterized in that: The circuit board also includes: Embedded heat dissipation channel: a microchannel network with a width of 50-80μm is etched inside the ceramic substrate, filled with phase change material, and the top of the channel is covered with a graphene thermal conductive film with a thickness of 3-5μm; Electromagnetic shielding grid: A three-dimensional nickel-based alloy mesh structure is integrated on the surface of the packaging layer, with a grid line width of 10-15μm and a hole density of 200-300 meshes. The surface is treated with plasma nitriding to form a nickel nitride layer with a thickness of 0.1-0.3μm; The heat dissipation channel is connected to the electromagnetic shielding grid via vertical interconnected through holes, and the through holes are filled with carbon nanotube-silver composite conductive glue, with a silver content of 70-85wt%.

9. A waste recycling system, applied to a circuit board packaging process as claimed in any one of claims 1 to 7, characterized in that: include: The molecular sieve adsorption device adopts ZSM-5 zeolite molecular sieve with mesoporous-microporous composite structure, with a median pore size of 0.55-0.65nm and a specific surface area of ​​≥600m 2 / g, and the dynamic adsorption capacity for copper and lead ions is ≥180mg / g and ≥220mg / g respectively; The real-time monitoring module contains a high-precision ion-selective electrode array with a detection range of: Copper ion concentration 1-500ppm, resolution ±0.5ppm; Lead ion concentration 0.5-200ppm, resolution ±0.2ppm; When the copper ion concentration is detected to be above 20ppm or the lead ion concentration is above 10ppm, a three-stage adsorption cycle is started through the PID control algorithm; The regeneration process adopts intermittent electrochemical regeneration process, and the specific parameters are: The electrolyte is a mixed solution of 0.8-1.2 mol / L citric acid and 0.1-0.3 mol / L sulfuric acid. A DC pulse current density of 50-80 mA / cm is applied. 2 , pulse width 100-200μs, regeneration time 20-30 minutes, heavy metal desorption rate of molecular sieve after regeneration ≥95%, can be reused ≥30 times; The system's circulation treatment efficiency reaches 15-20L of waste liquid per hour, and the heavy metal recovery purity is ≥99.5%.

10. The packaging process of a circuit board according to claim 1, characterized in that: The packaging process adopts the whole-line automation control strategy based on digital twin: Digital twin modeling: Establish a 3D process simulation model and dynamically associate the following entity parameters: Pressure gradient curve in dynamic hot-press bonding stage, thermogram of solder coating thickness distribution, cloud diagram of residual stress in plastic encapsulation layer and acceleration spectrum density curve of vibration aging treatment; Real-time parameter compensation: The 5G industrial module achieves millisecond-level synchronization between physical equipment and digital models, and triggers the compensation mechanism when any of the following deviations are detected: The local fluctuation of solder thickness exceeds the set value by ±3μm, the plastic sealing temperature gradient deviates from the model prediction value by ±5℃, and the stress elimination efficiency of vibration aging treatment is 15% lower than the theoretical value; The compensation algorithm uses a deep reinforcement learning framework, which includes: State space: 42-dimensional feature vector of packaging process; Action space: 18 adjustable process parameters; Reward function: packaging yield, defect rate, and energy consumption ratio are used as multi-objective optimization benchmarks; The system automatically updates the digital twin model every time 1,000 circuit boards are produced, and the model iteration error rate is ≤0.8%.

Images