Display device

Abstract

A display device is provided. The display device includes: a substrate; an active layer disposed on the substrate; a first metal layer over the active layer; a second metal layer over the first metal layer; a first transistor including a semiconductor region in the active layer, a drain electrode on a first side of the semiconductor region, a source electrode on a second side opposite the first side of the semiconductor region, and a gate electrode in the first metal layer; a first capacitor including a first capacitor electrode in the first metal layer and electrically connected to a gate electrode of the first transistor; a second capacitor including a second capacitor electrode in the first metal layer and electrically connected to a driving voltage line supplying a driving voltage; and a shield electrode in the second metal layer and overlapping the first capacitor electrode, the second capacitor electrode, and a drain electrode of the first transistor.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] With the development of the information society, various demands for display devices are continuously increasing. For example, display devices are adopted by various electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and smart TVs. Among them, a display device in which each of a plurality of pixels of a display panel includes a light-emitting element capable of emitting light by itself can display an image without a light-emitting device that supplies light to the display panel.

[0003] A display device includes pixels, data lines and gate lines electrically connected to the pixels, a data driver that supplies a data voltage to the data lines, and a gate driver that supplies a gate signal to the gate lines. The data driver and the gate driver can drive the pixels at an optional frequency.

[0004] It should be understood that the background part of this technical section is intended to provide useful background for understanding the technology. However, the background of this technical section may also include ideas, concepts, or cognitions that are not known or recognized before the corresponding effective filing date of the subject matter not disclosed in this article by those skilled in the relevant art. Summary of the Invention

[0005] The technical objectives to be achieved by the present disclosure are not limited to those described in this article, and those skilled in the art will clearly understand other technical objectives not mentioned in this article from the description of the present disclosure.

[0006] Aspects of the present disclosure provide a display device that can prevent a compensation error of a first transistor and improve image quality.

[0007] It should be noted that the objectives of the present disclosure are not limited to those mentioned above, and according to the following description, other objectives of the present disclosure will be obvious to those skilled in the art.

[0008] According to an embodiment, a display device includes: a substrate; an active layer disposed on the substrate; a first metal layer disposed above the active layer; a second metal layer disposed above the first metal layer; a first transistor including a semiconductor region disposed in the active layer, a drain electrode disposed on a first side of the semiconductor region, a source electrode disposed on a second side opposite to the first side of the semiconductor region, and a gate electrode disposed in the first metal layer; a first capacitor including a first capacitor electrode disposed in the first metal layer and electrically connected to the gate electrode of the first transistor; a second capacitor including a second capacitor electrode disposed in the first metal layer and electrically connected to a driving voltage line for supplying a driving voltage; and a shielding electrode disposed in the second metal layer and overlapping with the first capacitor electrode, the second capacitor electrode, and the drain electrode of the first transistor.

[0009] The display device may further include: a light-emitting element that receives a driving current from the first transistor. The shielding electrode may be electrically connected to a first electrode of the light-emitting element.

[0010] The display device may further include: a first connection electrode disposed in a third metal layer above the second metal layer and electrically connecting the source electrode of the first transistor to the shielding electrode.

[0011] The display device may further include: a bias electrode of the first transistor, which may be disposed in a fourth metal layer below the active layer, overlapping with the semiconductor region of the first transistor, and may be electrically connected to the shielding electrode through the first connection electrode.

[0012] The display device may further include: a data line that supplies a data voltage; a first gate line that supplies a first gate signal; and a second transistor including a semiconductor region disposed in the active layer, a drain electrode electrically connected to the data line, a source electrode electrically connected to the gate electrode of the first transistor, and a gate electrode disposed in the first metal layer and electrically connected to the first gate line.

[0013] In a plan view, the first capacitor and the second capacitor may be disposed between the first gate line and the first transistor.

[0014] The display device may further include: a bias electrode of the second transistor, which may be disposed in a fourth metal layer below the active layer, overlapping with the semiconductor region of the second transistor, and may be electrically connected to the gate electrode of the second transistor.

[0015] The display device may further include: a reference voltage line that supplies a reference voltage; a second gate line that supplies a second gate signal; and a third transistor that includes a semiconductor region disposed in the active layer, a drain electrode electrically connected to the reference voltage line, a source electrode electrically connected to the gate electrode of the first transistor, and a gate electrode disposed in the first metal layer and electrically connected to the second gate line.

[0016] In a plan view, the first capacitor and the second capacitor may be disposed between the second gate line and the first transistor.

[0017] The display device may further include: a bias electrode of the third transistor, which may be disposed in the fourth metal layer under the active layer, overlap with the semiconductor region of the third transistor, and may be a part of the second gate line.

[0018] The display device may further include: an initialization voltage line that supplies an initialization voltage; a third gate line that supplies a third gate signal; and a fourth transistor that includes a semiconductor region disposed in the active layer, a drain electrode electrically connected to the source electrode of the first transistor, a source electrode electrically connected to the initialization voltage line, and a gate electrode disposed in the first metal layer and electrically connected to the third gate line.

[0019] The display device may further include: a bias electrode of the fourth transistor, which may be disposed in the fourth metal layer under the active layer, overlap with the semiconductor region of the fourth transistor, and may be a part of the third gate line.

[0020] The display device may further include: an emission control line that supplies an emission signal; and a fifth transistor that includes a semiconductor region disposed in the active layer, a drain electrode electrically connected to the driving voltage line, a source electrode electrically connected to the drain electrode of the first transistor, and a gate electrode disposed in the first metal layer and electrically connected to the emission control line.

[0021] The display device may further include: a bias electrode of the fifth transistor, which may be disposed in the fourth metal layer under the active layer, overlap with the semiconductor region of the fifth transistor, and may be electrically connected to the gate electrode of the fifth transistor.

[0022] In a plan view, the emission control line may be disposed between the third gate line and the first transistor.

[0023] The display device may further include: a light-emitting element disposed in a third metal layer on the second metal layer; a sixth transistor electrically connected between a source electrode of the first transistor and a first electrode of the light-emitting element; and a seventh transistor that discharges the source electrode of the sixth transistor and the first electrode of the light-emitting element.

[0024] According to an embodiment, the display device includes: a first gate line extending in a first direction and supplying a first gate signal; a light-emitting element disposed on the first gate line; a first transistor that supplies a driving current to the light-emitting element; a second transistor that supplies a data voltage to a gate electrode of the first transistor based on the first gate signal; a first capacitor formed between the gate electrode of the first transistor and the source electrode of the first transistor; and a shielding electrode electrically connected to the source electrode of the first transistor and corresponding to a second electrode of the first capacitor. In a plan view, the first capacitor may be disposed between the first gate line and the first transistor.

[0025] The shielding electrode may be disposed on the first transistor and overlap with a drain electrode of the first transistor.

[0026] The display device may further include: a second gate line extending in the first direction and supplying a second gate signal; and a third transistor that supplies a reference voltage to the gate electrode of the first transistor based on the second gate signal. In a plan view, the first capacitor may be disposed between the second gate line and the first transistor.

[0027] The display device may further include: a third gate line extending in the first direction and supplying a third gate signal; an emission control line extending in the first direction and supplying an emission signal; a fourth transistor that discharges a first electrode of the light-emitting element based on the third gate signal; and a fifth transistor that supplies a driving voltage to a drain electrode of the first transistor based on the emission signal.

[0028] According to an embodiment of the present disclosure, in the display device, the shielding electrode may cover an upper surface of a drain electrode of the first transistor so as to prevent the drain electrode of the first transistor from being electrically connected to a voltage line or a signal line, thereby preventing a compensation error of the first transistor and improving an image quality of the display device.

[0029] It should be noted that the effects of the present disclosure are not limited to the above-mentioned effects, and according to the following description, other effects of the present disclosure will be apparent to those skilled in the art. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present disclosure will become more apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0031] Figure 1 is a perspective view showing a display device according to an embodiment of the present disclosure.

[0032] Figure 2 is a block diagram showing a display device according to an embodiment of the present disclosure.

[0033] Figure 3 is a schematic cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0034] Figure 4 is a schematic diagram showing an equivalent circuit of a pixel of a display device according to an embodiment of the present disclosure.

[0035] Figure 5 is supplied to Figure 4 a waveform diagram of a signal of the pixel shown in.

[0036] Figure 6 is a view showing a layout of pixels of a display device according to an embodiment of the present disclosure.

[0037] Figure 7 is shown along Figure 6 a schematic cross-sectional view of an example taken along line I-I'.

[0038] Figure 8 is a schematic diagram of an equivalent circuit of a pixel of a display device according to an embodiment of the present disclosure. Detailed Embodiments

[0039] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings showing embodiments. However, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0040] In the drawings, for ease of description and for clarity, the sizes, thicknesses, ratios, and dimensions of elements may be exaggerated. Throughout the specification, like reference numerals and / or reference characters refer to like elements.

[0041] In the specification and claims, for purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in the sense of a conjunctive or disjunctive connective and may be understood to be equivalent to "and / or".

[0042] In the specification and claims, for purposes of their meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group consisting of...". For example, "at least one of A and B" can be understood to mean "A, B, or both A and B".

[0043] The terms "overlap", "overlapping", or "overlapped" mean that a first object can be above, below, or to the side of a second object and vice versa. Additionally, the term "overlap" can include laminating, stacking, facing or being face-to-face, extending over, covering or partially covering, or any other suitable term as would be recognized and understood by one of ordinary skill in the art.

[0044] The terms "face" and "face-to-face" mean that a first element can be directly or indirectly opposite a second element. In cases where a third element is between the first element and the second element, the first element and the second element can be understood to be indirectly opposite each other, although still facing each other.

[0045] When an element is described as "non-overlapping" or "not overlapping" with another element, this can include multiple elements being spaced apart from each other, offset from each other, or separated from each other, or any other suitable term as would be recognized and understood by one of ordinary skill in the art.

[0046] Unless otherwise specified, the illustrated embodiments are to be understood as providing features of some ways in which the present disclosure can be implemented in practice. Thus, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments can be combined, separated, interchanged, and / or re-arranged in other ways without departing from the present disclosure.

[0047] The use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, scale, commonality between the illustrated elements, and / or any other characteristic, attribute, property, etc. of the elements.

[0048] Additionally, in the drawings, for clarity and / or descriptive purposes, the size and relative size of elements may be exaggerated. When an embodiment can be implemented in different ways, the specific process sequence can be performed differently from the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described order. Additionally, like reference numerals represent like elements.

[0049] It will be understood that when an element (or region, layer, portion, etc.) is referred to in the specification as being "on" another element, "disposed on" another element, "connected to" or "coupled to" another element, the element can be directly disposed on, connected to, or coupled to the other element, or intervening elements may be disposed therebetween. It will be understood that the terms "connected to" or "coupled to" can include physical connection or coupling or electrical connection or coupling.

[0050] In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and thus the X-axis, Y-axis, and Z-axis can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0051] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element.

[0052] For ease of description, the spatial relative terms "below", "beneath", "lower", "above", "upper", "side" (e.g., as in "sidewall") etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. It will be understood that, in addition to the orientation depicted in the figures, the spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, in the case where the device illustrated in the figures is flipped, a device positioned "below" or "beneath" another device will then be positioned "above" the other device. Thus, the illustrative term "below" can encompass both a lower position and an upper position. The device can also be oriented in other ways, and thus the spatial relative terms can be interpreted differently depending on the orientation. The element or component can also be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and thus the spatial relative descriptors used herein should be interpreted accordingly.

[0053] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" as used herein are also intended to include the plural forms.

[0054] When the terms "comprises", "comprising", "includes", "including", "has", "have" and / or "having" and their variants are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, components and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0055] Taking into account the measurements involved and the errors associated with a particular number of measurements (i.e., the limitations of the measurement system), as used herein, the terms "about", "approximately", "substantially" or other similar terms include the stated value and mean within an acceptable deviation for a particular value as determined by a person of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0056] Various embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic illustrations of the embodiments and / or intermediate structures. Accordingly, variations in the shape of the illustrations due to, for example, manufacturing techniques and / or tolerances are expected. Thus, the embodiments disclosed herein should not necessarily be construed as limited to the particular shapes of the regions of the illustrations, but include deviations in shape due to, for example, manufacturing. In this manner, the regions illustrated in the figures are essentially schematic, and the shapes of these regions may not reflect the actual shapes of the regions of the device and are therefore not necessarily intended to be limiting.

[0057] The phrase "in a plan view" means viewing an object from the top, and the phrase "in a schematic cross-sectional view" means viewing a cross-section of an object that has been cut vertically from the side. Thus, the expression "in a plan view" as used herein can mean viewing an object from the top in a third direction "Z". The phrase "in a schematic cross-sectional view" means viewing a cross-section of an object that has been cut vertically from the side in a first direction "X" or a second direction "Y". The direction "Z" can also be referred to as the "thickness direction".

[0058] In a case where an element is referred to as being "in contact with" or "having contacted" another element, etc., the one element can be "electrically in contact with" or "physically in contact with" the other element; or "indirectly in contact with" or "directly in contact with" the other element.

[0059] A description that a component is "configured to" perform a specified operation can be limited to a case where the component is constructed and arranged with structural features that enable the component to perform the specified operation.

[0060] Embodiments may be described and illustrated in the drawings in terms of functional blocks, units, portions, and / or modules.

[0061] Those skilled in the art will understand that these blocks, units, portions, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc. that may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques.

[0062] In cases where the blocks, units, portions, and / or modules are implemented by a microprocessor or other similar hardware, the blocks, units, portions, and / or modules may be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and the blocks, units, portions, and / or modules may optionally be driven by firmware and / or software.

[0063] It is also contemplated that each block, unit, portion, and / or module may be implemented by dedicated hardware or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions.

[0064] Without departing from the scope of the present disclosure, each block, unit, portion, and / or module of an embodiment may be physically separated into two or more interacting and discrete blocks, units, portions, and / or modules.

[0065] Furthermore, without departing from the scope of the present disclosure, the blocks, units, portions, and / or modules of an embodiment may be physically combined into more complex blocks, units, portions, and / or modules.

[0066] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a common dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0067] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings.

[0068] Figure 1 is a perspective view showing a display device according to an embodiment of the present disclosure.

[0069] Reference Figure 1, the display device 10 can display moving images or still images. The display device can be used as a display screen of portable electronic devices such as mobile phones, smartphones, tablet personal computers, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs), as well as display screens of various products such as televisions, notebook computers, display screens, billboards, and Internet of Things devices.

[0070] The display device 10 may include a display panel 100, a data driver 200, a timing controller 300, a power supply unit 400, a data circuit board 500, and a control circuit board 600, or a combination thereof.

[0071] In a plan view, the display panel 100 may have a quadrilateral shape (e.g., a rectangular shape), and in a schematic cross-sectional view, the display panel 100 may have a planar surface extending in a first direction and a second direction. For example, the display panel 100 may have a longer side in the first direction (X-axis direction) and a shorter side in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). Each of the plurality of corners where its longer side in the first direction (X-axis direction) intersects its shorter side in the second direction (Y-axis direction) may be optionally rounded with a curvature or may be a right angle. In a plan view, the shape of the display panel 100 is not limited to a quadrilateral shape, but may be formed into different polygonal shapes, circular shapes, or elliptical shapes. The display panel 100 may be formed flat, but the present disclosure is not limited thereto. For example, the display panel 100 may be formed at the left and right ends and may include bent portions having a constant curvature or a varying curvature. The display panel 100 may be formed to be flexible such that it can be bent, curved, folded, or rolled up.

[0072] The display panel 100 may include a display area DA where an image can be displayed and a non-display area NDA disposed around the display area DA. The display area DA may occupy most of the area of the display panel 100. The display area DA may be disposed at the center of the display panel 100. The display area DA may include pixels for displaying an image.

[0073] Each of the plurality of pixels may include a light-emitting element that emits light. The light-emitting element may include at least one of an organic light-emitting diode including an organic emission layer, a quantum dot light-emitting diode including a quantum dot emission layer, an inorganic light-emitting diode including an inorganic semiconductor, and a micro light-emitting diode (micro-LED), or a combination thereof, but is not limited thereto.

[0074] The non-display area NDA may be arranged adjacent to the display area DA. The non-display area NDA may be located on the outer side of the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA may be defined as the boundary of the display panel 100.

[0075] The non-display area NDA may include a gate driver, fan-out lines, and pads. The gate driver may supply gate signals to the gate lines of the display area DA. The fan-out lines may electrically connect the data driver 200 to the data lines of the display area DA. The pads may be electrically connected to the data circuit board 500. For example, the pads may be arranged at one edge of the display panel 100, and the gate driver portion may be arranged at another edge adjacent to the edge of the display panel 100. However, it should be understood that the present disclosure is not limited thereto.

[0076] The data driver 200 may output signals and voltages for driving the display panel 100. The data driver 200 may supply data voltages to the data lines. The data driver 200 may apply a power voltage to the voltage lines and may supply a gate control signal to the gate driver. The data driver 200 may be implemented as an integrated circuit (IC) and mounted on the data circuit board 500 by chip-on-film (COF) technology. As another example, the data driver 200 may be mounted in the non-display area NDA of the display panel 100 by chip-on-glass (COG) technology, chip-on-plastic (COP) technology, or ultrasonic bonding.

[0077] The timing controller 300 may be mounted on the control circuit board 600 and may receive digital video data and timing synchronization signals supplied from a display driving system or a graphics device through a user connector provided on the control circuit board 600. The timing controller 300 may appropriately coordinate the digital video data for the pixel setting structure in response to the timing synchronization signal and may supply the coordinated digital video data to the data driver 200. The timing controller 300 may generate a data control signal and a gate control signal based on the timing synchronization signal. The timing controller 300 may control the timing of applying the data voltage to the data driver 200 based on the data control signal and may control the timing of providing the gate signal to the gate driver based on the gate control signal.

[0078] The power supply unit 400 may be mounted on the control circuit board 600 to apply a power voltage to the display panel 100 and the data driver 200. For example, the power supply unit 400 may generate a driving voltage, a common voltage, an initialization voltage, or a reference voltage. The power supply unit 400 may supply a power voltage to drive the pixels and the data driver 200.

[0079] The data circuit board 500 may be disposed on pads arranged at one edge of the display panel 100. The data circuit board 500 may be attached to the pads using a conductive bonding member such as an anisotropic conductive film. The data circuit board 500 may be electrically connected to the signal lines of the display panel 100 through the anisotropic conductive film. The display panel 100 may receive a data voltage and a driving voltage through the data circuit board 500. For example, the data circuit board 500 may be a flexible printed circuit board (FPCB), a rigid printed circuit board (PCB), or a flexible film such as a chip on film (COF).

[0080] The control circuit board 600 may be attached to the data circuit board 500 using a low-resistance and high-reliability material such as an anisotropic conductive film or a self-assembled anisotropic conductive paste (SAP). The control circuit board 600 may be electrically connected to the data circuit board 500. The control circuit board 600 may be a flexible printed circuit board or a printed circuit board.

[0081] Figure 2 is a block diagram showing a display device according to an embodiment of the present disclosure.

[0082] Reference Figure 2 , the display panel 100 may include a display area DA and a non-display area NDA.

[0083] The display area DA may include pixels SP, voltage lines VL, gate lines GL, emission control lines EML, and data lines DL.

[0084] Each of the plurality of pixels SP may be electrically connected to the gate line GL, the data line DL, the emission control line EML, and the voltage line VL. Each of the plurality of pixels SP may include at least one transistor, a light-emitting element, and a capacitor.

[0085] The plurality of gate lines GL may extend in the X-axis direction and may be spaced apart from each other in the Y-axis direction intersecting the X-axis direction. The gate lines GL may sequentially supply gate signals to the pixels SP.

[0086] The plurality of emission control lines EML may extend in the X-axis direction and may be spaced apart from each other in the Y-axis direction. The emission control lines EML may sequentially supply emission signals to the pixels SP.

[0087] The plurality of data lines DL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction. The data lines DL may supply data voltages to the pixels SP. The data voltages may determine the brightness of each of the plurality of pixels SP.

[0088] A plurality of voltage lines VL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction. The voltage lines VL may supply a power voltage to the pixels SP. The power voltage may include at least one of a driving voltage, a common voltage, an initialization voltage, and a reference voltage or a combination thereof. For example, the driving voltage may be a high-level voltage for driving a light-emitting element of the pixel SP, and the common voltage may be a low-level voltage for driving a light-emitting element of the pixel SP.

[0089] The data driver 200 may convert digital video data DATA into a data voltage (e.g., an analog data voltage) and may supply the data voltage to the data lines DL through fan-out lines. A gate signal from the gate driver 810 may be used to select the pixels SP to which the data voltage is applied, and the selected pixels SP may receive the data voltage through the data lines DL.

[0090] The timing controller 300 may receive digital video data DATA and timing signals from the graphics device 700. For example, the graphics device 700 may be a graphics card of the display device 10, but is not limited thereto. The timing controller 300 may control the operation timing of the data driver 200 by generating a data control signal DCS based on the timing signals and supplying the data control signal DCS to the data driver 200. The timing controller 300 may supply the digital video data DATA to the data driver 200. The timing controller 300 may control the operation timing of the gate driver 810 by generating a gate control signal GCS based on the timing signals and supplying the gate control signal GCS to the gate driver 810. The timing controller 300 may control the operation timing of the emission control driver 820 by generating an emission control signal ECS based on the timing signals and supplying the emission control signal ECS to the emission control driver 820.

[0091] The power supply unit 400 may be disposed on the data circuit board 500 to supply a power voltage to the data driver 200 and the display panel 100. The power supply unit 400 may generate a driving voltage to supply the driving voltage to the driving voltage lines, may generate an initialization voltage to supply the initialization voltage to the initialization voltage lines, may generate a reference voltage to supply the reference voltage to the reference voltage lines, and may generate a common voltage to supply the common voltage to a common electrode shared by a plurality of light-emitting elements of a plurality of pixels SP.

[0092] The gate driver 810 may be disposed on one outer side of the display area DA or on one outer side of the non-display area NDA, and the emission control driver 820 may be disposed on the opposite outer side of the display area DA or on the opposite outer side of the non-display area NDA. However, it should be understood that the present disclosure is not limited thereto. As another example, the gate driver 810 and the emission control driver 820 may be disposed on one side or opposite sides of the non-display area NDA.

[0093] The gate driver 810 may include thin film transistors for generating a gate signal based on a gate control signal GCS. The emission control driver 820 may include thin film transistors for generating an emission signal based on an emission control signal ECS. For example, the transistors of the gate driver 810, the transistors of the emission control driver 820, and the transistors of each of the plurality of pixels SP may be arranged on the same layer. The gate driver 810 may supply the gate signal to the gate line GL, and the emission control driver 820 may supply the emission signal to the emission control line EML.

[0094] Figure 3 is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure.

[0095] Reference Figure 3 , the display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, an emission layer EDL, and a packaging layer TFEL.

[0096] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate capable of being bent, folded, or curled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. As another example, the substrate SUB may include a glass material or a metal material or a combination thereof.

[0097] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include thin film transistors forming pixel circuits of the pixels SP. The thin film transistor layer TFTL may further include a gate line GL, a data line DL, a voltage line VL, a gate control line, a fan-out line for connecting the data driver 200 to the data line DL, or a combination thereof. Each of the plurality of thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, in the case where the gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include thin film transistors.

[0098] The thin film transistor layer TFTL may be disposed in the display area DA and the non-display area NDA. The thin film transistors in each of the plurality of pixels SP, the gate line GL, the data line DL, and the voltage line VL in the thin film transistor layer TFTL may be disposed in the display area DA. The gate control line and the fan-out line in the thin film transistor layer TFTL may be disposed in the non-display area NDA.

[0099] The emission layer EDL may be disposed on the thin film transistor layer TFTL. The emission layer EDL may include a light-emitting element and a pixel defining film. In each of the plurality of light-emitting elements, a pixel electrode, the emission layer EDL, and a common electrode may be stacked on top of each other (e.g., stacked in sequence) to emit light, and the pixel defining film is used to define a pixel SP. The light-emitting elements in the emission layer EDL may be disposed in the display area DA.

[0100] For example, the emission layer EDL may be an organic light-emitting layer containing an organic material. The emission layer EDL may include a hole transport layer, an organic emission layer, and an electron transport layer. In the case where the pixel electrode receives a voltage and the common electrode receives a cathode voltage through a thin film transistor in the thin film transistor layer TFTL, holes and electrons move to the organic emission layer through the hole transport layer and the electron transport layer respectively, so that the holes and electrons combine in the organic emission layer to emit light. For example, the pixel electrode may be an anode electrode, and the common electrode may be a cathode electrode. However, it should be understood that the present disclosure is not limited thereto.

[0101] As another example, the light-emitting element may include a quantum dot light-emitting diode each containing a quantum dot emission layer, an inorganic light-emitting diode each containing an inorganic semiconductor, a micro light-emitting diode, or a combination thereof.

[0102] The encapsulation layer TFEL may cover the upper surface and the side surface of the emission layer EDL and may protect the emission layer EDL. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the emission layer EDL.

[0103] The touch sensing unit TSU may be disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a touch electrode for sensing a user's touch by capacitance sensing and a touch line for electrically connecting the touch electrode to a touch driver. For example, the touch sensing unit TSU may sense a user's touch by mutual capacitance sensing or self-capacitance sensing.

[0104] As another example, the touch sensing unit TSU may be disposed on a separate substrate disposed on the display unit DU. In this case, the substrate supporting the touch sensing unit TSU may be a base member for encapsulating the display unit DU.

[0105] The touch electrodes of the touch sensing unit TSU may be disposed in a touch sensor area overlapping the display area DA. The touch lines of the touch sensing unit TSU may be disposed in a touch peripheral area overlapping the non-display area NDA.

[0106] The color filter layer CFL may be disposed on the touch sensing unit TSU. The color filter layer CFL may include color filters respectively associated with emission regions. Each of the plurality of color filters may selectively transmit light of a specific wavelength and block or absorb light of other wavelengths. The color filter layer CFL may absorb some of the light introduced from the outside of the display device 10 to reduce the reflection of external light. Accordingly, the color filter layer CFL may prevent color distortion caused by the reflection of external light.

[0107] Since the color filter layer CFL may be directly disposed on the touch sensing unit TSU and in contact with the touch sensing unit TSU (e.g., direct contact), the display device 10 may not require a separate substrate for the color filter layer CFL. Accordingly, the thickness of the display device 10 may be relatively reduced.

[0108] Figure 4 is a schematic diagram showing an equivalent circuit of a pixel of a display device according to an embodiment of the present disclosure. Figure 5 is supplied to Figure 4 a waveform diagram of signals of the pixels shown in

[0109] Refer to Figure 4 and Figure 5 , the display panel 100 may include pixels SP arranged along p rows and q columns, where p and q are positive integers. Each of the plurality of pixels SP may be electrically connected to a first gate line GWL, a second gate line GRL, a third gate line GIL, an emission control line EML, a data line DL, a reference voltage line VRL, a driving voltage line VDDL, an initialization voltage line VIL, and a low-level voltage line VSSL.

[0110] Each of the plurality of pixels SP may include a pixel circuit and a light-emitting element ED. The pixel circuit may include a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, a first capacitor C1, and a second capacitor C2.

[0111] The first transistor ST1 may include a gate electrode, a source electrode, and a drain electrode. The first transistor ST1 may control a drain-source current (or driving current) based on a data voltage applied to the gate electrode. The driving current flowing through the channel of the first transistor ST1 may be proportional to the square of the difference between the threshold voltage of the first transistor ST1 and the voltage between the gate electrode and the source electrode of the first transistor ST1, i.e., Ids = k'×(Vth - Vgs) 2, where "Ids" represents the drain-source current of the first transistor ST1, i.e., the drive current, "k'" represents a proportionality coefficient determined by the structure and physical properties of the first transistor ST1, "Vgs" represents the gate-source voltage of the first transistor ST1, and "Vth" represents the threshold voltage of the first transistor ST1. The gate electrode of the first transistor ST1 can be electrically connected to the first node N1, the drain electrode of the first transistor ST1 can be electrically connected to the third node N3, and the source electrode of the first transistor ST1 can be electrically connected to the second node N2. The first transistor ST1 may further include a bias electrode electrically connected to the second node N2.

[0112] The light-emitting element ED can receive a drive current to emit light. The amount or brightness of the light emitted from the light-emitting element ED can be proportional to the magnitude of the drive current.

[0113] The light-emitting element ED can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode. As another example, the light-emitting element ED can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. As another example, the light-emitting element ED can be a quantum dot light-emitting element including a first electrode, a second electrode, and a quantum dot emission layer disposed between the first electrode and the second electrode. As another example, the light-emitting element ED can be a micro light-emitting diode.

[0114] The first electrode of the light-emitting element ED can be electrically connected to the second node N2. The first electrode of the light-emitting element ED can be electrically connected to the source electrode of the first transistor ST1, the drain electrode of the fourth transistor ST4, the second electrode of the first capacitor C1, and the second electrode of the second capacitor C2 through the second node N2. The second electrode of the light-emitting element ED can be electrically connected to the low-level voltage line VSSL and can receive a low-level voltage from the low-level voltage line VSSL.

[0115] The second transistor ST2 can be turned on by the first gate signal GW[n] of the first gate line GWL to electrically connect the data line DL to the first node N1 that is the gate electrode of the first transistor ST1. The second transistor ST2 can be turned on in response to the first gate signal GW[n] to apply a data voltage to the first node N1. The gate electrode of the second transistor ST2 can be electrically connected to the first gate line GWL, the drain electrode of the second transistor ST2 can be electrically connected to the data line DL, and the source electrode of the second transistor ST2 can be electrically connected to the first node N1. The second transistor ST2 may further include a bias electrode electrically connected to the first gate line GWL.

[0116] The third transistor ST3 can be turned on by the second gate signal GR[n] of the second gate line GRL to electrically connect the reference voltage line VRL to the first node N1 that serves as the gate electrode of the first transistor ST1. The third transistor ST3 can be turned on in response to the second gate signal GR[n] to apply a reference voltage to the first node N1. The gate electrode of the third transistor ST3 can be electrically connected to the second gate line GRL, the drain electrode of the third transistor ST3 can be electrically connected to the reference voltage line VRL, and the source electrode of the third transistor ST3 can be electrically connected to the first node N1. The third transistor ST3 can also include a bias electrode electrically connected to the second gate line GRL.

[0117] The fourth transistor ST4 can be turned on by the third gate signal GI[n] of the third gate line GIL to electrically connect the second node N2 that serves as the source electrode of the first transistor ST1 to the initialization voltage line VIL. When the fourth transistor ST4 is turned on based on the third gate signal GI[n], the first electrode of the light-emitting element ED can be discharged to the initialization voltage. The gate electrode of the fourth transistor ST4 can be electrically connected to the third gate line GIL, the drain electrode of the fourth transistor ST4 can be electrically connected to the second node N2, and the source electrode of the fourth transistor ST4 can be electrically connected to the initialization voltage line VIL. The fourth transistor ST4 can also include a bias electrode electrically connected to the third gate line GIL.

[0118] The fifth transistor ST5 can be turned on by the emission control signal EML of the emission control line EML and can electrically connect the drive voltage line VDDL to the drain electrode of the first transistor ST1. The gate electrode of the fifth transistor ST5 can be electrically connected to the emission control line EML, the drain electrode of the fifth transistor ST5 can be electrically connected to the drive voltage line VDDL, and the source electrode of the fifth transistor ST5 can be electrically connected to the third node N3. When all of the fifth transistor ST5 and the first transistor ST1 are turned on, a drive current can be supplied to the light-emitting element ED. The fifth transistor ST5 can also include a bias electrode electrically connected to the emission control line EML.

[0119] Each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, and the fifth transistor ST5 can include an oxide-based active layer ( Figure 7The active layer ACTL). The first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, and the fifth transistor ST5 may have a coplanar structure in which the gate electrode may be disposed on the top. The first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, and the fifth transistor ST5 may be n-type transistors, and may output a current introduced into the drain electrode via the source electrode based on a high gate voltage applied to the gate electrode. The oxide-based active layer may have a relatively small S factor, may increase the constant drive current at low gray levels, and may improve low gray level expression.

[0120] As another example, at least one of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, and the fifth transistor ST5 may include an active layer ACTL made of low-temperature polycrystalline silicon (LTPS). The first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, and the fifth transistor ST5 may be p-type transistors, and may output a current introduced into the source electrode via the drain electrode based on a low gate voltage applied to the gate electrode.

[0121] The first capacitor C1 may be electrically connected between a first node N1 that is the gate electrode of the first transistor ST1 and a second node N2 that is the source electrode of the first transistor ST1. For example, the first capacitor C1 may include a first capacitor electrode CPE1 that can be electrically connected to the first node N1 (see Figure 6 ). The first capacitor C1 may also include a corresponding second electrode that can be electrically connected to the second node N2 so as to maintain the potential difference between the gate electrode and the source electrode of the first transistor ST1.

[0122] The second capacitor C2 may be electrically connected between the drive voltage line VDDL and the second node N2 that is the source electrode of the first transistor ST1. For example, the second capacitor C2 may include a second capacitor electrode CPE2 that can be electrically connected to the drive voltage line VDDL (see Figure 6 ). The second capacitor C2 may also include a corresponding second electrode that can be electrically connected to the second node N2 so as to maintain the potential difference between the drive voltage line VDDL and the source electrode SE1 of the first transistor ST1.

[0123] Combined with Figure 4 Reference Figure 5 , the display device 10 may be driven at an optional driving frequency. One frame may include a first time period t1 to a sixth time period t6.

[0124] The third transistor ST3 may receive a second gate signal GR[n] at a high level during a first time period t1. The third transistor ST3 may be turned on based on the second gate signal GR[n] at the high level to apply a reference voltage to a first node N1 that is a gate electrode of the first transistor ST1.

[0125] The fourth transistor ST4 may receive a third gate signal GI[n] at a high level during a second time period t2 and a fifth time period t5. The fourth transistor ST4 may be turned on based on the third gate signal GI[n] at the high level and discharge a second node N2 that is a source electrode of the first transistor ST1 to an initialization voltage.

[0126] The fifth transistor ST5 may receive a high-level emission signal EM[n] during a third time period t3 and a sixth time period t6. The fifth transistor ST5 may be turned on based on the emission signal EM[n] at the high level to apply a driving voltage to a third node N3 that is a drain electrode of the first transistor ST1. The fifth transistor ST5 may compensate for the voltage of the third node N3 by applying the driving voltage during the third time period t3 and supply a driving current to the light-emitting element ED by applying the driving voltage during the sixth time period t6.

[0127] The second transistor ST2 may receive a first gate signal GW[n] at a high level during a fourth time period t4. The second transistor ST2 may be turned on based on the first gate signal GW[n] at the high level to apply a data voltage to a first node N1 that is a gate electrode of the first transistor ST1.

[0128] When the data voltage is received at the gate electrode of the first transistor ST1, the gate-source voltage of the first transistor ST1 may be equal to the difference voltage between the data voltage and the initialization voltage, and the gate-source voltage becomes greater than the threshold voltage, and thus the first transistor ST1 may be turned on. Therefore, the drain-source current of the first transistor ST1 may be determined based on the data voltage, the initialization voltage, and the threshold voltage of the first transistor ST1, that is, Ids = k'×(Vth-(Vdata-Vin)) 2, where "Ids" represents the drain-source current of the first transistor ST1, i.e., the driving current, "k'" represents a proportionality coefficient determined by the structure and physical properties of the first transistor ST1, "Vdata" represents the data voltage, "Vin" represents the initialization voltage, and "Vth" represents the threshold voltage of the first transistor ST1. The first transistor ST1 can supply the drain-source current to the second node N2 until the gate-source voltage reaches the threshold voltage of the first transistor ST1. In this way, when the first transistor ST1 is turned on, the voltage at the second node N2 and the drain-source current of the first transistor ST1 can change, and the voltage at the second node N2 can finally converge to the difference voltage between the data voltage and the threshold voltage of the first transistor ST1.

[0129] Figure 6 is a view showing the layout of pixels of a display device according to an embodiment of the present disclosure. Figure 7 is a view showing along Figure 6 a schematic cross-sectional view of an example taken along the line I-I'.

[0130] Referring to Figure 6 , the display area DA may include pixels SP, an initialization voltage line VIL, a reference voltage line VRL, a driving voltage line VDDL, a first gate line GWL, a second gate line GRL, a third gate line GIL, and an emission control line EML.

[0131] The first gate line GWL may be disposed on the fourth metal layer MTL4 and may extend in a first direction (X-axis direction). The first gate line GWL may be disposed on the upper side of the first capacitor C1 and the second capacitor C2. In the following description, "right side" refers to the direction indicated by the arrow of the X-axis, "left side" refers to the direction opposite to the direction indicated by the arrow of the X-axis, "upper side" refers to the direction indicated by the arrow of the Y-axis, and "lower side" refers to the direction opposite to the direction indicated by the arrow of the Y-axis. The first gate line GWL may be electrically connected to the gate electrode GE2 of the second transistor ST2 disposed on the second metal layer MTL2 (see Figure 7 ), and the gate electrode GE2 of the second transistor ST2 may be electrically connected to the bias electrode BE2 disposed on the first metal layer MTL1 (see Figure 7 ).

[0132] The second gate line GRL may be disposed on the first metal layer MTL1 and may extend in a first direction (X-axis direction). The second gate line GRL may be disposed on the upper side of the first gate line GWL. The second gate line GRL may be electrically connected to the gate electrode GE3 of the third transistor ST3 disposed on the second metal layer MTL2. The second gate line GRL may include the bias electrode BE3 of the third transistor ST3.

[0133] The third gate line GIL may be disposed on the first metal layer MTL1 and may extend in a first direction (X-axis direction). The third gate line GIL may be disposed on the lower side of the initialization voltage line VIL. The third gate line GIL may be electrically connected to the gate electrode GE4 of the fourth transistor ST4 disposed on the second metal layer MTL2. The third gate line GIL may include a bias electrode BE4 of the fourth transistor ST4 that overlaps with the gate electrode GE4 of the fourth transistor ST4.

[0134] The emission control line EML may be disposed on the fourth metal layer MTL4 and may extend in a first direction (X-axis direction). The emission control line EML may be disposed on the upper side of the initialization voltage line VIL. The emission control line EML may be disposed on the lower side of the first capacitor C1 and the second capacitor C2. The emission control line EML may be electrically connected to the gate electrode GE5 of the fifth transistor ST5 disposed on the second metal layer MTL2, and the gate electrode GE5 of the fifth transistor ST5 may be electrically connected to a bias electrode BE5 disposed on the first metal layer MTL1.

[0135] The reference voltage line VRL may be disposed on the fourth metal layer MTL4 and may extend in a first direction (X-axis direction). The reference voltage line VRL may be disposed on the upper side of the second gate line GRL. The reference voltage line VRL may be electrically connected to the drain electrode DE3 of the third transistor ST3 to apply a reference voltage.

[0136] The drive voltage line VDDL may be disposed on the fourth metal layer MTL4 and may extend in a first direction (X-axis direction). The drive voltage line VDDL may overlap with the first capacitor C1 and the second capacitor C2. The drive voltage line VDDL may be electrically connected to the drain electrode DE5 of the fifth transistor ST5 to apply a drive voltage. The drive voltage line VDDL may be electrically connected to the second capacitor electrode CPE2 to apply a drive voltage.

[0137] The initialization voltage line VIL may be disposed on the fourth metal layer MTL4 and may extend in a first direction (X-axis direction). The initialization voltage line VIL may be disposed between the third gate line GIL and the emission control line EML. The initialization voltage line VIL may be electrically connected to the source electrode SE4 of the fourth transistor ST4 to apply an initialization voltage.

[0138] The first transistor ST1 may include a semiconductor region ACT1, a gate electrode GE1, a drain electrode DE1, a source electrode SE1, and a bias electrode BE1. As Figure 6As shown in the figure, in the plan view, the drain electrode DE1 can be arranged on the first side of the semiconductor region ACT1, and the source electrode SE1 can be arranged on the second side opposite to the first side of the semiconductor region ACT1. The semiconductor region ACT1 of the first transistor ST1 can be arranged in the active layer ACTL and can overlap with the gate electrode GE1 of the first transistor ST1. The active layer ACTL can be arranged on the buffer layer BF covering the first metal layer MTL1.

[0139] The gate electrode GE1 of the first transistor ST1 can be arranged in the second metal layer MTL2. The gate electrode GE1 of the first transistor ST1 and the first capacitor electrode CPE1 of the first capacitor C1 can be integrated with each other in the second metal layer MTL2. The gate electrode GE1 of the first transistor ST1 and the first capacitor electrode CPE1 can be electrically connected to the source electrode SE2 of the second transistor ST2 and the source electrode SE3 of the third transistor ST3 through the third connection electrode CE3 of the fourth metal layer MTL4.

[0140] The drain electrode DE1 and the source electrode SE1 of the first transistor ST1 can be formed as conductors by heat-treating the active layer ACTL. The drain electrode DE1 and the source electrode SE1 can be made conductive as an n-type semiconductor, but the present disclosure is not limited thereto. The drain electrode DE1 of the first transistor ST1 and the source electrode SE5 of the fifth transistor ST5 can be integrated with each other. The source electrode SE1 of the first transistor ST1 can be electrically connected to the shielding electrode SDE through the first connection electrode CE1 of the fourth metal layer MTL4. The source electrode SE1 of the first transistor ST1 and the drain electrode DE4 of the fourth transistor ST4 can be integrated with each other.

[0141] The bias electrode BE1 of the first transistor ST1 can be arranged in the first metal layer MTL1 and overlap with the semiconductor region ACT1 and the gate electrode GE1 of the first transistor ST1. The bias electrode BE1 of the first transistor ST1 can be electrically connected to the shielding electrode SDE through the first connection electrode CE1.

[0142] The second transistor ST2 can include a semiconductor region ACT2, a gate electrode GE2, a drain electrode DE2, a source electrode SE2, and a bias electrode BE2. The active region ACT2 of the second transistor ST2 can be arranged in the active layer ACTL and can overlap with the gate electrode GE2 of the second transistor ST2. The gate electrode GE2 of the second transistor ST2 can be arranged in the second metal layer MTL2. The gate electrode GE2 of the second transistor ST2 can be electrically connected to the first gate line GWL and the bias electrode BE2.

[0143] The drain electrode DE2 and the source electrode SE2 of the second transistor ST2 can be formed as conductors by performing heat treatment on the active layer ACTL. The drain electrode DE2 of the second transistor ST2 can be electrically connected to the data line DL through the second connection electrode CE2 of the fourth metal layer MTL4 (see Figure 4 ). The drain electrode DE2 of the second transistor ST2 can receive the data voltage of the pixel SP from the data line DL. The data line DL is not shown in Figure 6 and Figure 7 , and can be arranged on the fourth metal layer MTL4, but the stacking structure of the data line DL is not limited thereto. The source electrode SE2 of the second transistor ST2 can be electrically connected to the gate electrode GE1 of the first transistor ST1 and the first capacitor electrode CPE1 through the third connection electrode CE3. The source electrode SE2 of the second transistor ST2 and the source electrode SE3 of the third transistor ST3 can be integrated with each other.

[0144] The bias electrode BE2 of the second transistor ST2 can be arranged in the first metal layer MTL1 and overlap with the semiconductor region ACT2 and the gate electrode GE2 of the second transistor ST2. The bias electrode BE2 of the second transistor ST2 can be electrically connected to the gate electrode GE2 of the second transistor ST2.

[0145] The third transistor ST3 can include a semiconductor region ACT3, a gate electrode GE3, a drain electrode DE3, a source electrode SE3, and a bias electrode BE3. The semiconductor region ACT3 of the third transistor ST3 can be arranged in the active layer ACTL and overlap with the gate electrode GE3 of the third transistor ST3. The gate electrode GE3 of the third transistor ST3 can be arranged in the second metal layer MTL2. The gate electrode GE3 of the third transistor ST3 can be electrically connected to the second gate line GRL.

[0146] The drain electrode DE3 and the source electrode SE3 of the third transistor ST3 can be formed as conductors by performing heat treatment on the active layer ACTL. The drain electrode DE3 of the third transistor ST3 can be electrically connected to the reference voltage line VRL to receive the reference voltage. The source electrode SE3 of the third transistor ST3 can be electrically connected to the gate electrode GE1 of the first transistor ST1 and the first capacitor electrode CPE1 through the third connection electrode CE3. The source electrode SE3 of the third transistor ST3 and the source electrode SE2 of the second transistor ST2 can be integrated with each other.

[0147] The bias electrode BE3 of the third transistor ST3 can be arranged in the first metal layer MTL1 and overlap with the semiconductor region ACT3 and the gate electrode GE3 of the third transistor ST3. The bias electrode BE3 of the third transistor ST3 can be a part of the second gate line GRL. The bias electrode BE3 of the third transistor ST3 can be electrically connected to the gate electrode GE3 of the third transistor ST3.

[0148] The fourth transistor ST4 may include a semiconductor region ACT4, a gate electrode GE4, a drain electrode DE4, a source electrode SE4, and a bias electrode BE4. The semiconductor region ACT4 of the fourth transistor ST4 may be disposed in the active layer ACTL and may overlap with the gate electrode GE4 of the fourth transistor ST4. The gate electrode GE4 of the fourth transistor ST4 may be disposed in the second metal layer MTL2. The gate electrode GE4 of the fourth transistor ST4 may be electrically connected to the third gate line GIL.

[0149] The drain electrode DE4 and the source electrode SE4 of the fourth transistor ST4 may be formed as conductors by heat-treating the active layer ACTL. The drain electrode DE4 of the fourth transistor ST4 may be electrically connected to the shielding electrode SDE through the first connection electrode CE1. The drain electrode DE4 of the fourth transistor ST4 and the source electrode SE1 of the first transistor ST1 may be integrated with each other. The source electrode SE4 of the fourth transistor ST4 may be electrically connected to the initialization voltage line VIL.

[0150] The bias electrode BE4 of the fourth transistor ST4 may be disposed in the first metal layer MTL1 and may overlap with the semiconductor region ACT4 and the gate electrode GE4 of the fourth transistor ST4. The bias electrode BE4 of the fourth transistor ST4 may be a part of the third gate line GIL. The bias electrode BE4 of the fourth transistor ST4 may be electrically connected to the gate electrode GE4 of the fourth transistor ST4.

[0151] The fifth transistor ST5 may include a semiconductor region ACT5, a gate electrode GE5, a drain electrode DE5, a source electrode SE5, and a bias electrode BE5. The semiconductor region ACT5 of the fifth transistor ST5 may be disposed in the active layer ACTL and may overlap with the gate electrode GE5 of the fifth transistor ST5. The gate electrode GE5 of the fifth transistor ST5 may be disposed in the second metal layer MTL2. The gate electrode GE5 of the fifth transistor ST5 may be electrically connected to the emission control line EML.

[0152] The drain electrode DE5 and the source electrode SE5 of the fifth transistor ST5 may be formed as conductors by heat-treating the active layer ACTL. The drain electrode DE5 of the fifth transistor may be electrically connected to the drive voltage line VDDL to receive a drive voltage. The source electrode SE5 of the fifth transistor ST5 and the drain electrode DE1 of the first transistor ST1 may be integrated with each other.

[0153] The first capacitor C1 may be formed by the first capacitor electrode CPE1 and the shielding electrode SDE. The first capacitor electrode CPE1 may be disposed in the second metal layer MTL2, and the shielding electrode SDE may be disposed in the third metal layer MTL3. The first capacitor electrode CPE1 may be the first electrode of the first capacitor C1 and may be electrically connected to Figure 4the first node N1. The shielding electrode SDE may correspond to the second electrode of the first capacitor C1 and may be electrically connected to Figure 4 the second node N2. Thus, the first capacitor C1 may maintain the potential difference between the first node N1 and the second node N2. The first capacitor C1 may be disposed on the right side of the second capacitor C2, but the positions of the first capacitor C1 and the second capacitor C2 may be interchanged.

[0154] The second capacitor C2 may be formed by the second capacitive electrode CPE2 and the shielding electrode SDE. The second capacitive electrode CPE2 may be disposed in the second metal layer MTL2, and the shielding electrode SDE may be disposed in the third metal layer MTL3. The second capacitive electrode CPE2 may be the first electrode of the second capacitor C2 and may be electrically connected to the driving voltage line VDDL. The shielding electrode SDE may be the second electrode of the second capacitor C2 and may be electrically connected to Figure 4 the second node N2. Thus, the second capacitor C2 may maintain the potential difference between the driving voltage line VDDL and the second node N2. The second capacitor C2 may be disposed on the left side of the first capacitor C1, but the positions of the first capacitor C1 and the second capacitor C2 may be interchanged.

[0155] The shielding electrode SDE may be electrically connected to the first electrode of the light-emitting element ED. The shielding electrode SDE may cover the upper surface of the drain electrode DE1 of the first transistor ST1. The shielding electrode SDE may prevent the drain electrode DE1 of the first transistor ST1 from being electrically connected to the voltage line VL or the signal line disposed on the third metal layer MTL3. Thus, the shielding electrode SDE may prevent the compensation error in the first transistor ST1 and may improve the image quality of the display device 10.

[0156] The first gate line GWL and the second gate line GRL may be spaced apart from the first transistor ST1 with the first capacitor C1 and the second capacitor C2 therebetween. The third gate line GIL may be spaced apart from the first transistor ST1 with the emission control line EML therebetween. Thus, the first gate line GWL, the second gate line GRL, and the third gate line GIL may be spaced apart from the drain electrode DE1 of the first transistor ST1 and may prevent the voltage of the drain electrode DE1 of the first transistor ST1 from being applied with the rising pulse or the falling pulse of the first gate signal GW[n], the second gate signal GR[n], and the third gate signal GI[n].

[0157] In Figure 7Among them, the display panel 100 may include a substrate SUB, a first metal layer MTL1, a buffer layer BF, an active layer ACTL, a gate insulator GI, a second metal layer MTL2, a first interlayer dielectric layer ILD1, a third metal layer MTL3, a second interlayer dielectric layer ILD2, a fourth metal layer MTL4, a first via layer VIA1, a second via layer VIA2, a pixel defining layer PDL, a light-emitting element ED, and a packaging layer TFEL.

[0158] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate capable of being bent, folded, or curled. For example, the substrate SUB may include a glass material or a metal material, but is not limited thereto. As another example, the substrate SUB may include a polymer resin such as polyimide (PI).

[0159] The first metal layer MTL1 may be disposed on the substrate SUB. The first metal layer MTL1 may include a first bias electrode BE1 and a fifth bias electrode BE5. The first metal layer MTL4 may be made of a single layer or multiple layers including at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0160] The buffer layer BF may be disposed on the first metal layer MTL1 and the substrate SUB. The buffer layer BF may include an inorganic insulating material capable of preventing the penetration of air or moisture. The buffer layer BF may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, or a combination thereof, but is not limited thereto.

[0161] The active layer ACTL may be disposed on the buffer layer BF. The active layer ACTL may include a semiconductor region ACT1 of a first transistor ST1, a drain electrode DE1, a semiconductor region ACT5 of a fifth transistor ST5, a drain electrode DE5, and a source electrode SE5. For example, the active layer ACTL may include an oxide-based active layer. As another example, the active layer ACTL may include low-temperature polycrystalline silicon (LTPS).

[0162] The gate insulator GI may be disposed on the active layer ACTL and the buffer layer BF. The gate insulator GI may insulate the active layer ACTL from the second metal layer MLT2. The gate insulator GI may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0163] The second metal layer MTL2 may be disposed on the gate insulator GI. The second gate layer MTL2 may include the gate electrode GE1 of the first transistor ST1, the gate electrode GE5 of the fifth transistor ST5, and the first capacitor electrode CPE1. The second metal layer MTL2 may be made of a single layer or multiple layers including at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0164] The first interlayer dielectric layer ILD1 may be disposed on the second metal layer MTL2 and the gate insulator GI. The first interlayer dielectric layer ILD1 may insulate the second metal layer MTL2 from the third metal layer MTL3. The first interlayer dielectric layer ILD1 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, or a combination thereof, but is not limited thereto.

[0165] The third metal layer MTL3 may be disposed on the first interlayer dielectric layer ILD1. The third metal layer MTL3 may include a shielding electrode SDE. The third metal layer MTL3 may be made of a single layer or multiple layers including at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0166] The second interlayer dielectric layer ILD2 may be disposed on the third metal layer MTL3 and the first interlayer dielectric layer ILD1. The second interlayer dielectric layer ILD2 may protect the pixel circuit of the pixel SP. The second interlayer dielectric layer ILD2 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, or a combination thereof, but is not limited thereto.

[0167] The fourth metal layer MTL4 may be disposed on the second interlayer dielectric layer ILD2. The fourth metal layer MTL4 may include a driving voltage line VDDL, a first connection electrode CE1, and a third connection electrode CE3. The fourth metal layer MTL4 may be made of a single layer or multiple layers including at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0168] The first via layer VIA1 may be disposed on the fourth metal layer MTL4 and the second interlayer dielectric layer ILD2. For example, the first via layer VIA1 may include an organic insulating material such as polyimide (PI), but is not limited thereto.

[0169] The second via layer VIA2 may be disposed on the first via layer VIA1. For example, the second via layer VIA2 may include an organic insulating material such as polyimide (PI), but is not limited thereto.

[0170] The pixel defining layer PDL may be disposed on the second via layer VIA2. The pixel defining layer PDL may define an emission region or an opening. The pixel defining layer PDL may separate and insulate the pixel electrodes PE of the plurality of pixels SP from each other.

[0171] The light emitting element ED may be disposed on the second via layer VIA2. The light emitting element ED of each of the plurality of pixels SP may include a pixel electrode PE, an emission layer EL, and a common electrode CAT. The pixel electrode PE may be disposed on the second via layer VIA2. The pixel electrode PE may overlap with one of the plurality of emission regions defined by the pixel defining layer PDL. For example, the pixel electrode PE may receive a driving current from the first transistor ST1.

[0172] The emission layer EL may be disposed on the pixel electrode PE. For example, the emission layer EL may be an organic emission layer made of an organic material, but is not limited thereto. If the emission layer EL is an organic emission layer, when the pixel circuit of the pixel SP applies an optional voltage to the pixel electrode PE and the common electrode CAT receives a common voltage or a cathode voltage, holes and electrons may move to the emission layer EL through the hole transport layer and the electron transport layer, respectively, and they combine in the emission layer EL to emit light.

[0173] The common electrode CAT may be disposed on the emission layer EL. For example, the common electrode CAT may be implemented in the form of a common electrode extending across all of the pixels SP. The common electrode CAT may be disposed on the emission layer EL in the emission region, and may be disposed on the pixel defining layer PDL in a region other than the emission region.

[0174] The encapsulation layer TFEL may be disposed on the common electrode CAT to cover the light emitting element ED. The encapsulation layer TFEL may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element ED. The encapsulation layer TFEL may include at least one organic film to protect the light emitting element ED from particles such as dust.

[0175] Figure 8 is a schematic diagram of an equivalent circuit of a pixel of a display device according to an embodiment of the present disclosure.

[0176] Reference Figure 8, each of the plurality of pixels SP may be electrically connected to a first gate line GWL, a second gate line GRL, a third gate line GIL, a fourth gate line EBL, an emission control line EML, a data line DL, a reference voltage line VRL, a driving voltage line VDDL, a first initialization voltage line VIL1, a second initialization voltage line VIL2, and a low-level voltage line VSSL.

[0177] Each of the plurality of pixels SP may include a pixel circuit and a light-emitting element ED. The pixel circuit may include a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, a sixth transistor ST6, a seventh transistor ST7, a first capacitor C1, and a second capacitor C2.

[0178] The first transistor ST1 may include a gate electrode, a source electrode, and a drain electrode. The first transistor ST1 may control a drain-source current (or driving current) based on a data voltage applied to the gate electrode. The driving current flowing through the channel of the first transistor ST1 may be proportional to the square of the difference between the threshold voltage of the first transistor ST1 and the voltage between the gate electrode and the source electrode of the first transistor ST1, i.e., Ids = k'×(Vth - Vgs) 2 , where "Ids" represents the drain-source current of the first transistor ST1, i.e., the driving current, "k'" represents a proportionality coefficient determined by the structure and physical properties of the first transistor ST1, "Vgs" represents the gate-source voltage of the first transistor ST1, and "Vth" represents the threshold voltage of the first transistor ST1. The gate electrode of the first transistor ST1 may be electrically connected to a first node N1, the drain electrode of the first transistor ST1 may be electrically connected to a third node N3, and the source electrode of the first transistor ST1 may be electrically connected to a second node N2.

[0179] The light-emitting element ED may receive a driving current to emit light. The amount or brightness of the light emitted from the light-emitting element ED may be proportional to the magnitude of the driving current.

[0180] The light-emitting element ED may be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode. As another example, the light-emitting element ED may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. As another example, the light-emitting element ED may be a quantum dot light-emitting element including a first electrode, a second electrode, and a quantum dot emission layer disposed between the first electrode and the second electrode. As another example, the light-emitting element ED may be a micro light-emitting diode.

[0181] The first electrode of the light-emitting element ED can be electrically connected to the source electrode of the sixth transistor ST6 and the drain electrode of the seventh transistor ST7. The second electrode of the light-emitting element ED can be electrically connected to the low-level voltage line VSSL and can receive a low-level voltage from the low-level voltage line VSSL.

[0182] The second transistor ST2 can be turned on by the first gate signal of the first gate line GWL to electrically connect the data line DL to the first node N1 that is the gate electrode of the first transistor ST1. The second transistor ST2 can be turned on in response to the first gate signal to apply a data voltage to the first node N1. The gate electrode of the second transistor ST2 can be electrically connected to the first gate line GWL, the drain electrode of the second transistor ST2 can be electrically connected to the data line DL, and the source electrode of the second transistor ST2 can be electrically connected to the first node N1.

[0183] The third transistor ST3 can be turned on by the second gate signal of the second gate line GRL to electrically connect the reference voltage line VRL to the first node N1 that is the gate electrode of the first transistor ST1. The third transistor ST3 can be turned on in response to the second gate signal to apply a reference voltage to the first node N1. The gate electrode of the third transistor ST3 can be electrically connected to the second gate line GRL, the drain electrode of the third transistor ST3 can be electrically connected to the reference voltage line VRL, and the source electrode of the third transistor ST3 can be electrically connected to the first node N1.

[0184] The fourth transistor ST4 can be turned on by the third gate signal of the third gate line GIL to electrically connect the second node N2 that is the source electrode of the first transistor ST1 to the first initialization voltage line VIL1. The fourth transistor ST4 can be turned on based on the third gate signal, thereby discharging the second node N2 to the first initialization voltage. The gate electrode of the fourth transistor ST4 can be electrically connected to the third gate line GIL, the drain electrode of the fourth transistor ST4 can be electrically connected to the second node N2, and the source electrode of the fourth transistor ST4 can be electrically connected to the first initialization voltage line VIL1.

[0185] The fifth transistor ST5 can be turned on by the emission signal of the emission control line EML and can electrically connect the drive voltage line VDDL to the drain electrode of the first transistor ST1. The gate electrode of the fifth transistor ST5 can be electrically connected to the emission control line EML, the drain electrode of the fifth transistor ST5 can be electrically connected to the drive voltage line VDDL, and the source electrode of the fifth transistor ST5 can be electrically connected to the third node N3.

[0186] The sixth transistor ST6 can be turned on by a fourth gate signal of the fourth gate line EBL to electrically connect the second node N2 to the first electrode of the light-emitting element ED. The gate electrode of the sixth transistor ST6 can be electrically connected to the fourth gate line EBL, the drain electrode of the sixth transistor ST6 can be electrically connected to the second node N2, and the source electrode of the sixth transistor ST6 can be electrically connected to the first electrode of the light-emitting element ED. When all of the fifth transistor ST5, the first transistor ST1, and the sixth transistor ST6 are turned on, a drive current can be supplied to the light-emitting element ED.

[0187] The seventh transistor ST7 can be turned on by a third gate signal of the third gate line GIL to electrically connect the first electrode of the light-emitting element ED to the second initialization voltage line VIL2. When the seventh transistor ST7 is turned on based on the third gate signal, the first electrode of the light-emitting element ED can be discharged to the second initialization voltage. The gate electrode of the seventh transistor ST7 can be electrically connected to the third gate line GIL, the drain electrode of the seventh transistor ST7 can be electrically connected to the first electrode of the light-emitting element ED, and the source electrode of the seventh transistor ST7 can be electrically connected to the second initialization voltage line VIL2.

[0188] Each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 can include an oxide-based active layer. The first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 can have a coplanar structure in which the gate electrode is arranged on top. The first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 can be n-type transistors, and can output a current introduced from the source electrode to the drain electrode based on a high gate voltage applied to the gate electrode. The oxide-based active layer can have a relatively small S factor, can increase the constant current drive region in the low gray level region, and can improve the low gray level performance.

[0189] As another example, at least one of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 can include an active layer ACTL made of low-temperature polycrystalline silicon (LTPS). The first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 can be p-type transistors, and can output a current introduced from the drain electrode to the source electrode based on a low gate voltage applied to the gate electrode.

[0190] The first capacitor C1 can be electrically connected between a first node N1 that serves as the gate electrode of the first transistor ST1 and a second node N2 that serves as the source electrode of the first transistor ST1. For example, a first electrode of the first capacitor C1 can be electrically connected to the first node N1, and a second electrode of the first capacitor C1 can be electrically connected to the second node N2 so that a potential difference between the gate electrode and the source electrode of the first transistor ST1 can be maintained.

[0191] The second capacitor C2 can be electrically connected between a drive voltage line VDDL and the second node N2 that serves as the source electrode of the first transistor ST1. For example, a first electrode of the second capacitor C2 can be electrically connected to the drive voltage line VDDL, and a second electrode of the second capacitor C2 can be electrically connected to the second node N2 so that a potential difference between the drive voltage line VDDL and the source electrode of the first transistor ST1 can be maintained.

[0192] Embodiments have been disclosed herein, and although terms are employed, the terms are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some instances, as will be apparent to those of ordinary skill in the art, features, characteristics, and / or elements described in connection with an embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments unless otherwise expressly indicated. Accordingly, those of ordinary skill in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A display device, comprising: substrate; an active layer, the active layer being arranged on the substrate; a first metal layer, the first metal layer being arranged above the active layer; a second metal layer, the second metal layer being arranged above the first metal layer; a first transistor including a semiconductor region arranged in the active layer, a drain electrode arranged on a first side of the semiconductor region, a source electrode arranged on a second side opposite to the first side of the semiconductor region, and a gate electrode arranged in the first metal layer; a first capacitor comprising a first capacitor electrode disposed in the first metal layer and electrically connected to the gate electrode of the first transistor; a second capacitor including a second capacitor electrode disposed in the first metal layer and electrically connected to a driving voltage line supplying a driving voltage; as well as A shielding electrode is disposed in the second metal layer and overlaps the first capacitor electrode, the second capacitor electrode, and the drain electrode of the first transistor.

2. The display device according to claim 1, further comprising: a light emitting element, the light emitting element receiving a driving current from the first transistor, Wherein, the shielding electrode is electrically connected to the first electrode of the light emitting element.

3. The display device according to claim 1, further comprising: A first connection electrode is arranged in a third metal layer above the second metal layer and electrically connects the source electrode of the first transistor with the shielding electrode.

4. The display device according to claim 3, further comprising: A bias electrode of the first transistor, the bias electrode of the first transistor is arranged in a fourth metal layer below the active layer, overlaps the semiconductor region of the first transistor, and is electrically connected to the shielding electrode through the first connection electrode.

5. The display device according to claim 1, further comprising: a data line, the data line supplying a data voltage; a first gate line, the first gate line supplying a first gate signal; as well as a second transistor including a semiconductor region arranged in the active layer, a drain electrode electrically connected to the data line, a source electrode electrically connected to the gate electrode of the first transistor, and a gate electrode arranged in the first metal layer and electrically connected to the first gate line.

6. The display device according to claim 5, wherein: In a plan view, the first capacitor and the second capacitor are arranged between the first gate line and the first transistor.

7. The display device according to claim 5, further comprising: A bias electrode of the second transistor, the bias electrode of the second transistor is arranged in a fourth metal layer below the active layer, overlaps the semiconductor region of the second transistor, and is electrically connected to the gate electrode of the second transistor.

8. The display device according to claim 5, further comprising: a reference voltage line, the reference voltage line supplying a reference voltage; a second gate line, the second gate line supplying a second gate signal; as well as A third transistor includes a semiconductor region arranged in the active layer, a drain electrode electrically connected to the reference voltage line, a source electrode electrically connected to the gate electrode of the first transistor, and a gate electrode arranged in the first metal layer and electrically connected to the second gate line.

9. The display device according to claim 8, wherein: In a plan view, the first capacitor and the second capacitor are arranged between the second gate line and the first transistor.

10. The display device according to claim 8, further comprising: A bias electrode of the third transistor, wherein the bias electrode of the third transistor is arranged in a fourth metal layer below the active layer, overlaps with the semiconductor region of the third transistor, and is a part of the second gate line.

11. The display device according to claim 8, further comprising: an initialization voltage line, the initialization voltage line supplying an initialization voltage; a third gate line, the third gate line supplying a third gate signal; as well as A fourth transistor, the fourth transistor including a semiconductor region arranged in the active layer, a drain electrode electrically connected to the source electrode of the first transistor, a source electrode electrically connected to the initialization voltage line, and a gate electrode arranged in the first metal layer and electrically connected to the third gate line.

12. The display device according to claim 11, further comprising: A bias electrode of the fourth transistor, wherein the bias electrode of the fourth transistor is arranged in a fourth metal layer below the active layer, overlaps with the semiconductor region of the fourth transistor, and is a part of the third gate line.

13. The display device according to claim 11, further comprising: a transmission control line, the transmission control line supplying a transmission signal; as well as A fifth transistor, the fifth transistor including a semiconductor region arranged in the active layer, a drain electrode electrically connected to the driving voltage line, a source electrode electrically connected to the drain electrode of the first transistor, and a gate electrode arranged in the first metal layer and electrically connected to the emission control line.

14. The display device according to claim 13, further comprising: A bias electrode of the fifth transistor, the bias electrode of the fifth transistor is arranged in a fourth metal layer below the active layer, overlaps with the semiconductor region of the fifth transistor, and is electrically connected to the gate electrode of the fifth transistor.

15. The display device according to claim 13, wherein: In a plan view, the emission control line is arranged between the third gate line and the first transistor.

16. The display device according to claim 13, further comprising: a light emitting element, the light emitting element being arranged in a third metal layer on the second metal layer; a sixth transistor electrically connected between the source electrode of the first transistor and the first electrode of the light emitting element; as well as A seventh transistor that discharges a source electrode of the sixth transistor and the first electrode of the light emitting element.

17. A display device, comprising: a first gate line extending in a first direction and supplying a first gate signal; A light emitting element, wherein the light emitting element is arranged on the first gate line; a first transistor that supplies a driving current to the light emitting element; a second transistor that supplies a data voltage to a gate electrode of the first transistor based on the first gate signal; a first capacitor formed between the gate electrode of the first transistor and a source electrode of the first transistor; as well as a shielding electrode electrically connected to the source electrode of the first transistor and corresponding to a second electrode of the first capacitor, Wherein, in a plan view, the first capacitor is arranged between the first gate line and the first transistor.

18. The display device according to claim 17, wherein: The shielding electrode is disposed on the first transistor and overlaps with a drain electrode of the first transistor.

19. The display device according to claim 17, further comprising: a second gate line extending in the first direction and supplying a second gate signal; as well as a third transistor that supplies a reference voltage to the gate electrode of the first transistor based on the second gate signal, Wherein, in a plan view, the first capacitor is arranged between the second gate line and the first transistor.

20. The display device according to claim 19, further comprising: a third gate line extending in the first direction and supplying a third gate signal; a transmission control line extending in the first direction and supplying a transmission signal; a fourth transistor configured to discharge the first electrode of the light emitting element based on the third gate signal; as well as a fifth transistor that supplies a driving voltage to a drain electrode of the first transistor based on the emission signal.

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