Array substrate, display device and preparation method of array substrate

Abstract

The invention provides an array substrate, a display device and a preparation method of the array substrate, the array substrate comprises a first-type transistor and a second-type transistor, the first-type transistor is a vertical channel transistor, the second-type transistor is a horizontal channel transistor, the first-type transistor comprises a first active structure, and the second-type transistor comprises a second active structure. The second type transistor comprises a second active structure, and the first active structure and the second active structure are arranged on the same layer. In the embodiment of the invention, the first type transistor and the second type transistor respectively have different characteristic advantages, so that the circuit requirements of the array substrate at different positions can be met, and the display and use reliability of a subsequently formed display panel is improved. And meanwhile, the first active structure and the second active structure are prepared and formed together in a same-layer arrangement mode, so that on one hand, the manufacturing process can be reduced, the manufacturing process complexity is reduced, the cost is reduced, on the other hand, the adverse effect on the overall thickness of the array substrate can be reduced, and light and thin design is facilitated.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular, to an array substrate, a display device, and a method for manufacturing an array substrate. Background Art

[0002] With the diversification of consumer market demands, consumers' requirements for display devices are also getting higher and higher. For most consumers, high-resolution and high-refresh-rate displays can bring a smoother gaming experience and visual experience. In order to achieve a higher-specification display effect, higher requirements are put forward for the circuit performance in the array substrate that drives panel display. Summary of the Invention

[0003] Embodiments of the present application provide an array substrate, a display device, and a method for manufacturing an array substrate, which can simplify the manufacturing process.

[0004] In a first aspect, embodiments of the present application provide an array substrate. The array substrate includes a first type of transistor and a second type of transistor. The first type of transistor is a vertical-channel transistor, and the second type of transistor is a horizontal-channel transistor. The first type of transistor includes a first active structure, and the second type of transistor includes a second active structure. The first active structure and the second active structure are disposed on the same layer.

[0005] In some embodiments, the first type of transistor includes a first pole, a second pole, and a first control end for controlling the conduction between the first pole and the second pole. The second type of transistor includes a third pole, a fourth pole, and a second control end for controlling the conduction between the third pole and the fourth pole. The array substrate further includes:

[0006] A substrate;

[0007] A first insulating layer disposed on one side of the substrate. The first insulating layer includes a first hole;

[0008] An active layer disposed on the side of the first insulating layer away from the substrate. The active layer includes a first active structure and a second active structure. At least a part of the first active structure is located in the first hole and is disposed in contact with the side wall of the first hole;

[0009] In some embodiments, the first active structure includes a first channel structure, and the second active structure includes a second channel structure. The first channel structure and the second channel structure are disposed on the same layer;

[0010] In some embodiments, the array substrate further includes a first conductor layer located between the first insulating layer and the substrate. The first conductor layer includes the first pole;

[0011] Wherein, the orthographic projection of the first pole on the substrate overlaps with the orthographic projection of the first hole on the substrate.

[0012] In some embodiments, the first electrode is located on the side of the first insulating layer facing the substrate, and at least part of the structures of the second control terminal are disposed on the same layer as the first electrode;

[0013] In some embodiments, all of the structures of the second control terminal are disposed on the same layer as the first electrode, and the orthographic projection of the second control terminal on the substrate overlaps with the orthographic projection of the second active structure on the substrate; or,

[0014] The second control terminal includes a first part disposed on the same layer as the first electrode and a second part located on the side of the active layer facing away from the substrate, and the orthographic projections of the first part and the second part on the substrate both overlap with the orthographic projection of the second active structure on the substrate;

[0015] In some embodiments, the second electrode is disposed between the first insulating layer and the first active structure and is disposed around the outer peripheral side of the first hole;

[0016] In some embodiments, the active layer includes an oxide semiconductor.

[0017] In some embodiments, a second insulating layer is further included and is disposed on the side of the active layer facing away from the substrate, and the second insulating layer covers the first active structure and the second active structure;

[0018] In some embodiments, the first control terminal is located on the side of the second insulating layer facing away from the substrate;

[0019] In some embodiments, the third electrode is located on the side of the second insulating layer facing away from the substrate;

[0020] In some embodiments, both the third electrode and the fourth electrode are located on the side of the second insulating layer facing away from the substrate;

[0021] In some embodiments, at least part of the structures of the second control terminal are located on the side of the second insulating layer facing away from the substrate.

[0022] In some embodiments, a second conductor layer is further included and is disposed on the side of the second insulating layer facing away from the substrate, and the second conductor layer includes the first control terminal and the third electrode;

[0023] In some embodiments, the second conductor layer includes the fourth electrode;

[0024] In some embodiments, the array substrate further includes a third conductor layer disposed between the second conductor layer and the second insulating layer, and a third insulating layer located between the third conductor layer and the second conductor layer, and at least part of the second control terminal is located within the third conductor layer.

[0025] In some embodiments, a second conductor layer is further included and is disposed on the side of the second insulating layer facing away from the substrate, and the second conductor layer includes at least part of the structures of the second control terminal and the first control terminal;

[0026] In some embodiments, the second conductor layer includes all the structures in the second control terminal, and the orthographic projection of the second control terminal on the substrate overlaps with the orthographic projection of the second active structure on the substrate; or,

[0027] The second control terminal includes a first portion on the side of the active layer facing the substrate and a second portion within the second conductor layer, and the orthographic projections of both the first portion and the second portion on the substrate overlap with the orthographic projection of the second active structure on the substrate;

[0028] In some embodiments, the second control terminal includes a first portion and a second portion, and the first portion is disposed on the same layer as the first electrode.

[0029] In some embodiments, the array substrate further includes a first conductor layer located between the first insulating layer and the substrate. The material of the first conductor layer is a light-shielding material, and the first conductor layer includes a light-shielding conductor portion and a first electrode;

[0030] In some embodiments, the orthographic projection of the light-shielding conductor portion on the substrate overlaps with the orthographic projection of the second active structure on the substrate;

[0031] In some embodiments, the light-shielding conductor portion is insulated from the first electrode;

[0032] In some embodiments, the light-shielding conductor portion transmits a constant voltage signal.

[0033] In some embodiments, the array substrate includes a plurality of pixel circuits, and each pixel circuit includes a first transistor and a storage capacitor. The storage capacitor includes a first electrode plate;

[0034] The first transistor is a first-type transistor, and the first control terminal of the first transistor is electrically connected to the first electrode plate;

[0035] In some embodiments, the array substrate further includes a gate driving circuit, and the gate driving circuit includes a second transistor;

[0036] The second transistor is a second-type transistor, and the third electrode of the second transistor is electrically connected to the scanning signal line.

[0037] In some embodiments, the array substrate includes a first region and a second region disposed around the periphery of the first region. Pixel circuits are provided in the first region, and a gate driving circuit is provided in the second region.

[0038] In a second aspect, an embodiment of the present application provides a display device, including the array substrate in any of the foregoing embodiments.

[0039] In a third aspect, an embodiment of the present application provides a method for manufacturing an array substrate. The manufacturing method includes:

[0040] Forming a first insulating material layer on one side of the substrate;

[0041] Pattern the first insulating material layer to form a first hole to obtain a first insulating layer;

[0042] Form an active material layer on the side of the first insulating layer facing away from the substrate;

[0043] Pattern the active material layer to form a first active structure and a second active structure to obtain an active layer. At least a part of the first active structure is located in the first hole and is disposed in contact with the side wall of the first hole.

[0044] In some embodiments, before the step of forming the first insulating material layer on one side of the substrate, it further includes:

[0045] Form a first conductor material layer on one side of the substrate;

[0046] Pattern the first conductor material layer to form a first pole and a second control end to obtain a first conductor layer. The orthographic projection of the first pole on the substrate overlaps with the orthographic projection of the first hole on the substrate;

[0047] In some embodiments, after the step of patterning the active material layer, it further includes:

[0048] Form a second insulating material layer on the side of the active layer facing away from the substrate, the second insulating material layer;

[0049] Pattern the second insulating material layer to form a second hole and a third hole to obtain a second insulating layer. The orthographic projections of the second hole and the third hole on the substrate are located within the orthographic projection of the second active structure on the substrate;

[0050] In some embodiments, after the step of patterning the second insulating material layer, it further includes:

[0051] Form a second conductor material layer on the side of the second insulating layer facing away from the substrate;

[0052] Pattern the second conductor material layer to form a first control end, a third pole and a fourth pole to obtain a second conductor layer. The orthographic projection of the first control end on the substrate overlaps with the orthographic projection of the first hole on the substrate, and the third pole and the fourth pole are respectively connected to the second active structure through the second hole and the third hole.

[0053] The embodiments of the present application provide an array substrate, a display device, and a method for manufacturing an array substrate. The array substrate includes at least two types of thin film transistors, namely a first type of transistor and a second type of transistor. The first type of transistor and the second type of transistor have different characteristic advantages respectively, so as to meet the circuit requirements at different parts of the array substrate and improve the display and use reliability of the subsequent formed display panel. At the same time, the first active structure of the first type of transistor and the second active structure of the second type of transistor are prepared and formed in the same layer setting manner. On the one hand, this can reduce the manufacturing process, reduce the process complexity and cost. On the other hand, it can also reduce the adverse impact on the overall thickness of the array substrate, which is beneficial to the thin and light design. Description of the Drawings

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0055] Figure 1 It is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the present application;

[0056] Figure 2 It is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the present application;

[0057] Figure 3 It is a schematic cross-sectional structure diagram of still another array substrate provided by an embodiment of the present application;

[0058] Figure 4 It is a schematic cross-sectional structure diagram of still another array substrate provided by an embodiment of the present application;

[0059] Figure 5 It is a schematic circuit structure diagram of a pixel circuit in still another array substrate provided by an embodiment of the present application;

[0060] Figure 6 It is a schematic structure diagram of still another array substrate provided by an embodiment of the present application;

[0061] Figure 7 It is a schematic structure diagram of a display device provided by an embodiment of the present application;

[0062] Figure 8 It is a flowchart of a method for manufacturing an array substrate provided by an embodiment of the present application;

[0063] Figures 9a to 9d It is a schematic process structure diagram of a method for manufacturing an array substrate provided by an embodiment of the present application;

[0064] Figure 10It is a flowchart of a method for manufacturing a thin film transistor provided by an embodiment of the present application;

[0065] Figures 11a to 11b It is a schematic structural diagram of the process of a method for manufacturing a thin film transistor provided by an embodiment of the present application;

[0066] Figure 12 It is a flowchart of a method for manufacturing an array substrate provided by an embodiment of the present application;

[0067] Figures 13a to 13b It is a schematic structural diagram of the process of a method for manufacturing an array substrate provided by an embodiment of the present application;

[0068] Figure 14 It is a flowchart of a method for manufacturing an array substrate provided by an embodiment of the present application;

[0069] Figures 15a to 15b It is a schematic structural diagram of the process of a method for manufacturing an array substrate provided by an embodiment of the present application.

[0070] Marking description:

[0071] 10. First type transistor; 11. First pole; 12. Second pole; 13. First control terminal; 14. First active structure; 141. First channel structure;

[0072] 20. Second type transistor; 21. Third pole; 22. Fourth pole; 23. Second control terminal; 231. First part; 232. Second part; 24. Second active structure; 241. Second channel structure; 25. Second hole; 26. Third hole;

[0073] 30. Substrate;

[0074] 41. First conductor layer; 42. Second conductor layer; 43. Third conductor layer;

[0075] 51. First insulating layer; 52. Second insulating layer; 53. Third insulating layer;

[0076] 60. Active layer;

[0077] D. Light-shielding conductor part;

[0078] D1. Pixel circuit; D2. Gate driving circuit;

[0079] H. First hole;

[0080] A1. First area; A2. Second area;

[0081] 51’. First insulating material layer; 60’. Active material layer; 41’. First conductor material layer; 52’. Second insulating material layer; 42’. Second conductor material layer. Detailed implementation manners

[0082] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the objectives, technical solutions and advantages of the present application more clear, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0083] It should be noted that, in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0084] In the driving circuit of a display panel, there are often multiple thin film transistors. The functions of the multiple thin film transistors often vary, so the performance requirements also vary. For example, the thin film transistor that plays a driving role needs to have a large on-state current to meet high brightness and large current, while the thin film transistor connected to the storage capacitor and acting as a switch requires a small off-state current to meet the voltage holding requirement of the capacitor. On this basis, it is difficult for a single type of thin film transistor structure to meet the performance requirements of different thin film transistors. Therefore, there need to be multiple different types of thin film transistors in the display panel, and multiple types of thin film transistors often lead to an increase in the complexity of the manufacturing process.

[0085] In view of the above problems, in a first aspect, please refer to Figure 1 , an embodiment of the present application provides an array substrate. The array substrate includes a first type of transistor 10 and a second type of transistor 20. The first type of transistor 10 is a vertical channel transistor, and the second type of transistor 20 is a horizontal channel transistor. The first type of transistor 10 includes a first active structure 14, and the second type of transistor 20 includes a second active structure 24. The first active structure 14 and the second active structure 24 are disposed on the same layer.

[0086] The array substrate is used to form a display panel subsequently. A circuit structure is provided in the array substrate. For example, the array substrate may include a pixel circuit D1 for controlling a light-emitting structure to implement a light-emitting function, a gate driving circuit D2 for providing a scanning signal, a light-emitting driving circuit for providing a light-emitting signal, a multiplexer, and the like.

[0087] The array substrate includes a first type of transistor 10 and a second type of transistor 20. The first type of transistor 10 and the second type of transistor 20 are different types of thin-film transistors. Among them, in the same circuit structure, such as in the pixel circuit D1, both the first type of transistor 10 and the second type of transistor 20 may be present simultaneously, or only one of the first type of transistor 10 and the second type of transistor 20 may be present. The embodiments of the present application do not limit this, as long as both the first type of transistor 10 and the second type of transistor 20 can be present simultaneously in the array substrate.

[0088] The first type of transistor 10 is a vertical-channel transistor. A vertical-channel transistor is a transistor having a vertical current flow path, and its design enables the current to flow in the vertical direction rather than the conventional lateral direction. This design brings multiple advantages, including higher current driving ability, lower power consumption, and higher reliability.

[0089] The second type of transistor 20 is a horizontal-channel transistor. A horizontal-channel transistor is a transistor having a lateral current flow path, that is, the current in the horizontal-channel transistor flows in the lateral direction. In the related art, since the structural layout methods of the vertical-channel transistor and the horizontal-channel transistor are different, generally, a vertical-channel transistor and a horizontal-channel transistor are not provided simultaneously in the array substrate. Further, even if a vertical-channel transistor and a horizontal-channel transistor are provided simultaneously in the array substrate in the related art, due to the structural differences between the two types of transistors, the vertical-channel transistor and the horizontal-channel transistor are usually arranged offset in the thickness direction of the array substrate. This design easily causes an increase in the overall thickness of the array substrate and an increase in the process complexity, which is not conducive to actual production applications.

[0090] In view of this, in addition to integrating two types of thin-film transistors, namely the first type of transistor 10 and the second type of transistor 20, in the array substrate to meet the circuit requirements at different positions of the array substrate, the embodiments of the present application also adjust the structural layout of the two types of thin-film transistors. Specifically, the first active structure 14 is the active structure of the first type of transistor 10, and the channel region in the first active structure 14 extends along the thickness direction of the array substrate to meet the requirement for the current to flow in the vertical direction. The second active structure 24 is the active structure of the second type of transistor 20, and the channel region in the second active structure 24 extends along the direction parallel to the plane where the array substrate is located to meet the requirement for the current to flow in the lateral direction.

[0091] Furthermore, the first active structure 14 of the first type transistor 10 and the second active structure 24 of the second type transistor 20 are arranged in the same layer, that is, the first active structure 14 and the second active structure 24 are made of the same material and are prepared together through the same process. On the one hand, this helps to improve the preparation efficiency of the first type transistor 10 and the second type transistor 20 and simplify the preparation process of the array substrate. On the other hand, it also makes the first type transistor 10 and the second type transistor 20 located at the same height position in the thickness direction of the array substrate, thereby reducing the adverse effect on the overall thickness of the array substrate and facilitating a lightweight design.

[0092] In summary, in the embodiment of the present application, the array substrate includes at least two types of thin film transistors, namely, a first type transistor 10 and a second type transistor 20. The first type transistor 10 and the second type transistor 20 have different characteristic advantages, respectively, so as to meet the circuit requirements of the array substrate at different locations, and improve the display and use reliability of the display panel formed subsequently. At the same time, the first active structure 14 of the first type transistor 10 and the second active structure 24 of the second type transistor 20 are prepared together in the same layer setting, which can reduce the process, reduce the process complexity and reduce the cost on the one hand, and reduce the adverse effect on the overall thickness of the array substrate on the other hand, which is conducive to the thin and light design.

[0093] In some embodiments, the first type transistor 10 includes a first electrode 11, a second electrode 12, and a first control terminal 13 that controls conduction between the first electrode 11 and the second electrode 12, and the second type transistor includes a third electrode 21, a fourth electrode 22, and a second control terminal 23 that controls conduction between the third electrode 21 and the fourth electrode 22.

[0094] The array substrate further includes a substrate 30, a first insulating layer 51 and an active layer 60. The first insulating layer 51 is disposed on one side of the substrate 30. The first insulating layer 51 includes a first hole H. The active layer 60 is disposed on a side of the first insulating layer 51 away from the substrate 30. The first active structure 14 is at least partially located in the first hole H and is disposed in contact with the side wall of the first hole H.

[0095] The first type of transistor 10 includes a first pole 11, a second pole 12, and a first control terminal 13 for controlling the conduction between the first pole 11 and the second pole 12. Optionally, the first pole 11 can be the source of the first type of transistor 10, the second pole 12 can be the drain of the first type of transistor 10, and the first control terminal 13 can be the gate of the first type of transistor 10. The second type of transistor includes a third pole 21, a fourth pole 22, and a second control terminal 23 for controlling the conduction between the third pole 21 and the fourth pole 22. Optionally, the third pole 21 can be the source of the second type of transistor 20, the fourth pole 22 can be the drain of the second type of transistor 20, and the second control terminal 23 can be the gate of the second type of transistor 20.

[0096] Next, the embodiments of the present application will describe the structures of the first type of transistor 10 and the second type of transistor 20 from the aspect of the film layer layout. The array substrate includes a substrate 30, a first insulating layer 51, and an active layer 60 that are sequentially stacked. Among them, the substrate 30 is a film layer in the array substrate for carrying other film layer structures, the active layer 60 is a film layer structure including semiconductor materials in the array substrate, and the first insulating layer 51 is a functional film layer in the array substrate including insulating materials and used to insulate and space the active layer 60 from other conductor layers or semiconductor layers.

[0097] A thin-film transistor is a transistor manufactured based on thin-film materials. It is an insulated-gate field-effect transistor mainly composed of a conductive structure and a semiconductor structure. On this basis, in addition to including the first pole 11, the second pole 12, and the first control terminal 13 in the conductor structure, the first type of transistor 10 also includes a first active structure 14 in the semiconductor structure. Similarly, in addition to including the third pole 21, the fourth pole 22, and the second control terminal 23 in the conductor structure, the second type of transistor 20 also includes a second active structure 24 in the semiconductor structure. Further, both the first active structure 14 and the second active structure 24 are located in the active layer 60, and they include the same material and are formed together in the same process.

[0098] The first insulating layer 51 includes a first hole H, and the first active structure 14 is at least partially located in the first hole H, that is, the first active structure 14 is arranged corresponding to the first hole H. During the preparation process, part of the material in the first active structure 14 will enter the first hole H, and contact and connect with the part of the structure exposed to the first hole H, such as the first pole, and the other part of the material will extend along the side wall of the first hole H to the side of the first insulating layer 51 away from the substrate 30, and contact and connect with the second pole 12 located on the side of the first insulating layer 51 away from the substrate 30, and the first control terminal 13 will be formed on the side of the first active structure 14 away from the substrate 30, and is spaced from the first active structure 14. Among them, the part of the structure in the first active structure 14 that is arranged in contact with the side wall of the first hole H is the part of the structure in the first active structure 14 located in the channel region. Under this design, the channel region in the first active structure 14 can extend along the thickness direction of the array substrate to meet the need for current to flow in the vertical direction.

[0099] As for the second type transistor 20, since the second active structure 24 is not arranged corresponding to the first hole H, that is, the second active structure 24 can be completely located on the side of the first insulating layer 51 away from the substrate 30, the channel region in the second active structure 24 can extend in a direction parallel to the plane where the array substrate is located to meet the need for current to flow in the lateral direction.

[0100] It should be noted that the specific positional relationship of the second control terminal 23, the third electrode 21 and the fourth electrode 22 in the second type transistor 20 relative to the second active structure 24 is not limited in the embodiment of the present application. For example, the second control terminal 23 can be completely located on the side of the second active structure 24 away from the substrate 30, that is, the second type transistor 20 can be a top-gate thin film transistor. Or the second control terminal 23 can be completely located on the side of the second active structure 24 facing the substrate 30, that is, the second type transistor 20 can be a bottom-gate thin film transistor. Or the second control terminal 23 can also be partially located on the side of the second active structure 24 facing the substrate 30, and partially located on the side of the second active structure 24 away from the substrate 30.

[0101] Further, considering that a plurality of second-type transistors 20 need to be provided in the array substrate, and at different circuit positions, the second-type transistors 20 may have different layout requirements. On this basis, the second-type transistors 20 at different positions may be different. For example, the second-type transistors 20 provided at some positions may be top-gate type, while the second-type transistors 20 at other positions may be bottom-gate type, and the embodiments of the present application do not limit this. As long as the active structure of the thin-film transistor is located in the active layer 60 and is a horizontal channel transistor, the thin-film transistor is a second-type transistor 20. The second-type transistors 20 at different positions may remain the same, or there may be differences.

[0102] The channel length of the first type of transistor 10 often depends on the axial dimension of the first hole H. Therefore, the corresponding channel length of the first type of transistor 10 is relatively short and can be applicable to situations that require a high on-state current. For example, it can be applicable to the driving transistor in the pixel circuit D1 that requires a high on-state current to meet the high brightness requirement. While the second type of transistor 20 can often have a larger channel length and thus can be applicable to situations with higher requirements for threshold stability.

[0103] Regarding the material composition mode of the active layer 60, the embodiments of the present application do not make any restrictions. The active layer 60 can include an oxide semiconductor or a low-temperature polycrystalline silicon semiconductor. Optionally, the active layer 60 includes an oxide semiconductor. This design helps to reduce the risk of current leakage between the first type of transistor 10 and the second type of transistor 20 and improve the reliability of the subsequent formed display panel.

[0104] In the embodiments of the present application, by patterning the first insulating layer 51 to include a first hole H corresponding to the first active structure 14, the channel region in the first active structure 14 can be extended along the thickness direction of the array substrate through the first hole H, meeting the preparation requirements of the vertical channel transistor. At the same time, by misplacing the second active structure 24 relative to the first hole H, the channel region in the second active structure 24 can be extended along the direction parallel to the plane where the array substrate is located, meeting the preparation requirements of the horizontal channel transistor. Further, this design can also meet the requirement of fabricating the first active structure 14 and the second active structure 24 on the same layer, thereby simplifying the preparation process of the array substrate.

[0105] In some embodiments, the first active structure 14 includes a first channel structure 141, the second active structure 24 includes a second channel structure 242, and the first channel structure 141 and the second channel structure 241 are arranged on the same layer.

[0106] The first channel structure 141 is a partial structure in the first active structure 14 located in the channel region. The first channel structure 141 is attached to the sidewall of the first hole H to enable current to flow in the vertical direction. The second channel structure 241 is a partial structure in the second active structure 24 located in the channel region. The second channel structure 241 can be attached to the surface of the first insulating layer 51 facing away from the substrate 30 to enable current to flow in the lateral direction.

[0107] Further, in the embodiment of the present application, the first channel structure 141 and the second channel structure 241 are arranged in the same layer, that is, the two include the same material and are prepared together in the same process, thereby simplifying the preparation process of the array substrate and improving the preparation efficiency. Optionally, the partial structure of the first active structure 14 located in the source region and the drain region is arranged in the same layer as the first channel structure 141, and the partial structure of the second active structure 24 located in the source region and the drain region is arranged in the same layer as the second channel structure 241, thereby further improving the preparation efficiency.

[0108] In some embodiments, the array substrate further includes a first conductor layer 41, the first conductor layer 41 is located between the first insulating layer 51 and the substrate 30, and the first conductor layer 41 includes a first electrode 11. The orthographic projection of the first electrode 11 on the substrate 30 overlaps with the orthographic projection of the first hole H on the substrate.

[0109] The first conductor layer 41 is a functional film layer including a conductor material and located on the side of the active layer 60 facing the substrate. The presence of the first insulating layer 51 can achieve an insulating gap between the first conductor layer 41 and the active layer 60. Further, the first conductor layer 41 includes a first pole 11, that is, the first pole 11 is formed between the first insulating layer 51 and the active layer 60, so that when the first insulating layer 51 is formed, the first pole 11 can be exposed relative to the first hole H, and when the active layer 60 is formed, the first active structure 14 can be contacted and bonded with a portion of the structure corresponding to the first hole H in the first pole 11.

[0110] In some embodiments, Figure 1 As shown, the first electrode 11 is located on the side of the first insulating layer 51 facing the substrate 30 , and at least part of the structure in the second control end 23 is arranged in the same layer as the first electrode 11 , that is, the first conductor layer 41 includes at least part of the structure in the second control end 23 and the first electrode 11 .

[0111] The second control terminal 23 may be completely located in the first conductor layer 41. In this case, the second control terminal 23 is completely located on the side of the second active structure 24 facing the substrate 30. In this case, the second type transistor 20 is a bottom-gate thin film transistor. Alternatively, the second control terminal 23 may be partially located in the first conductor layer 41 and partially located on the side of the second active structure 24 facing away from the substrate 30. In this case, the second type transistor 20 is a dual-gate thin film transistor.

[0112] It should be noted that, in view of different circuit requirements at different positions of the array substrate, the array substrate may have second-type transistors 20 with different structures at different positions, or may have second-type transistors 20 with the same structure. For example, at some positions, the second control terminal 23 may be completely located on the side of the second active structure 24 facing the substrate 30, while at other positions, the second control terminal 23 may be partially located in the first conductor layer 41 and partially located on the side of the second active structure 24 facing away from the substrate 30.

[0113] In the embodiment of the present application, at least part of the structure in the second control terminal 23 is arranged in the same layer as the first electrode 11, that is, at least part of the structure in the second control terminal 23 and the first electrode 11 include the same material and are prepared together in the same process. This helps to further simplify the process and reduce the process difficulty and preparation cost while meeting the needs of different types of thin film transistors of the display panel.

[0114] In some embodiments, all structures in the second control terminal 23 are arranged in the same layer as the first electrode 11, and the orthographic projection of the second control terminal 23 on the substrate 30 overlaps with the orthographic projection of the second active structure 24 on the substrate 30. In this case, the second control terminal 23 is completely located in the first conductor layer 41 and is completely formed together with the first electrode 11 in the same process, which is conducive to simplifying the process and reducing the difficulty of the process.

[0115] Or in some embodiments, see Figure 2 The second control terminal 23 includes a first portion 231 disposed in the same layer as the first pole 11, and a second portion 232 located on the side of the active layer 60 away from the substrate 30, and the orthographic projections of the first portion 231 and the second portion 232 on the substrate 30 overlap with the orthographic projections of the second active structure 24 on the substrate 30. Among them, the first portion 231 and the first pole 11 include the same material and are formed together in the same process, and the second portion 232 can include the same material as the first portion 231, or the second portion 232 can also include a different material from the first portion 231, and the embodiment of the present application is not limited to this. Furthermore, the performance of the second type transistor 20 can be improved by adjusting at least one of the material composition and positional relationship of the first portion 231 and the second portion 232 to meet the circuit requirements in different situations.

[0116] In some embodiments, Figure 1 and Figure 2 As shown, the second electrode 12 is disposed between the first insulating layer 51 and the first active structure 14 , and is disposed around the outer circumference of the first hole H.

[0117] In the embodiment of the present application, the positive projection of the second electrode 12 on the substrate 30 is disposed around the positive projection of the first hole H on the substrate 30, and the second electrode 12 can be disposed in contact with the surface of the first insulating layer 51 facing away from the substrate 30. On this basis, the structure of the first active structure 14 on the side of the first insulating layer 51 facing away from the substrate 30 can be in contact connection with the second electrode 12, so as to meet the structural requirements of the first type of transistor 10.

[0118] In some embodiments, as Figure 1 shown, the array substrate further includes a second insulating layer 52 disposed on the side of the active layer 60 facing away from the substrate 30, and the second insulating layer 52 covers the first active structure 14 and the second active structure 24.

[0119] The second insulating layer 52 is a film layer located on the side of the active layer 60 facing away from the substrate 30 and including an insulating material. The second insulating layer 52 can be a whole-surface structure and simultaneously cover the first active structure 14 and the second active structure 24. In this case, only by means of one insulating film layer of the second insulating layer 52, the insulating effects on both the first active structure 14 and the second active structure 24 can be achieved simultaneously. This design is beneficial to simplifying the manufacturing process, reducing the manufacturing difficulty and the preparation cost.

[0120] It should be noted that the "coverage" mentioned here means that the positive projection of the second insulating layer 52 on the substrate 30 overlaps with the positive projections of both the first active structure 14 and the second active structure 24 on the substrate 30 at the same time, and the outer contour of the positive projection of the second insulating layer 52 on the substrate 30 exceeds the outer contours of the positive projections of the first active structure 14 and the second active structure 24 on the substrate 30. Among them, in order to meet the preparation requirements of the second type of transistor 20, a second hole and a third hole can be provided in the second insulating layer 52, and the third electrode 21 and the fourth electrode 22 are respectively connected to the second active structure 24 through the second hole 25 and the third hole 26.

[0121] In some embodiments, the first control terminal 13 is located on the side of the second insulating layer 52 facing away from the substrate 30.

[0122] In the embodiment of the present application, the first control terminal 13 can be the gate of the first type of transistor 10, and the second insulating layer 52 can insulate and space apart the first control terminal 13 from the first active structure 14 to meet the operation requirements of the first type of transistor 10. Among them, the first control terminal 13 can be disposed in contact with the second insulating layer 52, or there can be other film layer structures between the first control terminal 13 and the second insulating layer 52, and the embodiment of the present application does not limit this.

[0123] Further optionally, a part of the surface of the second pole 12 facing away from the substrate 30 is covered by the first active structure 14, and a part is covered by the second insulating layer 52. In this case, the second insulating layer 52 can also play an insulating and protective role for the second pole 12, improving the reliability of use of the first type of transistor 10.

[0124] In some embodiments, the third pole 21 is located on the side of the second insulating layer 52 facing away from the substrate 30.

[0125] In the embodiments of the present application, the second insulating layer 52 can achieve an insulating interval between the third pole 21 and the second active structure 24, so as to meet the operating requirements of the second type of transistor 20. Among them, the third pole 21 can be disposed in contact with the second insulating layer 52, or there may be other film layer structures between the third pole 21 and the second insulating layer 52. The embodiments of the present application do not limit this.

[0126] It should be noted that according to different actual needs, the fourth pole 22 can be disposed on the same layer as the third pole 21, or the fourth pole 22 can also be located in a different film layer from the third pole 21. On this basis, the fourth pole 22 can be located on the side of the second insulating layer 52 facing away from the substrate 30, or can also be located on the side of the second insulating layer 52 facing the substrate 30. In some alternative embodiments, both the third pole 21 and the fourth pole 22 are located on the side of the second insulating layer 52 facing away from the substrate 30.

[0127] In some embodiments, at least part of the structure of the second control terminal 23 is located on the side of the second insulating layer 52 facing away from the substrate 30.

[0128] The second control terminal 23 can be completely located on the side of the second insulating layer 52 facing away from the substrate 30, that is, the second control terminal 23 can be completely located on the side of the second active structure 24 facing away from the substrate 30. Or the second control terminal 23 can also be only partially located on the side of the second insulating layer 52 facing away from the substrate 30, that is, part of the second control terminal 23 is located on the side of the second active structure 24 facing away from the substrate 30, and part is located on the side of the second active structure 24 facing the substrate 30.

[0129] In the embodiments of the present application, in addition to achieving an insulating interval between the third pole 21 and the second active structure 24, the second insulating layer 52 can also achieve an insulating interval between the second control terminal 23 and the second active structure 24, so as to further meet the operating requirements of the second type of transistor 20. Among them, at least part of the structure of the second control terminal 23 can be disposed in contact with the second insulating layer 52, or there may also be other film layer structures between at least part of the structure of the second control terminal 23 located on the side of the second insulating layer 52 facing away from the substrate 30 and the second insulating layer 52.

[0130] In some embodiments, such as Figure 1As shown, the array substrate further includes a second conductor layer 42 disposed on a side of the second insulating layer 52 facing away from the substrate 30. The second conductor layer 42 includes a first control terminal 13 and a third pole 21.

[0131] The second conductor layer 42 is a film layer located on a side of the second insulating layer 52 facing away from the substrate 30 and including a conductive material. Wherein, the second conductor layer 42 may be disposed in contact with the second insulating layer 52, or there may be other film layers between the second conductor layer 42 and the second insulating layer 52, and the embodiments of the present application do not limit this.

[0132] In the embodiments of the present application, both the first control terminal 13 and the third pole 21 are located within the second conductor layer 42, that is, the first control terminal 13 and the third pole 21 are disposed on the same layer, both are made of the same material, and are formed together in the same process. In this case, the first active structure 14 in the first type of transistor 10 and the second active structure 24 in the second type of transistor 20 can be formed together in the same process, and the first control terminal 13 in the first type of transistor 10 and the third pole 21 in the second type of transistor 20 can also be formed together in the same process, which helps to further simplify the manufacturing process, reduce the manufacturing difficulty and the manufacturing cost.

[0133] Regarding the positional relationship of the fourth pole 22 with respect to the second conductor layer 42, the embodiments of the present application do not limit this. Optionally, the second conductor layer 42 includes the fourth pole 22, that is, the third pole 21, the fourth pole 22, and the first control terminal 13 are all made of the same material and are formed together in the same process.

[0134] In some embodiments, as Figure 2 shown, the array substrate further includes a third conductor layer 43 disposed between the second conductor layer 42 and the second insulating layer 52, and a third insulating layer 53 located between the third conductor layer 43 and the second conductor layer 42. At least a part of the second control terminal 23 is located within the third conductor layer 43.

[0135] The third conductor layer 43 is a film layer located between the second conductor layer 42 and the second insulating layer 52 and including a conductive material. The third insulating layer 53 is a film layer located between the second conductor layer 42 and the third conductor layer 43 and including an insulating material. The third insulating layer 53 can achieve an insulating interval between the second conductor layer 42 and the third conductor layer 43.

[0136] Further, at least a part of the second control terminal 23 is located within the third conductor layer 43. Wherein, the second control terminal 23 may be completely located within the third conductor layer 43, or the second control terminal 23 may be partially located within the third conductor layer 43 and partially located on a side of the second active structure 24 facing the substrate 30.

[0137] In some embodiments, please refer to Figure 3, the array substrate further includes a second conductor layer 42 disposed on a side of the second insulating layer 52 away from the substrate 30. The second conductor layer 42 includes at least a part of the structure of the second control terminal 23 and the first control terminal 13.

[0138] The first control terminal 13 is completely located within the second conductor layer 42, and the second control terminal 23 may be completely located within the second conductor layer 42, or only a part of the second control terminal 23 may be located within the second conductor layer 42. The embodiments of the present application do not limit this. Further, at least a part of the structure of the second control terminal 23 located within the second conductor layer 42 may be made of the same material as the first control terminal 13, and the two may be formed together in the same process, which helps to further simplify the manufacturing process and reduce the manufacturing difficulty and preparation cost.

[0139] In addition, considering that the first control terminal 13 and the second control terminal 23 may be connected to the same type of signal line. For example, the first control terminal 13 and the second control terminal 23 may both be connected to one of a scan line, a light emission control signal line, and a reset signal line. Therefore, setting at least a part of the second control terminal 23 on the same layer as the first control terminal 13 also helps to simultaneously reduce the distances between the first control terminal 13 and the second control terminal 23 and the corresponding signal lines, thereby reducing the difficulty of signal transmission, reducing the voltage drop, and improving the use reliability of the subsequent formed display panel.

[0140] In some embodiments, please refer to Figure 4 , the second conductor layer 42 includes all the structures of the second control terminal 23, and the orthographic projection of the second control terminal 23 on the substrate 30 overlaps with the orthographic projection of the second active structure 24 on the substrate 30. In this case, the second control terminal 23 is completely located within the second conductor layer 42 and is formed together with the first control terminal 13 in the same process, which is beneficial to simplifying the manufacturing process and reducing the manufacturing difficulty.

[0141] Or in some embodiments, as Figure 3 shown, the second control terminal 23 includes a first part 231 on a side of the active layer 60 facing the substrate 30 and a second part 232 located within the second conductor layer 42. The orthographic projections of the first part 231 and the second part 232 on the substrate 30 both overlap with the orthographic projection of the second active structure 24 on the substrate 30. Among them, the second part 232 is made of the same material as the first control terminal 13 and is formed together in the same process, and the first part 231 may be made of the same material as the second part 232, or the first part 231 may be made of a different material from the second part 232. The embodiments of the present application do not limit this. Further, the performance of the second type of transistor 20 can be improved by adjusting at least one of the material composition and the positional relationship of the first part 231 and the second part 232 to meet the circuit requirements in different situations.

[0142] Further optionally, the second control terminal 23 includes a first portion 231 and a second portion 232. The first portion 231 is disposed on the same layer as the first pole 11, and the second portion 232 is located within the second conductor layer 42. In this case, the first portion 231 may be made of the same material as the first pole 11 and formed together in the same process, and the second portion 232 may be made of the same material as the first control terminal 13 and formed together in the same process, thereby further reducing the process complexity and improving the preparation efficiency.

[0143] In some embodiments, as Figure 4 shown, the array substrate further includes a first conductor layer 41. The first conductor layer 41 is located between the first insulating layer 51 and the substrate 30. The material of the first conductor layer 41 is a light-shielding material. The first conductor layer 41 includes a light-shielding conductor portion D and the first pole 11.

[0144] In the embodiments of the present application, since the conductive material in the first conductor layer 41 is a light-shielding conductive material, and the first conductor layer 41 is located on the side of the active layer 60 facing the substrate 30, the light-shielding conductor portion D in the first conductor layer 41 can absorb part of the reflected light, reducing the amount of reflected light propagating to the first active structure 14 or the second active structure 24, improving the operation reliability of at least one of the first type of transistor 10 and the second type of transistor 20, and thus contributing to improving the use reliability and display effect of the subsequent formed display panel.

[0145] And since both the light-shielding conductor portion D and the first pole 11 are located in the first conductor layer 41, they may be made of the same material and formed together in the same process, thereby helping to further simplify the process and reduce the process difficulty and preparation cost.

[0146] In some embodiments, the orthographic projection of the light-shielding conductor portion D on the substrate 30 overlaps with the orthographic projection of the second active structure 24 on the substrate 30.

[0147] In the embodiments of the present application, the light-shielding conductor portion D in the first conductor layer 41 is used to block or absorb the reflected light to reduce the amount of reflected light propagating to the second active structure 24, thereby reducing the influence of the reflected light on the carrier movement at the second active structure 24 and improving the operation reliability of the second type of transistor 20. Similarly, in some embodiments, the orthographic projection of the light-shielding conductor portion D on the substrate 30 may also overlap with the orthographic projection of the first active structure 14 on the substrate 30.

[0148] In some embodiments, the light-shielding conductor portion D is insulated from the first pole 11.

[0149] As can be seen from the foregoing, the light-shielding conductor portion D can be used to absorb or block the reflected light reflected to the second active structure 24 or the first active structure 14, so as to improve the reliability of the carrier movement at the first active structure 14 or the second active structure 24. However, the light-shielding conductor portion D is not used to control the on / off state of the second active structure 24 or the first active structure 14. In other words, the light-shielding conductor portion D is not used to form the first type of transistor 10 or the second type of transistor 20.

[0150] On this basis, in the embodiment of the present application, the light-shielding conductor portion D is disposed on the same layer as the first electrode 11 and insulated, so as to simplify the manufacturing process while reducing the influence of the light-shielding conductor portion D on the operation process of the first type of transistor 10 and improving the operation reliability of the first type of transistor 10.

[0151] It should be noted that, according to different actual needs, a specific voltage signal may be transmitted in the light-shielding conductor portion D, or no voltage signal may be transmitted in the light-shielding conductor portion D. The embodiment of the present application does not limit this. Optionally, the light-shielding conductor portion D transmits a constant voltage signal. In this way, the light-shielding conductor portion D can reduce the capacitance formed between the charges existing in the substrate 30 and the second active structure 24 in the second type of transistor 20, reduce the risk of leakage of the second type of transistor 20, and thereby improve the operation reliability of the second type of transistor 20.

[0152] In some embodiments, please refer to Figure 1 and Figure 5 , the array substrate includes a plurality of pixel circuits D1. The pixel circuit D1 includes a first transistor T3 and a storage capacitor C. The storage capacitor C includes a first electrode plate. The first transistor T3 is the first type of transistor 10, and the first control terminal 13 of the first transistor T3 is electrically connected to the first electrode plate.

[0153] The pixel circuit D1 is a circuit structure for driving and controlling whether the light-emitting structure emits light. The pixel circuit D1 can have various forms. For example, the pixel circuit D1 can be a 7T1C circuit, an 8T1C circuit, or other circuits, etc. The present application does not make a special limitation on this.

[0154] The figure shows the case when the pixel circuit D1 is a 7T1C circuit. Specifically, the pixel circuit D1 includes a first transistor T3. The first transistor T3 is a driving transistor, and the first control terminal 13 of the first transistor T3 is electrically connected to the first electrode plate of the storage capacitor. On this basis, by setting the first transistor T3 as the first type of transistor 10, the first transistor T3 can have a high on-state current to meet the high-brightness requirement, which helps to improve the display effect of the subsequent formed display panel.

[0155] In some embodiments, please refer to Figure 1 , Figure 5 andFigure 6 The array substrate includes a gate driving circuit D2, and the gate driving circuit D2 includes a second transistor (not shown in the figure). The second transistor is a second type transistor 20, and a third pole 21 of the second transistor is electrically connected to a first control terminal 13 of the first transistor. Further optionally, the array substrate includes a first region A1 and a second region A2 disposed around a peripheral side of the first region A1. The pixel circuit D1 is provided in the first region A1, and the gate driving circuit D2 is provided in the second region A2.

[0156] The array substrate has a first region A1 and a second region A2. The first region A1 corresponds to a region for realizing light-emitting display in a display panel to be formed subsequently, and the second region A2 corresponds to a border region in the display panel to be formed subsequently. The pixel circuit D1 is correspondingly disposed in the first region A1, and the gate driving circuit D2 is disposed in the second region A2. Among them, the gate driving circuit D2 is a circuit for providing a scanning signal in the array substrate.

[0157] For the specific structural composition manner of the gate driving circuit D2, the embodiments of the present application do not make any limitations. Among them, the second transistor is a transistor for outputting a scanning signal in the gate driving circuit D2. Specifically, the third pole 21 of the second transistor may be electrically connected to a scanning signal line, and the scanning signal line is electrically connected to one of transistors T2, T4, T5, and T6 in the pixel circuit D1, and transmits a scanning signal scan to the transistor and a control terminal of the transistor. On this basis, by setting the second transistor as the second type transistor 20, the requirement for relatively high threshold stability corresponding to the second transistor can be met, and the use reliability of the display panel to be formed subsequently can be improved.

[0158] In a second aspect, please refer to Figure 7 The embodiments of the present application provide a display device, and the display device includes an array substrate in any of the foregoing embodiments. Among them, the display device may include components such as a display panel and a middle frame. Further, the display device may also include optical elements such as an infrared sensor.

[0159] It should be noted that the display device in the embodiments of the present application may be various types of display devices. For example, it may be a liquid crystal display device including a liquid crystal layer, or it may be an organic light-emitting display device including an organic light-emitting material, or it may be an inorganic light-emitting display device including an inorganic light-emitting material.

[0160] In a third aspect, please refer to Figure 1 、 Figure 8 and FIG. 9, the embodiments of the present application provide a method for manufacturing an array substrate, and the manufacturing method includes:

[0161] S100: Form a first insulating material layer on one side of a substrate.

[0162] See also Figure 9a In step S100, the first insulating material layer 51' is a functional film layer including insulating material and used to subsequently form the first insulating layer 51. The first insulating material layer 51' may be a whole surface structure. Optionally, the first insulating material layer 51' may be formed by chemical vapor deposition in this step.

[0163] S110: patterning the first insulating material layer.

[0164] See also Figure 9b In step S110, a first hole H is formed by patterning to obtain a first insulating layer 51. Optionally, the first hole H may be formed by an etching process in this step.

[0165] S120: forming an active material layer 60' on a side of the first insulating layer facing away from the substrate.

[0166] See also Figure 9c In step S120, the active material layer 60' is a functional film layer including semiconductor material and used for subsequently forming the active layer 60. The active material layer 60' may be a whole surface structure. Optionally, the active material layer 60' may be formed by physical vapor deposition in this step.

[0167] S130: patterning the active material layer.

[0168] See also Figure 9d In step S130, a first active structure 14 and a second active structure 24 are formed by patterning to obtain an active layer 60, wherein the first active structure 14 is at least partially located in the first hole H and is disposed in contact with the sidewall of the first hole H. Optionally, in this step, the first active structure 14 and the second active structure 24 may be formed by exposure and development.

[0169] In the embodiment of the present application, the first active structure 14 and the second active structure 24 are respectively used to form two different types of thin film transistors, namely the first type transistor 10 and the second type transistor 20. On this basis, by adjusting the positions of the two transistors, the first active structure 14 and the second active structure 24 can be formed together using the same material and through the same process. This can reduce the process, reduce the process complexity and reduce the cost, and has strong practicality.

[0170] In some embodiments, see Figure 10 As shown in FIG11 , before step S100, the method further includes:

[0171] S140: forming a first conductor material layer on one side of the substrate.

[0172] See also Figure 11aIn step S140, the first conductor material layer 41' is a functional film layer including a conductor material and used to subsequently form the first conductor layer 41. The first conductor material layer 41' may be a whole surface structure. Optionally, in this step, the first conductor material layer 41' may be formed by physical vapor deposition.

[0173] S150: patterning the first conductor material layer.

[0174] See also Figure 11b In step S150, the first electrode 11 and the second control terminal 23 are formed by patterning to obtain the first conductor layer 41, and the orthographic projection of the first electrode 11 on the substrate 30 overlaps with the orthographic projection of the first hole H on the substrate 30. Optionally, in this step, the first electrode 11 and the second control terminal 23 can be formed by dry etching.

[0175] In an embodiment of the present application, for the two types of transistors in the array substrate, in addition to setting the first active structure 14 and the second active structure 24 in the two transistors to include the same material and be formed together in the same process, the first electrode 11 and the second control terminal 23 in the two transistors are also set to include the same material and be formed together in the same process, so as to further simplify the preparation process of the array substrate and improve the preparation efficiency.

[0176] In some embodiments, see Figure 12 As shown in FIG13 , after step S130, the method further includes:

[0177] S160: forming a second insulating material layer on a side of the active layer facing away from the substrate.

[0178] See also Figure 13a In step S160, the second insulating material layer 52' ​​is a functional film layer including insulating material and used to subsequently form the second insulating layer 52. The second insulating material layer 52' ​​may be a whole surface structure. Optionally, the second insulating material layer 52' ​​may be formed by chemical vapor deposition in this step.

[0179] S170: patterning the second insulating material layer.

[0180] See also Figure 13b In step S170, the second hole 25 and the third hole 26 are formed by patterning to obtain the second insulating layer 52, and the orthographic projections of the second hole 25 and the third hole 26 on the substrate 30 are located at the orthographic projections of the second active structure 24 on the substrate 30. The second hole 25 and the third hole 26 are via structures for connecting the source and drain electrodes of the horizontal channel transistor with the second active structure 24. Optionally, the second hole 25 and the third hole 26 can be formed by etching in this step.

[0181] In the embodiment of the present application, the insulating film layer for blocking the first control terminal and the first active structure in the vertical channel transistor and the insulating film layer for blocking the second control terminal and the third electrode in the horizontal channel transistor are formed in the same process, so as to further simplify the manufacturing process of the array substrate and improve the manufacturing efficiency.

[0182] In some embodiments, referring to Figure 14 and FIG. 15, after step S170, the following steps are further included:

[0183] S180: Form a second conductor material layer on the side of the second insulating layer facing away from the substrate.

[0184] Referring to Figure 15a , in step S180, the second conductor material layer 42' is a functional film layer including a conductor material and used for subsequently forming the second conductor layer 42, and the second conductor material layer 42' can have a full-surface structure. Optionally, the second conductor material layer 42' can be formed by physical vapor deposition in this step.

[0185] S190: Pattern the second conductor material layer.

[0186] Referring to Figure 15b , in step S190, the first control terminal 13, the third electrode 21, and the fourth electrode 22 are formed by patterning to obtain the second conductor layer 42. The orthographic projection of the first control terminal 13 on the substrate 30 overlaps with the orthographic projection of the first hole H on the substrate 30. The third electrode 21 and the fourth electrode 22 are respectively connected to the second active structure 24 through the second hole 25 and the third hole 26. Optionally, the first control terminal 13, the third electrode 21, and the fourth electrode 22 can be formed by dry etching in this step.

[0187] In the embodiment of the present application, for the two types of transistors in the array substrate, in addition to setting the first active structure 14 and the second active structure 24 in the two transistors to include the same material and be formed in the same process, the first control terminal 13 in the two transistors is also set such that the third electrode 21 and the fourth electrode 22 include the same material and are formed in the same process, so as to further simplify the manufacturing process of the array substrate and improve the manufacturing efficiency.

[0188] Although the embodiments disclosed in the present application are as above, the content described is only an embodiment adopted for the convenience of understanding the present application and is not intended to limit the present invention. Any person skilled in the art within the technical field to which the present application pertains can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present application. However, the protection scope of the present application shall still be subject to the scope defined by the appended claims.

[0189] As described above, this is only the specific implementation manner of the present application. Those skilled in the art can clearly understand that for the sake of convenience and brevity of description, the replacement of other connection manners described above, etc., can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein. It should be understood that the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of various equivalent modifications or replacements, and these modifications or replacements should all be covered within the protection scope of the present application.

Claims

1. An array substrate, characterized in that: It includes a first type transistor and a second type transistor, the first type transistor is a vertical channel transistor, the second type transistor is a horizontal channel transistor, the first type transistor includes a first active structure, the second type transistor includes a second active structure, and the first active structure and the second active structure are arranged in the same layer.

2. The array substrate according to claim 1, characterized in that: The first type transistor includes a first electrode, a second electrode, and a first control terminal for controlling the first electrode and the second electrode to be turned on; the second type transistor includes a third electrode, a fourth electrode, and a second control terminal for controlling the third electrode and the fourth electrode to be turned on; the array substrate further includes: substrate; A first insulating layer, disposed on one side of the substrate, wherein the first insulating layer comprises a first hole; an active layer, disposed on a side of the first insulating layer away from the substrate, the active layer comprising the first active structure and the second active structure, the first active structure being at least partially located in the first hole and being disposed in contact with a sidewall of the first hole; Preferably, the first active structure includes a first channel structure, the second active structure includes a second channel structure, and the first channel structure and the second channel structure are arranged in the same layer; Preferably, the array substrate further comprises a first conductor layer, the first conductor layer is located between the first insulating layer and the substrate, and the first conductor layer comprises the first electrode; The orthographic projection of the first pole on the substrate is overlapped with the orthographic projection of the first hole on the substrate.

3. The array substrate according to claim 2, characterized in that: The first electrode is located on a side of the first insulating layer facing the substrate, and at least a part of the structure of the second control end is arranged in the same layer as the first electrode; Preferably, all structures in the second control end are arranged in the same layer as the first pole, and the orthographic projection of the second control end on the substrate overlaps with the orthographic projection of the second active structure on the substrate; or, The second control end comprises a first portion disposed in the same layer as the first electrode, and a second portion located on a side of the active layer away from the substrate, wherein the orthographic projections of the first portion and the second portion on the substrate overlap with the orthographic projection of the second active structure on the substrate; Preferably, the second electrode is disposed between the first insulating layer and the first active structure, and is disposed around the outer circumference of the first hole; Preferably, the active layer includes an oxide semiconductor.

4. The array substrate according to claim 2, characterized in that: It also includes a second insulating layer disposed on a side of the active layer away from the substrate, wherein the second insulating layer covers the first active structure and the second active structure; Preferably, the first control end is located on a side of the second insulating layer away from the substrate; Preferably, the third electrode is located on a side of the second insulating layer facing away from the substrate; Preferably, the third electrode and the fourth electrode are both located on a side of the second insulating layer away from the substrate; Preferably, at least part of the structure in the second control end is located on a side of the second insulating layer away from the substrate; Preferably, the array substrate further comprises a second conductor layer disposed on a side of the second insulating layer away from the substrate, and the second conductor layer comprises the first control terminal and the third electrode; Preferably, the second conductor layer includes the fourth pole; Preferably, the array substrate further includes a third conductor layer arranged between the second conductor layer and the second insulating layer, and a third insulating layer located between the third conductor layer and the second conductor layer, and the second control end is at least partially located in the third conductor layer.

5. The array substrate according to claim 4, characterized in that: It also includes a second conductor layer disposed on a side of the second insulating layer away from the substrate, the second conductor layer including at least a partial structure of the second control end and the first control end; Preferably, the second conductor layer includes all structures in the second control terminal, and the orthographic projection of the second control terminal on the substrate overlaps with the orthographic projection of the second active structure on the substrate; or, The second control end includes a first portion located on a side of the active layer facing the substrate, and a second portion located in the second conductor layer, and the orthographic projections of the first portion and the second portion on the substrate overlap with the orthographic projection of the second active structure on the substrate; Preferably, the second control end includes the first part and the second part, and the first part is arranged in the same layer as the first terminal.

6. The array substrate according to claim 2, characterized in that: The array substrate further includes a first conductor layer, the first conductor layer is located between the first insulating layer and the substrate, the material of the first conductor layer is a light shielding material, and the first conductor layer includes a light shielding conductor portion and the first electrode; Preferably, the orthographic projection of the light-shielding conductor portion on the substrate overlaps with the orthographic projection of the second active structure on the substrate; Preferably, the light-shielding conductor portion is insulated from the first pole; Preferably, the light-shielding conductor portion transmits a constant voltage signal.

7. The array substrate according to claim 2, characterized in that: The array substrate includes a plurality of pixel circuits, the pixel circuit includes a first transistor and a storage capacitor, and the storage capacitor includes a first electrode plate; The first transistor is a transistor of the first type, and the first control terminal of the first transistor is electrically connected to the first electrode plate; Preferably, the array substrate further comprises a gate driving circuit, and the gate driving circuit comprises a second transistor; The second transistor is the second type transistor, and the third electrode of the second transistor is electrically connected to the scan signal line; Preferably, the array substrate comprises a first area and a second area arranged around the first area, the pixel circuit is arranged in the first area, and the gate driving circuit is arranged in the second area.

8. A display device, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 7.

9. A method for preparing an array substrate, characterized in that: The preparation method comprises: forming a first insulating material layer on one side of the substrate; Patterning the first insulating material layer to form a first hole to obtain a first insulating layer; forming an active material layer on a side of the first insulating layer facing away from the substrate; The active material layer is patterned to form a first active structure and a second active structure to obtain an active layer, wherein the first active structure is at least partially located in the first hole and is disposed in contact with a side wall of the first hole.

10. The preparation method according to claim 9, characterized in that: Before the step of forming a first insulating material layer on one side of the substrate, the method further includes: forming a first conductor material layer on one side of the substrate; Patterning the first conductor material layer to form a first electrode and a second control terminal to obtain a first conductor layer, wherein the orthographic projection of the first electrode on the substrate overlaps with the orthographic projection of the first hole on the substrate; Preferably, after the step of patterning the active material layer, the method further comprises: forming a second insulating material layer on a side of the active layer away from the substrate, the second insulating material layer; Patterning the second insulating material layer to form a second hole and a third hole to obtain a second insulating layer, wherein the orthographic projections of the second hole and the third hole on the substrate are located at the orthographic projection of the second active structure on the substrate; Preferably, after the step of patterning the second insulating material layer, the method further comprises: forming a second conductor material layer on a side of the second insulating layer facing away from the substrate; The second conductor material layer is patterned to form a first control terminal, a third pole and a fourth pole to obtain a second conductor layer, wherein the first control terminal is arranged so as to overlap the orthographic projection of the first hole on the substrate, and the third pole and the fourth pole are connected to the second active structure through the second hole and the third hole respectively.

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