A planar avalanche photodiode with cascaded noise reduction and method of fabrication

Abstract

The present application relates to the field of infrared photoelectric devices, and particularly to a cascade noise reduction planar avalanche photodiode, which comprises a cascade multiplication region between a substrate and a cap layer. A PN junction is formed in the cascade multiplication region, and the PN junction is a planar PN junction. The present application also comprises a preparation method of the cascade noise reduction planar avalanche photodiode. The present application improves and innovates the linear avalanche photodiode structure, introduces a multiplication region and a cascade gain stage, and through connecting multiple gain stages in series, each stage can amplify the signal once to maximize electron-induced collision ionization and minimize hole ionization. By optimizing the thickness and doping concentration of each sub-layer in each gain stage, the additional multiplication noise is reduced and the dark current is reduced, so that the device gain is improved and the device noise is reduced. The preparation method of the present application utilizes a planar junction process, utilizes two diffusion processes to form a P-type region to realize a planar junction, and reduces the dark current of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of infrared photoelectric devices, in particular to a planar avalanche photodiode with cascade noise reduction and a preparation method. BACKGROUND

[0002] Since near-infrared light is generally safer for the human eye than visible light, and InGaAs linear avalanche photodiodes (APD) can respond to short-wavelength infrared light of 950 to 1700 nm, they are a kind of high-sensitivity photoelectric detector, widely used in optical fiber communication, laser ranging, photon counting, laser radar and other fields. Its main advantages include high gain, low noise, fast response and linear output characteristics. Since it works near the breakdown voltage, the excess noise and dark current are large, which limits its development. For mesa-type avalanche photodiodes, the passivation of the mesa and the leakage generated by etching can cause excessive dark current, and the large dark current can cause saturation of the dark signal during coupling with the circuit. SUMMARY

[0003] The purpose of the present application is to provide a planar avalanche photodiode with cascade noise reduction and a preparation method, which can improve the gain of linear avalanche photodiodes and reduce their noise.

[0004] In order to achieve the above-mentioned purpose, the technical solution adopted by the present application is to provide a planar avalanche photodiode with cascade noise reduction, characterized in that it comprises a substrate, a cascade multiplication region and a cap layer; the bottom layer is the substrate, and the top layer is the cap layer; the cascade multiplication region is located between the substrate and the cap layer and is generated using a molecular beam epitaxy system; a PN junction is formed in the cap layer; the PN junction is a planar PN junction.

[0005] Further, from the bottom layer of the substrate upwards, it successively comprises a buffer layer, the cascade multiplication region, a barrier layer, a charge layer and a light absorption layer, and finally the cap layer at the top layer.

[0006] Further, the cascade multiplication region comprises a plurality of multiplication layers; a plurality of the multiplication layers are stacked in a periodic manner to form a cascade structure.

[0007] Further, the number of multiplication layers is 2 to 10.

[0008] Further, in the multiplication layer, from bottom to top, it successively comprises a first multiplication barrier layer, a multiplication potential well layer, a second multiplication barrier layer and a multiplication sub-charge layer.

[0009] Further, the materials of the first multiplication barrier layer and the second multiplication barrier layer are In 0.52 Al 0.48AS, thickness of 0.02 microns, doping concentration of N type 5*10 14 cm -3 -3; the material of the multiplication potential well layer is In 0.52 Al 0.24 As, thickness of 0.01 microns, doping concentration of N type 5*10 14 cm -3 -3; the material of the multiplication sub-charge layer is In 0.52 Al 0.48 As, thickness of 0.02 microns, doping concentration of N type 1*10 17 cm -3 .

[0010] Further, the substrate material is InP, doping concentration of N type 1*10 18 cm -3 -3; the buffer layer material is InP, thickness of 200 nanometers, doping concentration of N type 5*10 17 cm -3 -3; the barrier layer material is In 0.52 Al 0.48 As, thickness of 0.05 microns, doping concentration of N type 5*10 14 cm -3 -3; the charge layer material is In 0.52 Al 0.48 As, thickness of 130 nanometers, doping concentration of N type 2.3*10 17 cm -3 -3; the light absorption layer material is In 0.53 Ga 0.47 As, thickness of 1.5 microns, doping concentration of N type 5*10 14 cm -3 -3; the cap layer material is In 0.52 Al 0.48 As, thickness of 2 microns, doping concentration of N type 5*10 14 cm -3 .

[0011] The application further discloses a preparation method of the above-mentioned cascade noise reduction planar avalanche photodiode, and the method comprises the following steps:

[0012] Step S101: obtaining a base material; a bottom layer of the base material is the substrate, and a top layer of the base material is the cap layer; between the substrate and the cap layer, a molecular beam epitaxy system is used to generate the cascade multiplication region;

[0013] Step S102: forming a first diffusion hole and completing first diffusion; the first diffusion depth is equivalent to the cap layer thickness;

[0014] Step S103, forming second diffusion holes and completing second diffusion; the second diffusion is shallower than the first diffusion;

[0015] Step S104, heat-activating the base material;

[0016] Step S105, opening N slots on the surface and depositing a passivation film;

[0017] Step S106, opening electrode holes on the surface of the base material and growing electrodes; the electrode holes are located directly above the diffusion region;

[0018] Step S107, heat-annealing the whole base material;

[0019] Step S108, growing thick electrodes on the electrodes.

[0020] Further, the second diffusion holes and the first diffusion holes constitute concentric circles, and the diameter of the second diffusion holes is smaller than that of the first diffusion holes.

[0021] Further, in steps S104 and S107, the diffusion is zinc atom closed tube diffusion, comprising steps of:

[0022] Step S201, depositing a silicon nitride mask on the surface of the base material;

[0023] Step S202, covering a layer of photoresist on the silicon nitride mask;

[0024] Step S203, transferring the mask pattern of the first diffusion holes or the second diffusion holes to the silicon nitride mask by photolithography positioning;

[0025] Step S204, etching the silicon nitride mask to form the first diffusion holes or the second diffusion holes;

[0026] Step S205, putting zinc powder into a glass tube and heating by a diffusion furnace, so that zinc atoms diffuse downward into the base material through the first diffusion holes or the second diffusion holes.

[0027] In view of the above technical features, the cascade noise reduction planar avalanche photodiode and the preparation method have the following advantages:

[0028] 1. The cascade noise reduction planar avalanche photodiode improves and innovates the structure of linear avalanche photodiode, introduces multiplication region and cascade gain stage, and maximizes electron-induced collision ionization and minimizes hole ionization by connecting multiple gain stages in series.

[0029] 2. The preparation method of the cascade noise reduction planar avalanche photodiode utilizes planar junction technology to form a P-type region by twice diffusion to realize a planar junction and reduce device dark current. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a structure diagram of a preferred embodiment of the cascade noise reduction planar avalanche photodiode of the present application;

[0031] Figure 2 is a method flow chart of a preferred embodiment of the preparation method of the cascade noise reduction planar avalanche photodiode of the present application;

[0032] Figure 3 is a structure diagram of a non-cascade control avalanche photodiode corresponding to the preferred embodiment of the cascade noise reduction planar avalanche photodiode of the present application;

[0033] Figure 4 is a simulation result diagram of avalanche gain of the preferred embodiment of the cascade noise reduction planar avalanche photodiode of the present application and the non-cascade control avalanche photodiode;

[0034] Figure 5 is a simulation measurement result diagram of excess noise figure of the preferred embodiment of the cascade noise reduction planar avalanche photodiode of the present application and the non-cascade control avalanche photodiode.

[0035] In the figure: 1-substrate, 2-buffer layer, 3-cascade multiplication region, 4-barrier layer, 5-charge layer, 6-light absorption layer, 7-cap layer, 8-multiplication layer, 9-non-cascade charge layer;

[0036] 81-first multiplication barrier layer, 82-multiplication potential well layer, 82-second multiplication barrier layer, 84-multiplication sub-charge layer. DETAILED DESCRIPTION

[0037] The application will be further described below with reference to the specific embodiments. It should be understood that these embodiments are only used to explain the application and not used to limit the scope of the application. Furthermore, it should be understood that those skilled in the art can make various modifications or changes to the application after reading the content of the application, and these equivalent forms also fall within the scope of the appended claims.

[0038] Referring to Figure 1 , the application discloses a planar avalanche photodiode with a cascade noise reduction. As shown in the preferred embodiment, it comprises a plurality of semiconductor material layers, from the bottom substrate 1 upwards, a buffer layer 2, a cascade multiplication region 3, a barrier layer 4, a charge layer 5, a light absorption layer 6 and a cap layer 7 at the top. The PN junction constituting the diode is a planar junction, which is formed in the cascade multiplication region 3 by active doping downwards from the cap layer 7. In this embodiment, the material of the substrate 1 is InP, the doping concentration is N-type 1×10 18 cm -3 . The material of the buffer layer 2 is InP, the thickness is 200 nanometers, and the doping concentration is N-type 5×10 17 cm -3 . The material of the barrier layer 4 is In 0.52 Al 0.48 As, the thickness is 0.05 micrometers, and the doping concentration is N-type 5×10 14 cm -3 . The material of the charge layer 5 is In 0.52 Al 0.48 As, the thickness is 130 nanometers, and the doping concentration is N-type 2.3×10 17 cm -3 . The material of the light absorption layer 6 is In 0.53 Ga 0.47 As, the thickness is 1.5 micrometers, and the doping concentration is N-type 5×10 14 cm -3 . The material of the cap layer 7 is In 0.52 Al 0.48 As, the thickness is 2 micrometers, and the doping concentration is N-type 5×10 14 cm -3 .

[0039] The method uses the cascade multiplication region 3 to adjust the internal electric field, realizes the regulation of the carrier motion, and makes the carrier multiply at the specified position, thereby effectively reducing the edge breakdown and suppressing the dark current. In the cascade multiplication region 3, a plurality of multiplication layers 8 are contained. The internal structures of these multiplication layers 8 are the same, and they are repeatedly stacked in cycles, thereby constituting a cascade structure.

[0040] The cascade structure of the cascade multiplication region 3 is achieved by reducing the thickness of the multiplication layer 8 and changing the material structure design of the multiplication layer 8, so as to limit the area of carrier collision ionization and reduce the local collision ionization threshold and collision ionization rate, thereby achieving the purpose of increasing the gain and reducing the noise. A special electric field distribution is obtained by reasonably designing the composition, thickness and doping concentration of each multiplication sub-layer in the multiplication layer 8. The thickness of the high-field multiplication layer is specially designed to suppress the collision ionization caused by holes and locally increase the collision ionization caused by electrons, so as to achieve the single-pole carrier multiplication and reduce the noise. At the same time, by increasing the multiplication stages, the process is repeated, so as to obtain high gain while keeping low noise. The multiplication stages (i.e. the number) of the multiplication layer 8 are different in different implementations, and are generally 2 to 10. By adjusting the number of multiplication stages of the multiplication layer 8, the single-pole carrier multiplication process is repeated, so as to obtain high gain while keeping low noise. In the present embodiment, a three-stage cascade structure is adopted, i.e. three groups of multiplication layers 8 with the same structure are stacked together to form the cascade multiplication region 3.

[0041] Inside the multiplication layer 8, a plurality of multiplication sub-layers are included. By reasonably designing the composition and doping concentration of each multiplication sub-layer in the multiplication layer 8, the electric field distribution can be adjusted, and the thickness of the multiplication sub-layer can be adjusted to be comparable to the hole relaxation space length, so as to suppress the collision ionization caused by electrons and locally increase the collision ionization caused by holes, thereby achieving the single-pole carrier multiplication and reducing the noise. In the present embodiment, from the substrate 1 to the cap layer 7, there are in sequence a first multiplication blocking layer 81, a multiplication potential well layer 82, a second multiplication blocking layer 83 and a multiplication sub-charge layer 84. The parameters of the first multiplication blocking layer 81 and the second multiplication blocking layer 83 are consistent, and the material used is In 0.52 Al 0.48 AS with a thickness of 0.02 microns and an N-type doping concentration of 5x10 14 cm -3 . The material of the multiplication potential well layer 82 is In 0.52 Al 0.24 AS with a thickness of 0.01 microns and an N-type doping concentration of 5x10 14 cm -3 . The material of the multiplication sub-charge layer 84 is In 0.52 Al 0.48 AS with a thickness of 0.02 microns and an N-type doping concentration of 1x10 17 cm -3 .

[0042] The performance differences between the three-stage cascade noise reduction avalanche photodiode device and the non-cascade avalanche photodiode device are compared as follows. Please refer to Figure 3, as a control, the rest of the device structure parameters are exactly the same except for the cascade multiplication region 3, while in the corresponding three-stage cascade noise reduction avalanche photodiode, the non-cascade avalanche photodiode at this position corresponds to a non-cascade avalanche photodiode 0.52 Al 0.48 AS constitutes a non-cascade charge layer 9 with a thickness of 0.210 microns.

[0043] Please refer to Figure 4 , the obtained three-stage cascade noise reduction avalanche photodiode device and non-cascade avalanche photodiode device are respectively simulated for direct current dark current and photocurrent, and the gain coefficient of the device is obtained, and the actual measurement result is shown in Figure 4 . Figure 4 In the figure, the black solid line is the photocurrent and dark current curve of the three-stage cascade noise reduction avalanche photodiode, the gray dashed line is the photocurrent and dark current curve of the non-cascade avalanche photodiode, the black dot is the gain curve of the three-stage cascade noise reduction avalanche photodiode, and the gray diamond is the gain curve of the non-cascade avalanche photodiode. It can be seen that the gain of the three-stage cascade noise reduction avalanche photodiode device is about 220, while the gain of the non-cascade avalanche photodiode device is only about 100, and the gain is enhanced by about 2.2 times.

[0044] Please refer to Figure 5 , the measurement results of the excess noise coefficient are shown. In Figure 5 , the square solid point is the excess noise data of the three-stage cascade APD, and the circular solid point is the excess noise data of the non-cascade APD. The dashed line is the excess noise curve under different collision ionization coefficient ratios (k) calculated by theory. It can be seen that the excess noise coefficient of the three-stage cascade noise reduction avalanche photodiode is reduced to close to k=0.01, which is significantly lower than the excess noise of the non-cascade avalanche photodiode. From the results of Figure 4 and 5 , it is fully proved that the cascade noise reduction planar avalanche photodiode device structure of the present application is feasible in enhancing the gain of the avalanche detector and reducing the excess noise.

[0045] Please refer to Figure 2 , the present application also uses the preparation method of the above-mentioned cascade noise reduction planar avalanche photodiode. As shown in the figure, a preferred embodiment thereof comprises the following steps:

[0046] Step S1, obtaining a substrate material.

[0047] The bottom layer of the substrate material is an N-type substrate, and the top layer is a cap layer. From the substrate to the cap layer, the intermediate layers include, in order, a buffer layer, a cascade multiplication region, a barrier layer, a charge layer, and a light absorption layer. The cascade multiplication region adopts a three-stage cascade structure and includes three groups of stacked multiplication layers with the same structure. Each multiplication layer, from bottom to top, includes four multiplication sub-layers, in order, a first multiplication barrier layer, a multiplication potential well layer, a second multiplication barrier layer, and a multiplication sub-charge layer. The substrate material is obtained by growing on the substrate using a molecular beam epitaxy system.

[0048] Step S21: First depositing a mask.

[0049] A layer of silicon nitride mask is deposited on the surface of the substrate material, i.e., above the cap layer.

[0050] Step S22: First covering photoresist.

[0051] A layer of photoresist is covered on the silicon nitride mask.

[0052] Step S23: First lithography.

[0053] The first diffusion hole mask pattern is transferred to the silicon nitride mask by lithography positioning.

[0054] Step S24: First etching.

[0055] The first diffusion hole is etched on the silicon nitride mask to form a circular hole.

[0056] Step S25: First diffusion.

[0057] The first P diffusion is completed by using zinc atom closed tube diffusion technology. Specifically, zinc powder is placed in a glass tube, and the zinc atoms diffuse downward into the substrate material through the first diffusion hole by heating in a diffusion furnace. By controlling the diffusion time, the depth of the first diffusion is about the thickness of the cap layer.

[0058] Step S31: Second depositing a mask.

[0059] A layer of silicon nitride mask is deposited on the surface of the substrate material that has completed the first diffusion.

[0060] Step S32: Second covering photoresist.

[0061] A layer of photoresist is covered on the silicon nitride mask.

[0062] Step S33: Second lithography.

[0063] The first diffusion hole mask pattern is transferred to the silicon nitride mask by lithography positioning.

[0064] Step S34: Second etching.

[0065] The second diffusion hole is a circular hole, and the second diffusion hole is concentric with the first diffusion hole, and the diameter of the second diffusion hole is smaller than that of the first diffusion hole.

[0066] Step S35, second diffusion.

[0067] The second P diffusion is completed by using the zinc atom closed tube diffusion technology. Specifically, the zinc powder is placed in the glass tube, and the zinc atoms diffuse downward into the base material through the second diffusion hole by heating in the diffusion furnace.

[0068] The diffusion time is controlled to make the depth of the second diffusion shallower than that of the first diffusion.

[0069] The specific depth of the first diffusion and the second diffusion is determined by multiple single diffusion experiments.

[0070] Step S4, thermal activation.

[0071] The base material is thermally activated.

[0072] Step S5, surface slotting.

[0073] N slots are opened on the surface and a passivation film is deposited.

[0074] Step S6, growing P electrode.

[0075] The electrode hole is located directly above the P diffusion region.

[0076] Step S7, thermal annealing.

[0077] The entire base material is thermally annealed.

[0078] Step S8, growing thickened electrode.

[0079] The thickened electrode is continuously grown on the P electrode.

[0080] The above only describes the preferred embodiments of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent flow transformation using the content of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A cascaded noise-reducing planar avalanche photodiode, characterized in that, It comprises a substrate, a cascaded multiplication region, and a cap layer; the bottom layer is the substrate, and the top layer is the cap layer; the cascaded multiplication region is located between the substrate and the cap layer and is generated using a molecular beam epitaxy system; a PN junction is formed in the cap layer; the PN junction is a planar PN junction; The cascaded multiplication region contains multiple multiplication layers; Within the multiplication layer, from bottom to top, it sequentially comprises a first multiplication blocking layer, a multiplication potential well layer, a second multiplication blocking layer, and a multiplier charge layer; The materials of the first and second multiplication barrier layers are In. 0.52 Al 0.48 AS, with a thickness of 0.02 micrometers and a doping concentration of 5 × 10⁻⁶ N-type. 14 cm -3 The material of the multiplication potential well layer is In. 0.52 Al 0.24 AS, with a thickness of 0.01 micrometers and a doping concentration of 5 × 10⁻⁶ N-type. 14 cm -3 The material of the multiplier charge layer is In. 0.52 Al 0.48 AS, with a thickness of 0.02 micrometers and a doping concentration of 1×10⁻⁶ N-type. 17 cm -3 .

2. The cascaded noise-reducing planar avalanche photodiode as described in claim 1, characterized in that, Starting from the bottom substrate and moving upwards, the structure sequentially includes a buffer layer, the cascaded multiplication region, a blocking layer, a charge layer, and a light-absorbing layer, with the top cap layer at the very end.

3. The cascaded noise-reducing planar avalanche photodiode as described in claim 1, characterized in that, Multiple multiplication layers are stacked repeatedly in a periodic manner to form a cascaded structure.

4. The cascaded noise-reducing planar avalanche photodiode as described in claim 3, characterized in that, The number of multiplication layers is 2 to 10.

5. The cascaded noise-reducing planar avalanche photodiode as described in claim 2, characterized in that, The substrate material is InP, with a doping concentration of 1×10⁻⁶ N-type. 18 cm -3 The buffer layer material is InP, with a thickness of 200 nanometers and a doping concentration of 5 × 10⁻⁶ N-type. 17 cm -3 The barrier layer material is In. 0.52 Al 0.48 As, with a thickness of 0.05 micrometers and a doping concentration of 5 × 10⁻⁶ N-type. 14 cm -3 The charge layer material is In. 0.52 Al 0.48 As, with a thickness of 130 nanometers and a doping concentration of 2.3 × 10⁻⁶ N-type. 17 cm -3 The light-absorbing layer material is In. 0.53 Ga 0.47 As, with a thickness of 1.5 micrometers and a doping concentration of 5 × 10⁻⁶ N-type. 14 cm -3 The capping material is In. 0.52 Al 0.48 As, with a thickness of 2 micrometers and a doping concentration of 5 × 10⁻⁶ N-type. 14 cm -3 .

6. A method for fabricating a cascaded noise-reducing planar avalanche photodiode as described in claim 1, characterized in that, Includes the following steps: Step S101: Obtain a substrate material; the bottom layer of the substrate material is the substrate, and the top layer is the cap layer; between the substrate and the cap layer, the cascade multiplication region is generated using a molecular beam epitaxy system; Step S102: Form the first diffusion hole and complete the first diffusion; the depth of the first diffusion is equivalent to the thickness of the cap layer; Step S103: A second diffusion hole is formed, and the second diffusion is completed; the depth of the second diffusion is shallower than that of the first diffusion. Step S104: Thermally activate the substrate material; Step S105: Open N-grooves on the surface and deposit a passivation film; Step S106: Open electrode holes and grow electrodes on the surface of the substrate material; the electrode holes are located directly above the diffusion region; Step S107: Perform overall thermal annealing on the substrate material; Step S108: A thickened electrode is grown on the electrode.

7. The method for fabricating a cascaded noise-reducing planar avalanche photodiode as described in claim 6, characterized in that, The second diffusion hole and the first diffusion hole form a concentric circle, and the diameter of the second diffusion hole is smaller than that of the first diffusion hole.

8. The method for fabricating a cascaded noise-reducing planar avalanche photodiode as described in claim 6, characterized in that, In steps S104 and S107, the diffusion is a closed-tube diffusion of zinc atoms, comprising the steps of: Step S201: Deposit a silicon nitride mask on the surface of the substrate material; Step S202: Cover the silicon nitride mask with a layer of photoresist; Step S203: Use photolithography to transfer the mask pattern of the first diffusion hole or the second diffusion hole onto the silicon nitride mask; Step S204: Etch the silicon nitride mask to form the first diffusion hole or the second diffusion hole; Step S205: Zinc powder is placed in a glass tube and heated in a diffusion furnace, so that zinc atoms diffuse downward into the substrate material through the first diffusion hole or the second diffusion hole.

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