Contact hole forming method and image sensor

Abstract

The invention discloses a contact hole forming method and an image sensor, and the method comprises the steps: forming a contact hole etching stop layer on a device structure of a logic region and a pixel region of the image sensor; filling a thickened interlayer dielectric layer on the contact hole etching stop layer, wherein the increased thickness is equal to the thickness of the protective layer; forming a first hard mask layer and a second hard mask layer on the interlayer dielectric layer; etching a contact hole in the logic region by taking the first hard mask layer as a mask, and only forming a mask pattern on the pixel region under the protection of the second hard mask layer; forming a sacrificial layer for protecting the logic region contact hole; etching a contact hole of a pixel region until the contact hole is above the protective layer; the protection layer below the pixel area contact hole is etched downwards continuously, and the interlayer dielectric layer with the same thickness is etched at the same time; and removing the sacrificial layer of the logic region and filling all the contact holes. The contact holes of the logic region and the pixel region can be etched separately, over etching of the substrate in the logic region due to height difference is avoided, and electrical stability can be maintained.

Description

Technical Field

[0001] The present invention relates to the field of manufacturing semiconductor devices, and in particular, to a method for forming contact holes and an image sensor. Background Art

[0002] As Figure 1 shown, a CIS device (CMOS IMAGE SENSOR) includes a logic area and a pixel area. In the traditional process, before forming contact holes, in order to reduce contact resistance, a layer of metal silicide 105 is formed in the logic area; meanwhile, a layer of Self-Aligned Barrier Oxide (abbreviated as SAB OX) is formed in the pixel area in advance as a protective layer 104 to prevent the pixel area from contacting metal, resulting in metal contamination, further causing electrical offset, an increase in dark current and white point defects of the image sensor, and a decrease in the imaging quality of the image sensor.

[0003] Since the pixel area has an additional layer of SAB OX compared to the logic area, it is easy to cause over-etching damage to the substrate 101 and difficult filling of the Inter Layer Dielectric (ILD) 102 during the etching process of the contact hole 106. Specifically: 1) The active area (AA) plane and the top of the gate in the logic area only have a contact hole etching stop layer 103 (abbreviated as CESL), while the AA plane and the top of the gate in the pixel area are both a stack of SAB OX and CESL. Therefore, a stack difference is formed between the logic area and the pixel area. During the contact hole etching process, it is easy to cause over-etching of the logic area substrate when etching SAB OX (as shown at the position of the dotted circle in Figure 1 ), which easily leads to abnormal metal silicide and unstable resistance value. 2) Because of the stack difference between the logic area and the pixel area, a thicker CESL is required to eliminate the etching load effect. However, the thickened CESL will increase the aspect ratio of the via filling in the interlayer dielectric layer ILD, thereby causing a High Aspect Ratio Process (HARP), resulting in holes 107 and gaps in the filling, and a decrease in isolation performance. Summary of the Invention

[0004] The main purpose of the present invention is to provide a method for forming contact holes and an image sensor, which can prevent over-etching damage to the device and stabilize the contact resistance when forming contact holes.

[0005] The technical solution adopted by the present invention is as follows: Provide a method for forming contact holes, including the following steps: On the device structures of the logic region and the pixel region of the prefabricated image sensor, a contact hole etching stop layer is formed, where the device structure of the pixel region has one more protective layer than that of the logic region; A thickened interlayer dielectric layer is filled on the contact hole etching stop layer, and the increased thickness is equal to the thickness of the protective layer; and a first hard mask layer is formed on the interlayer dielectric layer, and a second hard mask layer is further formed above the first hard mask layer in the pixel region; Using the first hard mask layer as a mask, contact holes are etched in the logic region, and only a mask pattern is formed on the pixel region under the protection of the second hard mask layer; An organic carbon layer is spin-coated on both the logic region and the pixel region to form a sacrificial layer for protecting the contact holes in the logic region; The organic carbon layer is etched to expose the mask pattern in the pixel region, and contact hole etching in the pixel region is carried out until above the protective layer; Continue to etch the protective layer under the contact holes in the pixel region downward, and at the same time etch and thin the interlayer dielectric layer by the same thickness; Remove the sacrificial layer in the logic region and fill all the contact holes.

[0006] According to the above technical solution, the formed contact hole etching stop layer is a thinned contact hole etching stop layer, and its thickness is less than the thickness of the protective layer.

[0007] According to the above technical solution, the thickness of the first hard mask layer is the same as the thickness of the contact hole etching stop layer.

[0008] According to the above technical solution, the specific process of forming the contact holes in the logic region is as follows: a photoresist layer and an anti-reflection coating are formed on the first hard mask layer in the logic region and the second hard mask layer in the pixel region; through exposure and development, a contact hole mask pattern for the logic region and the pixel region is formed; a first etching gas is selected to etch the first hard mask layer in the logic region; a second etching gas is selected to etch the second hard mask layer in the pixel region, and at the same time, a part of the interlayer dielectric layer in the logic region is etched; a third etching gas is selected to continue to etch the logic region downward to form contact holes, and at the same time, the first hard mask layer in the pixel region is etched to form a contact hole mask pattern for the pixel region; the photoresist layer and the anti-reflection coating are removed.

[0009] According to the above technical solution, when etching the organic carbon layer, no photomask is required, and it is directly etched through an etching gas, and the etching gas is oxygen or an oxygen-containing gas.

[0010] According to the above technical solution, the specific process of forming the second hard mask layer in the pixel region is as follows: a second hard mask layer is formed on the first hard mask layer; a photoresist layer is formed on the second hard mask layer; through a photomask, exposure and development are carried out on the photoresist layer to form a mask layer, where the photomask is the photomask used when preparing the protective layer; using the mask layer as a mask, the second hard mask layer is etched; the photoresist is removed.

[0011] Continuing with the above technical solution, the process of etching the contact holes in the pixel region is specifically as follows: Using the mask pattern of the pixel region as a mask, the interlayer dielectric layer is etched to initially form the pixel region contact holes, and at the same time, the second hard mask layer is etched; The contact hole etch stop layer below the pixel region contact holes is continuously etched, and at the same time, the first hard mask layer in the pixel region and the logic region is etched; The protective layer below the pixel region contact holes is continuously etched to form the final pixel region contact holes.

[0012] Continuing with the above technical solution, the first hard mask layer and the contact hole etch stop layer are made of the same material.

[0013] Continuing with the above technical solution, the second hard mask layer and the first hard mask layer are made of different materials.

[0014] Continuing with the above technical solution, the second hard mask layer and the interlayer dielectric layer are made of the same material.

[0015] The present invention also provides an image sensor, which prepares the contact holes in the pixel region and the logic region by using the contact hole formation method described in the above technical solution.

[0016] The beneficial effects of the present invention are as follows: By introducing different hard mask layers in the logic region and the pixel region, with only one hard mask layer prepared in the logic region and two hard mask layers prepared in the pixel region, unexpectedly, under the action of different hard mask layers, the contact holes in the logic region and the pixel region can be etched separately, and over-etching will not occur due to the height difference; After the contact holes in the logic region are etched, a sacrificial layer for protecting the contact holes in the logic region is formed by spin-coating an organic carbon layer, so that the contact holes in the logic region will not be affected at all when the contact holes in the pixel region are etched; And when forming the interlayer dielectric layer, its thickness is increased to be the same as the thickness of the protective layer in the pixel region, so as to serve as an etching compensation when etching the protective layer subsequently, canceling each other out, still keeping the thickness of the interlayer dielectric layer unchanged and still keeping the aspect ratio unchanged when filling the contact holes subsequently.

[0017] Furthermore, by thinning the contact hole etch stop layer, the aspect ratio during the subsequent filling of the interlayer dielectric layer can be reduced, avoiding the occurrence of holes and gaps during filling and thus preventing the isolation performance from deteriorating.

[0018] Furthermore, when etching the contact holes in the logic region, by selecting different etching gases for etching, only the mask pattern transfer of the contact holes in the pixel region is completed while forming the contact holes in the logic region, so that the contact holes in the logic region and the pixel region can be completed in different regions and at different times, avoiding the over-etching of the logic region substrate caused by the height difference in the traditional synchronous etching method.

[0019] Furthermore, when forming the second hard mask layer in the pixel region, the photomask used for preparing the protective layer is directly used without an additional photomask, saving costs.

[0020] Further, when etching the contact holes in the pixel region, different layers are etched in segments by different etching methods. Since the thicknesses of the first hard mask layer and the contact hole etching stop layer are the same, both of them can be etched away simultaneously during etching.

[0021] Of course, not necessarily all the advantages described above need to be achieved simultaneously for any product implementing the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0023] Figure 1 is a cross-sectional schematic view of a CIS device with contact holes in the related art; Figure 2 is a flowchart of a method for forming contact holes according to an embodiment of the present invention; Figure 3A is a cross-sectional schematic view of a device when forming a contact hole etching stop layer according to an embodiment of the present invention; Figure 3B is a cross-sectional schematic view of forming a first hard mask layer and a second hard mask layer according to an embodiment of the present invention; Figure 3C is a cross-sectional schematic view of forming a contact hole mask pattern according to an embodiment of the present invention; Figure 3D is a cross-sectional schematic view after etching the first hard mask layer according to an embodiment of the present invention; Figure 3E is a cross-sectional schematic view after etching away the second hard mask layer according to an embodiment of the present invention; Figure 3F is a cross-sectional schematic view of forming a contact hole in the logic region according to an embodiment of the present invention; Figure 3G is a cross-sectional schematic view after spin-coating organic carbon according to an embodiment of the present invention; Figure 3H is a cross-sectional schematic view of forming a sacrificial layer in the logic region according to an embodiment of the present invention; Figure 3I is a cross-sectional schematic view of preliminarily forming a contact hole in the pixel region according to an embodiment of the present invention; Figure 3J is a cross-sectional schematic view of continuously etching the etching stop layer under the contact hole in the pixel region according to an embodiment of the present invention; Figure 3K is a cross-sectional schematic view of etching the protective layer under the contact hole in the pixel region according to an embodiment of the present invention; Figure 3L is a cross-sectional schematic diagram of removing the sacrificial layer in the logic region to form the final pixel region contact hole according to an embodiment of the present invention; Figure 3M is a cross-sectional schematic diagram after filling the contact hole according to an embodiment of the present invention.

[0024] In the figure: 101, substrate; 102, interlayer dielectric layer; 103, contact hole etching stop layer; 104, protective layer; 105, metal silicide; 106, contact hole; 107, hole; 301, substrate; 302, gate oxide layer; 303, polysilicon gate; 304, contact layer; 305, protective layer; 306, contact hole etching stop layer; 307, interlayer dielectric layer; 308, first hard mask layer; 309, second hard mask layer; 310, photoresist layer; 311, logic region contact hole; 312, organic carbon layer; 313, pixel region contact hole. Detailed implementation manners

[0025] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0026] It should be noted that the diagrams provided in the embodiments of the present invention only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation. The types, quantities and proportions of the components in actual implementation may be arbitrarily changed, and the component layout type may also be more complex.

[0027] In the present invention, it should also be noted that when terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, when terms such as "first" and "second" appear, they are only used for descriptive and distinguishing purposes and cannot be understood as indicating or implying relative importance.

[0028] In addition, it should also be noted that the features of various embodiments of the present invention can be partially or wholly combined or integrated, and as can be understood by those skilled in the art, they can interact and operate in different ways. Each embodiment can be implemented independently of each other or in an associated relationship.

[0029] In order to overcome the problem that the height difference between the logic area and the image area of the CIS device due to different structures affects the etching of subsequent contact holes, the solution of the present invention mainly completes the etching of contact holes by dividing regions. During this process, different hard mask layers are introduced in the logic area and the pixel area, and corresponding etching gases are selected for etching in stages. When etching the contact holes in the pixel area, a sacrificial layer for protecting the contact holes in the logic area is formed, so that the etching of the contact holes in the pixel area will not affect the contact holes in the logic area at all, thus avoiding the over-etching problem caused by the height difference.

[0030] As Figure 2 shown, the method for forming contact holes in the embodiment of the present invention mainly includes the following steps: S1. On the device structures in the logic area and the pixel area of the pre-completed image sensor, a contact hole etching stop layer is formed, wherein the device structure in the pixel area has one more protective layer than that in the logic area; S2. A thickened interlayer dielectric layer is filled on the contact hole etching stop layer, and the increased thickness is equal to the thickness of the protective layer; and a first hard mask layer is formed on the interlayer dielectric layer, and a second hard mask layer is also formed above the first hard mask layer in the pixel area; S3. Using the first hard mask layer as a mask, contact holes are etched in the logic area, and only a mask pattern is formed on the pixel area under the protection of the second hard mask layer; S4. An organic carbon layer is spin-coated in both the logic area and the pixel area to form a sacrificial layer for protecting the contact holes in the logic area; S5. The organic carbon layer is etched to expose the mask pattern in the pixel area, and the contact holes in the pixel area are etched until above the protective layer; S6. Continue to etch the protective layer below the contact holes in the pixel area, and at the same time etch and thin the interlayer dielectric layer by the same thickness; S7. Remove the sacrificial layer in the logic area and fill all the contact holes.

[0031] As Figure 3AAs shown, the device structures of the logic region and the pixel region of the image sensor have been pre-completed. It mainly includes a substrate 301. Above the substrate 301, it is divided into a logic region and a pixel region. The logic region includes a gate oxide layer 302 (Gate OX, abbreviated as GOX), a polysilicon gate 303, and a contact layer 304 from bottom to top. The contact layer 304 is located on top of the gate and is a metal silicide, such as nickel silicide or cobalt silicide. The film thickness of this contact layer 304 is relatively thin and is mainly used to reduce the contact resistance. Among them, the substrate 301 can be a silicon substrate, a silicon-germanium substrate, or other semiconductor material substrates well-known to those skilled in the art. The pixel region includes a gate oxide layer GOX, a polysilicon gate 303, and a protective layer 305 (i.e., Self-Aligned Barrier Oxide, abbreviated as SAB OX) from bottom to top. In some embodiments, a sidewall structure (for example, a sidewall with an ONO structure) will also be formed on the side of the polysilicon gate 303. It should be noted that the polysilicon gate, contact layer, sidewall, gate oxide layer, etc. in this embodiment can all be formed by traditional or known processes, and the specific details of these structures are not elaborated in this invention. In addition, an active region is also formed on the substrate 301, which can be prepared by known technologies, and this invention does not elaborate too much on the active region.

[0032] In step S1 of this embodiment, a contact hole etch stop layer 306 (selectable silicon nitride) is mainly formed on the pre-completed entire device structure. In order to reduce the difficulty of filling the interlayer dielectric layer, avoid gaps and holes during filling, and further reduce the aspect ratio of the interlayer dielectric layer filling, the thickness of the contact hole etch stop layer 306 can be thinned, and its thickness is less than the thickness of the protective layer 305. In the prior art, the thickness of the contact hole etch stop layer 306 is generally 350 angstroms, and in this embodiment, it can be thinned to 300 angstroms, that is, at least thinned by 10%.

[0033] As Figure 3B shown, in step S2, this embodiment increases the thickness of the interlayer dielectric layer 307, and the increased thickness is equal to the thickness of the protective layer 305. The purpose is to be used as an etch compensation when etching the protective layer 305 subsequently, cancel each other out, and keep the thickness of the interlayer dielectric layer unchanged and the aspect ratio of the subsequent contact hole filling unchanged. Specifically, the interlayer dielectric layer 307 can be deposited first, and then formed by chemical mechanical polishing. Specifically, the interlayer dielectric layer 307 can be formed by traditional or known processes, and will not be specifically elaborated here. In the embodiment of the present invention, the thickness of the protective layer 305 is about 330 angstroms, and the interlayer dielectric layer 307 also reserves an additional thickness of about 330 angstroms. The material of the interlayer dielectric layer 307 is generally an oxide layer, such as silicon dioxide, which is mainly used as a dielectric material between the device and the metal layer to form electrical isolation. The contact holes are many small vertical through holes formed in the interlayer dielectric layer 307 and are the connection channels between the transistors and the metal layer.

[0034] As Figure 3B shown, in the embodiment of the present invention, only the first hard mask layer 308 is formed on the interlayer dielectric layer 307, and a second hard mask layer 309 is further formed above the first hard mask layer 308 in the pixel region. The main purpose is to enable the contact holes in the subsequent logic region and pixel region to be etched separately, avoiding the over-etching of the logic region substrate caused by the height difference in the traditional synchronous etching. The thickness of the first hard mask layer 308 is close to the thickness of the contact hole etching stop layer 306, and the materials are similar or the same, so that when etching the contact holes in the pixel region later, both can be etched away simultaneously. Specifically, the formation process of the second hard mask layer 309 in the pixel region is as follows: form the second hard mask layer 309 on the first hard mask layer 308; form a photoresist layer 310 on the second hard mask layer 309; perform exposure and development on the photoresist layer 310 through a photomask to form a mask layer; etch the second hard mask layer 309 using this mask layer as a mask; remove the photoresist 310. The photomask used in this process is the same as the one used for preparing the protective layer 305, without the need for an additional photomask, thus saving costs.

[0035] As Figures 3C - 3F shown, in step S3, the formation process of the logic region contact holes is specifically as follows: (1) Form a photoresist layer 310 (abbreviated as PR) on the first hard mask layer 308 in the logic region and the second hard mask layer 309 in the pixel region, and an anti-reflection coating (abbreviated as BARC) can also be formed thereon; (2) Form a contact hole mask pattern for the logic region and the pixel region through exposure and development, as Figure 3C shown; (3) Select a first etching gas to etch the first hard mask layer 308 in the logic region, and specifically, it can be etched by a dry etching method, as Figure 3D shown. Since the materials of the first hard mask layer 308 and the second hard mask layer 309 are different, different etching gases are selected for etching. When etching the first hard mask layer 308, the second hard mask layer 309 will not be etched. Therefore, in this process, the pixel region is protected by the second hard mask layer 309 and is not etched; (4) Select a second etching gas to etch the second hard mask layer 309 in the pixel region, and at the same time, etch a part of the interlayer dielectric layer 307 in the logic region, as Figure 3E shown. Because the materials of the second hard mask layer 309 and the interlayer dielectric layer 307 are similar or the same, when the second etching gas etches the second hard mask layer 309, a part of the interlayer dielectric layer 307 is also etched; (5) Select a third etching gas to continue etching downward in the logic region to form contact holes (until the contact hole etching stop layer 306 is etched away), and at the same time, etch the first hard mask layer 308 in the pixel region to form a contact hole mask pattern for the pixel region, as Figure 3Fas shown; a gas with a high selectivity ratio such as C 4 F 8 or CF 4 is used for etching. Also, since the thickness of the first hard mask layer 308 in the pixel region is close to the thickness of the contact hole etching stop layer 306, this high-selectivity etching gas can etch only the first hard mask layer 308 in the pixel region while completing the etching of the contact holes 311 in the logic region, just forming a mask pattern for the pixel region contact holes 313 thereon; (6) Remove the photoresist layer 310 and the anti-reflection coating.

[0036] In step S4, organic carbon is spin-coated, which can fill the etched logic region contact holes 311. This serves as a sacrificial layer to self-align and protect the logic region contact holes 311, as Figure 3G shown. At the same time, the organic carbon also fills the voids in the mask pattern of the pixel region contact holes 313. The organic carbon in this part can be etched off first. At this time, no photomask is required, and it is directly etched through the etching gas, as Figure 3H shown. When forming the sacrificial layer for protecting the logic region contact holes by spin-coating organic carbon, it is specifically formed through a self-alignment process to reduce the complexity and cost in the manufacturing process, while improving the performance and reliability of the product. Spin-coated carbon self-alignment protection can avoid the overlay error problem in the traditional yellow light process.

[0037] Next, step S5 is carried out. An etching gas with a high selectivity ratio (this etching gas cannot etch the organic carbon layer 312 serving as a sacrificial layer in the logic region and the first hard mask layer 308) is selected to further etch the second hard mask layer 309 and the interlayer dielectric layer 307 in the pixel region until the contact hole etching stop layer 306, initially forming the pixel region contact holes 313, as Figure 3I shown. Continue to use the etching gas to etch the contact hole etching stop layer 306. Since the materials of the first hard mask layer 308 and the contact hole etching stop layer 306 are similar or the same, and their thicknesses are approximately the same, the first hard mask layer 308 is etched off while etching the contact hole etching stop layer 306, while the logic region is protected by the organic carbon layer 312 serving as a sacrificial layer and is not damaged, as Figure 3J shown.

[0038] In step S6, continue to etch the protective layer 305 in the pixel region downward to form the final pixel region contact holes 313, as Figure 3K shown. When etching the protective layer 305 in the pixel region, the interlayer dielectric layer 307 with the same thickness is etched at the same time. Since the thickness of the interlayer dielectric layer 307 is increased when forming the interlayer dielectric layer 307 to make it the same as the thickness of the protective layer 305 in the pixel region, when etching the protective layer 305 at this time, the thickened interlayer dielectric layer 307 serves as an etching compensation and cancels each other out, keeping the thickness of the interlayer dielectric layer unchanged and the aspect ratio during subsequent contact hole filling unchanged.

[0039] In step S7, the sacrificial layer in the logic region is removed, such as Figure 3L shown, and all contact holes are filled, such as Figure 3M shown. The main material for filling is conductive metal, such as tungsten. Also, since the contact holes in the logic region and the pixel region are formed separately, the contact hole etch stop layer 306 only needs to balance the height loads of their respective active regions and the polysilicon gate 303, and there is no need to consider the additional height load brought by the SAB OX protection layer 305. Thinning the thickness of the contact hole etch stop layer 306 can reduce the filling difficulty of the interlayer dielectric layer, which is beneficial to the HARP filling to form a seamless and hole-free structure, and further beneficial to the stability of the isolation performance.

[0040] The image sensor according to an embodiment of the present invention mainly uses the contact hole forming method of the above embodiment to prepare the contact holes in the pixel region and the logic region. The contact holes formed by this method will not over-etch the substrate 301, and the finally filled interlayer dielectric layer is seamless and hole-free, and the isolation performance is stable.

[0041] In summary, the present invention introduces different hard mask layers in the logic region and the pixel region. Only one hard mask layer is prepared in the logic region, while two hard mask layers are prepared in the pixel region. The unexpected effect is that the contact holes in the logic region and the pixel region can be etched separately, avoiding the over-etching of the logic region substrate caused by the height difference in the synchronous etching in the traditional solution; after the etching of the logic region contact hole 311 is completed, a sacrificial layer for protecting the logic region contact hole 311 is formed by spin-coating an organic carbon layer 312 self-aligned, so that the etching of the pixel region contact hole 313 will not affect the logic region contact hole 311 at all; and when forming the interlayer dielectric layer 307, its thickness is increased to be the same as the thickness of the protection layer 305 in the pixel region, so as to be used as an etching compensation when etching the protection layer 305 subsequently, canceling each other out, and still maintaining the aspect ratio unchanged during the subsequent hole filling.

[0042] It should be noted that according to the needs of implementation, each step / component described in this application can be split into more steps / components, or two or more steps / components or partial operations of steps / components can be combined into new steps / components to achieve the purpose of the present invention.

[0043] The sequence numbers of the steps in the above embodiments do not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of this application.

[0044] It should be understood that those of ordinary skill in the art can make improvements or transformations according to the above description, and all such improvements and transformations should fall within the protection scope of the appended claims of the present invention.

Claims

1. A contact hole forming method, characterized in that: The following steps are involved: Forming a contact hole etching stop layer on the device structures of the logic area and the pixel area of ​​the pre-finished image sensor, wherein the device structure of the pixel area has one more protective layer than that of the logic area; Filling a thickened interlayer dielectric layer on the contact hole etching stop layer, the increased thickness being equal to the thickness of the protection layer; and forming a first hard mask layer on the interlayer dielectric layer, and forming a second hard mask layer on the first hard mask layer in the pixel region; Using the first hard mask layer as a mask, a contact hole is etched in the logic area, and only a mask pattern is formed on the pixel area under the protection of the second hard mask layer; Spin-coat an organic carbon layer on both the logic area and the pixel area to form a sacrificial layer for protecting the contact holes of the logic area; Etching the organic carbon layer to expose the mask pattern of the pixel area, and etching the contact hole of the pixel area until it is above the protective layer; Continue to etch downward the protection layer below the contact hole in the pixel area, and at the same time etch and thin the interlayer dielectric layer to the same thickness; The sacrificial layer in the logic area is removed and all contact holes are filled.

2. The contact hole forming method according to claim 1, wherein: The formed contact hole etching stop layer is a thinned contact hole etching stop layer, and its thickness is less than that of the protection layer.

3. The contact hole forming method according to claim 1 or 2, characterized in that: The thickness of the first hard mask layer is the same as the thickness of the contact hole etching stop layer.

4. The contact hole forming method according to claim 1, wherein: The contact hole formation process of the logic area is specifically as follows: forming a photoresist layer and an anti-reflective coating on the first hard mask layer of the logic area and the second hard mask layer of the pixel area; forming contact hole mask patterns of the logic area and the pixel area by exposure and development; selecting a first etching gas to etch the first hard mask layer of the logic area; selecting a second etching gas to etch the second hard mask layer of the pixel area, and at the same time etching part of the interlayer dielectric layer of the logic area; selecting a third etching gas to continue to etch downward the logic area to form a contact hole, and at the same time etching the first hard mask layer of the pixel area to form a contact hole mask pattern of the pixel area; removing the photoresist layer and the anti-reflective coating.

5. The contact hole forming method according to claim 1, wherein: When etching the organic carbon layer, a mask is not required, and etching is performed directly by etching gas, which is oxygen or oxygen-containing gas.

6. The contact hole forming method according to claim 1, wherein: The formation process of the second hard mask layer in the pixel area is specifically as follows: forming a second hard mask layer on the first hard mask layer; forming a photoresist layer on the second hard mask layer; exposing and developing on the photoresist layer through a photomask to form a mask layer, wherein the photomask is the photomask used when preparing the protective layer; etching the second hard mask layer using the mask layer as a mask; and removing the photoresist.

7. The contact hole forming method according to claim 6, characterized in that: The second hard mask layer is made of a material different from that of the first hard mask layer.

8. The contact hole forming method according to claim 1, wherein: The contact hole etching process of the pixel area is specifically as follows: etching the interlayer dielectric layer with the mask pattern of the pixel area as a mask to initially form the contact hole of the pixel area, and etching the second hard mask layer at the same time; continuing to etch the contact hole etching stop layer below the contact hole of the pixel area, and etching the first hard mask layer of the pixel area and the logic area at the same time; Continue to etch the protection layer below the pixel region contact hole to form a final pixel region contact hole.

9. The contact hole forming method according to claim 1, characterized in that: The second hard mask layer is made of the same material as the interlayer dielectric layer.

10. An image sensor, characterized in that: The contact holes of the pixel area and the logic area are prepared by the contact hole forming method described in any one of claims 1 to 9.

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