Light-emitting substrate and display device

Abstract

The invention relates to a light-emitting substrate and a display device. The light-emitting substrate comprises a substrate body, a plurality of connecting electrodes located on one side of the substrate body and an insulating layer located on the side, away from the substrate body, of a driving wiring layer, the connecting electrodes comprise a plurality of connecting electrode sets, each connecting electrode set comprises at least two connecting electrodes, and the insulating layer is provided with a plurality of via holes. The plurality of solder parts are located on one side, far away from the substrate, of the insulating layer, the plurality of solder parts comprise a plurality of solder part groups, each solder part group comprises at least two solder parts, the solder parts in the same solder part group are electrically connected with the connecting electrodes in the same connecting electrode group through the via holes, and the plurality of light-emitting chips are located on one side, far away from the substrate, of the solder parts. The light-emitting chip is electrically connected with the solder parts in the same solder part group, the isolation structure is located between the insulating layer and the light-emitting chip, the isolation structure at least comprises a first isolation part, and the first isolation part is located between two adjacent solder parts in the same solder part group.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a light-emitting substrate and a display device. Background Art

[0002] Compared with OLED (Organic Light-Emitting Diode) display devices, MLED (MiniLED or MicroLED) display devices exhibit better performance in terms of low cost, high contrast ratio, high brightness, and thin and light form factor. In recent years, they have entered an accelerated development stage and have been widely used in the field of small and medium-sized display applications. Summary of the Invention

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a light-emitting substrate and a display device.

[0004] To achieve the above object, the present disclosure provides a light-emitting substrate, comprising:

[0005] A substrate;

[0006] A driving trace layer located on one side of the substrate. The driving trace layer includes a plurality of connection electrodes, and the plurality of connection electrodes include multiple groups of connection electrode groups. Each connection electrode group includes at least two connection electrodes;

[0007] An insulating layer located on the side of the driving trace layer away from the substrate. The insulating layer is provided with a plurality of vias, and the plurality of vias expose the connection electrodes;

[0008] A plurality of solder portions located on the side of the insulating layer away from the substrate. The plurality of solder portions include multiple groups of solder portion groups. Each solder portion group includes at least two solder portions. The solder portions in the same solder portion group are electrically connected to the connection electrodes in the same connection electrode group through the vias;

[0009] A plurality of light-emitting chips located on the side of the solder portions away from the substrate. The light-emitting chips are electrically connected to the solder portions within the same solder portion group;

[0010] An isolation structure located between the insulating layer and the light-emitting chips. The isolation structure at least includes a first isolation portion, and the first isolation portion is located between two adjacent solder portions in the same solder portion group.

[0011] In some embodiments, the isolation structure further includes a second isolation portion, and the second isolation portion is located between two adjacent solder portions in different solder portion groups;

[0012] The first isolation portion and the second isolation portion jointly surround at least one solder portion in the solder portion group.

[0013] In some embodiments, the light-emitting chip is in contact with the first isolation portion, or the light-emitting chip is in contact with both the first isolation portion and the second isolation portion.

[0014] In some embodiments, the surface of the insulating layer away from the substrate has at least one groove. The at least one groove includes at least one first groove on the surface of the insulating layer away from the substrate between two adjacent solder portions in the same solder portion group, and a part of the first isolation portion is located in the first groove.

[0015] In some embodiments, there is a first spacer groove between two adjacent connection electrodes in the same connection electrode group;

[0016] The insulating layer includes a first main body portion disposed opposite to the first spacer groove and at least partially located in the first spacer groove, and a first extension portion located on the side of the connection electrode away from the substrate and connected to the first main body portion;

[0017] The at least one first groove includes at least one first type of groove on the surface of the first main body portion away from the substrate and at least one second type of groove on the surface of the first extension portion away from the substrate. Among them, the groove depth of the first type of groove is greater than the groove depth of the second type of groove.

[0018] In some embodiments, the isolation structure further includes a second isolation portion. The at least one groove further includes at least one second groove on the surface of the insulating layer away from the substrate between two adjacent solder portions in different solder portion groups, and a part of the second isolation portion is located in the second groove.

[0019] In some embodiments, there is a second spacer groove between two adjacent connection electrodes in different connection electrode groups;

[0020] The insulating layer includes a second main body portion disposed opposite to the second spacer groove and at least partially located in the second spacer groove, and a second extension portion located on the side of the connection electrode away from the substrate and connected to the second main body portion;

[0021] The at least one second groove includes at least one third type of groove on the surface of the second main body portion away from the substrate and at least one fourth type of groove on the surface of the second extension portion away from the substrate. Among them, the groove depth of the third type of groove is greater than the groove depth of the fourth type of groove.

[0022] In some embodiments, a plurality of grooves located between two adjacent solder portions are arranged in a first direction, wherein the grooves extend in a second direction, and the second direction intersects the first direction;

[0023] Alternatively, the groove includes a plurality of sub-grooves that communicate with each other, and the extending directions of at least two of the sub-grooves are different;

[0024] Alternatively, a plurality of grooves located between two adjacent solder portions are arranged in multiple rows, and the grooves in adjacent two rows are arranged in a staggered manner.

[0025] In some embodiments, the maximum groove depth of the groove is not less than 50 nm, and / or the ratio of the maximum groove depth of the groove to the thickness of the insulating layer does not exceed 80%.

[0026] In some embodiments, the orthographic projection of the insulating layer on the substrate covers and extends beyond the orthographic projection of the isolation structure on the substrate.

[0027] In some embodiments, the light-emitting chip includes a chip body and at least two chip electrodes located on a side of the chip body close to the substrate, and the chip electrodes are electrically connected to the solder portions;

[0028] The surface of the isolation structure far from the substrate contacts the surface of the chip electrode close to the substrate.

[0029] In some embodiments, the maximum thickness of the solder portion is in the range of 50 μm - 80 μm, and / or the maximum thickness of the isolation structure is in the range of 50 μm - 80 μm.

[0030] In some embodiments, the material of the isolation structure includes an elastic material.

[0031] In some embodiments, at least a part of the isolation structure is in a compressed state.

[0032] In some embodiments, the elastic material includes an acrylic resin, a curing agent, and a dispersant;

[0033] Wherein, the mass ratio of the acrylic resin is 60% - 96%, the mass ratio of the curing agent is 0.1% - 4%, and the mass ratio of the dispersant is 0.1% - 10%.

[0034] In some embodiments, the material of the isolation structure includes an elastic material and hard particles located inside the elastic material.

[0035] In some embodiments, the material of the hard particles includes at least one of acrylic particles, calcium carbonate particles, and silicon spheres, and the particle size of the hard particles is in the range of 10 μm - 50 μm.

[0036] The present disclosure also provides a display device, including a light-emitting substrate as described in any one of the above.

[0037] Wherein, the light-emitting substrate is a display substrate.

[0038] Alternatively, the light-emitting substrate is a backlight substrate, and the display device further includes a liquid crystal display panel on one side of the light-emitting surface of the light-emitting substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings are used to provide a further understanding of the present disclosure, and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the drawings:

[0040] Figure 1A is a schematic plan view of the MLED display panel in some embodiments;

[0041] Figure 1B is Figure 1A a schematic plan view of each single-layer film in ;

[0042] Figure 2 is along Figure 1A a schematic cross-sectional view cut along the cutting line AA' in ;

[0043] Figure 3A 、 Figure 3B 、 Figure 3C are schematic views of each step in the process of printing and forming the solder part in some embodiments;

[0044] Figure 4 is a schematic plan view of the short circuit caused by solder overflow in some embodiments;

[0045] Figure 5 is a schematic cross-sectional view of the light-emitting substrate in some embodiments of the present disclosure;

[0046] Figure 6 is a schematic cross-sectional view of the light-emitting substrate in some other embodiments of the present disclosure;

[0047] Figure 7 is a schematic cross-sectional view of the light-emitting substrate in some other embodiments of the present disclosure;

[0048] Figure 8 is a schematic plan view of some film layers of the light-emitting substrate in some embodiments of the present disclosure;

[0049] Figure 9 is a schematic plan view of some film layers of the light-emitting substrate in some other embodiments of the present disclosure;

[0050] Figure 10It is a schematic plan view of partial film layers of a light-emitting substrate in some other embodiments of the present disclosure;

[0051] Figure 11 It is a schematic plan view of partial film layers of a light-emitting substrate in some other embodiments of the present disclosure;

[0052] Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 12D They are schematic diagrams of each step in the preparation process of a light-emitting substrate in some embodiments of the present disclosure;

[0053] Figure 13 It is a schematic cross-sectional view of an intermediate light-emitting substrate in some embodiments of the present disclosure;

[0054] Figure 14 It is a schematic cross-sectional view of a light-emitting substrate in some other embodiments of the present disclosure. Detailed Description of the Embodiments

[0055] The following will describe the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for the purpose of illustration and explanation of the present disclosure, and are not intended to limit the present disclosure.

[0056] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0057] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure belongs. The "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. The terms "connect" or "couple" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0058] As used herein, "parallel" and "perpendicular" include the described situations as well as situations similar to the described situations, where the range of the similar situations is within an acceptable deviation range, and the acceptable deviation range is determined by a person of ordinary skill in the art considering the measurements being discussed and the errors associated with the measurements of specific quantities (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism can be, for example, within a deviation of 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, within a deviation of 5°.

[0059] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can also be an intermediate layer between the layer or element and the other layer or substrate.

[0060] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be envisioned. Therefore, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but include shape deviations caused, for example, by manufacturing. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0061] The MLED display panel is formed by forming a driving trace layer on a substrate, then forming solder at corresponding positions on the driving trace layer through stencil printing, and attaching the light-emitting chips to the solder, thereby realizing the electrical connection between the light-emitting chips and the driving trace layer, and further enabling the light-emitting chips to emit light under the drive of the signals transmitted by the driving trace layer to form a light-emitting substrate, and finally packaging the light-emitting substrate to form the final display device.

[0062] Figure 1A is a schematic plan view of the MLED display panel in some embodiments. Specifically, Figure 1A only shows a schematic plan view of some of the film layers in the MLED display panel. Figure 1B is Figure 1A a schematic plan view of each single film layer in Figure 2 is along Figure 1A a schematic cross-sectional view cut along the cutting line AA' in

[0063] As Figure 2As shown, the MLED display panel includes a substrate 1, a driving circuit layer on one side of the substrate 1, a driving trace layer on the side of the driving circuit layer away from the substrate 1, and a light-emitting chip layer on the side of the driving trace layer away from the substrate 1. Among them, a plurality of thin-film transistors are provided in the driving circuit layer, and the light-emitting chip layer includes a plurality of light-emitting chips 9. The light-emitting chips 9 are electrically connected to the thin-film transistors through the driving trace layer. The thin-film transistors are used to provide driving signals for the light-emitting chips 9 so that the light-emitting chips 9 emit light.

[0064] Specifically, the thin-film transistor includes an active layer, a gate, and a source-drain electrode layer 3. For example, in one example, the active layer, the gate, and the source-drain electrode layer 3 of the thin-film transistor are stacked in sequence in a direction away from the substrate 1. Among them, the source-drain electrode layer 3 includes a source electrode and a drain electrode. The active layer includes a source connection portion, a drain connection portion, and a channel portion located between the source connection portion and the drain connection portion. The drain connection portion is electrically connected to the drain of the thin-film transistor, and the source connection portion is electrically connected to the source of the thin-film transistor. Both the source connection portion and the drain connection portion can be doped with impurities having a higher impurity concentration than that of the channel portion (for example, N-type impurities or P-type impurities). The channel portion is opposite to the gate of the thin-film transistor. When the voltage signal applied to the gate reaches a certain value, a carrier path is formed in the channel portion, so that the drain and source of the thin-film transistor are turned on, thereby enabling the thin-film transistor to provide a driving signal for the light-emitting chip 9.

[0065] The light-emitting chip 9 is specifically electrically connected to one of the source electrode and the drain electrode of the thin-film transistor through the driving trace layer. For example, FIG. 1 shows that the light-emitting chip 9 is electrically connected to the source-drain electrode layer 3 of the thin-film transistor through the driving trace layer. Among them, the source-drain electrode layer 3 in FIG. 1 can represent the drain electrode or the source electrode.

[0066] The driving trace layer includes a plurality of connection electrode groups, and the connection electrode groups correspond to the light-emitting chips 9 one by one. Each connection electrode group includes at least two connection electrodes 60. For the at least two connection electrodes 60 in each connection electrode group, each connection electrode 60 is electrically connected to the light-emitting chip 9 corresponding to the connection electrode group, and at least one of the connection electrodes 60 is also electrically connected to the source-drain electrode layer 3 of the thin-film transistor, and at least one other connection electrode 60 is electrically connected to the power supply signal line. Under the combined action of the signals respectively transmitted by the thin-film transistor and the power supply signal line, the light-emitting chip 9 can emit light.

[0067] Further, the connection between the connection electrode 60 and the light-emitting chip 9 is specifically realized through the solder portion 8. Specifically, an insulating layer 7 is provided between the connection electrode layer 6 and the light-emitting chip 9. The insulating layer 7 is provided with a plurality of first vias 71, and at least a part of the connection electrode 60 is exposed by the first vias 71. The solder portion 8 is located between the layer where the insulating layer 7 is located and the light-emitting chip 9, and one end of the solder portion 8 is electrically connected to the connection electrode 60 through an opening, and the other end of the solder portion 8 is electrically connected to the light-emitting chip 9.

[0068] Optionally, the MLED display panel further includes a first buffer layer 2 located between the thin-film transistor and the substrate 1, and a planarization layer 4 and a first passivation layer 5 that are located between the connection electrode layer 6 and the source-drain electrode layer 3 and are stacked in sequence along the direction away from the substrate 1. Correspondingly, the insulating layer 7 can specifically be a second passivation layer.

[0069] Optionally, the materials of the first buffer layer 2, the first passivation layer 5, and the insulating layer 7 can include at least one of SiOx and SiNx, and the thicknesses can all be set at

[0070] The material of the source-drain electrode layer 3 can include Ti / Al / Ti stacked in sequence, or Mo / Al / Mo stacked in sequence, and the thicknesses respectively correspond to

[0071] The material of the planarization layer 4 is selected as a photoresist material, and the thickness needs to be not less than

[0072] The material of the connection electrode layer 6 can include at least one of metals such as Cu, Al, Ni, and Nb, and can be, for example, a composite metal formed by at least two of the foregoing metals. The film height of the connection electrode layer 6 is

[0074] Among them, some of the connection electrodes 60 are electrically connected to the source-drain electrode layer 3 through second vias 51 that penetrate the first passivation layer 5 and the planarization layer 4.

[0075] Figure 1A Shows Figure 2 The schematic plan view of the stack of the insulating layer 7, the first passivation layer 5, and the solder portion 8 in Figure 1B Shows the schematic plan view of the respective film layers of the insulating layer 7, the first passivation layer 5, and the solder portion 8 in FIG. 1.

[0076] The solder portion 8 is formed by screen printing. Figure 3A 、 Figure 3B 、 Figure 3C Are the schematic diagrams of the respective steps in the process of printing and forming the solder portion 8 in some embodiments. Specifically, the formation of the solder portion 8 includes the following steps:

[0077] Step S1: As Figure 3A shown, place the first mesh frame 11 on the side of the driving trace layer away from the substrate 1, and apply solder, such as solder paste 13, on the side of the first mesh frame 11 away from the substrate 1, for example, at least at the position of the first vias 71 of the insulating layer 7. It can be understood that the via positions of the first mesh frame 11 and the first vias 71 are at least partially correspondingly arranged. Optionally, the first mesh frame 11 can specifically be a steel mesh frame.

[0078] Step S2: As Figures 3A to 3B shown, use a squeegee 12 to leave part of the solder paste 13 at the position of the first vias 71, that is, form the solder part 8 in the subsequent MLED display panel.

[0079] Step S3: As Figure 3C shown, peel off the first mesh frame 11. For example, specifically, the substrate 1, the driving circuit layer, the solder part 8, etc. can be moved as a whole along the Figure 3C direction indicated by the arrow in to peel off the first mesh frame 11 from the overall structure.

[0080] However, during the screen printing process, the solder paste 13 is relatively prone to the phenomenon of overflowing in an unfixed direction. Figure 4 is a schematic plan view of a short circuit caused by solder overflow in some embodiments. As Figure 4 shown, the solder paste 13 (i.e., the solder part 8) at the positions of adjacent first vias 71 overflows and will be electrically connected to each other, causing a short circuit. The short circuit phenomenon of adjacent solder paste 13 overflow will further cause the light-emitting chip 9 to emit light abnormally, seriously affecting the light-emitting effect of the light-emitting substrate.

[0081] In addition, it can be understood that the solder paste 13 in Step S3 is welded to the light-emitting chip 9 again. After the solder paste 13 solidifies, it is the solder part 8, and an MLED display panel can be obtained. However, during the welding process of the light-emitting chip 9 and the solder paste 13, the heated solder paste 13 still has the phenomenon of overflowing in an unfixed direction, which easily causes the fixed position of the light-emitting chip 9 to deviate, thereby affecting the light-emitting uniformity of the entire light-emitting substrate.

[0082] To at least alleviate or solve one of the above-mentioned technical problems, the present disclosure provides a light-emitting substrate and a display device.

[0083] Figure 5 is a schematic cross-sectional structure view of a light-emitting substrate in some embodiments of the present disclosure.

[0084] In some embodiments, as Figure 5 shown, a light-emitting substrate of the present disclosure includes: a substrate 1, a driving trace layer, an insulating layer 7, a plurality of solder parts 8, a plurality of light-emitting chips 9, and an isolation structure 10.

[0085] Among them, the driving trace layer is located on one side of the substrate 1. The driving trace layer includes a plurality of connection electrodes 60. The plurality of connection electrodes 60 includes multiple groups of connection electrode groups. Each connection electrode group includes at least two connection electrodes 60. In the embodiment of the present disclosure, an example in which each connection electrode group includes two connection electrodes 60 is used for illustration. For example, each connection electrode group includes a first connection electrode 61 and a second connection electrode 62.

[0086] The insulating layer 7 is located on the side of the driving trace layer away from the substrate 1. The insulating layer 7 is provided with a plurality of first vias 71, and the plurality of first vias 71 expose the connection electrodes 60. Among them, some of the first vias 71 expose the first connection electrode 61, and the other part of the first vias 71 expose the second connection electrode 62.

[0087] The solder part 8 is located on the side of the insulating layer 7 away from the substrate 1. And, the plurality of solder parts 8 includes multiple groups of solder part groups. Each solder part group includes at least two solder parts 8. In the embodiment of the present disclosure, an example in which each solder part group includes two solder parts 8 is used for illustration. For example, each group of solder part groups includes a first solder part 81 and a second solder part 82. The solder part groups correspond to the connection electrode groups one by one, and the solder parts 8 in the same solder part group are electrically connected to the connection electrodes 60 in the same connection electrode group through the first vias 71. For example, the first solder part 81 in the solder part group is electrically connected to the first connection electrode 61 in the corresponding connection electrode group, and the second solder part 82 in the solder part group is electrically connected to the second connection electrode 62 in the corresponding connection electrode group.

[0088] The light-emitting chip 9 is located on the side of the solder part 8 away from the substrate 1. The light-emitting chips 9 correspond to the solder part groups one by one. Each light-emitting chip 9 is electrically connected to each solder part 8 in the corresponding solder part group respectively. The light-emitting chip 9 includes a chip body 91 and at least two chip electrodes 92 electrically connected to the chip body 91. In the embodiment of the present disclosure, an example in which the light-emitting chip 9 includes two chip electrodes 92 is used for illustration. For example, the light-emitting chip 9 includes a first chip electrode 921 and a second chip electrode 922. Among them, the first chip electrode 921 is electrically connected to the first solder part 81 in the corresponding solder part group, and the second chip electrode 922 is electrically connected to the second solder part 82 in the corresponding solder part group.

[0089] The isolation structure 10 is located between the insulating layer 7 and the light-emitting chip 9. The isolation structure 10 at least includes a first isolation part 101, and the first isolation part 101 is located between two adjacent solder parts 8 in the same solder part group. For example, the first isolation part 101 is located between the first solder part 81 and the second solder part 82 in the same solder part group

[0090] In an embodiment of the present disclosure, by providing a first isolation portion 101 between two adjacent solder portions 8 in the same solder portion group, the first isolation portion 101 can prevent the adjacent two solder portions 8 in the same solder portion group from overflowing in the direction of approaching each other during the screen printing process, thereby avoiding short - circuit caused by the electrical connection between the adjacent two solder portions 8. For example, in the embodiment shown in FIG. 1, the first isolation portion 101 can prevent short - circuit between the first solder portion 81 and the second solder portion 82 in the same solder portion group, and further avoid short - circuit of the light - emitting chip 9 corresponding to the solder portion group, resulting in the light - emitting chip 9 not being able to light up.

[0091] Meanwhile, during the welding process between the solder portion 8 and the light - emitting chip 9, since the first isolation portion 101 is located between two adjacent solder portions 8 in the same solder portion group, the first isolation portion 101 can also prevent the adjacent two solder portions 8 in the same solder portion group from overflowing towards each other during the melting process and causing short - circuit, thus avoiding short - circuit of the light - emitting chip 9 and resulting in the light - emitting chip 9 not being able to light up.

[0092] Therefore, the embodiment of the present disclosure can avoid affecting the light - emitting effect of the light - emitting substrate, for example, avoiding the appearance of dark spots on the light - emitting substrate.

[0093] Figure 6 It is a schematic cross - sectional structure diagram of a light - emitting substrate in some other embodiments of the present disclosure.

[0094] In some other embodiments, as Figure 6 shown, the isolation structure 10 includes not only the first isolation portion 101 but also a second isolation portion 102. The second isolation portion 102 is located between two adjacent solder portions 8 in different solder portion groups. The first isolation portion 101 and the second isolation portion 102 jointly surround at least one solder portion 8 in the solder portion group. For example, the first isolation portion 101 and the second isolation portion 102 jointly surround each solder portion 8 on the light - emitting substrate.

[0095] It can be understood that the isolation structure 10 formed by the first isolation portion 101 and the second isolation portion 102 is generally in a "grid" shape, and correspondingly, the solder portion 8 is located at the "grid" position.

[0096] In addition to being able to avoid short - circuit between two adjacent solder parts 8 in the same solder part group through the first isolation part 101, the embodiment of the present disclosure can also avoid short - circuit between two adjacent solder parts 8 in different solder part groups through the second isolation part 102. For example, in one example, a second isolation part 102 is located between a first solder part 81 in one solder part group and a second solder part 82 in another solder part group. Then, the second isolation part 102 can avoid the first solder part 81 and the second solder part 82 in the different solder part groups from overflowing towards each other during the screen - printing process, thereby avoiding short - circuit between the first solder part 81 and the second solder part 82 in the different solder part groups. Therefore, the embodiment of the present disclosure can avoid short - circuit of the light - emitting chip 9, and further avoid affecting the light - emitting effect of the light - emitting substrate.

[0097] Meanwhile, the first isolation part 101 and the second isolation part 102 jointly surround each solder part 8 on the light - emitting substrate, and can also avoid excessive overflow of the melted solder part 8 in any direction during the welding of the light - emitting chip 9 and the solder part 8, thereby avoiding affecting the fixed position of the light - emitting chip 9. Therefore, the isolation structure 10 in the embodiment of the present disclosure can also ensure that the light - emitting chip 9 has less position deviation during the welding process with the solder part 8, or avoid position deviation of the light - emitting chip 9 during the welding process, so as to ensure that the light - emitting chip 9 can be at the preset position, and further ensure the light - emitting effect of the light - emitting substrate, such as ensuring the light - emitting uniformity of the light - emitting substrate.

[0098] Optionally, the first isolation part 101 and the second isolation part 102 are connected into an integral structure.

[0099] Actually, there is no specific requirement on whether the first isolation part 101 and the second isolation part 102 in the embodiment of the present disclosure are connected into an integral structure. However, in order to reduce the manufacturing process difficulty and cost of the isolation structure 10, the first isolation part 101 and the second isolation part 102 in the embodiment of the present disclosure are connected into an integral structure, that is, when manufacturing the isolation structure 10, the first isolation part 101 and the second isolation part 102 can be formed simultaneously by using the same manufacturing process.

[0100] In some embodiments, as Figure 5 and Figure 6 shown, the light - emitting chip 9 is in contact with the isolation structure 10.

[0101] For example, in one example, as Figure 5 shown, the isolation structure 10 only includes the first isolation part 101, and the light - emitting chip 9 is in contact with the first isolation part 101 located between the first solder part 81 and the second solder part 82 in the corresponding solder part group. Specifically, the light - emitting chip 9 is directly in contact with the surface of the first isolation part 101 far from the substrate 1.

[0102] In the embodiments of the present disclosure, the light-emitting chip 9 is in contact with the first isolation portion 101, which can ensure the isolation effect of the first isolation portion 101 on the adjacent first solder portion 81 and the second solder portion 82 in the corresponding solder portion group. At the same time, the flatness effect of the light-emitting chip 9 can be controlled by the upper surface of the first isolation portion 101 being flush, thereby controlling the light-emitting plane of the light-emitting chip 9.

[0103] In another example, as Figure 6 shown, the isolation structure 10 includes a first isolation portion 101 and a second isolation portion 102, and the light-emitting chip 9 is in contact with both the first isolation portion 101 and the second isolation portion 102. Correspondingly, the light-emitting chip 9 is specifically in contact with the surface of the second isolation portion 102 away from the substrate 1. And it can be understood that the surface of the second isolation portion 102 away from the substrate 1 is in contact with the light-emitting chips 9 corresponding to different solder portion groups, that is, the surface of the second isolation portion 102 away from the substrate 1 is in contact with a plurality of light-emitting chips 9.

[0104] In the embodiments of the present disclosure, the light-emitting chip 9 is in contact with the second isolation portion 102, which can ensure the isolation effect of the second isolation portion 102 on the adjacent solder portions 8 in different solder portion groups. At the same time, on the basis of controlling the flatness effect of the light-emitting chip 9 by the upper surface of the first isolation portion 101 being flush in the embodiments of the present disclosure, the flatness effect of different light-emitting chips 9 is also controlled by the upper surface of the second isolation portion 102. Therefore, the embodiments of the present disclosure can control the light-emitting planes of all the light-emitting chips 9 on the light-emitting substrate, thereby ensuring the overall light-emitting effect of the light-emitting substrate.

[0105] In some embodiments, as Figure 5 and Figure 6 shown, at least one groove 72 is formed on the surface of the insulating layer 7 away from the substrate 1, and a part of the isolation structure 10 is located in the groove 72.

[0106] In the embodiments of the present disclosure, by forming the groove 72 on the surface of the insulating layer 7 away from the substrate 1, when preparing the isolation structure 10, a part of the isolation structure 10 can be located in the groove 72. In this case, the position of the isolation structure 10 can be stabilized by the groove 72, thereby strengthening the adhesion of the isolation structure 10 to the insulating layer 7, and avoiding the separation of the isolation structure 10 from the insulating layer 7 when preparing the solder portion 8 by screen printing during the preparation process, which affects the product yield.

[0107] For example, in one example, as Figure 5 and Figure 6As shown, the isolation structure 10 includes a first isolation portion 101. The surface of the insulating layer 7 away from the substrate 1 between two adjacent solder portions 8 in the same solder portion group has at least one first groove 721, and a part of the first isolation portion 101 is located in the first groove 721. That is, at least one groove 72 includes at least one first groove 721.

[0108] The embodiment of the present disclosure can reinforce and stabilize the position of the first isolation portion 101 through the first groove 721, avoiding the slippage between the first isolation portion 101 and the insulating layer 7 when preparing the first solder portion 81 and the second solder portion 82 in the same solder portion group, which affects the formation of the first solder portion 81 and the second solder portion 82.

[0109] In another example, as Figure 6 shown, the isolation structure 10 includes not only the first isolation portion 101 but also a second isolation portion 102. Similarly, the surface of the insulating layer 7 away from the substrate 1 between two adjacent solder portions 8 in different solder portion groups has at least one second groove 722, and a part of the second isolation portion 102 is located in the second groove 722. That is, at least one groove 72 includes at least one first groove 721 and at least one second groove 722.

[0110] The embodiment of the present disclosure can not only reinforce and stabilize the position of the first isolation portion 101 through the first groove 721, but also reinforce and stabilize the position of the second isolation portion 102 through the second groove 722, avoiding the slippage between the first isolation portion 101 and the second isolation portion 102 and the insulating layer 7 when preparing the solder portion 8, which affects the formation of the solder portion 8.

[0111] In some embodiments, the maximum groove depth of the groove 72 is not less than 50 nm. For example, the maximum groove depth of the groove 72 can be 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, etc.

[0112] The embodiment of the present disclosure needs to further limit the groove depth of the groove 72. If the groove 72 is set too shallow, due to process and other reasons, the groove 72 may not be obvious, and it cannot be ensured that the isolation structure 10 can be firmly attached to the insulating layer 7, and further, the position stability of the isolation structure 10 during the preparation of the solder portion 8 by screen printing cannot be ensured. Therefore, the embodiment of the present disclosure sets the maximum groove depth of the groove 72 to be not less than 50 nm, which can enable the isolation structure 10 to be firmly attached to the insulating layer 7, and avoid the isolation structure 10 from detaching from the insulating layer 7 or shifting in position due to the scraping of the squeegee during the preparation of the solder portion 8 by screen printing.

[0113] In some embodiments, the ratio of the maximum groove depth of the groove 72 to the thickness of the insulating layer 7 does not exceed 80%. For example, the ratio of the groove depth of the groove 72 to the thickness of the insulating layer 7 can be 80%, 70%, 60%, 50%, etc.

[0114] In the embodiments of the present disclosure, the groove 72 can be formed on the surface of the extension portion 720 away from the substrate 1. The extension portion 720 is located on the side of the connecting electrode 60 away from the substrate 1, that is, the lower layer of the extension portion 720 is the connecting electrode 60. In order to ensure that the extension portion 720 covers the connecting electrode 60 and avoid the groove 72 affecting the lower connecting electrode 60, in the embodiments of the present disclosure, the ratio of the groove depth of the groove 72 to the thickness of the insulating layer 7 is set not to exceed 80%.

[0115] Further, the ratio of the groove depth of the groove 72 to the thickness of the insulating layer 7 is not less than 50%.

[0116] In the embodiments of the present disclosure, the ratio of the groove depth of the groove 72 to the thickness of the insulating layer 7 is set not to be less than 50% to ensure the depth of the groove 72 itself, thereby ensuring the strengthening effect of the groove 72 on the isolation structure 10.

[0117] For example, in a specific embodiment, in order to ensure that the groove 72 occupies sufficient space, the orthographic projection of the groove 72 on the substrate 1 may overlap with the orthographic projection of the lower connecting electrode 60 on the substrate, but the groove depth here needs to be controlled. When the thickness of the insulating layer 7 is at the position corresponding to the groove 72, the insulating layer 7 at least retains the thickness, that is, the groove depth of the groove 72 is so as to ensure effective coverage of the connecting electrode 60. On the other hand, setting the groove depth of the groove 72 not less than If the depth of the groove 72 is too shallow, the groove 72 will not be obvious, resulting in a significant reduction in the strengthening stability of the insulating layer 7 to the isolation structure 8, and it is easy for the isolation structure 8 to slip relative to the insulating layer 7.

[0118] In addition, it should be noted that those skilled in the art should be able to understand that when the thickness of the insulating layer 7 is not a unique fixed value, the ratio of the groove depth of the groove 72 to the thickness of the insulating layer 7 should refer to the groove depth of the groove 72 and the thickness of the insulating layer 7 at the position where the groove 72 is not provided before the groove 72 is formed.

[0119] For example, the ratio of the maximum depth of the groove located on the surface of the main body portion 710 away from the substrate 1 to the thickness of the main body portion 710 does not exceed 80%, and the ratio of the maximum depth of the groove located on the surface of the extension portion 720 away from the substrate 1 to the thickness of the extension portion 720 does not exceed 80%.

[0120] Specifically, in one example, the ratio of the maximum groove depth of the first type of groove to the thickness of the first main body portion 711 is 80%, and the ratio of the maximum groove depth of the second type of groove to the thickness of the first extension portion 712 is 80%.

[0121] In the embodiments of the present disclosure, since the thickness of the main body portion 710 is greater than the thickness of the extension portion 720, therefore, the groove depth of the groove located on the surface of the main body portion 710 can be greater than the groove depth of the groove located on the surface of the extension portion 720, while ensuring the coating of the connection electrode 60 by the extension portion 720 and increasing the reinforcement effect on the isolation structure 10 through the groove located on the surface of the main body portion 710.

[0122] Figure 7 It is a schematic cross-sectional structure diagram of a light-emitting substrate in some other embodiments of the present disclosure.

[0123] In some embodiments, as Figure 7 shown, there is a spacer groove between two adjacent connection electrodes 60. The insulating layer 7 includes a main body portion 710 disposed opposite to the spacer groove and at least partially located in the spacer groove, and an extension portion 720 located on the side of the connection electrode 60 away from the substrate 1 and connected to the main body portion 710. At least one groove 72 includes at least one groove 72 located on the surface of the main body portion 710 away from the substrate 1 and at least one groove 72 located on the surface of the extension portion 720 away from the substrate 1. Among them, the groove depth of the groove 72 located on the surface of the main body portion 710 away from the substrate 1 is greater than the groove depth of the groove 72 located on the surface of the extension portion 720 away from the substrate 1.

[0124] Specifically, in one example, as Figure 7 shown, the plurality of spacer grooves include at least one first spacer groove between two adjacent connection electrodes 60 in the same connection electrode group. For example, the first spacer groove between the first connection electrode 61 and the second connection electrode 62 in the same connection electrode group. The insulating layer 7 includes at least one first portion 701 between two adjacent solder portions 8 in the same solder portion group. The first portion 701 includes a first main body portion 711 disposed opposite to the first spacer groove and at least partially located in the first spacer groove, and at least two first extension portions 712 connected to the first main body portion 711. For example, the two first extension portions 712 are respectively located on the sides of the first connection electrode 61 and the second connection electrode 62 away from the substrate 1. At least one first groove 721 includes at least one first type of groove located on the surface of the first main body portion 711 away from the substrate 1 and at least one second type of groove located on the surface of the first extension portion 712 away from the substrate 1, where the groove depth of the first type of groove is greater than the groove depth of the second type of groove.

[0125] In another example, in addition to including at least one first spacer groove, the plurality of spacer grooves further include at least one second spacer groove located between two adjacent electrodes in different connection electrode groups. As Figure 7 shown, the insulating layer 7 further includes at least one second portion 702 located between two adjacent solder portions 8 in different solder portion groups. Similarly, the second portion 702 includes a second main body portion disposed opposite to the second spacer groove and at least partially located within the second spacer groove, and a plurality of second extension portions connected to the second main body portion. The plurality of second extension portions are respectively located on a side of different connection electrodes 60 away from the substrate 1. At least one second groove 722 includes at least one third type of groove located on a surface of the second main body portion away from the substrate 1 and at least one fourth type of groove located on a surface of the second extension portion away from the substrate 1, wherein the groove depth of the third type of groove is greater than the groove depth of the fourth type of groove.

[0126] In the embodiments of the present disclosure, since the extension portion 720 is located on a side of the connection electrode 60 away from the substrate 1, therefore, in order to ensure the coverage of the connection electrode 60 by the extension portion 720, the groove depth of the groove 72 on the surface of the extension portion 720 away from the substrate 1 is relatively small. Correspondingly, since at least a part of the main body portion 710 is located within the spacer groove, the thickness of the main body portion 710 is greater than the thickness of the extension portion 720. Therefore, in order to ensure the reinforcement stability of the groove 72 for the isolation structure 10, the groove depth of the groove 72 on the surface of the main body portion 710 away from the substrate 1 is relatively large.

[0127] Of course, those skilled in the art should be able to clearly understand that, in fact, the surface of the main body portion away from the substrate 1 may not be flush with the surface of the extension portion away from the substrate 1, but the thickness of the main body portion can be greater than the thickness of the extension portion. For example, the surface of the first main body portion 711 away from the substrate 1 is lower than the surface of the first extension portion 712 away from the substrate 1, but the thickness of the first main body portion 711 is greater than the thickness of the first extension portion 712.

[0128] In the embodiments of the present disclosure, the groove 72 can be one or more, and can be set according to actual situations. Optionally, the specific shape of the groove 72 is not limited, and it can be a columnar groove, specifically, for example, a cylindrical groove or a polygonal columnar groove. The polygonal columnar groove can be specifically, for example, a cuboid groove, a hexagonal prism groove, etc.

[0129] For example, in one example, there may be multiple grooves 72 between two adjacent solder parts 8, and the multiple grooves 72 located between two adjacent solder parts 8 may be arranged in a certain direction, where the arrangement direction is different from the extension direction of the grooves 72. In another example, the multiple grooves 72 located between two adjacent solder parts 8 are arranged in multiple rows, and the grooves 72 in two adjacent rows are staggeredly arranged. In another example, the groove 72 includes multiple interconnected sub-grooves, and at least two of the multiple sub-grooves have different extension directions. On this basis, there may be at least one groove 72 between two adjacent solder parts 8.

[0130] Specifically, in the embodiments of the present disclosure, the first groove 721 is taken as an example for illustration.

[0131] Figure 8 It is a schematic plan view of a partial film layer of a light-emitting substrate in some embodiments of the present disclosure. Figure 9 It is a schematic plan view of a partial film layer of a light-emitting substrate in some other embodiments of the present disclosure. Figure 10 It is a schematic plan view of a partial film layer of a light-emitting substrate in some other embodiments of the present disclosure.

[0132] In some embodiments, as Figure 8 shown, there may be multiple first grooves 721 between the first solder part 81 and the second solder part 82 in the same solder part group, and the multiple first grooves 721 are arranged along a first direction, while the first grooves 721 extend along a second direction, where the second direction intersects the first direction. The embodiments of the present disclosure do not limit the specific directions of the first direction and the second direction. For the convenience of preparation, one of the first direction and the second direction may be set as the arrangement direction of the first connection electrode 61 and the second connection electrode 62 in the same connection electrode group, and the other of the first direction and the second direction is perpendicular to the arrangement direction of the first connection electrode 61 and the second connection electrode 62 in the same connection electrode group. For example, in Figure 8 the embodiment shown, the first direction is the arrangement direction of two adjacent connection electrodes 60.

[0133] In some other embodiments, as Figure 9 shown, there may be multiple first grooves 721 between the first solder part 81 and the second solder part 82 in the same solder part group, and the multiple first grooves 721 are arranged in multiple rows, and the multiple first grooves 721 in two adjacent rows are staggeredly arranged. The multiple first grooves 721 are arranged in a "honeycomb" shape.

[0134] During the process of preparing the solder part 8 by screen printing, when the first screen frame 11 needs to be attached to the first isolation part 101, due to mechanical vibration, there will be a slight slip, that is, the first isolation part 101 will be subjected to a lateral shear stress, namely shear stress. In the embodiment of the present disclosure, the first groove 721 is designed to be distributed in a "honeycomb" mesh structure, which can disperse the shear stress and is beneficial to the reinforcement of the first isolation part 101.

[0135] In other embodiments, as Figure 10 shown, there may be at least one first groove 721 between the first solder part 81 and the second solder part 82 in the same solder part group, and the first groove 721 includes a plurality of first sub-grooves 723 that communicate with each other, and the extending directions of at least two of the first sub-grooves 723 are different.

[0136] In the embodiment of the present disclosure, the different extending directions of at least two first sub-grooves 723 can make the first groove 721 stabilize the first isolation part 101 in multiple directions. Specifically, when preparing the solder part 8 by screen printing, it is possible to prevent the first isolation part 101 from sliding in any direction due to the scraping of the squeegee 12, which affects the formation of the solder part 8.

[0137] Similarly, in the embodiment of the present disclosure, the arrangement and shape setting requirements of the second groove 722 between adjacent two solder parts 8 in different solder part groups are similar or the same as those of the first groove 721. Correspondingly, the technical effects produced by the second groove 722 on the second isolation part 102 are similar or the same as those produced by the first groove 721 on the first isolation part 101, and the embodiment of the present disclosure will not elaborate further.

[0138] It should be noted that the shapes of different first grooves 721 can be the same or different, the shapes of different second grooves 722 can be the same or different, and the shapes of the first groove 721 and the second groove 722 can be the same or different. The embodiment of the present disclosure does not limit this.

[0139] Figure 11 is a schematic plan view of a partial film layer of a light-emitting substrate in other embodiments of the present disclosure.

[0140] In some embodiments, as Figure 11 shown, the groove width W1 of the groove 72 can be set to 5 μm - 20 μm. Further, the groove width W1 of the groove 72 can be set to 5 μm - 10 μm.

[0141] It should be noted that the overall width W1 of the groove between adjacent two solder parts 8 is limited by the distance W3 between adjacent two solder parts 8. In addition, the safety distance W2 between the groove 72 and the solder part 8 needs to be considered. Obviously, the overall width of the groove 72 that can be set is after W3 - 2 * W2.

[0142] For example, in one example, as Figure 11 shown, the distance W3 between the first solder portion 81 and the second solder portion 82 in the same solder portion group is relatively small, and the specific spacing is W3 = 15.4 μm. In order to increase the adhesion between the first isolation portion 101 and the insulating layer 7, it is preferable to ensure that at least one groove 72 is formed on the upper surface of the insulating layer 7 between the first solder portion 81 and the second solder portion 82. At the same time, in order to prevent over-etching of the connection between the groove 72 and the first via 71 during etching, the spacing between the groove 72 and the first via 71 also needs to be considered, that is, the spacing between the groove 72 and the solder portion 8. For example, the minimum safety distance between the groove 72 and the first via 71 (which can be understood as the width of the insulating layer between the groove 72 and the first via 71) W2 = 2 μm - 3 μm, then the space width W1 left for the groove 72 in the middle is only about 10 μm, and at this time, the maximum width of the groove 72 is 10 μm.

[0143] For example, a groove 72 with a width of 10 μm can be specifically formed, or two grooves with a width of 4.5 μm can also be formed, and the spacing between the two grooves 72 is 1 μm.

[0144] In addition, the minimum width of the groove 72 is determined by the process limit. If the width of the groove 72 is too small, the process difficulty will be greater, which will increase the manufacturing cost. Of course, in actual production, the width of the groove 72 may also be related to parameters such as the shape and number of the groove 72, and it can be selected according to the actual situation during production.

[0145] Therefore, by selecting the groove width in the embodiments of the present disclosure, the reinforcement effect of the groove on the isolation structure 10 can be ensured while reducing the manufacturing difficulty.

[0146] In some embodiments, as Figures 5 to 7 shown, the surface of the isolation structure 10 away from the substrate 1 contacts the surface of the chip electrode 92 close to the substrate 1.

[0147] For example, in one example, as Figures 5 to 7 shown, the surface of the first isolation portion 101 away from the substrate 1 contacts the surface of the first chip electrode 921 of the same light-emitting chip 9 close to the substrate 1 and the surface of the second chip electrode 922 close to the substrate 1, respectively.

[0148] In the embodiments of the present disclosure, the first isolation portion 101 contacts the first chip electrode 921 and the second chip electrode 922 of the same light-emitting chip 9, and can completely isolate the first chip electrode 921 and the second chip electrode 922 of the same light-emitting chip 9. At the same time, since the first chip electrode 921 and the second chip electrode 922 of the same light-emitting chip 9 are electrically connected to the first solder portion 81 and the second solder portion 82 in the same solder portion group respectively, therefore, in the embodiments of the present disclosure, the first isolation portion 101 can completely isolate the first solder portion 81 and the second solder portion 82 in the same solder portion group, avoiding short circuit of the light-emitting chip 9 caused by overflow of the first solder portion 81 and the second solder portion 82.

[0149] In another example, the surface of the second isolation portion 102 away from the substrate 1 contacts the surface of the chip electrode 92 of different light-emitting chips 9 close to the substrate 1.

[0150] Similarly, in the embodiments of the present disclosure, the second isolation portion 102 can completely isolate the chip electrodes 92 of different light-emitting chips 9, and at the same time, can also completely isolate the solder portions 8 in different solder portion groups, avoiding the overflow of the solder portions 8 in different solder portion groups from affecting the light-emitting effect of the corresponding light-emitting chips 9.

[0151] In some embodiments, the orthographic projection of the chip electrode 92 on the substrate 1 and the orthographic projection of the isolation structure 10 on the substrate 1 have an overlapping area. For example, in one example, in the same light-emitting chip 9, the orthographic projection of the first chip electrode 921 on the substrate 1 overlaps with the orthographic projection of the first isolation portion 101 on the substrate 1 in the direction close to the second chip electrode 922, and the orthographic projection of the second chip electrode 922 on the substrate 1 overlaps with the orthographic projection of the first isolation portion 101 on the substrate 1 in the direction close to the first chip electrode 921. It can be understood that the first chip electrode 921 extends beyond the first solder portion 81 in the direction close to the second chip electrode 922, and the second chip electrode 922 extends beyond the second solder portion 82 in the direction close to the first chip electrode 921. In this case, the first isolation portion 101 can effectively isolate the first solder portion 81 and the second solder portion 82 located on both sides of the first isolation portion 101, thereby avoiding short circuit between the adjacent first solder portion 81 and the second solder portion 82.

[0152] It can be understood that the orthographic projection of the chip electrode 92 on the substrate 1 and the orthographic projection of the isolation structure 10 on the substrate 1 have an overlapping area, that is, the chip electrode 92 extends beyond the corresponding solder portion 8 in a certain direction. Therefore, the isolation structure 10 can prevent the solder portion 8 from overflowing in this direction.

[0153] Further, the orthographic projection of the chip electrode 92 on the substrate 1 can cover the orthographic projection of the corresponding solder portion 8 on the substrate 1. For example, the orthographic projection of the first chip electrode 921 on the substrate 1 covers and extends beyond the orthographic projection of the corresponding first solder portion 81 on the substrate 1, and the orthographic projection of the second chip electrode 922 on the substrate 1 covers and extends beyond the orthographic projection of the corresponding second solder portion 82 on the substrate 1.

[0154] In the embodiments of the present disclosure, the solder portion 8 is enclosed between the chip electrode 92 and the isolation structure 10. When the chip electrode 92 is welded to the solder portion 8, it can prevent the melted solder portion 8 from overflowing in all directions, ensuring the electrical connection relationship between the chip electrode 92 and the solder portion 8 and ensuring that the light-emitting chip 9 is maintained in the corresponding fixed position.

[0155] In some embodiments, the material of the isolation structure 10 includes an elastic material.

[0156] In the embodiments of the present disclosure, selecting an elastic material to prepare the isolation structure 10 can make the isolation structure 10 elastic. During the subsequent screen printing process of forming the solder portion 8, a first screen frame 11 needs to be placed above the isolation structure 10, and the first screen frame 11 will exert pressure on the isolation structure 10. On this basis, the thickness of the isolation structure 10 will shrink after being pressed, and the sum of the shrunk thickness and the thickness of the first screen frame 11 corresponds to the thickness of the solder portion 8 to be formed. During the screen printing process of forming the solder portion 8, the acting force between the isolation structure 10 and the first screen frame 11 can strengthen the adhesion between the isolation structure 10 and the first screen frame 11, thereby ensuring the coating effect of the solder portion 8.

[0157] Further, after the screen printing is completed, the first screen frame 11 is removed. At this time, the isolation structure 10 is no longer under pressure, so the thickness of the isolation structure 10 will rebound. The surface of the isolation structure 10 away from the substrate 1 after rebounding can be flush with the surface of the solder portion 8 away from the substrate 1, or can extend beyond the surface of the solder portion 8 away from the substrate 1. In this case, the solder portion 8 will not overflow. Adjacent solder portions 8 will also be separated by the isolation structure 10. Therefore, the embodiments of the present disclosure can completely avoid short-circuiting between two adjacent solder portions 8.

[0158] Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 12D are schematic diagrams of the respective steps in the preparation process of the light-emitting substrate in some embodiments of the present disclosure.

[0159] Correspondingly, in some embodiments, the method for preparing the light-emitting substrate of the present disclosure includes the following steps:

[0160] Step S10: As Figure 12AAs shown, a driving circuit layer, a driving trace layer, and an insulating layer 7 are sequentially formed on a substrate 1. The driving trace layer includes a plurality of connection electrodes 60. A patterning process is performed on the insulating layer 7 to form a plurality of first vias 71 in the insulating layer 7 and a plurality of grooves 72 on the surface of the insulating layer 7 away from the substrate 1. At least a part of the surface of the connection electrode 60 away from the substrate 1 is exposed by the first via 71. It can be understood that the first via 71 penetrates through the insulating layer 7, and the groove 72 does not penetrate through the insulating layer 7.

[0161] During the patterning process of the insulating layer 7, specifically, the groove 72 and the first via 71 can be formed by stepwise etching.

[0162] For example, in one example, one of the groove 72 and the first via 71 is etched by the first step of etching, and the other of the groove 72 and the first via 71 is etched by the second step of etching.

[0163] In another example, a part of the groove 72 and the first via 71 is etched by the first step of etching, and the other part of the first via 71 is etched by the second step of etching. Obviously, etching a part of the first via 71 means etching to form a groove that is not yet penetrated through the insulating layer 7 and has a depth equivalent to that of the groove 72, and etching the other part of the first via 71 is to continue etching along the groove that was not penetrated through the insulating layer 7 in the previous step to penetrate the insulating layer 7 to obtain the first via 71.

[0164] It should be noted that in order to prevent over-etching of the connection between the groove and the hole during etching, a safety distance needs to be maintained between the groove 72 closest to the first via 71 and the first via 71, and this safety distance can be 2μm - 3μm.

[0165] Similarly, in the case where the groove depth of the groove 72 on the surface of the main body 710 away from the substrate 1 is greater than the thickness of the insulating layer 7, distributed etching can also be used for the groove 72 on the surface of the main body 710 away from the substrate 1 and the first via 71.

[0166] For example, in one example, one of the groove 72 and the first via 71 is etched by the first step of etching, and the other of the groove 72 and the first via 71 is etched by the second step of etching.

[0167] In another example, a part of the groove 72 and the first via 71 are etched by the first step of etching, and the other part of the groove 72 is etched by the second step of etching.

[0168] Of course, for embodiments in which the plurality of grooves 72 have different depths, a similar etching process as in the above embodiments can also be used for preparation, and the embodiments of the present disclosure will not be elaborated herein.

[0169] Step S20: AsFigure 12B As shown, the second stencil 14 is disposed on the side of the insulating layer 7 away from the substrate 1, and the orthographic projection of the second stencil 14 on the substrate 1 covers and exceeds the orthographic projection of the first via 71 on the substrate 1. And an opening of the second stencil 14 exposes a part of the surface of the insulating layer 7 away from the substrate 1. A mixed liquid 15 capable of forming a photoresist is coated on the side of the second stencil 14 away from the substrate 1, and the excess photoresist mixed liquid 15 is removed using a squeegee 12. The remaining photoresist mixed liquid, after being processed and solidified, is the isolation structure 10.

[0170] Among them, the second stencil 14 can generally be a steel stencil. In order to avoid affecting the connection electrode 60, the stencil is disposed in the insulating layer 7.

[0171] Step S30: As Figure 12C shown, strip the second stencil 14 in step S20. At this time, the thickness H1 of the isolation structure 10 is the thickness in the natural state.

[0172] Step S40: As Figure 12D shown, the first stencil 11 is disposed on the side of the isolation structure 10 away from the substrate 1, and the orthographic projection of the first stencil 11 on the substrate 1 coincides with the orthographic projection of the isolation structure 10 on the substrate 1. At this time, since the isolation structure 10 is made of an elastic material, the thickness of the isolation structure 10 will be compressed to a certain extent under the gravity of the first stencil 11 and other mechanical external forces, and the thickness changes from Figure 12C H1 in Figure 12D to H2 in

[0173] That is, H2 < H1. Further, solder paste 13 is coated on the side of the first stencil 11 away from the substrate 1, and the excess solder paste 13 is scraped off using a squeegee 12. The remaining solder paste 13 is the solder portion 8, which is electrically connected to the connection electrode 60 through the first via 71.

[0174] After stripping the first stencil 11, the thickness of the isolation structure 10 will rebound. After rebounding, the surface of the isolation structure 10 away from the substrate 1 can be flush with the surface of the solder portion 8 away from the substrate 1, or can exceed the surface of the solder portion 8 away from the substrate 1 by a certain height.

[0175] Figure 13 is a schematic cross-sectional structure diagram of an intermediate light-emitting substrate in some embodiments of the present disclosure. The intermediate light-emitting substrate refers to the light-emitting substrate obtained after a certain manufacturing process is completed during the manufacturing process.

[0176] In some embodiments, as Figure 13As shown, the upper surface of the isolation structure 10 away from the substrate 1 after springback may be higher than the upper surface of the solder part 8 away from the substrate 1 by a certain height, and the height difference ΔH can be 1-10 μm. For example, specifically, it can be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm, etc. Finally, the light-emitting chip 9 is welded to the solder part 8 to obtain the light-emitting substrate. The light-emitting chip 9 can exert a certain pressure on the isolation structure 10, or a certain pressure can be exerted on the isolation structure 10 by other external forces during the process of welding the light-emitting chip 9 to the solder part 8, so that the thickness of the isolation structure 10 decreases after being compressed. In the final light-emitting substrate product, the surface of the solder part 8 away from the substrate 1 is flush with the surface of the isolation structure 10 away from the substrate 1.

[0177] In the embodiments of the present disclosure, using an elastic material to prepare the isolation structure 10 can avoid the solder paste 13 from overflowing between adjacent solder parts 8 during the process of coating and forming the solder part 8, resulting in short circuits between adjacent solder parts 8.

[0178] Obviously, based on the above description, it can be understood that in some embodiments, the surface of the solder part 8 away from the substrate 1 is flush with the surface of the isolation structure 10 away from the substrate 1, and the isolation structure 10 is in a compressed state. Of course, it can be understood that there may be a situation where the isolation structure 10 is not in a compressed state.

[0179] For example, the surface of the solder part 8 in the same solder part group away from the substrate 1 is flush with the surface of the first isolation part 101 away from the substrate 1, and the first isolation part 101 is in a compressed state. The surface of the solder part 8 in different solder part groups away from the substrate 1 is flush with the surface of the second isolation part 102 away from the substrate 1, and the second isolation part 102 is in a compressed state.

[0180] At least part of the compression structure 10 is in a compressed state, for example, it includes the case where a part of the isolation structure 10 is in a possible compressed state, and the case where the entire isolation structure 10 is in a compressed state. For example, in multiple embodiments where the isolation structure 10 only includes multiple first compression parts 101, in one example, a part of the multiple first compression parts 101 is in a compressed state, that is, a part of the isolation structure 10 is in a possible compressed state. In another example, each first compression part 101 is in a compressed state, that is, the entire isolation structure 10 is in a compressed state.

[0181] In the embodiments of the present disclosure, after the solder part 8 is coated by screen printing, the surface of the isolation structure 10 away from the substrate 1 after rebounding can be higher than the surface of the solder part 8 away from the substrate 1. After the subsequent welding of the light-emitting chip 9 and the solder part 8 is completed, since the light-emitting chip 9 is disposed on the upper layer of the isolation structure 10, therefore, under the action of the light-emitting chip 9, the thickness of the isolation structure 10 will be reduced to a certain extent, that is, the isolation structure 10 is in a compressed state, and in the final light-emitting substrate, the surface of the solder part 8 away from the substrate 1 is flush with the surface of the isolation structure 10 away from the substrate 1.

[0182] In some embodiments, as Figure 7 shown, the orthographic projection of the insulating layer 7 on the substrate 1 covers and exceeds the orthographic projection of the isolation structure 10 on the substrate 1, and the width D1 of the exceeding part is 1 μm - 5 μm, for example, it can specifically be 1 μm, 2 μm, 3 μm, 4 μm or 5 μm, etc.

[0183] Generally, in each direction parallel to the substrate 1, the orthographic projection of the insulating layer 7 on the substrate 1 exceeds the orthographic projection of the isolation structure 10 on the substrate 1. It can be understood that the part where the orthographic projection of the insulating layer 7 on the substrate 1 exceeds the orthographic projection of the isolation structure 10 on the substrate 1 includes a plurality of annular projection regions, and the ring width of the annular projection regions is 1 μm - 5 μm. It should be noted that the specific shape of the annular projection regions is not limited in the embodiments of the present disclosure.

[0184] For example, as Figure 7 shown, the orthographic projection of the first part 701 on the substrate 1 covers and exceeds the orthographic projection of the first isolation part 101 on the substrate 1, and the ring width D1 of the exceeding part is 1 μm - 5 μm.

[0185] Similarly, the orthographic projection of the second part 702 on the substrate 1 covers and exceeds the orthographic projection of the second isolation part 102 on the substrate 1, and the ring width of the exceeding part is 1 μm - 5 μm.

[0186] Combined with the steps of the method for preparing the light-emitting substrate in the foregoing embodiments, it can be known that a part of the insulating layer 7 exceeding the isolation structure 10 in the embodiments of the present disclosure is for facilitating the placement of the first screen frame 11 on the exceeding part of the insulating layer 7 during the process of forming the isolation structure 10 by screen printing. Specifically, the first screen frame 11 can cover the first via 71 and the exceeding part of the insulating layer 7, and the other part of the insulating layer 7 exposed by the opening on the first screen frame 11 is the formation position of the isolation structure 10.

[0187] In some embodiments, the elastic material includes acrylic resin, curing agent and dispersant, wherein the mass proportion of acrylic resin is 60%-96%, the mass proportion of curing agent is 0.1%-4%, and the mass proportion of dispersant is 0.1%-10%.

[0188] The photoresist formed by the acrylic resin, curing agent and dispersant in a certain mass ratio in the embodiment of the present disclosure has good elasticity and is easy to be coated to form the isolation structure 10.

[0189] Specifically, in some embodiments, the raw materials for preparing the elastic material may include 40%-90% ether or ester solvents, 5%-30% acrylate monomers, 5%-10% acrylate polymers, 0.1%-2% polymer resin dispersants, and 0.1%-5% curing initiators such as triphenylsulfonium salts, where the percentages refer to the mass ratio.

[0190] After the liquid mixture of the above materials is coated on the side of the insulating layer 7 away from the base substrate 1, the acrylate monomers and acrylate polymers may volatilize, leaving the acrylic resin formed by the acrylate polymer, as well as at least part of the curing agent and at least part of the dispersant.

[0191] Optionally, the elastic modulus of the elastic material is 0.1 GPa-10 GPa. The disclosed embodiment can adjust the elastic modulus of the elastic material by the mass proportion of each part of the elastic material. Generally speaking, in order to ensure that the isolation structure 10 has sufficient elasticity, the elastic modulus of the elastic material is as small as possible.

[0192] In addition, in order to prevent the elastic material from being too elastic and causing the isolation structure 10 to be too deformed during the process of being squeezed by the first mesh frame 11, thereby affecting the coating of the solder paste 13, particles such as acrylic and silicon balls can be added to the elastic material to control the lowest height of the elastic structure being compressed. That is, in some embodiments, the material of the isolation structure 10 includes an elastic material and hard particles located inside the elastic material.

[0193] It should be noted that hard particles can be understood as particles that do not deform or undergo small deformation when subjected to force, so as to achieve a supporting or spacer effect.

[0194] In the disclosed embodiment, by doping hard particles into the elastic material, it is possible to prevent the isolation structure 10 from being too thin after being compressed by the first screen frame 11 during the subsequent screen printing process of forming the solder portion 8, and from undergoing a large horizontal deformation, causing the isolation structure 10 to enter the first via 71 and affect the formation of the solder portion 8.

[0195] In some embodiments, the material of the hard particles includes at least one of acrylic particles, calcium carbonate particles, and silicon spheres. The particle size of the hard particles is in the range of 10 μm - 50 μm. For example, the particle size of the hard particles can be 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, or 50 μm, etc. Further, considering that the distance between adjacent chip electrodes 92 of some light-emitting chips 9 is small, that is, correspondingly, the distance between two adjacent solder parts 8 in the same solder part group is small. To facilitate the filling of the hard particles into the position of the isolation structure 10, it is preferred that the particle size of the hard particles is in the range of 10 μm - 20 μm.

[0196] It can be understood that the selection of the particle size is related to the distance between two adjacent solder parts 8. When the distance between two adjacent solder parts 8 is large, for example, the distance is 60 μm, hard particles with a particle size of 10 μm - 50 μm can be selected. When the distance between two adjacent solder parts 8 is small, for example, the distance is 15 μm, hard particles with a particle size of 10 μm - 12 μm need to be selected.

[0197] In the embodiments of the present disclosure, setting the minimum height of the hard particles can ensure the minimum thickness of the isolation structure 10 compressed by the first screen frame 11 during the process of screen printing to form the solder part 8. Further, the sum of this minimum thickness and the thickness of the first screen frame 11 can correspondingly be the thickness of the solder paste 13 coated in the first via 71 after being scraped by the squeegee 12. Therefore, the hard particles can act as a supporting spacer, so as to ensure the minimum support for the stencil after applying the stencil, and further avoid the pressure difference of the isolation structure 10 at different positions caused by different pressures of the stencil on the isolation structure 10 at different positions, resulting in too large a difference in the compressed deformation thickness at different positions of the isolation structure 10, leading to unevenness of the light-emitting surface of the light-emitting chip 9.

[0198] In some embodiments, for example, as Figure 7 shown, the maximum thickness H4 of the solder part 8 is in the range of 50 μm - 80 μm. In some embodiments, the maximum thickness H3 of the isolation structure 10 is in the range of 50 μm - 80 μm. Further, the maximum thickness H4 of the solder part 8 can be higher than the thickness of the insulating layer 7 by the maximum thickness H3 of the solder part 8.

[0199] The present disclosure also provides a display device, including a light-emitting substrate as described in any embodiment of the present disclosure.

[0200] In some embodiments, the light-emitting substrate in the display device is a display substrate. In the embodiments of the present disclosure, the light-emitting substrate includes a plurality of light-emitting chips 9. Among them, the color light emitted by the light-emitting chips 9 includes a variety of colors, for example, including red light, green light, and blue light.

[0201] Figure 14It is a schematic cross-sectional structure diagram of a light-emitting substrate in some other embodiments of the present disclosure.

[0202] Specifically, as Figure 14 shown, the chip body 91 of the light-emitting chip 9 includes a multi-quantum well (MQW) 912 and an electrode connection portion 911 that are respectively electrically connected to two chip electrodes 92. Optionally, the electrode connection portion 911 can be metal.

[0203] As Figure 14 shown, the light-emitting chip 9 further includes a conductive layer 913 and a second buffer layer 914 that are located on the side of the multi-quantum well 912 and the electrode connection portion 911 away from the chip electrode 92 and are stacked in sequence along the direction away from the chip electrode 92. Among them, the material of the conductive layer 913 can specifically include n-type GaN, and the material of the second buffer layer 914 can specifically include GaN.

[0204] As Figure 14 shown, the light-emitting chip 9 further includes a pixel defining layer 917 (bank) located on the side of the second buffer layer 914 away from the chip electrode 92. The pixel defining layer 917 is provided with a pixel opening, and a light-emitting layer 918 containing quantum dots is arranged in the pixel opening.

[0205] As Figure 14 shown, the light-emitting chip 9 further includes a light-shielding layer 919 located on the side of the pixel defining layer away from the chip electrode 92. The light-shielding layer can be a black matrix, for example. The black matrix is provided with a light-transmitting opening, and the light-transmitting opening is arranged opposite to the pixel opening. And a color filter portion 9111 is arranged in the light-transmitting opening. Among them, the color filter portion 9111 can transmit light of the same color as the light-emitting layer 918.

[0206] As Figure 14 shown, the light-emitting chip 9 further includes a third passivation layer 916 located between the pixel defining layer 917 and the second buffer layer 914 and an adhesive layer 915 located between the third passivation layer 916 and the second buffer layer 914. Among them, the material of the third passivation layer 916 can include SiNx, for example.

[0207] As Figure 14 shown, the light-emitting chip 9 further includes a protective layer 9110 located on the side of the light-shielding layer 919 and the color filter portion 9111 away from the chip electrode 92. The material of the protective layer 9110 can include Si.

[0208] In the embodiments of the present disclosure, the multi-quantum well and the quantum dots can enhance the light-emitting effect of the light-emitting chip 9, ensure the color gamut of the color light, and improve the display effect of the entire display substrate.

[0209] In some other embodiments, the light-emitting substrate in the display device is a backlight substrate, and the display device further includes a liquid crystal display panel on one side of the light-emitting surface of the light-emitting substrate. In the embodiments of the present disclosure, the light emitted by the light-emitting chip 9 is white light.

[0210] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present disclosure. However, the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the present disclosure.

Claims

1. A light-emitting substrate, characterized in that: include: substrate substrate; A driving wiring layer, located on one side of the base substrate, the driving wiring layer includes a plurality of connecting electrodes, the plurality of connecting electrodes include a plurality of connecting electrode groups, and the connecting electrode group includes at least two connecting electrodes; An insulating layer, located at a side of the driving wiring layer away from the substrate, the insulating layer is provided with a plurality of via holes, and the plurality of via holes expose the connecting electrodes; A plurality of solder portions, located on a side of the insulating layer away from the base substrate, the plurality of solder portions including a plurality of solder portion groups, the solder portion group including at least two solder portions, the solder portions in the same solder portion group being electrically connected to the connection electrodes in the same connection electrode group through the via holes; A plurality of light-emitting chips are located on a side of the solder portion away from the base substrate, and the light-emitting chips are electrically connected to the solder portions in the same solder portion group; The isolation structure is located between the insulating layer and the light-emitting chip, and the isolation structure at least includes a first isolation portion, and the first isolation portion is located between two adjacent solder portions in the same solder portion group.

2. The light-emitting substrate according to claim 1, characterized in that: The isolation structure further includes a second isolation portion, wherein the second isolation portion is located between two adjacent solder portions in different solder portion groups; The first isolation portion and the second isolation portion together surround at least one solder portion in the solder portion group.

3. The light-emitting substrate according to claim 2, characterized in that: The light emitting chip is disposed in contact with the first isolation portion, or the light emitting chip is disposed in contact with both the first isolation portion and the second isolation portion.

4. The light-emitting substrate according to any one of claims 1 to 3, characterized in that: The surface of the insulating layer away from the base substrate has at least one groove, and the at least one groove includes at least one first groove of the surface of the insulating layer away from the base substrate located between two adjacent solder parts in the same solder part group, and a part of the first isolation part is located in the first groove.

5. The light-emitting substrate according to claim 4, characterized in that: A first spacing groove is provided between two adjacent connecting electrodes in the same connecting electrode group; The insulating layer comprises a first main body portion which is arranged opposite to the first spacing groove and at least partially located in the first spacing groove, and a first extension portion which is located at a side of the connecting electrode away from the base substrate and connected to the first main body portion; The at least one first groove includes at least one first type groove located in the first main body away from the surface of the substrate substrate and at least one second type groove located in the first extension part away from the surface of the substrate substrate, wherein the groove depth of the first type groove is greater than the groove depth of the second type groove.

6. The light emitting substrate according to claim 4, characterized in that: The isolation structure further includes a second isolation portion, and the at least one groove further includes at least one second groove located between two adjacent solder portions in different solder portion groups and away from the surface of the substrate of the insulating layer, and a portion of the second isolation portion is located in the second groove.

7. The light-emitting substrate according to claim 6, characterized in that: A second spacing groove is provided between two adjacent connecting electrodes in different connecting electrode groups; The insulating layer comprises a second main body portion which is arranged opposite to the second spacing groove and at least partially located in the second spacing groove, and a second extension portion which is located at a side of the connecting electrode away from the base substrate and connected to the second main body portion; The at least one second groove includes at least one third type groove located in the second main body portion away from the surface of the substrate substrate and at least one fourth type groove located in the second extension portion away from the surface of the substrate substrate, wherein the groove depth of the third type groove is greater than the groove depth of the fourth type groove.

8. The light-emitting substrate according to claim 4, characterized in that: A plurality of grooves located between two adjacent solder portions are arranged along a first direction, wherein the grooves extend along a second direction, and the second direction intersects the first direction; Alternatively, the groove comprises a plurality of interconnected sub-grooves, wherein at least two of the sub-grooves extend in different directions; Alternatively, the plurality of grooves between two adjacent solder portions are arranged in a plurality of rows, and the plurality of grooves in two adjacent rows are arranged in a staggered manner.

9. The light-emitting substrate according to claim 4, characterized in that: The maximum groove depth of the groove is not less than 50 nm, and / or the ratio of the maximum groove depth of the groove to the thickness of the insulating layer is not more than 80%.

10. The light emitting substrate according to any one of claims 1 to 3, characterized in that: The orthographic projection of the insulating layer on the base substrate covers and exceeds the orthographic projection of the isolation structure on the base substrate.

11. The light emitting substrate according to any one of claims 1 to 3, characterized in that: The light emitting chip comprises a chip body and at least two chip electrodes located on a side of the chip body close to the base substrate, wherein the chip electrodes are electrically connected to the solder portion; A surface of the isolation structure away from the substrate is in contact with a surface of the chip electrode close to the substrate.

12. The light-emitting substrate according to any one of claims 1 to 3, characterized in that: The maximum thickness of the solder portion is within the range of 50 μm to 80 μm, and / or the maximum thickness of the isolation structure is within the range of 50 μm to 80 μm.

13. The light-emitting substrate according to any one of claims 1 to 3, characterized in that: The material of the isolation structure includes elastic material.

14. The light emitting substrate according to claim 13, characterized in that: At least a portion of the isolation structure is in a compressed state.

15. The light emitting substrate according to claim 13, characterized in that: The elastic material comprises acrylic resin, curing agent and dispersant; The mass proportion of the acrylic resin is 60%-96%, the mass proportion of the curing agent is 0.1%-4%, and the mass proportion of the dispersant is 0.1%-10%.

16. The light emitting substrate according to claim 13, characterized in that: The material of the isolation structure includes an elastic material and hard particles located inside the elastic material.

17. The light emitting substrate according to claim 16, characterized in that: The material of the hard particles includes at least one of acrylic particles, calcium carbonate particles and silicon balls, and the particle size of the hard particles is in the range of 10 μm-50 μm.

18. A display device, characterized in that: A light-emitting substrate comprising any one of claims 1 to 17; Wherein, the light-emitting substrate is a display substrate, Alternatively, the light-emitting substrate is a backlight substrate, and the display device further comprises a liquid crystal display panel located on a side of a light-emitting surface of the light-emitting substrate.

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