Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a substrate; a plurality of driving circuits on the substrate, each driving circuit comprising a driving transistor and at least one auxiliary transistor; wherein the grid electrode of the auxiliary transistor and the grid electrode of the driving transistor are connected and arranged on the same layer, and the active part of the auxiliary transistor and the active part of the driving transistor are connected and arranged on the same layer. According to the technical scheme, the display effect of the display panel is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the development of display technologies, people have higher and higher requirements for the display performance of display panels.

[0003] Currently, the display effect of display panels is poor and cannot meet the requirements for high-quality displays. Summary of the Invention

[0004] Embodiments of the present invention provide a display panel and a display device to improve the display effect of the display panel.

[0005] According to one aspect of the present invention, a display panel is provided, including:

[0006] A substrate;

[0007] A plurality of driving circuits located on the substrate, the driving circuit including a driving transistor and at least one auxiliary transistor;

[0008] Wherein, the gate of the auxiliary transistor is connected to the gate of the driving transistor and they are arranged in the same layer, and the active part of the auxiliary transistor is connected to the active part of the driving transistor and they are arranged in the same layer.

[0009] Optionally, the active part of the auxiliary transistor is located on at least one of the two opposite sides of the active part of the driving transistor along a first direction;

[0010] Optionally, the display panel includes scan lines extending along the first direction;

[0011] Optionally, at least one auxiliary transistor includes a first auxiliary transistor and a second auxiliary transistor, the active parts of the first auxiliary transistor and the second auxiliary transistor are located on the same side of the two opposite sides of the active part of the driving transistor along the first direction, and the active parts of the first auxiliary transistor and the second auxiliary transistor are connected and arranged in the same layer;

[0012] Optionally, the active parts of the first auxiliary transistor and the second auxiliary transistor are arranged along a second direction, and the second direction intersects with the first direction;

[0013] Optionally, at least part of the active part of the first auxiliary transistor and at least part of the active part of the second auxiliary transistor are located on the two opposite sides of the active part of the driving transistor along the second direction;

[0014] Optionally, the display panel includes data lines that extend in the second direction; optionally, an integrated structure formed by the active portions of the first auxiliary transistor, the active portion of the second auxiliary transistor, and the active portion of the driving transistor on a side close to the active portion of the first auxiliary transistor is in a T shape; optionally, at least a part of the active portion of the driving transistor is in an "Ω" shape or a Z shape.

[0015] Optionally, the driving circuit further includes a switching transistor, and the active portion of the switching transistor is located on a side of the active portion of the auxiliary transistor away from the active portion of the driving transistor.

[0016] An integrated structure formed by the active portion of the auxiliary transistor and the active portion of the switching transistor is in a broken line or a curve. In the same driving circuit, the active portion of the auxiliary transistor is closer to the central axis extending in the second direction of the driving circuit than the active portion of the switching transistor along the first direction; the active portion of the switching transistor extends in the second direction.

[0017] Optionally, at least one auxiliary transistor includes a first auxiliary transistor and / or a second auxiliary transistor.

[0018] The driving circuit further includes a data writing transistor and / or a first light emission control transistor; the display panel further includes a first power supply line and / or a data signal line, and the data writing transistor is electrically connected to the data signal line; the first light emission control transistor is electrically connected to the first power supply line.

[0019] Wherein, the active portion of the data writing transistor is connected to the active portion of the driving transistor through the active portion of the first auxiliary transistor; the active portion of the first light emission control transistor is connected to the active portion of the driving transistor through the active portion of the second auxiliary transistor.

[0020] Optionally, the active portion of the data writing transistor and / or the active portion of the first light emission control transistor are / is disposed on the same layer as the active portion of the driving transistor; wherein, the active portion of the data writing transistor, the active portion of the first auxiliary transistor, and the active portion of the second auxiliary transistor are arranged in sequence along the second direction, and / or, the active portion of the first auxiliary transistor, the active portion of the second auxiliary transistor, and the active portion of the first light emission control transistor are arranged in sequence along the second direction.

[0021] Optionally, an integrated structure formed by the active portion of the first auxiliary transistor and the active portion of the data writing transistor is in a broken line or a curve. In the same driving circuit, the active portion of the first auxiliary transistor is closer to the central axis extending in the second direction of the driving circuit than the active portion of the data writing transistor along the first direction; and / or, an integrated structure formed by the active portion of the second auxiliary transistor and the active portion of the first light emission control transistor is in a broken line or a curve. In the same driving circuit, the active portion of the second auxiliary transistor is closer to the central axis extending in the second direction of the driving circuit than the active portion of the first light emission control transistor along the first direction.

[0022] Optionally, the active portions of the first auxiliary transistor and the second auxiliary transistor extend along the second direction and are collinear, and / or the active portions of the data writing transistor and the first light emission control transistor extend along the second direction and are collinear;

[0023] Optionally, in the same driving circuit, the gates of the driving transistor and the auxiliary transistor form a common gate structure.

[0024] In the same driving circuit, the active portions of the driving transistor and the auxiliary transistor form a common active structure.

[0025] The display panel includes a plurality of driving units, and each driving unit includes two adjacent driving circuits arranged along the first direction. In the same driving unit, in the first direction, the active portions of the auxiliary transistors in the two driving circuits are located between the active portions of the two driving transistors.

[0026] In the same driving unit, in the first direction, the pitch along the first direction between the two common gate structures in the two driving circuits is less than or equal to the pitch along the first direction between the active portions of the two data writing transistors.

[0027] In the same driving unit, in the first direction, the pitch along the first direction between the two common active structures in the two driving circuits is greater than the pitch along the first direction between the active portions of the two data writing transistors.

[0028] In the same driving unit, in the first direction, the pitch along the first direction between the two common gate structures in the two driving circuits is less than or equal to the pitch along the first direction between the active portions of the two first light emission control transistors.

[0029] In the same driving unit, in the first direction, the pitch along the first direction between the two common active structures in the two driving circuits is greater than the pitch along the first direction between the active portions of the two first light emission control transistors.

[0030] Optionally, at least one auxiliary transistor includes a first auxiliary transistor and / or a second auxiliary transistor.

[0031] The length of the channel region of the active portion of the first auxiliary transistor is equal to the length of the channel region of the active portion of the second auxiliary transistor; and / or the width of the channel region of the active portion of the first auxiliary transistor is equal to the width of the channel region of the active portion of the second auxiliary transistor.

[0032] Optionally, the width of the channel region of the active portion of the driving transistor is equal to the widths of the channel regions of the active portions of the first auxiliary transistor and the second auxiliary transistor.

[0033] Optionally, at least a portion of the length of the channel region of the active portion of the first auxiliary transistor is a dimension along the second direction, and at least a portion of the length of the channel region of the active portion of the second auxiliary transistor is a dimension along the second direction.

[0034] And / or, at least part of the width of the channel region of the active portion of the first auxiliary transistor is a dimension along the first direction, and at least part of the width of the channel region of the active portion of the second auxiliary transistor is a dimension along the first direction, and the first direction and the second direction intersect.

[0035] Optionally, in the same driving circuit, the gate of the driving transistor and the gate of the auxiliary transistor form a common gate structure.

[0036] In the same driving circuit, the active part of the driving transistor and the active part of the auxiliary transistor form a common active structure.

[0037] In the same driving circuit, the spacing along the first direction between the orthographic projection of the common gate structure on the substrate and the orthographic projection of the common active structure on the substrate close to the same side boundary of the auxiliary transistor is greater than or equal to 2 micrometers; the boundary of the orthographic projection of the common gate structure on the substrate close to the auxiliary transistor is farther away from the central axis of the driving circuit extending along the second direction than the boundary of the orthographic projection of the common active structure on the substrate close to the auxiliary transistor;

[0038] And / or, the display panel includes a plurality of driving units, each driving unit includes two driving circuits arranged in a first direction and adjacent to each other, and in the same driving unit, in the first direction, active portions of the auxiliary transistors in the two driving circuits are located between active portions of the two driving transistors;

[0039] In the same driving unit, in the first direction, the spacing between two common gate structures in two driving circuits along the first direction is smaller than the spacing between two common active structures along the first direction;

[0040] In the same driving unit, in the first direction, a spacing between common gate structures in two driving circuits along the first direction is greater than or equal to 2 micrometers;

[0041] In the same driving unit, the spacing between the common active structures in the two driving circuits along the first direction is greater than or equal to 6 micrometers;

[0042] Optionally, in the same driving unit, two adjacent driving circuits arranged along the first direction are mirror-symmetrical.

[0043] Optionally, the driving circuit further includes a second initialization transistor, and the display panel further includes a second initialization voltage transmission line, and the second initialization voltage transmission line is electrically connected to the first electrode of the light-emitting element through the second initialization transistor;

[0044] The driving circuit further includes a first initialization transistor, and the display panel further includes a first gate control signal transmission line connected to the first gate of the first initialization transistor, and / or a second gate control signal transmission line connected to the second gate of the first initialization transistor;

[0045] The second initialization voltage transmission line and the first gate control signal transmission line have at least a partial overlap in the positive projection on the substrate, and / or the second initialization voltage transmission line and the second gate control signal transmission line have at least a partial overlap in the positive projection on the substrate;

[0046] Optionally, in the same driving circuit, the first gate control signal transmission line is connected to the second gate control signal transmission line; the first gate and the second gate of the first initialization transistor are located on opposite sides of the active portion of the first initialization transistor along the thickness direction of the substrate;

[0047] Optionally, the first gate control signal transmission line, the second gate control signal transmission line, and the second initialization voltage transmission line extend along a first direction;

[0048] Optionally, the driving circuit further includes a third initialization transistor, and the display panel further includes a third initialization voltage transmission line;

[0049] Wherein, the auxiliary transistor includes a second auxiliary transistor, the third initialization voltage transmission line is connected to the first pole of the third initialization transistor, and the second pole of the third initialization transistor is connected to the driving transistor through the second auxiliary transistor;

[0050] Optionally, the third initialization voltage transmission line extends along the first direction, and at least a part of the third initialization voltage transmission line is in a zigzag shape or a curved shape;

[0051] Optionally, the third initialization voltage transmission lines in two adjacent driving circuits along the first direction include a first sub-segment, a second sub-segment, and a third sub-segment extending along the first direction; and a fourth sub-segment and a fifth sub-segment extending along a second direction and arranged along the first direction; wherein, the first sub-segment, the fourth sub-segment, the second sub-segment, the fifth sub-segment, and the third sub-segment are connected in sequence;

[0052] The first direction intersects with the second direction;

[0053] Optionally, the display panel further includes a first initialization voltage transmission line, and the first initialization voltage transmission line is electrically connected to the gate of the driving transistor through the first initialization transistor;

[0054] The first initialization voltage transmission line extends along the first direction;

[0055] The orthographic projection of the first initialization voltage transmission line on the substrate overlaps with the orthographic projection of the third initialization voltage transmission line, and the orthographic projection of the first initialization voltage transmission line on the substrate does not overlap with the orthographic projection of the third initialization voltage transmission line;

[0056] Optionally, the first sub-segment of the third initialization voltage transmission line overlaps at least partially with the orthographic projection of the first initialization voltage transmission line on the substrate; and / or, the third sub-segment of the third initialization voltage transmission line overlaps at least partially with the orthographic projection of the first initialization voltage transmission line on the substrate;

[0057] Optionally, the second sub-segment of the third initialization voltage transmission line does not overlap at least partially with the orthographic projection of the first initialization voltage transmission line on the substrate;

[0058] Optionally, the second sub-segment of the third initialization voltage transmission line does not overlap with the orthographic projection of the first initialization voltage transmission line on the substrate;

[0059] Or, the width of the overlapping region of the first sub-segment of the third initialization voltage transmission line and the orthographic projection of the first initialization voltage transmission line on the substrate in the second direction is greater than the width of the overlapping region of the second sub-segment of the third initialization voltage transmission line and the orthographic projection of the first initialization voltage transmission line on the substrate in the second direction,

[0060] and / or, the width of the overlapping region of the third sub-segment of the third initialization voltage transmission line and the orthographic projection of the first initialization voltage transmission line on the substrate in the second direction is greater than the width of the overlapping region of the second sub-segment of the third initialization voltage transmission line and the orthographic projection of the first initialization voltage transmission line on the substrate in the second direction;

[0061] Optionally, the second sub-segment overlaps with the orthographic projection of the active part of the third initialization transistor on the substrate and is connected through vias in the overlapping region;

[0062] Optionally, multiple second sub-segments are arranged at intervals along the first direction;

[0063] Optionally, the display panel includes multiple driving units, and each driving unit includes two adjacent driving circuits arranged along the first direction. In the same driving unit, the second sub-segment is connected between the active parts of two third initialization transistors;

[0064] Optionally, the display panel further includes a control signal transmission line connected to the gate of the third initialization transistor; the control signal transmission line connected to the gate of the third initialization transistor extends along the first direction;

[0065] Optionally, the orthographic projection of the control signal transmission line connected to the gate of the third initialization transistor on the substrate overlaps at least partially with the orthographic projection of the first initialization voltage transmission line on the substrate;

[0066] Optionally, in the thickness direction of the substrate, the first initialization voltage transmission line is located between the third initialization voltage transmission line and the control signal transmission line connected to the gate of the third initialization transistor;

[0067] Optionally, the driving circuit further includes a second light-emitting control transistor, and the second light-emitting control transistor is connected between the first pole of the light-emitting element and the second pole of the driving transistor.

[0068] Optionally, the driving circuit further includes a compensation transistor and / or a first initialization transistor; the compensation transistor is connected between the second pole and the gate of the driving transistor; the first initialization transistor is electrically connected to the gate of the driving transistor;

[0069] Optionally, the active part of the compensation transistor and the active part of the driving transistor are arranged in different layers, and / or the active part of the first initialization transistor and the active part of the driving transistor are arranged in different layers. Optionally, the active parts of the compensation transistor and the first initialization transistor are connected and arranged in the same layer; Optionally, the film layer where the active part of the compensation transistor and / or the active part of the first initialization transistor is located is on the side away from the substrate of the film layer where the active part of the driving transistor is located; Optionally, the active part of the compensation transistor and / or the active part of the first initialization transistor includes a metal oxide semiconductor material, and the active part of the driving transistor includes a polysilicon semiconductor material.

[0070] Optionally, the driving circuit further includes a storage capacitor, and the storage capacitor includes a first electrode plate, and the first electrode plate multiplexes the gates of the driving transistor and the auxiliary transistor; Optionally, the storage capacitor further includes a second electrode plate, and the second electrode plates of the storage capacitors in the driving circuit arranged adjacent to each other along the second direction are connected.

[0071] According to another aspect of the present invention, a display panel is provided, including:

[0072] A substrate;

[0073] A plurality of driving circuits located on the substrate, and the driving circuit includes a driving transistor, a first initialization transistor and a third initialization transistor connected to the driving transistor;

[0074] A first initialization voltage transmission line and a third initialization voltage transmission line; the first initialization voltage transmission line is connected to the first initialization transistor; the third initialization voltage transmission line is connected to the third initialization transistor;

[0075] Among them, the first initialization voltage transmission line extends along the first direction, the third initialization voltage transmission line extends along the first direction, and at least a part of the third initialization voltage transmission line is in a zigzag or curved shape; a part of the positive projection of the first initialization voltage transmission line and the third initialization voltage transmission line on the substrate overlaps, and a part of the positive projection of the first initialization voltage transmission line and the third initialization voltage transmission line on the substrate does not overlap.

[0076] According to another aspect of the present invention, a display device is provided, and the display device includes the display panel provided in any embodiment of the present invention.

[0077] The technical solution provided by the embodiment of the present invention is to set at least one auxiliary transistor in the driving circuit, and set the gate of the auxiliary transistor to be connected to the gate of the driving transistor and arranged in the same layer, and the active part of the auxiliary transistor to be connected to the active part of the driving transistor and arranged in the same layer. It is equivalent to setting a gate extension part on one side of the gate of the driving transistor, and setting the vertical projection of the gate extension part on the first active layer to cover the first pole of the driving transistor, so that an auxiliary transistor can be additionally formed at the first pole of the driving transistor, equivalently increasing the size of the channel region of the driving transistor, making the variation amplitude of the gray-scale voltage of the display panel conform to the voltage regulation amplitude of the driving chip, thereby obtaining a better gray-scale expansion effect and improving the display effect of the display panel; there is no need to increase the size of the channel region of the driving transistor by expanding the size of the first active layer where the channel region of the driving transistor is located, which is beneficial to the development trend of high resolution of the display panel.

[0078] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Description of the Drawings

[0079] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0080] Figure 1 is a layout structure schematic diagram of a display panel provided by an embodiment of the present invention;

[0081] Figure 2 is Figure 1 a schematic cross-sectional structure diagram of the structure shown along AA1;

[0082] Figure 3 is a layout structure schematic diagram of a display panel provided in the related art;

[0083] Figure 4 is Figure 3 Schematic cross-sectional structure diagram of the structure shown along BB1;

[0084] Figure 5 is Figure 1 Schematic contour diagram of the channel region of the driving transistor and the channel region of the first auxiliary transistor in the structure;

[0085] Figure 6 is Figure 1 Schematic contour diagram of the channel region of the driving transistor and the channel region of the second auxiliary transistor in the structure;

[0086] Figure 7 Schematic layout structure diagram of another display panel provided by an embodiment of the present invention;

[0087] Figure 8 Schematic layout structure diagram of another display panel provided by an embodiment of the present invention;

[0088] Figure 9 is Figure 8 Schematic cross-sectional structure diagram of the structure shown along CC1;

[0089] Figure 10 Schematic layout structure diagram of another display panel provided by an embodiment of the present invention;

[0090] Figure 11 Schematic layout structure diagram of another display panel provided by an embodiment of the present invention;

[0091] Figure 12 Schematic layout structure diagram of another display panel provided by an embodiment of the present invention;

[0092] Figure 13 is Figure 12 Schematic cross-sectional structure diagram of the structure shown along DD1;

[0093] Figure 14 Circuit diagram of a driving circuit provided by an embodiment of the present invention;

[0094] Figure 15 Schematic layout structure diagram of another display panel provided by an embodiment of the present invention;

[0095] Figure 16 Circuit diagram of another driving circuit provided by an embodiment of the present invention;

[0096] Figure 17 Location diagram of different types of connection holes in a display panel provided by an embodiment of the present invention;

[0097] Figure 18It is a schematic diagram of the layout structure of another display panel provided by an embodiment of the present invention;

[0098] Figure 19 It is Figure 18 A schematic cross-sectional structure diagram of the shown structure along EE1;

[0099] Figure 20 It is Figure 18 A schematic cross-sectional structure diagram of the shown structure along FF1;

[0100] Figure 21 It is Figure 18 An enlarged view of region N1 in the shown structure;

[0101] Figure 22 It is a schematic diagram of the layout structure of another display panel provided by an embodiment of the present invention;

[0102] Figure 23 It is a schematic diagram of the layout structure of another display panel provided by an embodiment of the present invention. Detailed implementation manners

[0103] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. In addition, it should be noted that, for the sake of convenience of description, only parts related to the present invention rather than all structures are shown in the drawings.

[0104] As the resolution of the display panel becomes higher and higher, the size of the transistors in the driving circuit will be correspondingly reduced to enable a larger number of driving circuits to be arranged in a limited space, resulting in a reduction in the channel length of the driving transistors; and the channel length of the driving transistors in the driving circuit affects the gray-scale expansion. The larger the channel length, the better the gray-scale expansion effect and the more accurate the screen display. Therefore, it is necessary to increase the size of the channel region of the driving transistors as much as possible while keeping the driving circuit space unchanged to improve the display effect of the display panel.

[0105] Based on this, an embodiment of the present invention provides a display panel, Figure 1 It is a schematic diagram of the layout structure of a display panel provided by an embodiment of the present invention, Figure 2 It is Figure 1 A schematic cross-sectional structure diagram of the shown structure along AA1. Referring to Figure 1 and Figure 2 , the display panel includes:

[0106] Substrate 10;

[0107] A plurality of driving circuits located on the substrate 10, and the driving circuit includes a driving transistor T1 and at least one auxiliary transistor;

[0108] Among them, the gate of the auxiliary transistor is connected to the gate GT1 of the driving transistor T1 and is arranged on the same layer, and the active part of the auxiliary transistor is connected to the active part of the driving transistor T1 and is arranged on the same layer.

[0109] Specifically, the display panel includes a substrate 10 and at least one active layer and multiple conductive layers stacked on one side of the substrate 10. The substrate 10 is used to provide protection and support for the display panel. The substrate 10 can be a flexible substrate formed of materials such as polyimide (PI), polyethylene naphthalate (PEN), or polyethylene terephthalate (PET), or a rigid substrate formed of materials such as glass. At least one active layer and multiple conductive layers are arranged on one side of the substrate 10, and the multiple conductive layers are isolated from each other by insulating layers.

[0110] At least one active layer and multiple conductive layers form at least one driving circuit, and the driving circuit is used to drive the light-emitting element to emit light. The driving circuit includes a driving transistor T1 and at least one auxiliary transistor. Figure 1 In the exemplary structure, the driving circuit is shown to include two auxiliary transistors, namely a first auxiliary transistor T9 and a second auxiliary transistor T10. The multiple conductive layers include a first conductive layer M1, and at least one active layer includes a first active layer Q1. The first conductive layer M1 can be located on the side of the first active layer Q1 away from the substrate 10. The gate of the auxiliary transistor is connected to the gate GT1 of the driving transistor T1 and is arranged on the same layer, and the gate of the auxiliary transistor and the gate GT1 of the driving transistor T1 are located on the first conductive layer M1. The active part of the auxiliary transistor is connected to the active part of the driving transistor and is arranged on the same layer, and the active part of the auxiliary transistor and the active part of the driving transistor are located on the first active layer Q1.

[0111] The active portion of the driving transistor T1 may include a first pole ST1 (e.g., source), a second pole DT1 (e.g., drain), and a channel region QT1 connecting the first pole ST1 and the second pole DT1; the gate GT1 of the driving transistor T1 is located in the first conductive layer M1, and the orthogonal projection of the gate GT1 of the driving transistor T1 on the substrate overlaps with the orthogonal projection of the channel region QT1 of the driving transistor T1 on the substrate. A gate extension gT1 is provided on one side of the gate GT1 of the driving transistor T1, and the gate of the auxiliary transistor is located in the gate extension gT1. The gate extension gT1 can be understood as being formed by extending the gate GT1 of the driving transistor T1 outward by a preset length, which is equivalent to increasing the gate GT1 of the driving transistor T1 in the related art. In the embodiment of the present invention, the vertical projection of the gate extension gT1 on the first active layer Q1 extends from the channel region QT1 of the driving transistor T1 towards the first pole ST1 of the driving transistor T1 and covers the first pole ST1 of the driving transistor T1, and a new transistor (auxiliary transistor) can be added at the first pole of the driving transistor T1, wherein the gate of the auxiliary transistor is located in the gate extension gT1, and the first pole ST1 of the driving transistor T1 is reused as at least part of the active portion of the auxiliary transistor. Therefore, the active portion of the auxiliary transistor and the active portion of the driving transistor are connected and arranged on the same layer. Among them, the first pole ST1 of the driving transistor T1 can be a source, the second pole DT1 of the driving transistor T1 can be a drain, and the channel region QT1 of the driving transistor T1 is located between the first pole ST1 and the second pole DT1 of the driving transistor T1. The material of the first active layer Q1 can be a-Si (amorphous silicon) or polysilicon.

[0112] It should be noted that in the embodiment of the present invention, the first pole ST1 (source of the driving transistor T1) of the driving transistor T1 is reused as at least part of the active portion of the auxiliary transistor, which is equivalent to the driving transistor T1 having no first pole. The active portion of the driving transistor T1 includes the second pole (e.g., drain DT1) of the driving transistor T1 and the channel region QT1 connecting the second pole.

[0113] In addition, the vertical projection of the gate extension gT1 on the first active layer Q1 extends from the channel region QT1 of the driving transistor T1 to the first region of the driving transistor T1 and covers the first pole of the driving transistor T1. This is equivalent to the side of the auxiliary transistor close to the driving transistor T1 having no source or drain, and the first pole ST1 (source) of the driving transistor T1 is reused as at least part of the channel region of the auxiliary transistor. Therefore, the channel region QT1 of the driving transistor T1 is connected to the channel region of the auxiliary transistor, equivalently increasing the size of the channel region of the driving transistor, enabling the gradation voltage change amplitude of the display panel to conform to the voltage regulation amplitude of the driving chip, thereby obtaining a better gradation expansion effect and improving the display effect of the display panel. There is no need to increase the size of the channel region of the driving transistor by expanding the size of the first active layer where the channel region of the driving transistor is located, which is beneficial to the development trend of high resolution of the display panel.

[0114] Figure 3 is a schematic layout structure diagram of a display panel provided in the related art. Figure 4 is Figure 3 a schematic cross-sectional structure diagram of the structure shown along BB1, refer to Figure 3 and Figure 4 , in the related art, no gate extension gT1 is provided on one side of the gate GT1 of the driving transistor T1. The length of the channel region QT1 of the driving transistor T1 is its actual length, and the channel region QT1 of the driving transistor T1 is short, resulting in the problem that the gradation voltage change amplitude of the display panel is much smaller than the output voltage resolution of the driving chip, which affects the display effect of the display panel.

[0115] The technical solution provided by the embodiment of the present invention forms at least one auxiliary transistor additionally at the first pole of the driving transistor T1 by providing a gate extension gT1 on one side of the gate of the driving transistor T1 and setting the vertical projection of the gate extension gT1 on the first active layer Q1 to cover the first pole of the driving transistor T1, so that the size of the channel region of the driving transistor T1 can be equivalently increased, thereby obtaining a better gradation expansion effect and improving the display effect of the display panel.

[0116] The above is the core inventive point of the present invention. The structure of the display panel will be specifically described below.

[0117] Based on the above embodiments, optionally, the active part of the auxiliary transistor is located on at least one of the two sides opposite to the active part of the driving transistor along the first direction X. Among them, Figure 1 in the structure shown, the active part of the auxiliary transistor is located on one of the two sides opposite to the active part of the driving transistor along the first direction X.

[0118] Optionally, the display panel includes scan lines that extend along the first direction X. The scan lines can be connected to the gates of the switching transistors. The switching transistors can include one or more of a data writing transistor, a compensation transistor, and an initialization transistor.

[0119] Based on the above embodiments, optionally, referring to Figure 1 , two transistors are newly added at the first pole of the driving transistor T1, namely a first auxiliary transistor T9 and a second auxiliary transistor T10. The active portions of the first auxiliary transistor T9 and the second auxiliary transistor T10 are located on the same side of the two opposite sides of the active portion of the driving transistor along the first direction X. The active portions of the first auxiliary transistor T9 and the second auxiliary transistor T10 are connected and arranged on the same layer.

[0120] Specifically, the gates of the first auxiliary transistor T9 and the second auxiliary transistor T10 are located in the gate extension portion gT1. Therefore, the gate of the driving transistor T1 is electrically connected and arranged on the same layer as the gates of the first auxiliary transistor T9 and the second auxiliary transistor T10. The active portion of the driving transistor T1 is connected and arranged on the same layer as the active portions of the first auxiliary transistor T9 and the second auxiliary transistor T10, and the active portions of the first auxiliary transistor T9 and the second auxiliary transistor T10 are connected and arranged on the same layer, so that the active portions of the driving transistor T1, the first auxiliary transistor T9, and the second auxiliary transistor T10 are connected to each other pairwise.

[0121] Based on the above embodiments, optionally, the active portions of the first auxiliary transistor T9 and the second auxiliary transistor T10 are arranged along the second direction Y, so that the first auxiliary transistor T9 and the second auxiliary transistor T10 can be arranged along the second direction Y on the same side of the driving transistor T1, where the second direction Y intersects the first direction X. Optionally, the display panel includes data lines that extend along the second direction Y. Optionally, the first direction X intersects the second direction Y, for example, they are perpendicular to each other.

[0122] Based on the above embodiments, optionally, at least part of the active portion of the first auxiliary transistor T9 and at least part of the active portion of the second auxiliary transistor T10 are located on the two opposite sides of the active portion of the driving transistor along the second direction Y, which can facilitate the electrical connection between the active portion of the driving transistor T1 and the active portions of the first auxiliary transistor T9 and the second auxiliary transistor T10 respectively.

[0123] Based on the above embodiments, optionally, the integrated structure formed by the active portion of the first auxiliary transistor T9, the active portion of the second auxiliary transistor T10, and the side of the active portion of the driving transistor T1 close to the active portion of the first auxiliary transistor T9 is in a T shape.

[0124] Specifically, Figure 5 it is Figure 1 a schematic diagram of the outline of the channel region of the driving transistor and the channel region of the first auxiliary transistor in the structure, Figure 6 it is Figure 1 a schematic diagram of the outline of the channel region of the driving transistor and the channel region of the second auxiliary transistor in the structure, refer to Figure 5 and Figure 6 , the active part of the first auxiliary transistor T9 (including the channel region QT9 of the first auxiliary transistor T9) and the active part of the second auxiliary transistor T10 (including the channel region QT10 of the second auxiliary transistor T10) are both located in the first active layer Q1, and the active part of the first auxiliary transistor T9 and the active part of the second auxiliary transistor T10 partially overlap to form a common channel Qc.

[0125] The region in the channel region QT9 of the first auxiliary transistor T9 that does not overlap with the channel region QT10 of the second auxiliary transistor T10 extends from the common channel Qc in the third direction Y1, and the region in the channel region QT10 of the second auxiliary transistor T10 that does not overlap with the channel region QT9 of the first auxiliary transistor T9 extends from the common channel Qc in the fourth direction Y2; wherein, the third direction Y1 is opposite to the fourth direction Y2, and both are parallel to the second direction Y, and the common channel Qc is connected to the active part (channel region QT1 of the driving transistor T1) of the driving transistor T1 close to the active part of the first auxiliary transistor T9, so that the integrated structure formed by the active part of the first auxiliary transistor T9, the active part of the second auxiliary transistor T10, and the active part of the driving transistor T1 close to the active part of the first auxiliary transistor T9 is in a T shape. Such a setting is beneficial to saving space.

[0126] Furthermore, at least part of the active part of the driving transistor T1 is in the shape of "Ω" or several characters or U shape, which can increase the length of the channel region of the driving transistor T1 while meeting the requirement of saving space, and a better gray-scale expansion effect can be obtained, improving the display effect of the display panel.

[0127] Based on the above embodiments, optionally, the driving circuit PX further includes a switching transistor, and the active part of the switching transistor is located on the side of the active part of the auxiliary transistor away from the active part of the driving transistor T1,

[0128] The integrated structure formed by the active part of the auxiliary transistor and the active part of the switching transistor is in a broken line or curve shape. In the same driving circuit PX, the active part of the auxiliary transistor is closer to the central axis extending along the second direction Y of the driving circuit PX than the active part of the switching transistor along the first direction X; for example, the active part of the switching transistor extends along the second direction Y.

[0129] Based on the above embodiments, optionally,Figure 7 It is a schematic layout structure diagram of another display panel provided by an embodiment of the present invention. Figure 8 It is a schematic layout structure diagram of another display panel provided by an embodiment of the present invention. Figure 7 The shown structure shows the first active layer Q1 in the display panel. Figure 8 The shown structure shows the first active layer Q1 and the first conductive layer M1 in the display panel. Refer to Figure 7 and Figure 8 , at least one auxiliary transistor includes the first auxiliary transistor T9 and / or the second auxiliary transistor T10, the driving circuit PX further includes a data writing transistor T2 and / or a first light-emitting control transistor T5, and the switching transistor includes the writing transistor T2 and / or the first light-emitting control transistor T5; the display panel further includes a first power supply line and / or a data signal line (not shown), the data writing transistor T2 is electrically connected to the data signal line; the first light-emitting control transistor T5 is electrically connected to the first power supply line; wherein, the active part of the data writing transistor T2 is connected to the active part of the driving transistor T1 through the active part of the first auxiliary transistor T9; the active part of the first light-emitting control transistor T5 is connected to the active part of the driving transistor T1 through the active part of the second auxiliary transistor T10.

[0130] Specifically, the active part of the data writing transistor T2 includes a first pole, a channel region, and a second pole connected in sequence, and the active part of the first light-emitting control transistor T5 includes a first pole, a channel region, and a second pole connected in sequence. The first pole of the data writing transistor T2 is electrically connected to the data signal line, and the second pole of the data writing transistor T2 is electrically connected to the first pole of the first auxiliary transistor T9 to be electrically connected to the driving transistor T1 through the first auxiliary transistor T9; the first pole of the first light-emitting control transistor T5 is electrically connected to the first power supply line, and the second pole of the first light-emitting control transistor T5 is electrically connected to the first pole of the second auxiliary transistor T10 to be electrically connected to the driving transistor T1 through the second auxiliary transistor T10.

[0131] Among them, the first pole of the first auxiliary transistor T9 is electrically connected to the second pole of the data writing transistor T2. The first pole of the first auxiliary transistor T9 and the second pole of the data writing transistor T2 can be in a relationship of being multiplexed on the same layer or can be independently set in different layers. The first pole of the second auxiliary transistor T10 is electrically connected to the second pole of the first light-emitting control transistor T5. The first pole of the second auxiliary transistor T10 and the second pole of the first light-emitting control transistor T5 can be in a relationship of being multiplexed on the same layer or can be independently set in different layers. The data signal line is used to transmit the data voltage Data, and the first power supply line is used to transmit the first power supply voltage VDD. The first auxiliary transistor T9 is turned on when inputting the data voltage Data to the gate of the driving transistor T1. The data voltage Data is input to the gate GT1 of the driving transistor T1 after passing through the data writing transistor T2, the first auxiliary transistor T9, the active part of the driving transistor T1, and the compensation transistor T3 in sequence. The first auxiliary transistor T9 is turned on when providing the first power supply voltage VDD to the driving transistor T1. The first power supply voltage VDD is input to the driving transistor T1 after passing through the first light-emitting control transistor T5 and the second auxiliary transistor T10 in sequence to generate a driving current for lighting the light-emitting element D.

[0132] Based on the above embodiments, referring to Figure 5 and Figure 6 , optionally, the length of the channel region QT9 of the active part of the first auxiliary transistor T9 is equal to the length of the channel region QT10 of the active part of the second auxiliary transistor T10; and / or, the width of the channel region QT9 of the active part of the first auxiliary transistor T9 is equal to the width of the channel region QT10 of the active part of the second auxiliary transistor T10.

[0133] Among them, at least part of the length of the channel region QT9 of the active part of the first auxiliary transistor T9 is the dimension along the second direction X, and at least part of the length of the channel region QT10 of the active part of the second auxiliary transistor T10 is the dimension along the second direction X; at least part of the width of the channel region QT9 of the active part of the first auxiliary transistor T9 is the dimension along the first direction Y, and at least part of the width of the channel region QT10 of the active part of the second auxiliary transistor T10 is the dimension along the first direction Y. The first direction X and the second direction Y intersect.

[0134] Specifically, the length of the channel region is the length of the extension trajectory of the channel region, and its value can be equal to the average value of the two boundaries of the channel region in the extension direction (the length of the dotted line). The width of the channel region is the distance between the two boundaries in the extension direction. Referring to Figure 5 and Figure 6, the length of the channel region QT1 of the driving transistor is the length of the dashed line in the channel region QT1, the length of the channel region QT9 of the first auxiliary transistor is the length of the dashed line in the channel region QT9, part of the length is the dimension along the second direction Y, and part of the length is the dimension along the first direction X. The length of the channel region QT10 of the second auxiliary transistor is the length of the dashed line in the channel region QT10, part of the length is the dimension along the second direction Y, and part of the length is the dimension along the first direction X. Among them, the dimensions of the channel regions QT10 and QT9 along the first direction X are equal.

[0135] During the data voltage Data writing stage, the channel region length of the driving transistor T1 is equivalently increased to be the length of the channel region QT9 of the first auxiliary transistor T9; during the light emitting stage, the channel region length of the driving transistor T1 is equivalently increased to be the length of the channel region QT10 of the second auxiliary transistor T10, so that the variation amplitude of the gray-scale voltage of the display panel is more in line with the output voltage resolution of the driving chip, thereby obtaining a better gray-scale expansion effect, improving the display effect of the display panel, and without increasing the actual size of the first active layer Q1 where the channel region QT1 of the driving transistor T1 is located, which is beneficial to the development trend of high resolution of the display panel.

[0136] In the embodiment of the present invention, the length of the channel region QT9 of the first auxiliary transistor T9 is set to be equal to the length of the channel region QT10 of the second auxiliary transistor T10, and the width of the channel region QT9 of the first auxiliary transistor T9 is equal to the width of the channel region QT10 of the second auxiliary transistor T10, so that the dimensions of the channel regions of the first auxiliary transistor T9 and the second auxiliary transistor T10 in the first direction X and in the second direction Y are consistent, which can ensure that the total area of the channel region QT1 of the driving transistor T1 and the channel region QT9 of the first auxiliary transistor T9 during the data voltage Data writing stage is equal to the total area of the channel region QT1 of the driving transistor T1 and the channel region QT10 of the second auxiliary transistor T10 during the light emitting stage, and further enables the channel region QT9 of the first auxiliary transistor T9 and the channel region QT10 of the second auxiliary transistor T10 to compensate each other, further ensuring the display effect of the display panel.

[0137] Further, referring to Figure 7 , the width W of the channel region of the active part of the driving transistor T1 T1 is equal to the width W of the channel region of the active part of the first auxiliary transistor T9 T9 , and / or, the width W of the channel region of the active part of the driving transistor T1 T1 is equal to the width W of the channel region of the active part of the second auxiliary transistor T10 T10 . And / or, the width W T9 is equal to the width W T10 .

[0138] Specifically, the width W of the channel region of the first auxiliary transistor T9 is set T9 to be equal to the width W of the channel region of the driving transistor T1 T1 , which can ensure that only the length of the channel region of the driving transistor T1 is equivalently adjusted through the channel region of the first auxiliary transistor T9, and the width W of the channel region of the second auxiliary transistor T10 is set T9 to be equal to the width W of the channel region of the driving transistor T1 T1 , which can ensure that only the length of the channel region of the driving transistor T1 is equivalently adjusted through the channel region of the second auxiliary transistor T10. In addition, it can also ensure that the difference in the sizes of the channel regions of the first auxiliary transistor T9 and the second auxiliary transistor T10 is only caused by the length, which is convenient for setting the channel regions of the first auxiliary transistor T9 and the second auxiliary transistor T10, and ensures that the total area of the channel region QT1 of the driving transistor T1 and the channel region QT9 of the first auxiliary transistor T9 during the data voltage Data writing stage is equal to the total area of the channel region QT1 of the driving transistor T1 and the channel region QT10 of the second auxiliary transistor T10 during the light emitting stage.

[0139] Based on the above embodiments, Figure 9 is Figure 8 a schematic cross-sectional structure diagram of the structure shown along CC1, referring to Figure 8 and Figure 9 , referring to Figures 7 - 9 , the active part of the data writing transistor T2 and / or the active part of the first light emitting control transistor T5 are / is arranged on the same layer as the active part of the driving transistor T1; wherein, the active parts of the data writing transistor T7, the first auxiliary transistor T9, and the second auxiliary transistor T10 are arranged in sequence along the second direction Y, and / or, the active parts of the first auxiliary transistor T9, the second auxiliary transistor T10, and the first light emitting control transistor T5 are arranged in sequence along the second direction Y.

[0140] For example, multiple structures arranged on the same layer can be obtained by patterning the same film layer to simplify the process.

[0141] Specifically, the channel region QT2 of the data writing transistor T2 and the channel region QT5 of the first light emitting control transistor T5 are located in the first active layer Q1; wherein, the channel region QT2 of the data writing transistor T2 is located on the side of the channel region of the first auxiliary transistor T9 extending along the third direction Y1 away from the common channel Qc; the channel region QT5 of the first light emitting control transistor T5 is located on the side of the channel region of the second auxiliary transistor T10 extending along the fourth direction Y2 away from the common channel Qc.

[0142] Setting the channel region QT2, the first pole, and the second pole of the data writing transistor T2 in the first active layer Q1 can make the first pole of the first auxiliary transistor T9 and the second pole of the data writing transistor T2 in a relationship of being multiplexed on the same layer, which is beneficial to saving space and improving the resolution of the display panel. Setting the channel region QT5, the first pole, and the second pole of the first light-emitting control transistor T5 in the first active layer Q1 can make the first pole of the second auxiliary transistor T10 and the second pole of the first light-emitting control transistor T5 in a relationship of being multiplexed on the same layer, which is beneficial to saving space and improving the resolution of the display panel.

[0143] Based on the above embodiments, referring to Figure 8 , optionally, the integrated structure formed by the active part of the first auxiliary transistor T9 and the active part of the data writing transistor T2 forms a broken line or a curve. For example, in the same driving circuit PX, the active part of the first auxiliary transistor T9 is closer to the central axis L extending along the second direction Y of the driving circuit PX along the first direction X compared to the active part of the data writing transistor T2 (not limited to the axis of symmetry, which is equivalent to the extension line extending along the second direction at the middle position of the width of the driving circuit along the first direction); and / or, the integrated structure formed by the active part of the second auxiliary transistor T10 and the active part of the first light-emitting control transistor T5 forms a broken line or a curve. In the same driving circuit PX, the active part of the second auxiliary transistor T10 is closer to the central axis L extending along the second direction Y of the driving circuit PX along the first direction X compared to the active part of the first light-emitting control transistor T5.

[0144] Optionally, the active parts of the first auxiliary transistor T9 and the second auxiliary transistor T10 extend along the second direction Y and are collinear, and / or, the active parts of the data writing transistor T2 and the first light-emitting control transistor T5 extend along the second direction and are collinear.

[0145] Specifically, the gate extension gT1 of the driving transistor T1 covers the first pole ST1 (the source of the driving transistor T1) of the driving transistor T1 in the vertical projection on the first active layer Q1, and continues to extend beyond the boundary of the first pole of the driving transistor T1, so as to ensure that the vertical projection of the gate extension gT1 on the first active layer Q1 can completely cover the first pole of the driving transistor T1, thereby maximizing the length of the equivalent channel region of the driving transistor T1 in the first direction X. Since the gate GT1 of the driving transistor T1 in different driving circuits PX is independently controlled, and the vertical projection of the gate extension gT1 of the driving transistor T1 on the first active layer Q1 covers the first pole of the driving transistor T1 and continues to extend beyond the boundary of the first pole of the driving transistor T1, the distance between two adjacent gate extensions gT1 becomes smaller. Therefore, in order to avoid the contact between two adjacent gate extensions gT1, resulting in a short circuit between the gates GT1 of the driving transistors T1 in two adjacent driving circuits PX, in the embodiments of the present invention, the active part of the data writing transistor T2 is extended along the second direction Y and is arranged in a staggered manner with the active part of the first auxiliary transistor T9 extended along the second direction Y, which can make the active part of the first auxiliary transistor T9 shrink inward in the direction of its respective driving circuit PX, thereby increasing the distance between the channel regions of the first auxiliary transistors T9 in two adjacent driving circuits PX, and further providing sufficient space for the extension of the gate extension gT1. The active part of the first light control transistor T5 is extended along the second direction Y and is arranged in a staggered manner with the active part of the second auxiliary transistor T10 extended along the second direction Y2, which can make the active part of the second auxiliary transistor T10 shrink inward in the direction of its respective driving circuit PX, thereby increasing the distance between the active parts of the second auxiliary transistors T10 in two adjacent driving circuits PX, and further providing sufficient space for the extension of the gate extension gT1.

[0146] Based on the above embodiments, please continue to refer to Figure 8 , optionally, in the same driving circuit, the gate GT1 of the driving transistor T1 and the gate of the auxiliary transistor (equivalent to the gate extension gT1) form a common gate structure; in the same driving circuit, the active part of the driving transistor T1 and the active part of the auxiliary transistor (such as the auxiliary transistors T9 and / or T10) form a common active structure. And a plurality of driving circuits form at least one driving circuit unit. The driving circuit unit includes at least two adjacent driving circuits PX arranged along the first direction X.

[0147] For example, in the same driving unit, in the first direction X, the active parts of the auxiliary transistors in two driving circuits PX are located between the active parts of two driving transistors T1.

[0148] For example, in the same driving unit, in the first direction X, the distance d2 between the two common gate structures in the two driving circuits PX along the first direction X is less than or equal to the distance d41 between the active parts of the two data writing transistors T2 along the first direction X.

[0149] For example, in the same driving unit, in the first direction X, a distance d3 between two common active structures in two driving circuits PX along the first direction X is greater than a distance d41 between active portions of two data writing transistors T2 along the first direction X.

[0150] For example, in the same driving unit, in the first direction X, the distance d2 between the two common gate structures in the two driving circuits PX along the first direction X is less than or equal to the distance d42 between the active parts of the two first light emitting control transistors T5 along the first direction X.

[0151] For example, in the same driving unit, in the first direction X, a distance d3 between two common active structures in two driving circuits PX along the first direction PX is greater than a distance d42 between active portions of two first light emitting control transistors T5 along the first direction X.

[0152] For example, in the same driving unit, in the first direction X, a distance d41 between active portions of two data writing transistors T2 along the first direction X is equal to a distance d42 between active portions of two first light emission control transistors T5 along the first direction X.

[0153] Based on the above embodiments, please continue to refer to Figure 8 In the same driving circuit, the gate GT1 of the driving transistor T1 and the gate of the auxiliary transistor (equivalent to the gate extension gT1) form a common gate structure; in the same driving circuit, the active part of the driving transistor T1 and the active part of the auxiliary transistor (auxiliary transistor T9 and / or T10) form a common active structure.

[0154] In the same driving circuit, the spacing d1 between the positive projection of the common gate structure on the substrate 10 and the positive projection of the common active structure on the substrate 10 close to the same side boundary of the auxiliary transistor along the first direction X is greater than or equal to 2 microns, so as to prevent the gate extensions gT1 in two adjacent driving circuits PX from contacting and causing a short circuit. The positive projection of the common gate structure on the substrate close to the boundary of the auxiliary transistor is farther away from the central axis L of the driving circuit PX extending along the second direction Y than the positive projection of the common active structure on the substrate close to the boundary of the auxiliary transistor. For example, d1 can be equal to 2 microns, 2.1 microns, 2.2 microns, 2.3 microns, 2.4 microns, 2.5 microns, etc.

[0155] Optionally, the display panel includes a plurality of driving units, and each driving unit includes two adjacent driving circuits PX arranged along the first direction X. In the same driving unit, in the first direction X, the active portions of the auxiliary transistors in the two driving circuits PX are located between the active portions of the two driving transistors T1. For example, in the same driving unit, the two adjacent driving circuits PX arranged along the first direction X are mirror-symmetrical. The driving circuit PX may be a pixel circuit.

[0156] In the same driving unit, in the first direction X, the pitch d2 along the first direction X between the two common gate structures in the two driving circuits PX is less than the pitch d3 along the first direction X between the two common active structures.

[0157] In the same driving unit, in the first direction X, the pitch d2 along the first direction X between the common gate structures in the two driving circuits PX is greater than or equal to 2 micrometers. For example, d2 may be equal to 2 micrometers, 2.1 micrometers, 2.2 micrometers, 2.3 micrometers, 2.4 micrometers, 2.5 micrometers, etc.

[0158] In the same driving unit, the pitch d3 along the first direction X between the common active structures in the two driving circuits PX is greater than or equal to 6 micrometers to leave enough extension space for the gate extension gT1. For example, d3 may be equal to 6 micrometers, 6.1 micrometers, 6.2 micrometers, 6.3 micrometers, 6.4 micrometers, 6.5 micrometers, etc.

[0159] In the same driving unit, the distance d4 between the channel regions of two adjacent writing transistors T2 is greater than or equal to 2 um, and the distance d4 between the channel regions of the first light-emitting control transistors T5 in two adjacent driving circuits PX is greater than or equal to 2 um, to prevent the writing transistors T2 in two adjacent driving circuits PX from contacting and causing a short circuit, and to prevent the first light-emitting control transistors T5 in two adjacent driving circuits PX from contacting and causing a short circuit.

[0160] Furthermore, the distance d5 between the gate GT1 of the driving transistor T1 and the second pole DT1 (such as the drain) of the driving transistor T1 is greater than or equal to 0.5 um, to prevent the vertical projection of the gate GT1 of the driving transistor T1 and the second pole of the driving transistor T1 on the substrate from overlapping. For example, d5 may be equal to 0.5 micrometers, 0.6 micrometers, 0.7 micrometers, 0.8 micrometers, 0.9 micrometers, 1 micrometer, etc.

[0161] Based on the above embodiments, optionally, the driving circuit further includes a compensation transistor and a first initialization transistor; the compensation transistor is connected between the second pole of the driving transistor T1 and the gate of the driving transistor T1; the first initialization transistor is electrically connected to the gate of the driving transistor T1 and is used to input a first initialization voltage Vrefn1 to the gate of the driving transistor T1 to initialize the gate voltage of the driving transistor T1.

[0162] Optionally, the active part of the compensation transistor and the active part of the driving transistor T1 are arranged in different layers, and / or the active part of the first initialization transistor and the active part of the driving transistor T1 are arranged in different layers.

[0163] Optionally, the active part of the compensation transistor and the active part of the first initialization transistor are connected and arranged in the same layer.

[0164] Optionally, the film layer where the active part of the compensation transistor and / or the active part of the first initialization transistor is located is on the side of the film layer where the active part of the driving transistor is located away from the substrate 10.

[0165] Optionally, the active part of the compensation transistor and / or the active part of the first initialization transistor includes a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO). And / or, the active part of the driving transistor includes a polysilicon semiconductor material.

[0166] Based on the above embodiments, Figure 10 is a schematic layout structure diagram of another display panel provided by an embodiment of the present invention. Figure 11 is a schematic layout structure diagram of another display panel provided by an embodiment of the present invention. Figure 12 is a schematic layout structure diagram of another display panel provided by an embodiment of the present invention. Figure 13 is Figure 12 a schematic cross-sectional structure diagram of the structure shown along DD1, where Figure 10 the structure shown shows the first active layer Q1, the first conductive layer M1, and the second conductive layer M2 in the display panel; Figure 11 the structure shown shows the first active layer Q1, the first conductive layer M1, the second conductive layer M2, and the second active layer Q2 in the display panel. Figure 12 the structure shown shows the first active layer Q1, the first conductive layer M1, the second conductive layer M2, the second active layer Q2, and the auxiliary conductive layer Mc in the display panel. Refer to Figures 10 - 13 , optionally, the display panel further includes a second active layer Q2; the multi-layer conductive layer further includes a second conductive layer M2 and an auxiliary conductive layer Mc.

[0167] Among them, the second conductive layer M2 is located on the side of the first conductive layer M1 away from the substrate 10, the second active layer Q2 is located on the side of the second conductive layer M2 away from the substrate 10, and the auxiliary conductive layer Mc is located on the side of the second active layer Q2 away from the substrate 10. The channel region QT3 of the active part of the compensation transistor T3 is located in the second active layer Q2, the first gate (such as the bottom gate GT3a) of the compensation transistor T3 is located in the second conductive layer M2, and the second gate (such as the top gate GT3b) of the compensation transistor T3 is located in the auxiliary conductive layer Mc; the first gate and the second gate of the compensation transistor T3 are located on opposite sides of the active part of the compensation transistor T3 along the thickness direction of the substrate 10.

[0168] The channel region QT4 of the active part of the first initialization transistor T4 is located in the second active layer Q2, the first gate (such as the bottom gate GT4a) of the first initialization transistor T4 is located in the second conductive layer M2, and the second gate (such as the top gate GT4b) of the first initialization transistor T4 is located in the auxiliary conductive layer Mc; the first gate and the second gate of the first initialization transistor T4 are located on opposite sides of the active part of the first initialization transistor T4 along the thickness direction of the substrate 10.

[0169] Furthermore, the material of the second active layer Q2 can be indium gallium zinc oxide (IGZO), that is, both the compensation transistor T3 and the first initialization transistor T4 are double-gate IGZO devices. Compared with the PSI device, the IGZO device has a smaller leakage current, and the electron mobility of the IGZO material is greater than that of a-Si (amorphous silicon), which can transmit electrons faster, thereby improving the response speed and energy efficiency of the display panel and enabling a dynamic refresh rate of 1-120Hz.

[0170] The first active layer Q1 includes a plurality of first active regions, and the active parts (channel region, first pole, and second pole) of the same transistor in the first active layer are located in the same first active region. The second active layer includes a plurality of second active regions, and the active parts (channel region, first pole, and second pole) of the same transistor in the second active layer are located in the same second active region.

[0171] Based on the above embodiments, referring to Figure 12 , optionally, in the same driving circuit PX, the active part of the compensation transistor T3 and the active part of the first initialization transistor T4 form a continuously extending second active region; the active parts of the first light-emitting control transistor T5, the first auxiliary transistor T9, the second auxiliary transistor T10, and the data writing transistor T2 form a continuously extending first active region.

[0172] Among them, the projection of the second active region on the substrate 10 and the projection of the first active region on the substrate 10 are located on opposite sides of the vertical projection of the channel region of the driving transistor T1 on the substrate 10, so that the compensating transistor T3 and the first initialization transistor T4 with a connection relationship are arranged on one side of the driving transistor T1; the first light-emitting control transistor T5, the second auxiliary transistor T10, the first auxiliary transistor T9, and the writing transistor T2 with a connection relationship are arranged on the other side of the driving transistor T1, which facilitates the arrangement of the compensating transistor T3, the first initialization transistor T4, the first light-emitting control transistor T5, the second auxiliary transistor T10, the first auxiliary transistor T9, and the writing transistor T2 around the driving transistor T1, and simplifies the connection manner between the transistors.

[0173] Further, the continuously extending first active region formed by the compensating transistor T3 and the first initialization transistor T4 extends along the second direction Y, and the continuously extending second active region formed by the first light-emitting control transistor T5, the second auxiliary transistor T10, the first auxiliary transistor T9, and the data writing transistor T2 extends along the second direction Y. Thus, the first light-emitting control transistor T5, the second auxiliary transistor T10, the first auxiliary transistor T9, and the data writing transistor T2 can be arranged using the vertical space, and the compensating transistor T3 and the first initialization transistor T4 can be arranged using the vertical space, which is beneficial to reducing the width of the driving circuit PX.

[0174] Based on the above embodiments, referring to Figure 12 , optionally, the driving circuit PX further includes a storage capacitor Cst. The storage capacitor Cst includes a first electrode plate c11 and a second electrode plate c12. The first electrode plate c11 of the storage capacitor Cst is located in the first conductive layer M1; the second electrode plate c12 of the storage capacitor Cst is located in the second conductive layer M2 and at least partially overlaps with the vertical projection of the first electrode plate c11 on the substrate 10. The storage capacitor Cst is used to store the gate voltage of the driving transistor T1.

[0175] Further, the first electrode plate c11 of the storage capacitor Cst multiplexes the gate of the driving transistor T1 and / or the gate of the auxiliary transistor. That is, the first electrode plate c11 of the storage capacitor Cst multiplexes the gate of the driving transistor T1, or the first electrode plate c11 of the storage capacitor Cst multiplexes the gate extension gT1 of the driving transistor T1, or the first electrode plate c11 of the storage capacitor Cst multiplexes the gate and the gate extension gT1 of the driving transistor T1. Arranging the first electrode plate c11 of the storage capacitor Cst to multiplex the gate of the driving transistor T1 and / or the gate of the auxiliary transistor is beneficial to saving space and improving the resolution of the display panel. The second electrode plates c12 of the storage capacitors Cst in the driving circuits PX arranged along the second direction Y and adjacent to each other are connected.

[0176] Based on the above embodiments, please continue to refer to Figure 12 , optionally, the driving circuit PX further includes a second light-emitting control transistor T6 and a second initialization transistor T7; wherein, the second light-emitting control transistor T6 is connected between the first pole of the light-emitting element D and the second pole of the driving transistor T1. The first pole of the second light-emitting control transistor T6 is connected to the second pole of the driving transistor T1, the second pole of the second light-emitting control transistor T6 is electrically connected to the first pole (e.g., anode) of the light-emitting element D, and the gate of the second light-emitting control transistor T6 is electrically connected to the gate of the first light-emitting control transistor T5 to receive the same light-emitting control signal EM and turn on and off synchronously.

[0177] The first pole of the second initialization transistor T7 is used to input a second initialization voltage Vrefn2. The second pole of the driving transistor T1 is electrically connected to the first pole (e.g., anode) of the light-emitting element D. The second initialization transistor T7 is used to input the second initialization voltage Vrefn2 to the first pole (e.g., anode) of the light-emitting element D when turned on to initialize the potential of the first pole (e.g., anode) of the light-emitting element D. The display panel further includes a second initialization voltage Vrefn2 transmission line, and the second initialization voltage Vrefn2 transmission line is electrically connected to the first pole of the light-emitting element D through the second initialization transistor T7. The second pole (e.g., cathode) of the light-emitting element D is connected to a second power supply line (which can be used to transmit a second power supply voltage VSS).

[0178] , optionally, the active part of the second light-emitting control transistor T6 (i.e., the first pole, channel region, and second pole of the second light-emitting control transistor T6) is located in the first active layer Q1, and the gate of the second light-emitting control transistor T6 is located in the first conductive layer M1; the active part of the second initialization transistor T7 (i.e., the first pole, channel region, and second pole of the second initialization transistor T7) is located in the first active layer Q1, and the gate of the second initialization transistor T7 is located in the first conductive layer M1.

[0179] Since the driving transistor T1 is connected between the first light-emitting control transistor T5 and the second light-emitting control transistor T6, the active part of the second light-emitting control transistor T6 and the active part of the first light-emitting control transistor T5 can be respectively located on opposite sides of the driving transistor T1, which can simplify the connection manner between the first light-emitting control transistor T5 and the second light-emitting control transistor T6 and the driving transistor T1.

[0180] The active part of the second initialization transistor T7 is connected to the active part of the second light-emitting control transistor T6, so that the second pole of the second initialization transistor T7 and the second pole of the second light-emitting control transistor T6 are in a common multiplexing relationship, which is beneficial to saving space and improving the resolution of the display panel.

[0181] Further, the active part of the second initialization transistor T7 and the active part of the second light-emitting control transistor T6 form a broken line shape, which is beneficial to saving space and improving the resolution of the display panel. Among them, the active part of the second light-emitting control transistor T6 extends along the second direction Y, and after bending along the boundary of the channel region of the driving transistor T1, the active part of the second initialization transistor T7 continues to extend along the second direction Y, so as to improve the compactness between the transistors in the driving circuit PX.

[0182] Figure 14 is a circuit diagram of a driving circuit provided by an embodiment of the present invention, which is Figure 12 an equivalent circuit diagram of the shown structure, refer to Figure 14 , the driving circuit includes multiple transistors and a storage capacitor Cst, and the multiple transistors include some or all of the driving transistor T1, the first auxiliary transistor T9, the second auxiliary transistor T10, the writing transistor T2, the first light-emitting control transistor T5, the writing transistor T2, the supplementary transistor T3, the first initialization transistor T4, and the second initialization transistor T7, such as a driving circuit of "9T1C".

[0183] In another embodiment of the present invention, please refer to Figure 15 , Figure 15 is a schematic layout structure diagram of another display panel provided by an embodiment of the present invention. The driving circuit further includes a third initialization transistor T8, and the display panel further includes a third initialization voltage transmission line (for transmitting the third initialization voltage VrefP); among them, the auxiliary transistor includes the second auxiliary transistor T10, the third initialization voltage transmission line is connected to the first pole of the third initialization transistor T8, and the second pole of the third initialization transistor T8 is connected to the driving transistor T1 through the second auxiliary transistor T10.

[0184] Specifically, the first pole of the third initialization transistor T8 is used to input the third initialization voltage VrefP, the second pole of the third initialization transistor T8 is electrically connected to the first pole of the second auxiliary transistor T10, and when the third initialization transistor T8 is turned on, it is used to input the third initialization voltage VrefP to the first pole of the second auxiliary transistor T10 to initialize the potential of the first pole of the second auxiliary transistor T10. Figure 16 is a circuit diagram of another driving circuit provided by an embodiment of the present invention, which is Figure 15 an equivalent circuit diagram of the shown structure, refer to Figure 16 , the driving circuit PX includes 10 transistors and a storage capacitor Cst. On the basis of Figure 14 , a third initialization transistor T8 is added to form a "10T1C" driving circuit.

[0185] Further, the active part of the third initialization transistor T8 (i.e., the first pole, channel region, and second pole of the third initialization transistor T8) is located in the first active layer Q1, and the gate of the third initialization transistor T8 is located in the first conductive layer M1. The gate of the third initialization transistor T8 can be electrically connected to the gate of the second initialization transistor T7 to receive the same control signal SP2, and they are turned on and off simultaneously. The active part of the third initialization transistor T8 can be arranged between the active part of the second initialization transistor T2 and the active part of the first light-emitting control transistor T5, so as to facilitate the electrical connection between the gate of the third initialization transistor T8 and the gate of the second initialization transistor T7, and at the same time facilitate the electrical connection between the second pole of the third initialization transistor T8 and the first pole of the second auxiliary transistor T10; in addition, it can also improve the compactness between the transistors in the driving circuit PX.

[0186] Based on the above embodiments, Figure 17 is a schematic diagram showing the positions of different types of connection holes in a display panel provided by an embodiment of the present invention. Figure 18 is a schematic layout structure diagram of another display panel provided by an embodiment of the present invention. Refer to Figure 17 and Figure 18 The multi-layer conductive layer further includes a third conductive layer M3, and the third conductive layer M3 is located on the side of the auxiliary conductive layer Mc away from the substrate. In the third conductive layer M3, there are transmission lines for transmitting the second initialization voltage Vrefn2, transmission lines for transmitting the third initialization voltage Vrefp, and wires for electrically connecting different-layer film layers. The auxiliary conductive layer Mc further includes a transmission line for transmitting the first initialization voltage Vrefn1, a fourth gate control signal line for transmitting the control signal SN2 to the second gate (such as the top gate) of the compensation transistor T3, and a second gate control signal line for transmitting the control signal SN1 to the second gate (such as the top gate) of the first initialization transistor T4. The first conductive layer M1 further includes signal lines for transmitting the control signal SP1, signal lines for transmitting the control signal SP2, and signal lines for transmitting the light-emitting control signal EM; the second conductive layer M2 further includes a third gate control signal line for transmitting the control signal SN2 to the first gate (such as the bottom gate) of T3, and a first gate control signal line for transmitting the control signal SN1 to the first gate (such as the bottom gate) of T4. Insulating layers for electrical isolation are provided between adjacent conductive layers and between adjacent active layers and conductive layers. The display panel also includes a plurality of first-type connection holes K1, second-type connection holes K2, third-type connection holes K3, fourth-type connection holes K4, and fifth-type connection holes K5. The wires located in the third conductive layer M3 achieve electrical connection of different-layer film layers through the connection holes. Figure 19 is Figure 18 a schematic cross-sectional structure diagram of the structure shown along EE1. Figure 20 is Figure 18Schematic cross-sectional structure diagram of the shown structure along FF1, refer to Figure 19 and Figure 20 , the first active layer Q1 is located on the substrate 10, the first conductive layer M1 is located on the side of the first active layer Q1 away from the substrate 10, and a first insulating layer 110 is provided between the first active layer Q1 and the first conductive layer M1. The second conductive layer M2 is located on the side of the first conductive layer M1 away from the substrate 10, and a second insulating layer 120 is provided between the first conductive layer M1 and the second conductive layer M2. The second active layer Q2 is located on the side of the second conductive layer M2 away from the substrate 10, and a third insulating layer 130 is provided between the second conductive layer M2 and the second active layer Q2. The auxiliary conductive layer Mc is located on the side of the second active layer Q2 away from the substrate 10, and a fourth insulating layer 140 is provided between the second active layer Q2 and the auxiliary conductive layer Mc. The third conductive layer M3 is located on the side of the auxiliary conductive layer Mc away from the substrate 10, and a fifth insulating layer 150 is provided between the auxiliary conductive layer Mc and the third conductive layer M3.

[0187] Among them, the first type of via hole K1 sequentially penetrates the fifth insulating layer 150, the fourth insulating layer 140, the third insulating layer 130, the second insulating layer 120, and the first insulating layer 110 to electrically connect the first active layer Q1. The second type of via hole K2 sequentially penetrates the fifth insulating layer 150, the fourth insulating layer 140, the third insulating layer 130, and the second insulating layer 120 to electrically connect the first conductive layer M1. The third type of via hole K3 sequentially penetrates the fifth insulating layer 150, the fourth insulating layer 140, and the third insulating layer 130 to electrically connect the second conductive layer M2. The fourth type of via hole K4 sequentially penetrates the fifth insulating layer 150 and the fourth insulating layer 140 to electrically connect the second active layer Q2. The fifth type of via hole K5 penetrates the fifth insulating layer 150 to electrically connect the auxiliary conductive layer Mc.

[0188] Based on the above embodiments, refer to Figure 18 , optionally, the positive projection of the second initialization voltage transmission line (for transmitting the second initialization voltage Vrefn2) and the first gate control signal transmission line (for transmitting the control signal SN1) on the substrate at least partially overlaps, and / or, the positive projection of the second initialization voltage transmission line and the second gate control signal transmission line (for transmitting the control signal SN1) on the substrate at least partially overlaps.

[0189] In the same driving circuit, the first gate control signal transmission line of the first initialization transistor T4 is connected to the second gate control signal transmission line, that is, the same control signal (control signal SN1) is transmitted. For example, the first gate control signal transmission line and the second gate control signal transmission line of the first initialization transistor T4 are arranged in different layers and are located on opposite sides of the active part of the first initialization transistor T4 along the thickness direction of the substrate.

[0190] Optionally, the first gate control signal transmission line of the first initialization transistor T4 extends along the first direction X, and / or the second gate control signal transmission line extends along the first direction X, and / or the second initialization voltage transmission line extends along the first direction X.

[0191] Optionally, please continue to refer to Figure 18 the third initialization voltage transmission line (for transmitting the third initialization voltage Vrefp) connected to the third initialization transistor T8 extends along the first direction X, and at least a part of the third initialization voltage transmission line is in a broken line shape or a curved shape.

[0192] For example, the third initialization voltage transmission line and the first initialization voltage transmission line overlap in the positive projection on the substrate, which is beneficial to reducing the occupied area of the wiring and improving the pixel resolution. For example, the third initialization voltage transmission line and the first initialization voltage transmission line do not overlap in the positive projection on the substrate, which is beneficial to reducing the risk of short circuit between the third initialization voltage transmission line and the first initialization voltage transmission line. During the manufacturing process, particles are likely to enter the insulating layer between the third initialization voltage transmission line and the first initialization voltage transmission line, resulting in a short circuit.

[0193] Optionally, the third initialization voltage transmission line includes a first sub-segment r1, a second sub-segment r2, and a third sub-segment r3 that extend along the first direction X, and a fourth sub-segment r4 and a fifth sub-segment r5 that extend along the second direction Y; wherein, the first sub-segment, the fourth sub-segment, the second sub-segment, the fifth sub-segment, and the third sub-segment are connected in sequence. The fourth sub-segment r4 is connected between the first sub-segment r1 and the second sub-segment r2, and the fifth sub-segment r5 is connected between the second sub-segment r2 and the third sub-segment r3; the first direction X intersects the second direction Y.

[0194] Optionally, the display panel further includes a first initialization voltage transmission line (for transmitting the first initialization voltage Vrefn1), and the first initialization voltage transmission line is electrically connected to the gate of the driving transistor T1 through the first initialization transistor T4. The first initialization voltage transmission line extends along the first direction X and is, for example, in a broken line shape.

[0195] For example, the first initialization voltage transmission line and the third initialization voltage transmission line overlap in the positive projection on the substrate, and the first initialization voltage transmission line and the third initialization voltage transmission line do not overlap in the positive projection on the substrate.

[0196] Optionally, at least a part of the first sub-segment r1 of the third initialization voltage transmission line overlaps with the positive projection of the first initialization voltage transmission line on the substrate; and / or at least a part of the third sub-segment r3 of the third initialization voltage transmission line overlaps with the positive projection of the first initialization voltage transmission line on the substrate.

[0197] Optionally, at least a part of the positive projection of the second sub-segment r2 of the third initialization voltage transmission line on the substrate does not overlap with the positive projection of the first initialization voltage Vrefn1 transmission line on the substrate.

[0198] Figure 21 Yes Figure 18 An enlarged view of region N1 in the shown structure, refer to Figure 21 , at least a part of the positive projection of the second sub-segment r2 of the third initialization voltage transmission line on the substrate overlaps with the positive projection of the first initialization voltage Vrefn1 transmission line on the substrate.

[0199] Optionally, Figure 22 is a schematic layout structure diagram of another display panel provided by an embodiment of the present invention. Refer to Fig. 22, the positive projection of the second sub-segment r2 of the third initialization voltage transmission line on the substrate does not overlap with the positive projection of the first initialization voltage transmission line on the substrate.

[0200] Optionally, the width of the overlapping region of the first sub-segment r1 of the third initialization voltage transmission line and the positive projection of the first initialization voltage transmission line on the substrate in the second direction Y is greater than the width of the overlapping region of the second sub-segment r2 of the third initialization voltage transmission line and the positive projection of the first initialization voltage transmission line on the substrate in the second direction.

[0201] And / or, please continue to refer to Figure 21 , the width d7 of the overlapping region of the third sub-segment r3 of the third initialization voltage transmission line and the positive projection of the first initialization voltage transmission line on the substrate in the second direction Y is greater than the width d8 of the overlapping region of the second sub-segment r2 of the third initialization voltage transmission line and the positive projection of the first initialization voltage transmission line on the substrate in the second direction Y.

[0202] Optionally, the second sub-segment r2 overlaps with the active part of the third initialization transistor T8 on the positive projection of the substrate 10, and is connected through vias in the overlapping region.

[0203] Optionally, multiple second sub-segments r2 are arranged at intervals along the first direction X, for example, arranged at equal intervals.

[0204] Optionally, the display panel includes multiple driving units, and each driving unit includes two adjacent driving circuits PX arranged along the first direction X. In the same driving unit, the second sub-segment r2 is connected between the active parts of two third initialization transistors T8.

[0205] Optionally, the display panel further includes a control signal transmission line (for transmitting the control signal SP2) connected to the gate of the third initialization transistor T8; the control signal transmission line connected to the gate of the third initialization transistor T8 extends along the first direction X, for example, in a zigzag shape.

[0206] Optionally, a positive projection of a control signal transmission line connected to a gate of a third initialization transistor T8 on a substrate at least partially overlaps with a positive projection of a first initialization voltage transmission line on the substrate.

[0207] Optionally, along a thickness direction of the substrate 10, the first initialization voltage transmission line is located between the third initialization voltage transmission line and a control signal transmission line connected to the gate of the third initialization transistor T8.

[0208] Optionally, the display panel includes a plurality of driving units, and in the driving circuit unit, two adjacent driving circuits PX arranged along a first direction X are mirror-symmetrical. Figure 15 and Figure 18 Exemplarily, a driving circuit PX unit is shown, and two driving circuits PX that are mirror-symmetrical to each other in the driving circuit PX unit.

[0209] In another embodiment of the present invention, Figure 23 is a schematic layout structure diagram of another display panel provided by an embodiment of the present invention. Refer to Figure 23 , exemplarily, a driving circuit unit is shown, and the driving circuit unit includes three driving circuits, namely a first driving circuit PX1, a second driving circuit PX2, and a third driving circuit PX3. Among them, the first driving circuit PX1 and the second driving circuit PX2 are mirror-symmetrical, and the third driving circuit PX3 and the second driving circuit PX2 are mirror-symmetrical. A driving circuit unit includes the first driving circuit PX1 and the second driving circuit PX2.

[0210] Each signal line or trace (such as a scan line, an initialization voltage transmission line, a power line, a data line, etc.) can extend in a straight line, a broken line, a curve, an irregular shape (such as a dendritic shape), etc. or a combination of one or more of them along its own extension direction.

[0211] Refer to Figure 18 , the present invention further provides a display panel, including:

[0212] A substrate;

[0213] A plurality of driving circuits, located on the substrate, and the driving circuits include a driving transistor T1, a first initialization transistor T4 connected to the driving transistor T1, and a third initialization transistor T8;

[0214] A first initialization voltage transmission line (for transmitting a first initialization voltage Vrefn1) and a third initialization voltage transmission line (for transmitting a third initialization voltage Vrefp); the first initialization voltage transmission line is connected to the first initialization transistor T4; the third initialization voltage transmission line is connected to the third initialization transistor T8;

[0215] Among them, the first initialization voltage transmission line extends along the first direction X, the third initialization voltage transmission line extends along the first direction X, and at least part of the third initialization voltage transmission line is in a broken line shape or a curved line shape; a part of the positive projection of the first initialization voltage transmission line and the third initialization voltage transmission line on the substrate overlaps, and a part of the positive projection of the first initialization voltage transmission line and the third initialization voltage transmission line on the substrate does not overlap.

[0216] For example, the overlapping of the positive projection parts of the third initialization voltage transmission line and the first initialization voltage transmission line on the substrate is beneficial to reducing the occupied area of the wiring and improving the pixel resolution. For example, the non-overlapping of the positive projection parts of the third initialization voltage transmission line and the first initialization voltage transmission line on the substrate is beneficial to reducing the risk of short circuit between the third initialization voltage transmission line and the first initialization voltage transmission line. During the manufacturing process, particles are likely to enter the insulating layer between the third initialization voltage transmission line and the first initialization voltage transmission line, resulting in a short circuit.

[0217] This embodiment can be combined with some or all of the features in the above embodiments, and will not be elaborated here.

[0218] An embodiment of the present invention further provides a display device, which includes the display panel provided in any embodiment of the present invention. Therefore, the display device also has the beneficial effects described in any of the above embodiments. In this embodiment, the display device can be a mobile phone or any electronic product with a display function, including but not limited to the following categories: display panels in televisions, laptop computers, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control devices, touch interaction terminals, etc. The embodiments of the present invention do not make special limitations on this.

[0219] Note that the above is only a preferred embodiment of the present invention and the applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described here, and various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: substrate; A plurality of driving circuits, located on the substrate, the driving circuits comprising a driving transistor and at least one auxiliary transistor; The gate of the auxiliary transistor is connected to the gate of the driving transistor and is disposed in the same layer, and the active part of the auxiliary transistor is connected to the active part of the driving transistor and is disposed in the same layer.

2. The display panel according to claim 1, characterized in that: The active portion of the auxiliary transistor is located on at least one of two sides of the active portion of the driving transistor that are opposite to each other along the first direction; Optionally, the display panel includes a scan line, and the scan line extends along the first direction; Optionally, the at least one auxiliary transistor includes a first auxiliary transistor and a second auxiliary transistor, the active portion of the first auxiliary transistor and the active portion of the second auxiliary transistor are located on the same side of two sides of the active portion of the driving transistor that are opposite to each other along the first direction, and the active portion of the first auxiliary transistor and the active portion of the second auxiliary transistor are connected and arranged in the same layer; Optionally, the active portion of the first auxiliary transistor and the active portion of the second auxiliary transistor are arranged along a second direction, and the second direction intersects with the first direction; Optionally, at least part of the active portion of the first auxiliary transistor and at least part of the active portion of the second auxiliary transistor are located on two opposite sides of the active portion of the driving transistor along the second direction; Optionally, the display panel includes data lines, and the data lines extend along the second direction; Optionally, an integrated structure formed by the active portion of the first auxiliary transistor, the active portion of the second auxiliary transistor and the active portion of the driving transistor close to a side of the active portion of the first auxiliary transistor is in a T shape; Optionally, at least part of the active portion of the driving transistor is in an "Ω" shape or a "X" shape.

3. The display panel according to claim 1, characterized in that: The driving circuit further comprises a switching transistor, wherein an active portion of the switching transistor is located on a side of the active portion of the auxiliary transistor away from the active portion of the driving transistor, The active portion of the auxiliary transistor and the active portion of the switch transistor form an integrated structure that forms a broken line or a curve. In the same drive circuit, the active portion of the auxiliary transistor is closer to the central axis of the drive circuit extending in the second direction along the first direction than the active portion of the switch transistor; the active portion of the switch transistor extends along the second direction; Optionally, the at least one auxiliary transistor includes a first auxiliary transistor and / or a second auxiliary transistor. The driving circuit further includes a data writing transistor and / or a first light emission control transistor; the display panel further includes a first power line and / or a data signal line, the data writing transistor is electrically connected to the data signal line; the first light emission control transistor is electrically connected to the first power line; The active part of the data writing transistor is connected to the active part of the driving transistor through the active part of the first auxiliary transistor; the active part of the first light emission control transistor is connected to the active part of the driving transistor through the active part of the second auxiliary transistor; Optionally, the active portion of the data writing transistor and / or the active portion of the first light emission control transistor are arranged in the same layer as the active portion of the driving transistor; wherein the active portion of the data writing transistor, the active portion of the first auxiliary transistor, and the active portion of the second auxiliary transistor are arranged in sequence along the second direction, and / or the active portion of the first auxiliary transistor, the active portion of the second auxiliary transistor, and the active portion of the first light emission control transistor are arranged in sequence along the second direction; Optionally, the integrated structure formed by the active portion of the first auxiliary transistor and the active portion of the data writing transistor forms a broken line or a curve, and in the same driving circuit, the active portion of the first auxiliary transistor is closer to the central axis of the driving circuit extending along the second direction along the first direction compared to the active portion of the data writing transistor; and / or, the integrated structure formed by the active portion of the second auxiliary transistor and the active portion of the first light emission control transistor forms a broken line or a curve, and in the same driving circuit, the active portion of the second auxiliary transistor is closer to the central axis of the driving circuit extending along the second direction along the first direction compared to the active portion of the first light emission control transistor; Optionally, the active portion of the first auxiliary transistor and the active portion of the second auxiliary transistor extend along the second direction and are collinear, and / or the active portion of the data writing transistor and the active portion of the first light emission control transistor extend along the second direction and are collinear; Optionally, in the same driving circuit, the gate of the driving transistor and the gate of the auxiliary transistor form a common gate structure. In the same driving circuit, the active portion of the driving transistor and the active portion of the auxiliary transistor form a common active structure. The display panel comprises a plurality of driving units, each of the driving units comprises two driving circuits arranged and adjacent to each other in a first direction, and in the same driving unit, in the first direction, active portions of the auxiliary transistors in the two driving circuits are located between active portions of the two driving transistors; In the same driving unit, in the first direction, a distance between two common gate structures in two driving circuits along the first direction is less than or equal to a distance between active portions of two data writing transistors along the first direction; In the same driving unit, in the first direction, a distance between two common active structures in two driving circuits along the first direction is greater than a distance between active parts of two data writing transistors along the first direction; In the same driving unit, in the first direction, a distance between two common gate structures in two driving circuits along the first direction is less than or equal to a distance between active parts of two first light emission control transistors along the first direction; In the same driving unit, in the first direction, a distance between two common active structures in two driving circuits along the first direction is greater than a distance between active parts of two first light emission control transistors along the first direction.

4. The display panel according to claim 1, characterized in that: The at least one auxiliary transistor comprises a first auxiliary transistor and / or a second auxiliary transistor, The length of the channel region of the active portion of the first auxiliary transistor is equal to the length of the channel region of the active portion of the second auxiliary transistor; and / or, the width of the channel region of the active portion of the first auxiliary transistor is equal to the width of the channel region of the active portion of the second auxiliary transistor; Optionally, the width of the channel region of the active portion of the driving transistor is equal to the width of the channel region of the active portion of the first auxiliary transistor and the width of the channel region of the active portion of the second auxiliary transistor; Optionally, at least part of the length of the channel region of the active portion of the first auxiliary transistor is a dimension along the second direction, and at least part of the length of the channel region of the active portion of the second auxiliary transistor is a dimension along the second direction. And / or, at least part of the width of the channel region of the active portion of the first auxiliary transistor is a dimension along a first direction, and at least part of the width of the channel region of the active portion of the second auxiliary transistor is a dimension along the first direction, and the first direction and the second direction intersect.

5. The display panel according to claim 1, characterized in that: In the same driving circuit, the gate of the driving transistor and the gate of the auxiliary transistor form a common gate structure. In the same driving circuit, the active portion of the driving transistor and the active portion of the auxiliary transistor form a common active structure. In the same driving circuit, a spacing along the first direction between an orthographic projection of a common gate structure on the substrate and an orthographic projection of a common active structure on the substrate close to a same side boundary of the auxiliary transistor is greater than or equal to 2 micrometers; The orthographic projection of the common gate structure on the substrate is closer to the boundary of the auxiliary transistor than the orthographic projection of the common active structure on the substrate is closer to the boundary of the auxiliary transistor and farther away from the central axis of the driving circuit extending along the second direction; And / or, the display panel comprises a plurality of driving units, the driving unit comprises two driving circuits arranged and adjacent to each other in a first direction, and in the same driving unit, in the first direction, active parts of the auxiliary transistors in the two driving circuits are located between active parts of the two driving transistors; In the same driving unit, in the first direction, a spacing between two common gate structures in two driving circuits along the first direction is smaller than a spacing between two common active structures along the first direction; In the same driving unit, in the first direction, a spacing between common gate structures in two driving circuits along the first direction is greater than or equal to 2 micrometers; In the same driving unit, the spacing between the common active structures in the two driving circuits along the first direction is greater than or equal to 6 micrometers; Optionally, in the same driving unit, two adjacent driving circuits arranged along the first direction are mirror-symmetrical.

6. The display panel according to claim 1, characterized in that: The driving circuit further includes a second initialization transistor, and the display panel further includes a second initialization voltage transmission line, and the second initialization voltage transmission line is electrically connected to the first electrode of the light emitting element through the second initialization transistor; The driving circuit further includes a first initialization transistor, and the display panel further includes a first gate control signal transmission line connected to a first gate of the first initialization transistor, and / or a second gate control signal transmission line connected to a second gate of the first initialization transistor; The orthographic projection of the second initialization voltage transmission line and the first gate control signal transmission line on the substrate at least partially overlaps, and / or the orthographic projection of the second initialization voltage transmission line and the second gate control signal transmission line on the substrate at least partially overlaps; Optionally, in the same driving circuit, the first gate control signal transmission line is connected to the second gate control signal transmission line; the first gate and the second gate of the first initialization transistor are located on opposite sides of the active portion of the first initialization transistor along the thickness direction of the substrate; Optionally, the first gate control signal transmission line, the second gate control signal transmission line and the second initialization voltage transmission line extend along a first direction; Optionally, the driving circuit further includes a third initialization transistor, and the display panel further includes a third initialization voltage transmission line; Wherein, the auxiliary transistor includes a second auxiliary transistor, the third initialization voltage transmission line is connected to a first electrode of the third initialization transistor, and a second electrode of the third initialization transistor is connected to the driving transistor through the second auxiliary transistor; Optionally, the third initialization voltage transmission line extends along the first direction, and at least a portion of the third initialization voltage transmission line is in a zigzag or curved line shape; Optionally, the third initialization voltage transmission line includes a first sub-segment, a second sub-segment, and a third sub-segment extending along the first direction, and includes a fourth sub-segment and a fifth sub-segment extending along the second direction and arranged along the first direction; wherein the first sub-segment, the fourth sub-segment, the second sub-segment, the fifth sub-segment, and the third sub-segment are connected in sequence; The first direction intersects the second direction; Optionally, the display panel further includes a first initialization voltage transmission line, and the first initialization voltage transmission line is electrically connected to the gate of the driving transistor through the first initialization transistor; The first initialization voltage transmission line extends along a first direction; The orthographic projections of the first initialization voltage transmission line and the third initialization voltage transmission line on the substrate partially overlap, and the orthographic projections of the first initialization voltage transmission line and the third initialization voltage transmission line on the substrate do not overlap; Optionally, the first subsegment of the third initialization voltage transmission line at least partially overlaps with the orthographic projection of the first initialization voltage transmission line on the substrate; and / or the third subsegment of the third initialization voltage transmission line at least partially overlaps with the orthographic projection of the first initialization voltage transmission line on the substrate; Optionally, the second subsegment of the third initialization voltage transmission line does not overlap with the orthographic projection of the first initialization voltage transmission line on the substrate at least in part; Optionally, the second subsegment of the third initialization voltage transmission line does not overlap with the orthographic projection of the first initialization voltage transmission line on the substrate; Alternatively, the width of the overlapping area between the first sub-segment of the third initialization voltage transmission line and the orthographic projection of the first initialization voltage transmission line on the substrate in the second direction is greater than the width of the overlapping area between the second sub-segment of the third initialization voltage transmission line and the orthographic projection of the first initialization voltage transmission line on the substrate in the second direction, and / or, a width in the second direction of an overlapping region between a third subsegment of the third initialization voltage transmission line and an orthographic projection of the first initialization voltage transmission line on the substrate is greater than a width in the second direction of an overlapping region between a second subsegment of the third initialization voltage transmission line and an orthographic projection of the first initialization voltage transmission line on the substrate; Optionally, the second sub-segment overlaps with an orthographic projection of an active portion of the third initialization transistor on the substrate, and is connected via a via in the overlapping region; Optionally, a plurality of second sub-segments are arranged at intervals along the first direction; Optionally, the display panel includes a plurality of driving units, the driving unit includes two driving circuits arranged and adjacent to each other along the first direction, and in the same driving unit, the second sub-segment is connected between active portions of two third initialization transistors; Optionally, the display panel further comprises a control signal transmission line connected to the gate of the third initialization transistor; the control signal transmission line connected to the gate of the third initialization transistor extends along a first direction; optionally, an orthographic projection of the control signal transmission line connected to the gate of the third initialization transistor on the substrate at least partially overlaps with an orthographic projection of the first initialization voltage transmission line on the substrate; Optionally, along the thickness direction of the substrate, the first initialization voltage transmission line is located between the third initialization voltage transmission line and a control signal transmission line connected to the gate of the third initialization transistor; Optionally, the driving circuit further includes a second light emitting control transistor, which is connected between the first electrode of the light emitting element and the second electrode of the driving transistor.

7. The display panel according to claim 1, characterized in that: The driving circuit further comprises a compensation transistor and / or a first initialization transistor; The compensation transistor is connected between the second electrode of the driving transistor and the gate of the driving transistor; A first initialization transistor is electrically connected to the gate of the driving transistor; Optionally, the active portion of the compensation transistor and the active portion of the driving transistor are arranged in different layers, and / or the active portion of the first initialization transistor and the active portion of the driving transistor are arranged in different layers, Optionally, the active portion of the compensation transistor and the active portion of the first initialization transistor are connected and arranged in the same layer; Optionally, the film layer where the active part of the compensation transistor and / or the active part of the first initialization transistor is located is located on a side of the film layer where the active part of the driving transistor is located away from the substrate; Optionally, the active portion of the compensation transistor and / or the active portion of the first initialization transistor comprises a metal oxide semiconductor material, and the active portion of the driving transistor comprises a polysilicon semiconductor material.

8. The display panel according to claim 1, characterized in that: The driving circuit further includes a storage capacitor, The storage capacitor comprises a first electrode plate, and the first electrode plate multiplexes the gate of the driving transistor and the gate of the auxiliary transistor; Optionally, the storage capacitor further includes a second electrode plate, and the second electrode plates of the storage capacitors in the drive circuits that are arranged along the second direction and adjacent to each other are connected.

9. A display panel, characterized in that: include: substrate; A plurality of driving circuits are located on the substrate, wherein the driving circuits include a driving transistor, a first initialization transistor and a third initialization transistor connected to the driving transistor; A first initialization voltage transmission line and a third initialization voltage transmission line; the first initialization voltage transmission line is connected to the first initialization transistor; the third initialization voltage transmission line is connected to the third initialization transistor; Among them, the first initialization voltage transmission line extends along the first direction, the third initialization voltage transmission line extends along the first direction, and at least a part of the third initialization voltage transmission line is in a zigzag or curved line shape; the orthographic projections of the first initialization voltage transmission line and the third initialization voltage transmission line on the substrate partially overlap, and the orthographic projections of the first initialization voltage transmission line and the third initialization voltage transmission line on the substrate do not overlap.

10. A display device, characterized in that: include: The display panel according to any one of claims 1 to 9.

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